DS99R101VS/NOPB [TI]
3-40MHz 直流平衡 24 位 LVDS 串行器 | PFB | 48 | 0 to 70;
| 型号： | DS99R101VS/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-40MHz 直流平衡 24 位 LVDS 串行器 | PFB | 48 | 0 to 70 |
| 文件： | 总29页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS99R101, DS99R102
www.ti.com
SNLS240D –MARCH 2007–REVISED APRIL 2013
DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Check for Samples: DS99R101, DS99R102
1
FEATURES
Receiver
•
•
•
•
•
48-Pin TQFP Package
2
•
3 MHz–40 MHz Clock Embedded and DC-
Balancing 24:1 and 1:24 Data Transmissions
Pure CMOS .35 μm Process
Power Supply Range 3.3V ± 10%
Temperature Range 0°C to +70°C
8 kV HBM ESD Tolerance
•
•
User Selectable Clock Edge for Parallel Data
on Both Transmitter and Receiver
Internal DC Balancing Encode/Decode –
Supports AC-Coupling Interface with No
External Coding Required
DESCRIPTION
•
•
Individual Power-Down Controls for Both
Transmitter and Receiver
The DS99R101/DS99R102 Chipset translates a 24-
bit parallel bus into a fully transparent data/control
LVDS serial stream with embedded clock information.
This single serial stream simplifies transferring a 24-
bit bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and
connector size and pins.
Embedded Clock CDR (Clock and Data
Recovery) on Receiver and No External Source
of Reference Clock Needed
•
•
•
•
•
•
All Codes RDL (Random Data Lock) to Support
Live-Pluggable Applications
LOCK Output Flag to Ensure Data Integrity at
Receiver Side
The DS99R101/DS99R102 incorporates LVDS
signaling on the high-speed I/O. LVDS provides a low
power and low noise environment for reliably
transferring data over a serial transmission path. By
optimizing the serializer output edge rate for the
operating frequency range EMI is further reduced.
Balanced TSETUP/THOLD Between RCLK and
RDATA on Receiver Side
PTO (Progressive Turn-On) LVCMOS Outputs
to Reduce EMI and Minimize SSO Effects
All LVCMOS Inputs and Control Pins Have
Internal Pulldown
Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
On-Chip Filters for PLLs on Transmitter and
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS99R101, DS99R102
SNLS240D –MARCH 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
DEN
VODSEL
REN
D
OUT
+
R +
IN
24
24
R
D
OUT
IN
R
IN
-
D
OUT
-
TRFB
TCLK
Timing
and
Control
PLL
PLL
LOCK
RCLK
RRFB
RPWDNB
Timing
and
Clock
Recovery
TPWDNB
Control
SERIALIZER œ DS99R101
DESERIALIZER œ DS99R102
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to (VDD +0.3V)
−0.3V to (VDD +0.3V)
−0.3V to 3.9V
−0.3V to 3.9V
10 ms
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity 48L TQFP
Package De-rating:
1/θJA °C/W above +25°C
45.8 (4L(3)); 75.4 (2L(3)) °C/W
21.0°C/W
DS99R101
θJA
θJC
θJA
θJC
DS99R102
45.4 (4L(3)); 75.0 (2L(3))°C/W
21.1°C/W
ESD Rating (HBM)
≥±8 kV
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) JEDEC
2
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SNLS240D –MARCH 2007–REVISED APRIL 2013
Recommended Operating Conditions
Min
3.0
0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VDD
)
Operating Free Air Temperature (TA)
Clock Rate
+25
+70
40
°C
3
MHz
mVP-P
Supply Noise
±100
Electrical Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS
VIH
VIL
High Level Voltage
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
2.0
1.5
1.5
VDD
0.8
V
V
Low Level Input Voltage
Input Clamp Voltage
GND
VCL
ICL = −18 mA(4)
−0.8
−1.5
V
Rx: RPWDNB, RRFB,
REN
IIN
Input Current
VIN = 0V or 3.6V
Tx: DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
−10
±5
+10
+20
µA
µA
Rx: RPWDNB, RRFB,
REN
−20
±5
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE™ Output Current
IOH = −4 mA
IOL = +4 mA
VOUT = 0V(4)
Rx: ROUT[23:0], RCLK,
LOCK
2.3
3.0
VDD
0.5
V
V
GND 0.33
−40
−70
−110
mA
IOZ
RPWDNB, REN = 0V
VOUT = 0V or 2.4V
Rx: ROUT[23:0], RCLK,
LOCK
−15
±0.4
+15
+50
µA
LVDS DC SPECIFICATIONS
VTH
VTL
IIN
Differential Threshold High
Voltage
VCM = +1.2V
Rx: RIN+, RIN−
mV
mV
Differential Threshold Low
Voltage
−50
Input Current
VIN = +2.4V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
±200
±200
µA
µA
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Typical values represent most likely parametric norms at VCC = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions
at the time of product characterization and are not guaranteed.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(4) Specification is guaranteed by characterization and is not tested in production.
Copyright © 2007–2013, Texas Instruments Incorporated
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
VOD
Output Differential Voltage
RL = 100Ω
VODSEL = L (Figure 10)
Tx: DOUT+, DOUT−
250
400
600
1200
50
mV
(DOUT+)–(DOUT−
)
RL = 100Ω
VODSEL = H (Figure 10)
450
750
4
mV
mV
ΔVOD
Output Differential Voltage
Unbalance
RL = 100Ω
VOS
ΔVOS
IOS
Offset Voltage
RL = 100Ω
RL = 100Ω
1.00
1.25
1
1.50
50
V
Offset Voltage Unbalance
Output Short Circuit Current
mV
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
−2
−5
−8
mA
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
−7
−10
−13
mA
µA
IOZ
TRI-STATE Output Current
TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
−15
±1
+15
SER/DES SUPPLY CURRENT (DVDD(5), PVDD(5) and AVDD(5) pins)
IDDT
Serializer (Tx)
Total Supply Current
(includes load current)
RL = 100Ω
f = 40 MHz
f = 40 MHz
VODSEL = L
40
80
mA
Checker-board pattern (Figure 1)(6)
RL = 100Ω
VODSEL = H
40
1
85
100
95
mA
µA
Checker-board pattern (Figure 1)(6)
IDDTZ
IDDR
Serializer (Tx)
Supply Current Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
Deserializer (Rx)
CL = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)(6)
f = 40 MHz
f = 40 MHz
Total Supply Current
(includes load current)
mA
Deserializer (Rx)
Total Supply Current
(includes load current)
CL = 8 pF LVCMOS Output
Random pattern
90
50
mA
µA
IDDRZ
Deserializer (Rx)
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/ RIN-= 0V)
Supply Current Power-down
1
(5) Digital, PLL, and Analog VDDs
(6) Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Conditions
Min Typ Max Units
Figure 5(1)
25
T
333
ns
ns
ns
ns
tTCIH
tTCIL
tCLKT
tJIT
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
0.4T 0.5T 0.6T
0.4T 0.5T 0.6T
Figure 4
3
6
(2)
See
ps
(RMS)
33
(1) Figure 5, Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
(2) tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
4
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SNLS240D –MARCH 2007–REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLLHT
tLHLT
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
RL = 100Ω, (Figure 3)
CL = 10 pF to GND
VODSEL = L
0.6
ns
0.6
ns
tDIS
tDIH
tHZD
tLZD
tZHD
tZLD
tPLD
tSD
DIN (23:0) Setup to TCLK
RL = 100Ω,
5
5
ns
ns
ns
ns
ns
ns
ms
CL = 10 pF to GND(1)
DIN (23:0) Hold from TCLK
DOUT ± HIGH to TRI-STATE Delay
DOUT ± LOW to TRI-STATE Delay
DOUT ± TRI-STATE to HIGH Delay
DOUT ± TRI-STATE to LOW Delay
Serializer PLL Lock Time
RL = 100Ω,
15
15
CL = 10 pF to GND
(Figure 6)(2)
200
200
RL = 100Ω, (Figure 7)
RL = 100Ω, (Figure 8)(3)
VODSEL = L, TRFB = H
RL = 100Ω, (Figure 8)(3)
10
Serializer Delay
3.5T
+ 10
3.5T + 2.85
ns
ns
3.5T
+ 10
3.5T + 2.85
0.68
VODSEL = L, TRFB = L
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
3–40 MHz
UI(5)
(Figure 9)(4)
(1) Specification is guaranteed by characterization and is not tested in production.
(2) When the Serializer output is at TRI-STATE, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(3) Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
(4) tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
(5) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
tRDC
tCLH
Parameter
Receiver out Clock Period
RCLK Duty Cycle
Conditions
Pin/Freq.
RCLK
Min
25
Typ
T
Max
333
55
Units
ns
(1)
tRCP = tTCP
RCLK
45
50
%
LVCMOS Low-to-High
Transition Time
CL = 8 pF
(lumped load)
(Figure 11)
ROUT [23:0],
LOCK, RCLK
2.5
3.5
3.5
ns
ns
ns
ns
ns
ns
ns
ns
tCHL
tROS
tROH
tROS
tROH
tROS
tROH
LVCMOS High-to-Low
Transition Time
2.5
ROUT (7:0) Setup Data to
RCLK (Group 1)
(Figure 15)(2)
(Figure 15)(2)
(Figure 15)(2)
(Figure 13)
ROUT [7:0]
(0.40)*
tRCP
(29/56)*tRCP
(27/56)*tRCP
0.5*tRCP
ROUT (7:0) Hold Data to RCLK
(Group 1)
(0.40)*
tRCP
ROUT (15:8) Setup Data to
RCLK (Group 2)
ROUT [15:8],
LOCK
(0.40)*
tRCP
ROUT (15:8) Hold Data to
RCLK (Group 2)
(0.40)*
tRCP
0.5*tRCP
ROUT (23:16) Setup Data to
RCLK (Group 3)
ROUT [23:16]
(0.40)*
tRCP
(27/56)*tRCP
(29/56)*tRCP
ROUT (23:16) Hold Data to
RCLK (Group 3)
(0.40)*
tRCP
tHZR
tLZR
tZHR
tZLR
tDD
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
ROUT [23:0],
RCLK, LOCK
3
3
3
3
10
10
10
10
ns
ns
ns
ns
ns
(Figure 12)(3)
RCLK
[4+(3/56)]T [4+(3/56)]T
+5.9 +18.5
(1) Specification is guaranteed by characterization and is not tested in production.
(2) Figure 5, Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
(3) Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
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Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tDRDL
Parameter
Conditions
Pin/Freq.
3 MHz
Min
Typ
5
Max
50
Units
ms
(3)
Deserializer PLL Lock Time
from Powerdown(4)
(Figure 14)
(5) (1)
40 MHz
5
50
ms
RxIN_TOL_L Receiver INput TOLerance
Left
(Figure 16)
3 MHz–40 MHz
0.25
0.25
UI
UI
(6) (1) (7)
RxIN_TOL_R Receiver INput TOLerance
Right
(Figure 16)
3 MHz–40 MHz
(6) (1) (7)
(4) tDRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. tDRDL is specified with an external
synchronization pattern.
(5) The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
(6) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(7) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 1. Serializer Input Checker-board Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 2. Deserializer Output Checker-board Pattern
10 pF
DOUT+
DOUT-
80%
20%
80%
Differential
Signal
100W
Vdiff = 0V
20%
10 pF
Vdiff = (DOUT+) - (DOUT-)
t
t
LHLT
LLHT
Figure 3. Serializer LVDS Output Load and Transition Times
6
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SNLS240D –MARCH 2007–REVISED APRIL 2013
V
DD
80%
80%
TCLK
20%
20%
0V
t
t
CLK
CLKT
Figure 4. Serializer Input Clock Transition Times
t
TCP
TCLK
V
DD
/2
V
DD
/2
V
/2
DD
t
t
DIH
DIS
V
DD
DIN [0:23]
Setup
Hold
V
/2
V
DD
/2
DD
0V
Figure 5. Serializer Setup/Hold Times
Parasitic package and
Trace capcitance
DOUT+
5 pF
100W
DOUT-
DEN
t
LZD
V
/2
V
/2
CC
DEN
CC
(single-ended)
0V
0V
CLK1
CLK1
t
t
TCP
TCP
DOUT±
(differential)
200 mV
200 mV
DCA
DCA
DCA
t
ZLD
DCA
DCA DCA DCA DCA
All data —0“s
All data —1“s
t
HZD
V
/2
V
/2
CC
DEN
CC
(single-ended)
0V
0V
t
DCA
DCA DCA DCA DCA
ZHD
DCA
DCA
DCA
200 mV
200 mV
DOUT±
(differential)
t
t
TCP
TCP
CLK0
CLK0
Figure 6. Serializer TRI-STATE Test Circuit and Delay
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2.0V
PWDWN
TCLK
0.8V
t
or
HZD
t
LZD
t
or
ZHD
t
PLD
t
ZLD
Output
Active
TRI-STATE
TRI-STATE
DOUT±
Figure 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
DIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
t
SD
TCLK
STOP START
BIT BIT
STOP START
BIT BIT
STOP START
BIT BIT
STOP START
BIT BIT
STOP
BIT
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
DOUT0-23
DCA, DCB
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
23
Figure 8. Serializer Delay
Ideal Data Bit
End
Ideal Data Bit
Beginning
TxOUT_E_O
t (1/2UI)
BIT
t
(1/2UI)
BIT
Ideal Center Position (t /2)
BIT
t
(1UI)
BIT
Figure 9. Transmitter Output Eye Opening (TxOUT_E_O)
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SNLS240D –MARCH 2007–REVISED APRIL 2013
DOUT+
R
24
DIN
L
DOUT-
TCLK
VOD = (DOUT+) – (DOUT -
)
Differential output signal is shown as (DOUT+) – (DOUT -), device in Data Transfer mode.
Figure 10. Serializer VOD Diagram
Single-ended
80%
80%
20%
Signal
Deserializer
20%
8 pF
lumped
t
t
CHL
CLH
Figure 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times
START
BIT
STOP START
BIT BIT
STOP START
BIT BIT
STOP START
BIT BIT
SYMBOL N+3
STOP
BIT
SYMBOL N
SYMBOL N+1
SYMBOL N+2
RIN0-23
DCA, DCB
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
23
t
DD
RCLK
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
ROUT0-23
Figure 12. Deserializer Delay
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500W
VREF
VREF = V /2 for t
DD
or t ,
LZR
ZLR
or t
+
-
VREF = 0V for t
C
= 8pF
ZHR
HZR
L
REN
VOH
VOL
V
DD
/2
V /2
DD
REN
t
t
ZLR
LZR
VOL + 0.5V
VOL + 0.5V
VOH - 0.5V
VOL
t
t
ZHR
HZR
ROUT [23:0]
VOH
VOH + 0.5V
Note: CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
2.0V
PWDN
0.8V
t
DRDL
RIN±
LOCK
5}v[š /ꢀŒꢁ
TRI-STATE
TRI-STATE
t
or t
LZR
HZR
ROUT [0:23]
RCLK
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
REN
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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t
t
HIGH
LOW
RCLK
V
/2
V
DD
/2
DD
t
t
ROH
ROS
(group 1)
(group 1)
Data Valid
Before RCLK
Data Valid
After RCLK
ROUT [7:0]
V
/2
V
DD
/2
DD
1/2 UI
1/2 UI
t
t
ROH
ROS
(group 2)
(group 2)
Data Valid
Before RCLK
Data Valid
After RCLK
ROUT [15:8], LOCK
V
/2
V
DD
/2
DD
1/2 UI
1/2 UI
t
t
ROH
ROS
(group 3)
(group 3)
Data Valid
Before RCLK
Data Valid
After RCLK
ROUT [23:16]
V
/2
V
DD
/2
DD
Figure 15. Deserializer Setup and Hold Times
Ideal Data Bit
End
Ideal Data Bit
Beginning
Sampling
Window
RxIN_TOL -L
RxIN_TOL -R
Ideal Sampling Position
t
BIT
( )
2
t
BIT
(1UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
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DS99R101 Serializer Pin Descriptions
Pin #
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
4-1,
DIN[23:0]
LVCMOS_I
Transmitter Parallel Interface Data Inputs Pins. Tie LOW if unused, do not float.
48-44,
41-32,
29-25
10
TCLK
LVCMOS_I
Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I
Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
18
DEN
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
11
12
TRFB
LVCMOS_I
LVCMOS_I
Transmitter Rising/Falling Bar
TRFB = H; DIN LVCMOS Input clocked on Rising TCLK
TRFB = L; DIN LVCMOS Input clocked on Falling TCLK
VODSEL
VOD Level Select
VODSEL = L; LVDS Driver Output is ≈±400 mV (RL = 100Ω)
VODSEL = H; LVDS Driver Output is ≈±750 mV (RL = 100Ω)
5
DCAOFF
DCBOFF
RESRVD
NC
LVCMOS_I
LVCMOS_I
LVCMOS_I
NC
RESERVED – This pin MUST be tied LOW.
RESERVED – This pin MUST be tied LOW.
RESERVED – This pin MUST be tied LOW.
No Connect – Make NO connection – leave open
8
13
23
LVDS SERIAL INTERFACE PINS
20
DOUT+
LVDS_O
Transmitter LVDS True (+) Output. This output is intended to be loaded with a 100 ohm load to
the DOUT+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
19
DOUT−
LVDS_O
Transmitter LVDS Inverted (-) Output This output is intended to be loaded with a 100 ohm load to
the DOUT- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
22
21
16
17
14
15
30
31
7
VDDDR
VSSDR
VDDPT0
VSSPT0
VDDPT1
VSSPT1
VDDT
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
GND
Analog Voltage Supply, LVDS Output Power
Analog Ground, LVDS Output Ground
Analog Voltage supply, VCO Power
Analog Ground, VCO Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Digital Voltage supply, Tx Serializer Power
Digital Ground, Tx Serializer Ground
Digital Voltage supply, Tx Logic Power
Digital Ground, Tx Logic Ground
Digital Voltage supply, Tx Input Power
Digital Ground, Tx Input Ground
ESD Ground
VSST
VDDL
6
VSSL
42
43
24
VDDIT
VSSIT
VSS
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DS99R101 Pin Diagram
DIN[10]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
V
SS
DIN[11]
DIN[12]
DIN[13]
DIN[14]
NC
V
V
DR
DD
DR
SS
DOUT+
DOUT-
DEN
V
IT
IT
DS99R101
48 PIN TQFP
DD
V
SS
DIN[15]
DIN[16]
DIN[17]
DIN[18]
DIN[19]
V
V
V
V
PT0
SS
PT0
PT1
DD
SS
DD
PT1
RESRVD
Figure 17. Serializer - DS99R101
TOP VIEW
DS99R102 Deserializer Pin Descriptions
Pin #
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O
LVCMOS_O
LVCMOS_O
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 1
Receiver Parallel Interface Data Outputs – Group 2
Receiver Parallel Interface Data Outputs – Group 3
13-16, ROUT[15:8]
21-24
3-6, 9- ROUT[23:16]
12
18
RCLK
Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
17
2
LOCK
LVCMOS_O
LVCMOS_I
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
RESRVD
RESERVED – This pin MUST be tied LOW.
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DS99R102 Deserializer Pin Descriptions (continued)
Pin #
Pin Name
I/O
Description
LVDS SERIAL INTERFACE PINS
41
42
RIN+
LVDS_I
LVDS_I
Receiver LVDS True (+) Input This input is intended to be terminated with a 100 ohm load to the
RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
RIN−
Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100 ohm load to
the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
39
40
47
46
45
44
37
38
36
35
30
29
20
19
7
VDDIR
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
Analog LVDS Voltage supply, Power
Analog LVDS Ground
VSSIR
VDDPR0
VSSPR0
VDDPR1
VSSPR1
VDDR1
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL VCO Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
VSSR1
VDDR0
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
VSSR0
VDDOR1
VSSOR1
VDDOR2
VSSOR2
VDDOR3
VSSOR3
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
8
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DS99R102 Pin Diagram
PTO GROUP 1
37
38
39
40
41
42
43
44
45
46
47
48
24
ROUT[8]
ROUT[9]
ROUT[10]
ROUT[11]
V
R1
R1
DD
23
22
21
20
19
18
17
16
15
14
13
V
SS
V
IR
IR
DD
V
SS
RIN+
RIN-
V
V
OR2
DD
OR2
DS99R102
48 PIN TQFP
SS
RRFB
RCLK
LOCK
V
SS
PR1
PR1
PR0
PR0
ROUT[12]
ROUT[13]
ROUT[14]
ROUT[15]
V
DD
V
SS
V
DD
REN
PTO GROUP 3
Figure 18. Deserializer - DS99R102
TOP VIEW
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FUNCTIONAL DESCRIPTION
The DS99R101 Serializer and DS99R102 Deserializer chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 72 Mbps to 960 Mbps throughput.
The DS99R101 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream
with embedded clock. The DS99R102 receives the LVDS serial data stream and converts it back into a 24-bit
wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data
over shielded twisted pair (STP) at clock speeds from 3 MHz to 40 MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source. The
Deserializer synchronizes to the Serializer regardless of data pattern, delivering true automatic “plug and lock”
performance. The Deserializer recovers the clock and data by extracting the embedded clock information and
validating data integrity from the incoming data stream and then deserializes the data. The Deserializer monitors
the incoming clock information, determines lock status, and asserts the LOCK output high when lock occurs.
Each has a power down control to enable efficient operation in various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS99R101 and DS99R102 must be established before each device sends or receives data.
Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks
to the input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization
step.
Step 1: When VDD is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE
and internal circuitry is disabled by on-chip power-on circuitry. When VDD reaches VDD OK (2.2V) the PLL in
Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The
Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer
block is now ready to send data patterns. The Deserializer output will remain in TRI-STATE while its PLL locks to
the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low until its
PLL locks to incoming data and sync-pattern on the RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special
patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (non-
repetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded clock
within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit
stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded
input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a
series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this
locking procedure is independent on the data pattern, total random locking duration may vary. At the point when
the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on
the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s
LOCK pin is a convenient way to ensure data integrity is achieved on receiver side.
DATA TRANSFER
After lock is established, the Serializer inputs DIN0–DIN23 are used to input data to the Serializer. Data is
clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the
TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer
outputs (DOUT±) are intended to drive point-to-point connections or limited multi-point applications.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1
bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits
in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on
transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This
bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data
integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically
performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 3 MHz to 40 MHz. Every clock cycle, 24 databits are sent along
with 4 additional overhead control bits. Thus the line rate is 1.12 Gbps maximum (84 Mbps minimum). The link is
extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to
only 1 single LVDS pair providing a compression ratio of better then 25 to 1.
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Serialized data and clock/control bits (24+4 bits) are transmitted from the serial data output (DOUT±) at 28 times
the TCLK frequency. For example, if TCLK is , the serial rate is 40 x 28 = 1.12 Giga bits per second. Since only
24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 40
MHz, the payload data rate is 40 x 24 = 960 Mbps. TCLK is provided by the data source and must be in the
range of 3 MHz to 40 MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection as
shown in Figure 19. The outputs transmit data when the enable pin (DEN) is high and TPWDNB is high. The
DEN pin may be used to TRI-STATE the outputs when driven low.
When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT(0-23), LOCK and RCLK outputs will each drive a maximum of 8 pF load with a 40 MHz clock.
REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer.
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system must monitor the LOCK pin to determine whether data on the ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing
supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL must
lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before
data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In powerdown
mode, the PLL stops and the outputs enter TRI-STATE. To bring the Deserializer block out of the powerdown
state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the encoded clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both
driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state
as long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (VDD = 0V).
AC-COUPLING AND TERMINATION
The DS99R101 and DS99R102 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use AC coupled connection between the Serializer and Deserializer, insert
external AC coupling capacitors in series in the LVDS signal path as illustrated in . The Deserializer input stage
is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.2V. With AC
signal coupling, capacitors provide the ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common
used capacitor value for the interface is 100 nF (0.1 uF) capacitor.
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A termination resistor across DOUT± is also required for proper operation to be obtained. The termination
resistor should be equal to the differential impedance of the media being driven. This should be in the range of
90 to 132 Ohms. 100 Ohms is a typical value common used with standard 100 Ohm transmission media. This
resistor is required for control of reflections and also to complete the current loop. It should be placed as close to
the Serializer DOUT± outputs to minimize the stub length from the pins. To match with the deferential impedance
on the transmission line, the LVDS I/O are terminated with 100 ohm resistors on Serializer DOUT± outputs pins.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5UI
apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce.
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APPLICATIONS INFORMATION
USING THE DS99R101 AND DS99R102
The DS99R101/DS99R102 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a
serial LVDS link up to 960 Mbps. Serialization of the input data is accomplished using an on-board PLL at the
Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The Deserializer monitors the incoming clockl information to
determine lock status and will indicate lock by asserting the LOCK output high.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. IDD curve of CMOS
designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
Serializer: TCLK jitter, VDD noise (noise bandwidth and out-of-band noise)
Media: ISI, VCM noise
Deserializer: VDD noise
For a graphical representation of noise margin, please see Figure 16.
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point configuration, through a PCB trace, or through
twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of
the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most
applications that involve cables, the transmission distance will be determined on data rates involved, acceptable
bit error rate and transmission medium.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live pluggable applications. The “Hot Inserted” operation on the
serial interface does not disrupt communication data on the active data lines. The automatic receiver lock to
random data “plug & go” live insertion capability allows the DS99R102 to attain lock to the active data stream
during a live insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
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A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS (LVTTL) signals away from the
LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of
100 Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that
coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will
also radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at
both ends of the devices. Nominal value is 100 Ohms to match the line’s differential impedance. Place the
resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting
stub between the termination resistor and device.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS/LVTTL signal
•
•
•
•
•
Minimize the number of VIA
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
DOUT+
RIN+
100 nF
100 nF
100 nF
100W
DOUT-
100W
RIN-
100 nF
Figure 19. AC Coupled Application
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DS99R101 (SER)
3.3V
VDDDR
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
C1
C2
C3
C4
VDDPT0
VDDPT1
DIN8
DIN9
C5
C6
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
VDDIT
VDDL
VDDT
LVCMOS
Parallel
Interface
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
DOUT+
DOUT-
C7
Serial
LVDS
Interface
TCLK
R1
GPO if used, or tie High (ON)
TPWDNB
3.3V
C8
DEN
TRFB
NC
VSSDR
VSSPT0
VSSPT1
VSST
VSSL
VSSIT
VSS
Notes:
Open
TPWDNB = System GPO
DEN = High (ON)
TRFB = High (Rising edge)
VODSEL = Low (400mV)
NC = No Connect
RESRVD = Low
VODSEL
DCAOFF
C1 to C3 = 0.01 mF
C4 to C6 = 0.1 mF
C7, C8 = 100 nF; 50WVDC, NPO or X7R
R1 = 100W
DCBOFF
RESRVD
DCAOFF = Low
DCBOFF = Low
Figure 20. DS99R101 Typical Application Connection
Copyright © 2007–2013, Texas Instruments Incorporated
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Product Folder Links: DS99R101 DS99R102
DS99R101, DS99R102
SNLS240D –MARCH 2007–REVISED APRIL 2013
www.ti.com
DS99R102 (DES)
3.3V
3.3V
VDDIR
VDDPR0
VDDPR1
C3
C4
C7
C8
C5
C1
C2
VDDOR1
VDDOR2
VDDOR3
VDDR0
VDDR1
C6
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
C9
RIN+
RIN-
Serial
LVDS
Interface
R1
ROUT8
ROUT9
C10
3.3V
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
REN
RRFB
LVCMOS
Parallel
Interface
GPO if used, or tie High (ON)
RPWDNB
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RESRVD
VSSPR0
VSSPR1
VSSR0
VSSR1
VSSIR
VSSOR1
VSSOR2
VSSOR3
Notes:
C1 to C4 = 0.01 m F
C5 to C8 = 0.1 m F
C9, C10 = 100 nF; 50WVDC, NPO or X7R
R1 = 100W
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RESRVD = Low
RCLK
LOCK
Figure 21. DS99R102 Typical Application Connection
TRUTH TABLES
DS99R101 Serializer Truth Table
TPWDNB
(Pin 9)
DEN
(Pin 18)
Tx PLL Status
(Internal)
LVDS Outputs
(Pins 19 and 20)
L
X
L
X
X
Hi Z
Hi Z
Hi Z
H
H
H
H
H
Not Locked
Locked
Serialized Data with Embedded Clock
DS99R102 Deserializer Truth Table
RPWDNB
(Pin 1)
REN
(Pin 48)
Rx PLL Status
ROUTn and RCLK
(See Pin Diagram)
LOCK
(Pin 17)
(Internal)
L
X
L
X
X
Hi Z
Hi Z
Hi Z
H
L = PLL Unocked;
H = PLL Locked
H
H
H
H
Not Locked
Locked
Hi Z
L
Data and RCLK Active
H
22
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Product Folder Links: DS99R101 DS99R102
DS99R101, DS99R102
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SNLS240D –MARCH 2007–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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Product Folder Links: DS99R101 DS99R102
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
(1)
(2)
(3)
(4/5)
(6)
DS99R101VS/NOPB
DS99R102VS/NOPB
ACTIVE
TQFP
TQFP
PFB
48
48
RoHS & Green
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 70
0 to 70
DS99R101
VS
ACTIVE
PFB
SN
DS99R102
VS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS99R101VS/NOPB
DS99R102VS/NOPB
PFB
PFB
TQFP
TQFP
48
48
250
250
10 x 25
10 x 25
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
Pack Materials-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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