DS99R124AQ-Q1 [TI]
5MHz 至 43MHz 18 位彩色 FPD-Link II 至 FPD-Link 转换器;
| 型号： | DS99R124AQ-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5MHz 至 43MHz 18 位彩色 FPD-Link II 至 FPD-Link 转换器 光电二极管 转换器 |
| 文件： | 总32页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS99R124AQ
www.ti.com
SNLS342A –JULY 2011–REVISED APRIL 2013
DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter
Check for Samples: DS99R124AQ
1
FEATURES
DESCRIPTION
The DS99R124AQ converts FPD-Link II to FPD-Link.
It translates a high-speed serialized interface with an
embedded clock over a single pair (FPD-Link II) to
three LVDS data/control streams and one LVDS clock
pair (FPD-Link). This serial bus scheme greatly eases
system design by eliminating skew problems between
clock and data, reduces the number of connector
pins, reduces the interconnect size, weight, and cost,
and overall eases PCB layout. In addition, internal
DC balanced decoding is used to support AC-coupled
interconnects.
2
•
5 – 43 MHz Support (140 Mbps to 1.2 Gbps
Serial Link)
•
4-Channel (3 data + 1 clock) FPD-Link LVDS
Outputs
•
•
3 Low-Speed Over-Sampled LVCMOS Outputs
AC Coupled STP Interconnect up to 10 Meters
in Length
•
•
•
•
•
Integrated Input Termination
@ Speed Link BIST Mode and Reporting Pin
Optional I2C Compatible Serial Control Bus
RGB666 + VS, HS, DE Converted from 1 Pair
The DS99R124AQ converter recovers the data
(RGB) and control signals and extracts the clock from
a serial stream (FPD-Link II). It is able to lock to the
incoming data stream without the use of a training
sequence or special SYNC patterns and does not
require a reference clock. A link status (LOCK) output
signal is provided.
Power Down Mode Minimizes Power
Dissipation
•
FAST Random Data Lock; No Reference Clock
Required
•
•
•
•
•
•
Adjustable Input Receive Equalization
LOCK (Real Time Link Status) Reporting Pin
Low EMI FPD-Link Output
Adjustable input equalization of the serial input
stream provides compensation for transmission
medium losses of the cable and reduces the medium-
induced deterministic jitter. EMI is minimized by the
use of low voltage differential signaling, output state
select feature, and additional output spread spectrum
generation.
SSCG Option for Lower EMI
1.8V or 3.3V Compatible I/O Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
With fewer wires to the physical interface of the
display, FPD-Link output with LVDS technology is
ideal for high speed, low power and low EMI data
transfer.
•
>8 kV HBM and ISO 10605 ESD Rating
APPLICATIONS
The DS99R124AQ is offered in a 48-pin WQFN
package and is specified over the automotive AEC-
Q100 Grade 2 temperature range of -40˚C to +105˚C.
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS99R124AQ
SNLS342A –JULY 2011–REVISED APRIL 2013
www.ti.com
Applications Diagram
FPD-Link
FPD-Link II
FPD-Link
VDDIO
(1.8V or 3.3V)
3.3V
1.8V 3.3V
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
TxOUT2+/-
DOUT+
RIN+
RIN-
HOST
Graphics
Processor
RGB Display
QVGA to WVGA
18-bit Color Depth
RxIN1+/-
TxOUT1+/-
TxOUT0+/-
RxIN0+/-
DOUT-
100W STP Cable
RxCLKIN+/-
PWDNB
TxCLKOUT+/-
DS99R421Q
Converter
DS99R124AQ
Converter
CMF
OS[2:0]
LOCK
PASS
SSC[2:0]
LFMODE
BISTM
OS[2:0]
BISTEN
BISTEN
PDB
DEN
PRE
VODSEL
VODSEL
OEN
OSSEL
SCL
Optional
SDA
ID[x]
Figure 1.
DS99R124AQ Pin Diagram
RES[1]
VDDA
GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
ID[x]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
RIN+
RIN-
DS99R124AQ
CMF
TOP VIEW
VDDA
GND
DAP = GND
GND
VDDP
VDDP
GND
RES[0]
GND
VDDTX
Figure 2. FPD-Link II to FPD-Link Convertor
WQFN Package
See package Number RHS0048A
2
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Pin Name
SNLS342A –JULY 2011–REVISED APRIL 2013
PIN DESCRIPTIONS(1)
Pin No.
I/O, Type
Description
FPD-Link II Input Interface
RIN+
RIN-
CMF
40
41
42
I, LVDS
True input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
I, LVDS
Inverting input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
FPD-Link Output Interface
TxOUT[2:0]+
TxOUT[2:0]-
TxCLKOUT+
TxCLKOUT-
19, 21, 23
20, 22, 24
17
O, LVDS
O, LVDS
O, LVDS
O, LVDS
True LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
Inverting LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
True LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
18
Inverting LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
LVCMOS Outputs
OS[2:0]
12, 11, 10
O, LVMOS
O, LVMOS
Over-Sampled Low Frequency Outputs
These bits map to the DS99R421's OS[2:0] over-sampled low-frequency inputs. Signals must
be slower the TxCLK/5. On the DS90UR241 these map to the DIN[23:21] inputs. OS0 =
DIN21, OS1 = DIN22, OS2 = DIN23.
LOCK
27
LOCK Status Output
LOCK = 1, PLL is locked, outputs are active.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL.
Maybe used as a Link Status or to flag when the Video Data is active (ON/OFF).
Control and Configuration
PDB
1
I, LVCMOS
Power Down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the output are controlled by the settings. Control registers
are RESET.
VODSEL
OEN
33
34
I, LVCMOS
Differential Driver Output Voltage Select
w/ pull-down VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ), see Table 2
I, LVCMOS
Output Enable Input
w/ pull-down OEN = 1, FPD-Link outputs are enabled (active).
OEN = 0, FPD-Link outputs are TRI-STATE.
OSS_SEL
LFMODE
35
36
I, LVCMOS
w/ pull-down
Output Sleep State Select Input, see Table 1
I, LVCMOS
Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-43 MHz)
SSC[2:0]
RES[1:0]
7, 3, 2
37, 15
I, LVCMOS
w/ pull-down See Table 3 and Table 4
Spread Spectrum Clock Generation (SSCG) Range Select
I, LVCMOS Reserved
w/ pull-down Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon power-
up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
28 [PASS]
STRAP
I, LVCMOS
EQ Gain Control of FPD-Link II Input
EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
(1) 1 = HIGH, 0 = LOW
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PIN DESCRIPTIONS(1) (continued)
Pin Name
Pin No.
I/O, Type
Description
Optional BIST Mode
BISTEN
BISTM
PASS
29
30
28
I, LVCMOS
BIST Enable Input – Optional
w/ pull-down BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
I, LVCMOS
BIST Mode Input – Optional
w/ pull-down BISTM = 1, selects Payload Error Mode
BISTM = 0, selects Pass / Fail Result-Only Mode
O, LVCMOS PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL
SDA
ID[x]
5
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO
.
4
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain
SDA requires an external pull-up resistor to VDDIO.
16
I, Analog
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 5.
Power and Ground
VDDL
VDDA
VDDP
VDDTX
VDDIO
GND
6, 31
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
38, 43
8, 46, 47
13
Analog Power, 1.8 V ±5%
SSC Generator Power, 1.8 V ±5%
FPD-Link Power, 3.3 V ±10%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
Ground
25
9, 14, 26,
32, 39, 44,
45, 48
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
Block Diagram
DS99R124AQ œ CONVERTER
SSC[2:0]
OEN
VODSEL
SSCG
CMF
TxOUT[2]
TxOUT[1]
TxOUT[0]
RIN+
RIN-
TxCLKOUT
OS[2:0]
3
Error
Detector
PASS
PDB
SCL
SCA
LOCK
ID[x]
Timing and
Control
PLL
BISTEN
BISTM
OSS_SEL
LFMODE
Figure 3. FPD-Link II to FPD-Link Convertor
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SNLS342A –JULY 2011–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDTX (3.3V)
Supply Voltage – VDDIO
LVCMOS I/O Voltage
−0.3V to +2.5V
−0.3V to +4.0V
−0.3V to +4.0V
−0.3V to +(VDDIO + 0.3V)
−0.3V to (VDD + 0.3V)
−0.3V to (VDDTX + 0.3V)
+150°C
Receiver Input Voltage
LVDS Output Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4s)
48L WQFN Package
Derate above 25°C
1/ θJA°C/W
27.7 °C/W
3.0 °C/W
≥±30 kV
≥±6 kV
Maximum Power Dissipation Capacity at 25°C
θJA
θJC
Air Discharge (RIN+, RIN−
)
ESD Rating (IEC, powered-up only), RD
=
330Ω, CS = 150pF
Contact Discharge (RIN+, RIN−
Air Discharge (RIN+, RIN−
Contact Discharge (RIN+, RIN−
Air Discharge (RIN+, RIN−
Contact Discharge (RIN+, RIN−
)
)
)
)
≥±15 kV
≥±8 kV
ESD Rating (ISO10605), RD = 330Ω, CS = 150
and 330pF
)
≥±15 kV
≥±8 kV
ESD Rating (ISO10605), RD = 2kΩ, CS = 150
and 330pF
ESD Rating (HBM)
ESD Rating (CDM)
ESD Rating (MM)
≥±8 kV
≥±1.25 kV
≥±250 V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions
Min
1.71
1.71
3.0
Nom
1.8
Max
1.89
1.89
3.6
Units
V
Supply Voltage (VDDn
)
LVCMOS Supply Voltage (VDDIO
LVCMOS Supply Voltage (VDDIO
)
)
1.8
V
3.3
V
Operating Free Air Temperature (TA)
TxCLK Clock Frequency
Supply Noise(1)
−40
5
+25
+105
43
°C
MHz
mVP-P
100
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Parameter
Test Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link LVDS Output
VODSEL = L
100
200
250
400
500
800
1
400
600
mV
mV
|VOD
|
Differential Output Voltage
VODSEL = H
VODSEL = L
VODSEL = H
mVp-p
mVp-p
mV
Differential Output Voltage
A-B
VODp-p
ΔVOD
VOS
RL = 100Ω
TxCLKOUT+,
TxCLKOUT-,
TxOUT[2:0]+,
TxOUT[2:0]-
Output Voltage Unbalance
Offset Voltage
50
VODSEL = L
VODSEL = H
1.0
-10
1.2
1.2
1
1.5
V
V
ΔVOS
Offset Voltage Unbalance
Output Short Circuit Current
50
mV
IOS
Vout = GND
-5
mA
OEN = GND,
Vout =VDDTX, or GND
IOZ
Output TRI-STATE Current
+10
µA
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
PDB,
VODSEL,
OEN,
2.2
VDDIO
0.8
V
V
GND
OSS_SEL,
LFMODE,
SSC[2:0],
BISTEN,
BISTM
IIN
Input Current
VIN = 0V or VDDIO
−15
±1
+15
μA
VDDIO
0.2
-
VOH
High Level Output Voltage
IOH = −0.5 mA
VDDIO
V
LOCK,
PASS,
OS[2:0]
VOL
IOS
Low Level Output Voltage
Output Short Circuit Current
IOL = +0.5 mA
VOUT = 0V
GND
-10
0.2
V
mA
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
IOZ
TRI-STATE Output Current
−10
+10
µA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
PDB,
VODSEL,
OEN,
OSS_SEL,
LFMODE,
SSC[2:0],
BISTEN,
BISTM
0.7
VDDIO
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VDDIO
V
V
0.35*
VDDIO
GND
IIN
Input Current
VIN = 0V or VDDIO
−10
±1
+10
μA
VDDIO
- 0.2
VOH
High Level Output Voltage
IOH = −0.1 mA
VDDIO
V
LOCK,
PASS,
OS[2:0]
VOL
IOS
IOZ
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE Output Current
IOL = +0.1 mA
VOUT = 0V
GND
0.2
V
-3
mA
µA
VOUT = 0V or VDDIO
-15
+15
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDDn = 1.8V, VDDTX = 3.3V, VDDIO = 1.8V or 3.3V, Ta = +25 °C, and at the
Recommended Operation Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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SNLS342A –JULY 2011–REVISED APRIL 2013
DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Parameter
Test Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link II LVDS RECEIVER DC SPECIFICATIONS
Differential Input Threshold
High Voltage
VTH
+50
mV
mV
VCM = +1.2V (Internal VBIAS
)
Differential Input Threshold Low
Voltage
VTL
−50
RIN+, RIN-
Common Mode Voltage,
Internal VBIAS
VCM
RT
1.2
V
Input Termination
80
100
120
80
Ω
SUPPLY CURRENT
All VDD(1.8)
pins
IDD1
VDDn= 1.89V
70
mA
Supply Current
(includes load current)
43 MHz Clock
Checker Board Pattern,
VODSEL = H, SSCG =
On Figure 4
IDDTX1
IDDIO1
VDDTX = 3.6V VDDTX
30
0.35
1
40
1
mA
mA
mA
VDDIO=1.89V
VDDIO
VDDIO = 3.6V
1.5
All VDD(1.8)
pins
IDDZ
VDD= 1.89V
0.15
4
mA
PDB = 0V, All other
LVCMOS Inputs = 0V
IDDTXZ
VDDTX = 3.6V VDDTX
0.01
0.1
0.1
0.4
0.8
mA
mA
mA
Supply Current Power Down
VDDIO=1.89V
VDDIO
IDDIOZ
VDDIO = 3.6V
0.4
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Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)
Parameter
Test Conditions
Pin/Freq.
Min
Typ
Max
Units
FPD-Link II
tDDLT
SSCG = Off
5 MHz
5 MHz
43 MHz
43 MHz
6
14
5
ms
ms
ms
ms
SSCG = On
SSCG = Off
SSCG = On
Lock Time(3)
8
tDJIT
EQ = Off
Jitter Frequency > 10 MHz
Input Jitter Tolerance
>0.45
UI
FPD-Link Output
tTLHT
tTHLT
tDCCJ
Low to High Transition Time
0.3
0.3
900
75
0.6
0.6
ns
ns
ps
ps
TxCLKOUT±,
TxOUT[2:0]±
RL = 100Ω
High to Low Transition Time
TxCLKOUT = 5 MHz
TxCLKOUT = 43 MHz
2100
125
Cycle-to-Cycle Output Jitter(4)(5)
TxCLKOUT±
tTTP1
tTTP0
tTPP6
tTTP5
tTTP4
tTTP3
tTTP2
tTPDD
tTXZR
Transmitter Pulse Position for
bit 1
0
1
UI
UI
UI
UI
UI
UI
UI
ns
ns
Transmitter Pulse Position for
bit 0
Transmitter Pulse Position for
bit 6
2
Transmitter Pulse Position for
bit 5
TxOUT[2:0]±
3
Transmitter Pulse Position for
bit 4
4
Transmitter Pulse Position for
bit 3
5
Transmitter Pulse Position for
bit 2
6
Power Down Delay active to
OFF, Figure 6
TxCLKOUT = 43 MHz
TxCLKOUT = 43 MHz
6
10
55
Enable Delay OFF to active
Figure 7
40
LVCMOS Outputs
tCLH
tCHL
tPASS
Low to High Transition Time
10
10
15
15
ns
ns
ns
ns
CL = 8 pF, Figure 5
LOCK, PASS, OS[2:0]
PASS
High to Low Transition Time
TxCLKOUT = 5 MHz
TxCLKOUT = 43 MHz
560
70
570
75
BIST PASS Valid Time,
BISTEN = 1, Figure 12
SSCG Mode
fDEV
Spread Spectrum Clocking
Deviation Frequency
TxCLKOUT = 5 to 43
MHz, SSC[3:0] = ON
See(6)
See(6)
±0.5
8
±2
%
fMOD
Spread Spectrum Clocking
Modulation Frequency
TxCLKOUT = 5 to 43
MHz, SSC[3:0] = ON
100
kHz
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDDn = 1.8V, VDDTX = 3.3V, VDDIO = 1.8V or 3.3V, Ta = +25 °C, and at the
Recommended Operation Conditions at the time of product characterization and are not ensured.
(3) tDDLT is the time required by the deserializer to obtain lock when exiting power-down state with an active PCLK.
(4) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(5) Specification is ensured by characterization and is not tested in production.
(6) Specification is ensured by design and is not tested in production.
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Recommended Timing for the Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
0
Typ
Max
100
400
Units
kHz
kHz
us
fSCL
Standard Mode
Fast Mode
SCL Clock Frequency
0
tLOW
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
SCL Low Period
SCL High Period
us
tHIGH
Standard Mode
Fast Mode
us
us
tHD;STA Hold time for a start or a
repeated start condition,
Figure 13
Standard Mode
us
Fast Mode
0.6
4.7
0.6
us
us
us
tSU:STA Set Up time for a start or a
repeated start condition,
Figure 13
Standard Mode
Fast Mode
tHD;DAT
Standard Mode
Fast Mode
0
3.45
0.9
us
us
ns
ns
us
us
us
us
ns
ns
ns
ns
Data Hold Time, Figure 13
0
tSU;DAT
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
1.3
Data Set Up Time, Figure 13
tSU;STO
Standard Mode
Fast Mode
Set Up Time for STOP
Condition, Figure 13
tBUF
Standard Mode
Fast Mode
Bus Free Time Between STOP
and START, Figure 13
tr
Standard Mode
Fast Mode
1000
300
300
300
SCL and SDA Rise Time,
Figure 13
tf
Standard Mode
Fast mode
SCL and SDA Fall Time,
Figure 13
DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
Typ
Max
Units
VIH
VIL
0.7*
VDDIO
Input High Level
SDA and SCL
SDA and SCL
VDDIO
V
0.3*
VDDIO
Input Low Level Voltage
Input Hysteresis
GND
V
VHY
VOL
Iin
>50
mV
V
SDA, IOL = +0.5 mA
0
0.36
+10
SDA or SCL, Vin = VDDIO or GND
-10
µA
ns
ns
ns
ns
ns
pF
tR
SDA RiseTime – READ
SDA Fall Time – READ
800
50
SDA, RPU = X, Cb ≤ 400pF
tF
tSU;DAT Set Up Time — READ
tHD;DAT Hold Up Time — READ
540
600
50
tSP
Cin
Input Filter
Input Capacitance
SDA or SCL
<5
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AC Timing Diagrams and Test Circuits
+V
OD
TxCLKOUT
-V
OD
+V
OD
TxOUT[odd]
TxOUT[even]
-V
OD
+V
OD
-V
OD
Cycle N
Cycle N+1
Figure 4. Checkerboard Data Pattern
V
DDIO
80%
20%
GND
t
t
CHL
CLH
Figure 5. LVCMOS Transition Times
PDB
RIN
VILmax
X
t
TPDD
LOCK
Z
Z
Z
PASS
OS[2:0]
TxCLKOUT
TxOUT[2:0]
Z
Z
Figure 6. FPD-Link and LVCMOS Powerdown Delay
PDB
LOCK
tTXZR
OEN
VIHmin
Z
Z
TxCLKOUT
TxOUT[2:0]
Figure 7. FPD-Link Outputs Enable Delay
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PDB
VIH(min)
R ±
IN
tDDLT
LOCK
VIH(min)
TRI-STATE
Figure 8. Deserializer PLL Lock Times
|VOD|
VOS
GND
+VOD
0V
VODp-p
-VOD
t
t
THLT
TLHT
Figure 9. FPD-Link (LVDS) Single-ended and Differential Waveforms
Cycle N
TxCLKOUT±
TxOUT[2:0]±
bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
t
t
t
TTP1
TTP2
TTP3
1UI
2UI
3UI
4UI
5UI
6UI
7UI
t
t
TTP4
TTP5
t
t
TTP6
TTP7
Figure 10. FPD-Link Transmitter Pulse Positions
Sampling
Window
Ideal Data Bit
End
Ideal Data Bit
Beginning
RxIN_TOL -L
RxIN_TOL -R
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
Figure 11. Receiver Input Jitter Tolerance
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BISTEN
1/2 V
DDIO
tPASS
PASS
(w/ errors)
1/2 V
DDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 12. BIST PASS Waveform
SDA
t
BUF
t
t
f
t
HD;STA
t
r
LOW
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 13. Serial Control Bus Timing Diagram
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Typical Performance Characteristics
Typical Total IDD Current (1.8V Supply) as a Function of
PCLK
70
Typical Input Jitter Tolerance Curve at 43 MHz
0.63
SSCG = ON
VODSEL = H or L
0.61
0.58
0.56
0.53
0.51
0.48
0.46
60
SSCG = OFF
VODSEL = H or L
50
40
1.0E+05
1.0E+06
1.0E+07
0
5
10 15 20 25 30 35 40 45
JITTER FREQUENCY (kHz)
PCLK (MHz)
Figure 14.
Figure 15.
Typical IDDTX Current (3.3V Supply) as a Function of PCLK
40
VODSEL = H
SSCG = ON or OFF
30
20
VODSEL = L
SSCG = ON or OFF
10
0
5
10 15 20 25 30 35 40 45
PCLK (MHz)
Figure 16.
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FUNCTIONAL DESCRIPTION
The DS99R124AQ receives 24-bits of data over a single serial FPD-Link II pair operating at 140Mbps to
1.2Gbps. The serial stream also contains an embedded clock, and the DC-balance information which enhances
signal quality and supports AC coupling. The receiver copnverts the serial stream into a 4-channel (3 data and 1
clock) FPD-Link LVDS Interface. The device is intended to be used with the DS90UR241or the DS99R421 FPD-
Link II serializers.
The Des converts a single input serial data stream to a FPD-Link output bus, and also provides a signal check
for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or through the
optional serial control bus. The Des features enhance signal quality on the link by supporting the FPD-Link II
data coding that provides randomization, scrambling, and DC balancing of the data. The Des includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the data, FPD-Link LVDS Output interface, and also the output spread spectrum clock generation
(SSCG) support. The Des' power saving features include a power down mode, and optional LVCMOS (1.8 V)
interface compatibility.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream.
The DS99R421Q / DS99R124AQ chipset supports 18-bit color depth, HS, VS and DE video control signals and
up to three over-sampled low-speed (general purpose) data bits.
DATA TRANSFER
The DS99R124AQ will receive a pixel of data in the following format: C1 and C0 represent the embedded clock
in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled data. DCB is the
DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit
determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream. Both DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically.
Figure 17 illustrates the serial stream per PCLK cycle.
b
1
0
b
1
1
D
C
A
b
0
b
1
b
2
b
3
b
5
b
9
C
1
b
4
b
6
b
7
b
8
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 17. FPD-Link II Serial Stream (DS99R421/DS99R124A)
The device supports clocks in the range of 5 MHz to 43 MHz. With every clock cycle 24 bits of payload are
received along with the four overhead bits. Thus, the line rate is 1.2 Gbps maximum (140 Mbps minimum) with
an effective data rate of 1.03 Gbps maximum. The link is extremely efficient at 86% (24/28).
The FPD-Link output will pass along the data to the Display in the format shown in Figure 18.
TxCLKOUT
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
DE VS HS B5 B4 B3 B2
TxOUT0
TxOUT1
TxOUT2
Figure 18. FPD-Link Output Format
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FPD-LINK II INPUT
Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
OUTPUT INTERFACES (LVCMOS and FPD-LINK)
OS[2:0] LVCMOS Outputs
Additional signals maybe received across the serial link per PCLK. The over-sampled bits are restricted to be low
speed signals and should be less than 1/5 of the frequency of the PCLK. Signals should convey level information
only, as pulse width distrotion will occur by the over sampling technique and location of the sampling clock. The
three over sampled bits are exactly mapped to DS99R421's; and to DS90UR421 bits are: OS0 = DIN21, OS1 =
DIN22, and OS2 = DIN23.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is Low and the FPD-Link
interface state is determined by the state of the OSS_SEL pin.
After the DS99R124AQ completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the FPD-Link outputs. The TxCLK
output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered
clock (or vice versa). Note that the FPD-Link outputs may be held in an inactive state (TRI-STATE) through the
use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
Table 1. Output State Table
INPUTS
OEN
X
OUTPUTS
OTHER OUTPUTS
PDB
OSS_SEL
LOCK
L
L
Z
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are TRI-STATE
PASS is TRI-STATE
L
H
H
H
H
X
L
H
L
L
L
L
L
L
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is HIGH
L
H
L
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are LOW
PASS is LOW
H
H
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are TRI-STATE
PASS is HIGH
H
TxCLKOUT is TRI-STATE
TxOUT[2:0] areLOW
OS[2:0] are LOW
PASS is LOW
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Table 1. Output State Table (continued)
INPUTS
OUTPUTS
OTHER OUTPUTS
PDB
OEN
OSS_SEL
LOCK
H
L
X
H
TxCLKOUT is TRI-STATE
TxOUT[2:0] areTRI-STATE
OS[2:0] are Active
PASS is Active
(This setting allows the system to run BIST or use the OS[2:0]
bits while the panel is off)
H
H
X
H
TxCLKOUT is Active
TxOUT[2:0] are Active
OS[2:0] are Active
PASS is Active
(Normal operating mode)
LVCMOS 1.8V / 3.3V VDDIO Operation
The LVCMOS inputs and outputs can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
FPD-LINK OUTPUT
VODSEL
The differential output voltage of the FPD-Link interface is controlled by the VODSEL input.
Table 2. VODSEL Configuration Table
VODSEL
Result
VOD is 250mV TYP (500mVp-p)
VOD is 400mV TYP (800mVp-p)
L
H
SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 3 and Table 4. This feature may be controlled by pins
or by register. The LFMODE should be set appropriately if the SSCG is being used. Set LFMODE High if the
clock frequency is between 5 MHz and 20 MHz, set LFMODE Low if the clock frequency is between 20 MHz and
43 MHz.
Table 3. SSCG Configuration (LFMODE = L) — Des Output
SSC[2:0] Inputs
LFMODE = L (20 - 43 MHz)
Result
SSC2
SSC1
SSC0
fdev (%)
OFF
±0.9
fmod (kHz)
L
L
L
L
L
H
L
OFF
L
H
H
L
±1.2
CLK/2168
CLK/1300
L
H
L
±1.9
H
H
H
H
±2.3
L
H
L
±0.7
H
H
±1.3
H
±1.7
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Table 4. SSCG Configuration (LFMODE = H) — Des Output
SSC[2:0] Inputs
LFMODE = H (5 - 20 MHz)
Result
SSC2
SSC1
SSC0
fdev (%)
OFF
±0.7
fmod (kHz)
L
L
L
L
L
H
L
OFF
L
H
H
L
±1.3
CLK/625
CLK/385
L
H
L
±1.8
H
H
H
H
±2.2
L
H
L
±0.7
H
H
±1.2
H
±1.7
Frequency
fdev(max)
F
F
PCLK+
F
PCLK
fdev(min)
Time
PCLK-
1/fmod
Figure 19. SSCG Waveform
POWER SAVING FEATURES
PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and output
valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL status.
Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
Built In Self Test (BIST) — Optional
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only an input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
The PASS output pin toggles to flag any payloads that are received with 1 to 24 bit errors. The BISTM pin
selects the operational mode of the PASS pin. If BISTM = L, the PASS pins reports the final result only. If BISTM
= H, the PASS pins counts payload errors and also results the result. The result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the Des BISTEN pin.
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Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 20. BIST Mode Flow Diagram
Sample BIST Sequence
See Figure 20 for the BIST mode flow diagram.
Step 1: For the DS99R421 FPD-Link II Ser BIST Mode is enabled via the BISTEN pin. For the DS90UR241 Ser,
BIST mode is enetered by setting all the input data of the device to Low state. A PCLK is required for all the Ser
options. When the Des detects the BIST mode pattern and command (DCA and DCB code) the RGB and control
signal outputs are shut off.
Step 2: Place the DS99R124AQ Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST
mode. If BISTM = H, the Des will check the incoming serial payloads for errors. If an error in the payload (1 to
24) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS
output can be monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set Low. The Des stops checking the data. The final test
result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more
errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device
is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal
operation.
Figure 21 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
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BISTEN
(SER)
BISTEN
(DES)
PCLK
(RFB = L)
RGB[7:0]
HS, VS, DE
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
X
X
PASS
w/ BISTM = L
X = bit error(s)
DATA
(internal)
X
PASS
w/ BISTM = H
FAIL
Prior Result
BIST
Result
Normal
PRBS
Normal
BIST Test
BIST Duration
Held
Figure 21. BIST Waveforms
Serial Bus Control — Optional
The DS99R124AQ may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 22.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
V
DDIO
10k
ID[X]
4.7k
4.7k
SER
or
R
ID
HOST
SCL
SDA
SCL
SDA
DES
To Other
Devices
Figure 22. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to
VDD1.8V, NOT VDDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 5 for the Des.
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The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 23.
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 23. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 24 and a WRITE is shown in Figure 25.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 5. ID[x] Resistor Value – DS99R124AQ Des
Resistor RID kΩ
Address 8'b
0 appended (WRITE)
Address 7'b
(5%tol)
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
Open
Register Address
Slave Address
Slave Address
Data
a
c
k
a
c
k
a
c
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
0
S
S
1
P
k
Figure 24. Serial Control Bus — READ
Register Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
0
S
P
Figure 25. Serial Control Bus — WRITE
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Table 6. DS99R124AQ — Serial Bus Control Registers
ADD ADD
(dec) (hex)
Default
(bin)
Register Name
Bit(s)
R/W
Function
LFMODE
Description
0
0
Des Config 1
7
R/W
0
SSCG Mode – low frequency support
0: 20 to 43 MHz Operation
1: 5 to 20 MHz Operation
6
R/W
0
OSS_SEL
Output Sleep State Select
TBD
5
4
R/W
R/W
R/W
R/W
0
0
Reserved
Reserved
Reserved
SLEEP
Reserved
Reserved
Reserved
3:2
1
00
0
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG Control
ADD_SEL
0: Configurations set from control pins
1: Configurations set from registers (except I2C_ID)
1
2
1
2
Slave ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 1110000 ID[X]
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71); 8b ' 1110 0010 (h'E2)
7b '1110 010 (h'72); 8b ' 1110 0100 (h'E4)
7b '1110 011 (h'73); 8b ' 1110 0110 (h'E6)
7b '1110 110 (h'76); 8b ' 1110 1100 (h'EC)
All other addresses are Reserved.
Des Features 1
7
R/W
0
OEN
Output Enable Input
0: FPD-Link output are TRI-STATE
1: FPD-Link outputs are enabled (active)
6
5:4
3
R/W
R/W
R/W
0
00
0
Reserved
Reserved
VODSEL
Reserved
Reserved
Differential Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
2:0
R/W
00
OSC_SEL
000: OFF
001: Reserved
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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Table 6. DS99R124AQ — Serial Bus Control Registers (continued)
ADD ADD
(dec) (hex)
Default
(bin)
Register Name
Bit(s)
R/W
Function
EQ Gain
Description
3
3
Des Features 2
7:5
R/W
000
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
4
R/W
0
EQ Enable
0: EQ = disabled
1: EQ = enabled
3
R/W
R/W
0
Reserved
Reserved
2:0
000
SSC
IF LFMODE = 0, then:
000: SSCG OFF
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/1300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.57%, fmod = CLK/1300
IF LFMODE = 1, then:
000: SSCG OFF
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
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Applications Information
DISPLAY APPLICATION
The DS99R124AQ, in conjunction with the DS99R421Q or DS90UR241Q, is intended for interfacing between a
host (graphics processor) and a Display. It supports an 18-bit color depth (RGB666) and up to WVGA display
formats. In a RGB666 application, 18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) are supported across the serial link with PCLK rates from 5 to 43MHz.
TYPICAL APPLICATION CONNECTION
Figure 26 shows a typical application of the DS99R124AQQ Des in pin mode for a 43 MHz WVGA Display
Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver provides internal
termination. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power
lines for effective noise suppression.
DS99R124AQ (CON)
1.8V
3.3V
FB4
FB1
VDDL
VDDTX
VDDIO
VDDIO
C7
C3
C4
VDDL
VDDIO
FB5
FB2
FB3
VDDA
VDDA
C8
VDDP
VDDP
VDDP
C9
C5
C6
TxCLKOUT+
TxCLKOUT-
TxOUT2+
TxOUT2-
FPD-Link
Interface
C1
TxOUT1+
TxOUT1-
LVDS
100 Ohm
Termination
RIN+
Serial
FPD-Link II
Interface
TxOUT0+
TxOUT0-
RIN-
CMF
C2
OS[2]
OS[1]
OS[0]
LOCK
PASS
C10
BISTEN
Host
Control
BISTM
OE
PDB
R
VODSEL
OSS_SEL
LFMODE
SSC[2]
SSC[1]
SSC[0]
C13
SCL
SDA
ID[X]
Tie to
desired
setting
C1 - C2 = 0.1 mF (50 WV)
C3 - C9 = 0.1 mF
C10 - C12 = 4.7 mF
C13 = > 10 mF
NC
2
R = 10 kW
FB1 - FB5: Impedance = 1 kW
Low DC resistance (< 1W)
GND
DAP (GND)
8
Figure 26. DS99R124AQ Typical Connection Diagram — Pin Control
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POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn), VDDTX and VDDIO supply ramps should be faster than 1.5 ms with a monotonic rise. Supplies
may power up in any order, however device operation should be initiated only after all supplies are in their valid
operating ranges. The optional serial bus address selection is done upon power up also. Thus, if using this
optional feature, the PDB signal must be delayed to allow time for the ID setting to occur. The delay maybe done
by simply holding the PDB pin at a Low, or with an external RC delay based off the VDDIO rail which would then
need to lag the others in time. If the PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a
10 uF cap to GND to delay the PDB input signal.
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through
twisted pair cable. The Ser and Des provide internal terminations providing a clean signaling environment. The
interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may
be used depending upon the noise environment and application requirements.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug
and go” hot insertion capability allows the DS99R124AQ to attain lock to the active data stream during a live
insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS Ser/Des devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
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SNLS342A –JULY 2011–REVISED APRIL 2013
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
web site at: www.ti.com/lvds
Revision History
•
•
•
•
•
•
March 2, 2011
Pin assignments for SSC[1] and SSC[0] have changed
Pin assignments for OS[2] and OS[0] have changed
RTlimits have changed from 75(min) and 92(max) to 80(min) and 120(max)
IDDTXZmax has changed from 0.05mA to 0.1mA
Serial control bus timing parameters updated to typical only: tR, tF, tSU:DAT HD:DAT
t
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS99R124AQSQ/NOPB
DS99R124AQSQE/NOPB
DS99R124AQSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RHS
RHS
RHS
48
48
48
1000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
99R124AQ
SN
SN
99R124AQ
99R124AQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS99R124AQSQ/NOPB WQFN
DS99R124AQSQE/NOPB WQFN
DS99R124AQSQX/NOPB WQFN
RHS
RHS
RHS
48
48
48
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
1.3
1.3
1.3
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS99R124AQSQ/NOPB
DS99R124AQSQE/NOPB
DS99R124AQSQX/NOPB
WQFN
WQFN
WQFN
RHS
RHS
RHS
48
48
48
1000
250
356.0
208.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
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IC LINE TRANSCEIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LLP-48, Line Driver or Receiver
NSC
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