DSD1791_08 [TI]
24 BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER;![DSD1791_08](http://pdffile.icpdf.com/pdf2/p00231/img/icpdf/DSD1791DBRG4_1355518_icpdf.jpg)
型号: | DSD1791_08 |
厂家: | ![]() |
描述: | 24 BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER |
文件: | 总56页 (文件大小:638K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
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D
Dual Supply Operation:
FEATURES
− 5-V Analog, 3.3-V Digital
5-V Tolerant Digital Inputs
Small 28-Lead SSOP Package
D
D
D
Supports both DSD and PCM Formats
24-Bit Resolution
D
D
Analog Performance:
− Dynamic Range: 113 dB
− THD+N: 0.001%
APPLICATIONS
D
D
D
D
D
D
D
A/V Receivers
− Full-Scale Output: 2.1 V RMS (at Postamp)
SACD Players
D
D
Differential Voltage Output: 3.2 Vp-p
DVD Players
8× Oversampling Digital Filter:
− Stop-Band Attenuation: –82 dB
− Pass-Band Ripple: 0.002 dB
HDTV Receivers
Car Audio Systems
Digital Multitrack Recorders
Other Applications Requiring 24-Bit Audio
D
D
Sampling Frequency: 10 kHz to 200 kHz
System Clock: 128, 192, 256, 384, 512, or
768 f With Autodetect
S
DESCRIPTION
D
D
Accepts 16-, 20-, and 24-Bit PCM Audio Data
The DSD1791 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI’s advanced segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The DSD1791 provides balanced
voltage outputs, allowing the user to optimize analog
performance externally. The DSD1791 accepts PCM and
DSD audio data formats, providing easy interfacing to
audio DSP and decoder chips. The DSD1791 also accepts
interface to external digital filter devices (DF1704,
DF1706, PMD200). Sampling rates up to 200 kHz are
supported. A full set of user-programmable functions is
accessible through an SPI control port, which supports
register write and readback functions. The DSD1791 also
supports the time-division-multiplexed command and
audio (TDMCA) data format.
2
PCM Data Formats: Standard, I S, and
Left-Justified
D
D
DSD Format Interface Available
Optional Interface to External Digital Filter or
DSP Available
D
D
TDMCA Interface Available
User-Programmable Mode Controls:
− Digital Attenuation: 0 dB to –120 dB,
0.5 dB/Step
− Digital De-Emphasis
− Digital Filter Rolloff: Sharp or Slow
− Soft Mute
− Zero Flag for Each Output/PCM and DSD
Formats
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢑꢚ ꢙ ꢀꢘ ꢖ ꢊꢉ ꢙꢓ ꢀ ꢏꢊꢏ ꢛꢜ ꢝꢞ ꢟ ꢠꢡ ꢢꢛꢞꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢꢛ ꢞꢜ ꢪꢡ ꢢꢦꢫ ꢑꢟ ꢞꢪꢥ ꢤꢢꢣ
ꢤ ꢞꢜ ꢝꢞꢟ ꢠ ꢢꢞ ꢣ ꢧꢦ ꢤ ꢛ ꢝꢛ ꢤ ꢡ ꢢꢛ ꢞꢜꢣ ꢧ ꢦꢟ ꢢꢬꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢊꢦꢭ ꢡꢣ ꢉꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ ꢣꢢ ꢡꢜꢪ ꢡꢟ ꢪ ꢮ ꢡꢟ ꢟ ꢡ ꢜꢢꢯꢫ
ꢑꢟ ꢞ ꢪꢥꢤ ꢢ ꢛꢞ ꢜ ꢧꢟ ꢞ ꢤ ꢦ ꢣ ꢣ ꢛꢜ ꢰ ꢪꢞ ꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ ꢢꢦ ꢣꢢꢛ ꢜꢰ ꢞꢝ ꢡꢩ ꢩ ꢧꢡ ꢟ ꢡꢠ ꢦꢢꢦ ꢟ ꢣꢫ
Copyright 2006, Texas Instruments Incorporated
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
ORDERING INFORMATION
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
PACKAGE CODE
DSD1791DB
Tube
DSD1791DB
28-lead SSOP
28DB
–25°C to 85°C
DSD1791
DSD1791DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
DSD1791
V
V
F, V L, V C, V
R
–0.3 V to 6.5 V
–0.3 V to 4 V
0.1 V
CC
DD
CC CC CC
Supply voltage
Supply voltage differences: V F, V L, V C, V
R
CC CC CC CC
Ground voltage differences: AGNDF, AGNDL, AGNDC, AGNDR, DGND
0.1 V
(2)
(2)
PLRCK, PDATA, PBCK, DSDL, DSDR, DBCK, MS , MDI , MC, SCK, RST
(3) (3)
ZEROL, ZEROR, MS , MDI
–0.3 V to 6.5 V
Digital input voltage
Analog input voltage
–0.3 V to (V
+ 0.3 V) < 4 V
DD
–0.3 V to (V
+ 0.3 V) < 6.5 V
CC
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
10 mA
–40°C to 125°C
–55°C to 150°C
150°C
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
260°C, 5 s
260°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input mode
Output mode
(2)
(3)
ELECTRICAL CHARACTERISTICS
all specifications at T = 25°C, V
= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted
DD S S
A
CC
DSD1791DB
PARAMETER
UNIT
MIN
TYP
MAX
RESOLUTION
24
Bits
DATA FORMAT (PCM Mode)
2
Audio data interface format
Audio data bit length
Audio data format
Standard, I S, left justified
16-, 20-, 24-bit selectable
MSB first, 2s complement
f
S
Sampling frequency
System clock frequency
10
200
kHz
128, 192, 256, 384, 512, 768 f
S
DATA FORMAT (DSD Mode)
Audio data interface format
Audio data bit length
DSD (direct stream digital)
1 Bit
f
S
Sampling frequency
2.8224
MHz
MHz
System clock frequency
2.8224
11.2896
2
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T = 25°C, V
= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted
DD S S
A
CC
PARAMETER
DIGITAL INPUT/OUTPUT
DSD1791DB
TYP
TEST CONDITIONS
UNIT
MIN
MAX
Logic family
TTL compatible
V
V
2
IH
Input logic level
VDC
µA
0.8
IL
I
I
V
V
= V
DD
10
IH
IN
Input logic current
Output logic level
= 0 V
–10
IL
IN
V
V
I
I
= –2 mA
= 2 mA
2.4
OH
OH
VDC
0.4
OL
OL
(1)
DYNAMIC PERFORMANCE (PCM MODE)
f
f
f
= 44.1 kHz
= 96 kHz
0.001%
0.0015%
0.003%
113
0.002%
S
S
S
THD+N at V
OUT
= 0 dB
= 192 kHz
EIAJ, A-weighted, f = 44.1 kHz
S
110
110
106
EIAJ, A-weighted, f = 96 kHz
S
113
Dynamic range
dB
dB
EIAJ, A-weighted, f = 192 kHz
113
S
EIAJ, A-weighted, f = 44.1 kHz
S
113
EIAJ, A-weighted, f = 96 kHz
S
113
Signal-to-noise ratio
Channel separation
EIAJ, A-weighted, f = 192 kHz
113
S
f
S
f
S
f
S
= 44.1 kHz
= 96 kHz
110
110
dB
dB
= 192 kHz
109
Level linearity error
V
OUT
= –120 dB
1
(1) (2)
DYNAMIC PERFORMANCE (DSD MODE)
THD+N at V
OUT
= 0 dB
2.1 V rms
0.001%
113
Dynamic range
Signal-to-noise ratio
ANALOG OUTPUT
–60 dB, EIAJ, A-weighted
EIAJ, A-weighted
dB
dB
113
Gain error
–8
–3
–2
3
0.5
0.5
3.2
1.4
8
3
2
% of FSR
% of FSR
% of FSR
V p-p
Gain mismatch, channel-to-channel
Bipolar zero error
At BPZ
(3)
Differential output voltage
Full scale (0 dB)
At BPZ
(3)
Bipolar zero voltage
V
(3)
Load impedance
R
1
= R
1.7
kΩ
2
(1)
Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 33. Analog performance specifications
are measured using the System Twot Cascade audio measurement system by Audio Precisiont in the averaging mode. For all
sampling-frequencyoperations, measurement bandwidth is limited with a 20-kHz AES17 filter.
(2)
(3)
Analog performance in the DSD mode is specified as the DSD modulation index of 100%. This is equivalent to PCM mode performance at
44.1 kHz and 64 f .
S
These parameters are defined at the DSD1791 output pins. Load impedances, R and R , are input resistors of the postamplifier. They are defined
1
2
as dc loads.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
3
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at T = 25°C, V
= 5 V, V = 3.3 V, f = 44.1 kHz, system clock = 256 f , and 24-bit data, unless otherwise noted
DD S S
A
CC
DSD1791DB
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
DIGITAL FILTER PERFORMANCE
De-emphasis error
0.1
dB
FILTER CHARACTERISTICS-1: SHARP ROLLOFF
0.002 dB
–3 dB
0.454 f
0.49 f
S
Pass band
S
Stop band
0.546 f
S
Pass-band ripple
0.002
dB
Stop band = 0.546 f
Stop band = 0.567 f
–75
–82
S
Stop-band attenuation
dB
s
S
Delay time
29/f
S
FILTER CHARACTERISTICS-2: SLOW ROLLOFF
0.04 dB
–3 dB
0.274 f
S
Pass band
0.454 f
S
Stop band
0.732 f
S
Pass-band ripple
0.002
dB
dB
s
Stop-band attenuation
Delay time
Stop band = 0.732 f
–82
S
29/f
S
POWER SUPPLY REQUIREMENTS
V
V
3
3.3
5
3.6
5.5
8
VDC
VDC
DD
Voltage range
4.5
CC
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz
= 96 kHz
6.5
13.5
28
(1)
(1)
I
Supply current
mA
mA
mW
DD
= 192 kHz
= 44.1 kHz
= 96 kHz
14
16
15
I
Supply current
CC
= 192 kHz
= 44.1 kHz
= 96 kHz
16
90
110
(1)
120
170
Power dissipation
= 192 kHz
TEMPERATURE RANGE
Operation temperature
Thermal resistance
–25
85
°C
θ
JA
28-pin SSOP
100
°C/W
(1)
Input is BPZ data.
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
PIN ASSIGNMENTS
DSD1791
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
PLRCK
PBCK
PDATA
DBCK
SCK
MS
MC
MDI
DSDL
DSDR
ZEROL
ZEROR
2
3
4
5
6
RST
7
V
DD
8
DGND
AGNDF
V
V
F
L
CC
9
CC
V
R
10
11
12
13
14
AGNDL
CC
AGNDR
V
V
L–
L+
OUT
V
V
R–
R+
OUT
OUT
AGNDC
OUT
V
V
C
COM
CC
5
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
AGNDC
AGNDF
AGNDL
AGNDR
DBCK
DGND
DSDL
DSDR
MC
PIN
16
9
–
–
–
–
I
Analog ground (internal bias and current DAC)
Analog ground (DACFF)
19
11
4
Analog ground (L-channel I/V)
Analog ground (R-channel I/V)
(1)
Bit clock input for DSD mode
Digital ground
8
–
I
(1)
(1)
25
24
27
26
28
2
L-channel audio data input for DSD mode
R-channel audio data input for DSD mode
I
(1)
I
Mode control clock input
(2)
Mode control data input
MDI
I/O
I/O
I
(2)
(1)
MS
Mode control chip select input
PBCK
PDATA
PLRCK
RST
Bit clock input for PCM mode
(1)
3
I
Serial audio data input for PCM mode
(1)
1
I
Left and right clock (f ) input for PCM mode
S
(1)
6
I
Reset
(1)
SCK
5
I
System clock input
V
V
V
V
V
V
V
V
V
V
C
F
L
15
21
20
10
14
7
–
–
–
–
–
–
O
O
O
O
O
O
Analog power supply (internal bias and current DAC), 5 V
Analog power supply (DACFF), 5 V
Analog power supply (L-channel I/V), 5 V
Analog power supply (R-channel I/V), 5 V
Internal bias decoupling pin
CC
CC
CC
CC
R
COM
DD
Digital power supply, 3.3 V
L+
17
18
13
12
23
22
L-channel analog voltage output +
L-channel analog voltage output –
R-channel analog voltage output +
R-channel analog voltage output –
Zero flag for L-channel
OUT
OUT
OUT
OUT
L–
R+
R–
ZEROL
ZEROR
Zero flag for R-channel
(1)
(2)
Schmitt-trigger input, 5-V tolerant
Schmitt-trigger input and output. 5-V tolerant input and CMOS output.
6
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
PLRCK
Current
Segment
DAC
V
V
L–
L+
Audio
PBCK
OUT
Data Input
PDATA
I/F
OUT
and
I/V Buffer
D/S and Filter
8
Oversampling
Digital
Filter
and
Function
Control
DBCK
DSDL
DSDR
RST
Advanced
Segment
DAC
Bias
and
Vref
V
COM
Modulator
Current
Segment
DAC
and
I/V Buffer
V
V
R+
R–
MDI
MC
MS
OUT
Function
Control
I/F
OUT
D/S and Filter
ZEROL
ZEROR
System
Clock
Manager
Zero
Detect
Power Supply
7
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
AMPLITUDE
AMPLITUDE
vs
vs
FREQUENCY
FREQUENCY
0
−20
0.003
0.002
−40
0.001
−60
−80
0
−100
−120
−140
−160
–0.001
–0.002
–0.003
0.0
0
1
2
3
4
0.1
0.2
0.3
0.4
0.5
Frequency[× f ]
Frequency[× f ]
S
S
Figure 1. Frequency Response, Sharp Rolloff
Figure 2. Pass-Band Ripple, Sharp Rolloff
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−20
0
−2
−4
−40
−6
−8
−60
−10
−12
−14
−16
−18
−20
−80
−100
−120
−140
0
1
2
3
4
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency[× f ]
Frequency[× f ]
S
S
Figure 3. Frequency Response, Slow Rolloff
Figure 4. Transition Characteristics, Slow Rolloff
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
De-Emphasis Filter
DE-EMPHASIS LEVEL
DE-EMPHASIS ERROR
vs
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
0.3
0.2
0.1
f
= 32 kHz
f
S
= 32 kHz
S
−
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
f – Frequency – kHz
f – Frequency – kHz
Figure 5
Figure 6
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.5
0.4
f
= 44.1 kHz
f
S
= 44.1 kHz
S
0.3
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f – Frequency – kHz
f – Frequency – kHz
Figure 7
Figure 8
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
De-Emphasis Filter (Continued)
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
0.5
0.4
f
S
= 48 kHz
f = 48 kHz
S
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
f – Frequency – kHz
f – Frequency – kHz
Figure 9
Figure 10
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
118
116
114
112
110
108
0.01
f
= 192 kHz
= 96 kHz
S
f
f
= 96 kHz
S
S
f
S
= 44.1 kHz
0.001
f
S
= 44.1 kHz
f
S
= 192 kHz
0.0001
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 11
Figure 12
SIGNAL-to-NOISE RATIO
vs
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
118
116
114
112
110
108
114
112
110
108
106
104
102
f
= 44.1 kHz
S
f
S
= 96 kHz
f
= 96 kHz
S
f
S
= 192 kHz
f
S
= 192 kHz
f
S
= 44.1 kHz
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 13
Figure 14
NOTE: PCM mode, T = 25°C, V
DD
= 3.3 V
A
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Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
118
116
114
112
110
108
0.01
f
= 192 kHz
S
f
= 96 kHz
S
f
= 96 kHz
S
f
= 44.1 kHz
S
f
S
= 192 kHz
0.001
f
= 44.1 kHz
S
0.0001
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
SIGNAL-to-NOISE RATIO
vs
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
118
116
114
112
110
108
114
112
110
108
106
104
f
= 44.1 kHz
S
f
= 44.1 kHz
S
f
= 96 kHz
S
f
S
= 96 kHz
f = 192 kHz
S
f
S
= 192 kHz
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 17
Figure 18
NOTE: PCM mode, V
= 3.3 V, V = 5 V.
CC
DD
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AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
−50
−60
−50
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−150
−100
−110
−120
−130
−140
−150
−160
−160
0
5
10
15
20
0
10 20 30 40 50 60 70 80 90 100
f – Frequency – kHz
f – Frequency – kHz
Figure 19. –60-dB Output Spectrum, BW = 20 kHz Figure 20. –60-dB Output Spectrum, BW = 100 kHz
NOTE: PCM mode, f = 44.1 kHz, 32768 points, 8 average, T = 25°C, V
DD
= 3.3 V, V = 5 V
CC
S
A
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
100
10
1
0.1
0.01
0.001
0.0001
−100
−80
−60
−40
−20
0
Input Level – dBFS
Figure 21. THD+N vs Input Level, PCM Mode
NOTE: PCM mode, f = 44.1 kHz, T = 25°C, V
DD
= 3.3 V, V = 5 V
CC
S
A
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AMPLITUDE
vs
FREQUENCY
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
−160
0
5
10
15
20
f – Frequency – kHz
Figure 22. –60-dB Output Spectrum, DSD Mode
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
100
10
1
0.1
0.01
0.001
0.0001
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Level – dBFS
Figure 23. THD+N vs Input Level, DSD Mode
NOTE: DSD mode (FIR-2), T = 25°C, V
= 3.3 V, V = 5 V.
CC
A
DD
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SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1791 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 5). The DSD1791 has a system clock detection circuit
that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock
frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as
128 f , the system clock frequency is required over 256 f .
S
S
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the DSD1791 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
512 f
SCK
SAMPLING FREQUENCY
128 f
192 f
256 f
384 f
768 f
S
S
S
S
S
S
32 kHz
44.1 kHz
48 kHz
4.096
5.6488
6.144
6.144
8.4672
9.216
8.192
11.2896
12.288
24.576
49.152
12.288
16.9344
18.432
36.864
73.728
16.384
24.576
33.8688
36.864
22.5792
24.576
96 kHz
12.288
24.576
18.432
36.864
49.152
(1)
73.728
(1)
192 kHz
(1)
This system clock rate is not supported for the given sampling frequency.
t
(SCKH)
H
2 V
0.8 V
System Clock (SCK)
L
t
t
(SCY)
(SCKL)
PARAMETERS
MIN MAX UNITS
t
System clock pulse cycle time
13
5
ns
ns
ns
(SCY)
t
System clock pulse duration, HIGH
System clock pulse duration, LOW
(SCKH)
t
5
(SCKL)
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The DSD1791 includes a power-on reset function. Figure 25 shows the operation of this function. With V
> 2 V,
DD
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
> 2 V. After the initialization period, the DSD1791 is set to its default reset state, as described in the MODE
V
DD
CONTROL REGISTERS section of this data sheet.
The DSD1791 also includes an external reset capability using the RST input (pin 6). This allows an external controller
or master reset circuit to force the DSD1791 to initialize to its default reset state.
Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the DSD1791 power
up and system clock activation.
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V
DD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 25. Power-On Reset Timing
RST (Pin 6)
1.4 V
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
PARAMETERS
MIN MAX UNITS
20 ns
t
Reset pulse duration, LOW
(RST)
Figure 26. External Reset Timing
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AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 1), PBCK (pin 2), and PDATA (pin 3). PBCK
is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of
the audio interface. Serial data is clocked into the DSD1791 on the rising edge of PBCK. PLRCK is the serial audio
left/right word clock.
The DSD1791 requires the synchronization of PLRCK and the system clock, but does not need a specific phase
relationship between PLRCK and the system clock.
If the relationship between PLRCK and system clock changes more than 6 PBCK, internal operation is initialized
within 1/f and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the
S
system clock is completed.
PCM Audio Data Formats and Timing
2
The DSD1791 supports industry-standard audio data formats, including standard right-justified, I S, and left-justified.
The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0], in control
2
register 18. The default data format is 24-bit I S. All formats require binary 2s complement, MSB-first audio data.
Figure 27 shows a detailed timing diagram for the serial audio interface.
1.4 V
1.4 V
1.4 V
PLRCK
PBCK
t
t
(BCL)
t
(BCH)
(LB)
t
t
(BCY)
(BL)
PDATA
t
t
(DS)
(DH)
PARAMETERS
MIN MAX UNITS
t
t
t
t
t
t
t
PBCK pulse cycle time
PBCK pulse duration, LOW
PBCK pulse duration, HIGH
PBCK rising edge to PLRCK edge
PLRCK edge to PBCK rising edge
PDATA setup time
70
30
30
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
(BCY)
(BCL)
(BCH)
(BL)
(LB)
(DS)
PDATA hold time
(DH)
—
PLRCK clock data
50% 2 bit clocks
Figure 27. Timing of Audio Interface
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(1) Standard Data Format (Right Justified) ; L-Channel = HIGH, R-Channel = LOW
1/f
S
PLRCK
R-Channel
L-Channel
PBCK
Audio Data Word = 16-Bit
14 15 16
1
2
15 16
LSB
1
2
15 16
PDATA
MSB
Audio Data Word = 20-Bit
18 19 20
1
2
19 20
LSB
1
2
19 20
23 24
PDATA
MSB
Audio Data Word = 24-Bit
22 23 24
1
2
23 24
LSB
1
2
PDATA
MSB
(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/f
S
PLRCK
PBCK
R-Channel
L-Channel
Audio Data Word = 24-Bit
PDATA
1
2
23 24
LSB
1
2
23 24
1
2
MSB
2
(3) I S Data Format; L-Channel = LOW, R-Channel = HIGH
1/f
S
PLRCK
L-Channel
R-Channel
PBCK
Audio Data Word = 16-Bit
PDATA
1
1
2
2
15 16
LSB
1
2
2
15 16
1
1
2
2
MSB
MSB
Audio Data Word = 24-Bit
PDATA
23 24
LSB
1
23 24
Figure 28. Audio Data Input Formats
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External Digital Filter Interface and Timing
The DSD1791 supports an external digital filter interface with a 3- or 4-wire synchronous serial port, which allows
the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific
Microsonics PMD200, or a programmable digital signal processor.
In the external DF mode, PLRCK (pin 1), PBCK (pin 2), and PDATA (pin 3) are defined as WDCK, the word clock;
BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using
the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1791.
When the DFMS bit of control register 19 is set, the DSD1791 can process stereo data. In this case, DSDL (pin 25)
and DSDR (pin 24) are defined as L-channel data and R-channel data input, respectively.
Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL
DIGITAL FILTER INTERFACE section of this data sheet.
Direct Stream Digital (DSD) Format Interface and Timing
The DSD1791 supports the DSD format interface operation, which includes out-of-band noise filtering using an
internal analog FIR filter. The DSD format interface consists of a 3-wire synchronous serial port, which includes DBCK
(pin 4), DSDL (pin 25), and DSDR (pin 24). DBCK is the serial bit clock, DSDL and DSDR are the L-chaqnnel and
R-channel DSD data inputs, respectively.They are clocked onto the DSD1791 on the rising edge of DBCK. PLRCK
(pin 1) and PBCK (pin 2) should be connected to GND in the DSD mode. The DSD format (DSD mode) interface is
activated by setting the DSD bit of control register 20.
Detailed information for the DSD mode is provided in the APPLICATION FOR DSD-FORMAT (DSD MODE)
INTERFACE section of this data sheet.
TDMCA Interface
The DSD1791 supports the time-division-multiplexed command and audio (TDMCA) data format to enable control
of and communication with a number of external devices over a single serial interface.
Detailed information for the TDMCA format is provided in the TDMCA INTERFACE FORMAT section of this data
sheet.
FUNCTION DESCRIPTIONS
Zero Detect
The DSD1791 has a zero-detect function. When the DSD1791 detects the zero conditions as shown in Table 2, the
DSD1791 sets ZEROL (pin 23) and ZEROR (pin 22) to HIGH.
Table 2. Zero Conditions
MODE
DETECTING CONDITION AND TIME
DATA is continuously LOW for 1024 LRCKs.
PCM
External DF mode DATA is continuously LOW for 1024 WDCKs.
DZ0
DZ1
There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23 ms.
The input data is 1001 0110 continuously for 23 ms.
DSD
Serial Control Interface (SPI)
The serial control interface is a 3-wire synchronous serial port which operates asynchronously to the serial audio
interface and the system clock (SCK). The serial control interface is used to program and read the on-chip mode
registers. The control interface includes MDI (pin 26), MC (pin 27), and MS (pin 28). MDI is the serial data input, used
to program the mode registers; MC is the bit clock, used to shift data in and out of the control port, and MS is the
mode control enable, used to enable the internal-mode register access.
The serial interface can also read the mode registers to set the MDOE of control register 19 to 1. In that case, ZEROL
(pin 23) is defined as the serial data output pin, and ZEROR (pin 22) is the logical AND of the L-channel and R-channel
zero conditions.
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Register Read/Write Operation
All read/write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word
format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For
read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or
address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to,
or the data that was read from, the register specified by IDX[6:0].
Figure 30 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1
state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen
clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data
on ZEROL. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on
ZEROL during the read operation. After the sixteenth clock cycle has completed, the data is latched into the
indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once.
LSB
D0
MSB
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
D3
D2
D1
Register Index (or Address)
Register Data
Figure 29. Control Data Word Format for MDI
MS
MC
MDI
R/W A6 A5 A4 A3
A2 A1 A0 D7 D6 D5 D4
D3 D2 D1 D0
D3 D2 D1 D0
ZEROL
D7 D6 D5 D4
When Read Mode Is Instructed
NOTE: B15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14–8 are used for register
address. Bits 7–0 are used for register data.
Figure 30. Serial Control Format
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t
(MHH)
MS
1.4 V
t
t
(MCL)
(MSS)
t
t
(MSH)
(MCH)
MC
1.4 V
1.4 V
t
(MCY)
LSB
MDI
t
t
(MOS)
(MDS)
t
(MDH)
ZEROL
50% of V
DD
PARAMETER
MIN
100
40
MAX UNITS
t
MC pulse cycle time
MC low-level time
MC high-level time
MS high-level time
ns
ns
ns
ns
ns
ns
ns
ns
(MCY)
t
(MCL)
t
40
(MCH)
t
80
(MHH)
t
MS falling edge to MC rising edge
(1)
15
(MSS)
t
MS hold time
15
(MSH)
t
MDI hold time
15
(MDH)
t
MDI setup time
15
(MDS)
t
MC falling edge to ZEROL stable
30
ns
(MOS)
(1)
MC rising edge for LSB to MS rising edge
Figure 31. Control Interface Timing
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The DSD1791 includes a number of user-programmable functions which are accessed via mode control registers.
The registers are programmed using the serial control interface, which was previously discussed in this data sheet.
Table 3 lists the available mode-control functions, along with their default reset conditions and associated register
index.
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Table 3. User-Programmable Function Controls
DF
BYPASS
FUNCTION
Digital attenuation control
DEFAULT
REGISTER
BIT
PCM
DSD
0 dB
Attenuation disabled
Register 16 ATL[7:0] (for L-ch)
Register 17 ATR[7:0] (for R-ch)
yes
0 dB to –120 dB and mute, 0.5 dB/step
Attenuation load control
Disabled, enabled
Register 18 ATLD
yes
yes
2
Input audio data format selection
24-bit I S format
Register 18 FMT[2:0]
yes
16-, 20-, 24-bit standard (right-justified) format
24-bit MSB-first left-justified format
2
16-/24-bit I S format
(1)
yes
Sampling rate selection for de-emphasis
Disabled, 44.1 kHz, 48 kHz, 32 kHz
De-emphasis disabled
De-emphasis disabled
Mute disabled
Register 18 DMF[1:0]
Register 18 DME
Register 18 MUTE
Register 19 REV
yes
yes
yes
yes
yes
yes
yes
De-emphasis control
Disabled, enabled
Soft mute control
Mute disabled, enabled
Output phase reversal
Normal, reverse
Normal
yes
yes
Attenuation speed selection
×1 f
Register 19 ATS[1:0]
S
×1 f , ×(1/2)f , ×(1/4)f , ×(1/8)f
S
S
S
S
DAC operation control
Enabled, disabled
DAC operation enabled Register 19 OPE
yes
yes
yes
yes
yes
MDO output enable
Enabled, disabled
Disabled
Register 19 MDOE
Register 19 DFMS
Register 19 FLT
Stereo DF bypass mode select
Monaural, stereo
Monaural
Sharp rolloff
Disabled
Digital filter rolloff selection
Sharp rolloff, slow rolloff
yes
yes
yes
yes
yes
yes
yes
yes
yes
Infinite zero mute control
Disabled, enabled
Register 19 INZD
Register 20 SRST
Register 20 DSD
Register 20 DFTH
Register 20 MONO
Register 20 CHSL
Register 20 OS[1:0]
Register 21 PCMZ
Register 21 DZ[1:0]
yes
yes
System reset control
Reset operation, normal operation
Normal operation
Disabled
yes
yes
DSD interface mode control
DSD enabled, disabled
Digital-filter bypass control
DF enabled, DF bypassed
DF enabled
Stereo
yes
yes
yes
yes
yes
Monaural mode selection
Stereo, monaural
yes
yes
Channel selection for monaural mode data
L-channel, R-channel
L-channel
(2)
yes
Delta-sigma oversampling rate selection
×64 f
S
×64 f , ×128 f , ×32 f
S
S
S
PCM zero output enable
Enabled, disabled
Enabled
Disabled
DSD zero output enable
Enabled, disabled
yes
Function Available Only for Read
Zero detection flag
Not zero, zero detected
Not zero = 0
Zero detected = 1
Register 22 ZFGL (for L-ch)
ZFGR (for R-ch)
yes
yes
yes
yes
yes
Device ID (at TDMCA)
–
Register 23 ID[4:0]
(1)
(2)
When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection.
When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.
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Register Map
The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether
a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.
Table 4. Mode Control Register Map
B15
Register 16 R/W
Register 17 R/W
Register 18 R/W
Register 19 R/W
Register 20 R/W
Register 21 R/W
B14 B13
B12
1
B11
0
B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ATL7 ATL6 ATL5 ATL4
ATL3
ATL2
ATL1
ATL0
1
0
ATR7 ATR6 ATR5 ATR4 ATR3
ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE
ATR2 ATR1 ATR0
1
0
1
0
REV ATS1 ATS0 OPE MDOE DFMS
RSV SRST DSD DFTH MONO CHSL
FLT
OS1
DZ0
INZD
OS0
1
0
1
0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
ID4
RSV
RSV
ID3
DZ1
RSV
ID2
PCMZ
Register 22
Register 23
R
R
1
0
ZFGR ZFGL
ID1 ID0
1
0
Register Definitions
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
0
1
0
0
0
0
ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
Register 17 R/W
0
0
1
0
0
0
1
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
R/W: Read/Write Mode Select
When R/W = 0, a write operaton is performed.
When R/W = 1, a read operaton is performed.
Default value: 0
ATx[7:0]: Digital Attenuation Level Setting
These bits are available for read and write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB
steps. Alternatively, the attenuator can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control
register 18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The
attenuation level can be set using the following formula:
Attenuation level (dB) = 0.5 dB • (ATx[7:0]
– 255)
DEC
where ATx[7:0]
= 0 through 255
DEC
For ATx[7:0]
levels for various settings:
= 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation
DEC
ATx[7:0]
1111 1111b
1111 1110b
1111 1101b
L
Decimal Value
Attenuation Level Setting
255
254
253
L
0 dB, no attenuation (default)
–0.5 dB
–1.0 dB
L
0001 0000b
0000 1111b
0000 1110b
L
16
15
14
L
–119.5 dB
–120.0 dB
Mute
L
0000 0000b
0
Mute
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B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 18
R/W
0
0
1
0
0
1
0
ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE
R/W: Read/Write Mode Select
When R/W = 0, a write operaton is performed.
When R/W = 1, a read operaton is performed.
Default value: 0
ATLD: Attenuation Load Control
This bit is available for read and write.
Default value: 0
ATLD = 0
ATLD = 1
Attenuation control disabled (default)
Attenuation control enabled
The ATLD bit enables loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the
attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and
17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally.
FMT[2:0]: Audio Interface Data Format
These bits are available for read and write.
Default value: 101
FMT[2:0]
000
Audio Data Format Selection
16-bit standard format, right-justified data
20-bit standard format, right-justified data
24-bit standard format, right-justified data
24-bit MSB-first, left-justified format data
001
010
011
2
100
16-bit I S format data
2
101
24-bit I S format data (default)
110
Reserved
Reserved
111
The FMT[2:0] bits select the data format for the serial audio interface.
For the external digital filter interface mode (DFTH mode), this register is operated as shown in the APPLICATION
FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet.
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
These bits are available for read and write.
Default value: 00
DMF[1:0]
De-Emphasis Sampling Frequency Selection
00
01
10
11
Disabled (default)
48 kHz
44.1 kHz
32 kHz
The DMF[1:0] bits select the sampling frequency used by the digital de-emphasis function when it is enabled by
setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this
data sheet.
For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter
response plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data
sheet.
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DME: Digital De-Emphasis Control
This bit is available for read and write.
Default value: 0
DME = 0
DME = 1
De-emphasis disabled (default)
De-emphasis enabled
The DME bit enables or disables the de-emphasis function for both channels.
MUTE: Soft Mute Control
This bit is available for read and write.
Default value: 0
MUTE = 0
MUTE = 1
MUTE disabled (default)
MUTE enabled
The MUTE bit enables or disables the soft mute function for both channels.
Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the
attenuation rate selected in the ATS register.
B15 B14 B13 B12 B11 B10
R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 19
0
0
1
0
0
1
1
REV ATS1 ATS0 OPE MDOE DFMS FLT
INZD
R/W: Read/Write Mode Select
When R/W = 0, a write operaton is performed.
When R/W = 1, a read operaton is performed.
Default value: 0
REV: Output Phase Reversal
This bit is available for read and write.
Default value: 0
REV = 0
REV = 1
Normal output (default)
Inverted output
The REV bit inverts the output phase for both channels.
ATS[1:0]: Attenuation Rate Select
These bits are available for read and write.
Default value: 00
ATS[1:0]
Attenuation Rate Selection
Every PLRCK (default)
PLRCK/2
00
01
10
11
PLRCK/4
PLRCK/8
The ATS[1:0] bits select the rate at which the attenuator is decremented/incremented during level transitions.
OPE: DAC Operation Control
This bit is available for read and write.
Default value: 0
OPE = 0
OPE = 1
DAC operation enabled (default)
DAC operation disabled
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The OPE bit enables or disables the analog output for both channels. Disabling the analog outputs forces them to
the bipolar zero level (BPZ) even if digital audio data is present on the input.
MDOE: MDO Output Control
This bit is available for read and write.
Default value: 0
MDOE = 0
MDOE = 1
MDO output disabled (default)
MDO output enabled
The MDOE bit enables or disables the serial mode data output. The serial mode data is output from ZEROL (pin 23).
DFMS: Stereo DF Bypass Mode Select
This bit is available for read and write.
Default value: 0
DFMS = 0
DFMS = 1
Monaural (default)
Stereo input enabled
The DFMS bit enables stereo operation in DF bypass mode. In DF bypass mode, when DFMS is set to 0, the pin
for the input data is PDATA (pin 3) only; therefore, the DSD1791 operates as a monaural DAC. When DFMS is set
to 1, the DSD1791 can operate as a stereo DAC with inputs of L-channel and R-channel data on DSDL (pin 25) and
DSDR (pin 24), respectively.
FLT: Digital Filter Rolloff Control
This bit is available for read and write.
Default value: 0
FLT = 0
FLT = 1
Sharp rolloff (default)
Slow rolloff
The FLT bit selects the digital filter rolloff characteristic. The filter responses for these selections are shown in the
TYPICAL PERFORMANCE CURVES section of this data sheet.
INZD: Infinite Zero Detect Mute Control
This bit is available for read and write.
Default value: 0
INZD = 0
INZD = 1
Infinite zero detect mute disabled (default)
Infinite zero detect mute enabled
The INZD bit enables or disables the zero detect mute function. Setting INZD to 1 forces muted analog outputs to
hold a bipolar zero level when the DSD1791 detects a zero condition in both channels. The infinite zero detect mute
function is not available in the DSD mode.
B15 B14 B13 B12 B11 B10
R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 20
0
0
1
0
1
0
0
RSV SRST DSD DFTH MONO CHSL OS1
OS0
R/W: Read/Write Mode Select
When R/W = 0, a write operaton is performed.
When R/W = 1, a read operaton is performed.
Default value: 0
SRST: System Reset Control
This bit is available for write only.
Default value: 0
SRST = 0
SRST = 1
Normal operation (default)
System reset operation (generate one reset pulse)
The SRST bit resets the DSD1791 to the initial system condition.
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DSD: DSD Interface Mode Control
This bit is available for read and write.
Default value: 0
DSD = 0
DSD = 1
DSD interface mode disabled (default)
DSD interface mode enabled
The DSD bit enables or disables the DSD interface mode.
DFTH: Digital Filter Bypass (or Through Mode) Control
This bit is available for read and write.
Default value: 0
DFTH = 0
DFTH = 1
Digital filter enabled (default)
Digital filter bypassed for the external digital filter
The DFTH bit enables or disables the external digital filter interface mode.
MONO: Monaural Mode Selection
This bit is available for read and write.
Default value: 0
MONO = 0
MONO = 1
Stereo mode (default)
Monaural mode
The MONO function changes the operation mode from the normal stereo mode to the monaural mode. When the
monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel
selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately
following.
CHSL: Channel Selection for Monaural Mode
This bit is available for read and write.
Default value: 0
CHSL = 0
CHSL = 1
L-channel selected (default)
R-channel selected
This bit is available when MONO = 1.
The CHSL bit selects L-channel or R-channel data to be used in monaural mode.
OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
OS[1:0]
00
Operation Speed Select
64 times f (default)
S
01
32 times f
S
10
128 times f
Reserved
S
11
The OS bits change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to
stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 f oversampling rate is not
S
available at sampling rates above 100 kHz. If the 128-f oversampling rate is selected, a system clock of more than
S
256 f is required.
S
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In DSD mode, these bits select the speed of the bit clock for DSD data coming into the analog FIR filter.
B15 B14 B13 B12 B11 B10
Register 21 R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0 PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operaton is performed.
When R/W = 1, a read operaton is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
DZ[1:0]
00
Zero Output Enable
Disabled (default)
01
Even pattern detect
1x
96 pattern detect
H
The DZ bits enable or disable the output zero flags, and select the zero pattern in the DSD mode.
PCMZ: PCM Zero Output Enable
This bit is available for read and write.
Default value: 1
PCMZ = 0
PCMZ = 1
PCM zero output disabled
PCM zero output enabled (default)
The PCMZ bit enables or disables the output zero flags in the PCM mode and the external DF mode.
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV ZFGR ZFGL
R: Read Mode Select
Value is always 1, specifying the readback mode.
ZFGx: Zero-Detection Flag
where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx = 0
ZFGx = 1
Not zero
Zero detected
These bits show zero conditions. Their status is the same as that of the zero flags at ZEROL (pin 23) and ZEROR
(pin 22). See Zero Detect in the FUNCTIONAL DESCRIPTIONS section.
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 23
R
0
0
1
0
1
1
1
RSV
RSV
RSV
ID4
ID3
ID2
ID1
ID0
R: Read Mode Select
Value is always 1, specifying the readback mode.
ID[4:0]: Device ID
The ID[4:0] bits hold a device ID in the TDMCA mode.
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TYPICAL CONNECTION DIAGRAM
PCM Decoder
L/R Clock (f )
S
PLRCK
PBCK
PDATA
DBCK
SCK
MS
MC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Bit Clock
Audio Data
MDI
3
Controller
DSDL
DSDR
ZEROL
ZEROR
4
System Clock
5
RST
6
V
DD
7
3.3 V
+
DSD1791
DSD Decoder
DGND
V
V
F
L
8
CC
AGNDF
9
CC
Rch Data
Lch Data
V R
CC
AGNDL
L–
10
11
12
13
14
Analog
Output Stage
(See Figure 33)
Analog
Output Stage
(See Figure 33)
AGNDR
V
OUT
Bit Clock
V
V
V
R–
V
L+
OUT
OUT
AGNDC
R+
OUT
V
C
CC
COM
Figure 32. Typical Application Circuit
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APPLICATION INFORMATION
ANALOG OUTPUTS
PLRCK
MS
MC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PBCK
PDATA
DBCK
SCK
MDI
3
DSDL
DSDR
ZEROL
ZEROR
4
5
RST
6
V
DD
7
DSD1791
DGND
V
V
F
L
8
0.1 µF
CC
5 V
+
AGNDF
9
CC
10 µF
R L
R L
4
V R
CC
AGNDL
10
11
12
13
14
R L
6
2
C L
3
AGNDR
V
L–
L+
OUT
C L
1
V
V
V
R–
V
OUT
OUT
–
+
V
OUT
L-Channel
R L
1
R L
5
AGNDC
R+
OUT
V
C
CC
C L
2
COM
R L
3
+
1 µF
R R
4
R R
2
R R
6
C R
3
C R
1
–
+
V
OUT
R-Channel
R R
1
R R
5
C R
2
R R
3
NOTE: Example R and C values for f = 77 kHz – R , R : 1.8 kΩ, R ,R : 3.3 kΩ, R ,R : 680 Ω, C : 1800 pF, C , C : 560 pF.
C
1
2
3
4
5
6
1
2
3
Figure 33. Typical Application for Analog Output Stage
Analog Output Level and LPF
The signal level of the DAC differential-voltage output {(V
L+)–(V
L–), (V
R+)–(V
R–)} is 3.2 Vp-p
OUT
OUT
OUT
OUT
at 0 dB (full scale). The voltage output of the LPF is given by following equation:
V
= 3.2 Vp-p × (R /R )
OUT
f
i
Here, R is the feedback resistor in the LPF, and R = R in a typical application circuit. R is the input resistor
f
3
4
i
in the LPF, and R = R in a typical application circuit.
1
2
Operational Amplifier for LPF
An OPA2134 or 5532 type operational amplifier is recommended for the LPF circuit to obtain the specified audio
performance. Dynamic performance such as gain bandwidth, settling time, and slew rate of the operational
amplifier largely determines the audio dynamic performance of the LPF section. The input noise specification
of the operational amplifier should be considered to obtain a 113-dB S/N ratio.
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Analog Gain of Balanced Amplifier
The DAC voltage outputs are followed by balanced amplifier stages, which sum the differential signals for each
channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a third-order
low-pass filter function, which band limits the audio output signal. The cutoff frequency and gain are determined
by external R and C component values. In this case, the cutoff frequency is 77 kHz with a gain of 1.83. The
output voltage for each channel is 5.9 Vp-p, or 2.1 V rms.
Application for Monaural-Mode Operation
A single-channel signal from the stereo audio data input is output from both V
L and V
R as a differential
OUT
OUT
output. The channel to be output is selected by setting the CHSL bit in register 20. The advantage of monaural
operation is to provide over 115 dB of dynamic range for high-end audio applications.
L/R Clock
Bit Clock
Analog
V
OUT
L-Channel
Output
Stage
System Clock
Audio Data
DSD1791
Controller
Analog
Output
Stage
V
OUT
R-Channel
DSD1791
Analog Output Stage
R
6
R
R
2
V
L–
OUT
18
17
C
3
R
R
4
8
V L+
OUT
DSD1791
C
1
–
+
R
R
1
7
V
R+
R–
13
12
OUT
3
R
5
C
2
V
OUT
NOTE: Example R and C values for f = 77 kHz, R1–R4: 3.6 kΩ, R5, R6: 3.3 kΩ, R7, R8: 680 Ω, C1: 1800 pF, C2, C3: 560 pF.
C
Figure 34. Connection Diagram for Monaural Mode Interface
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APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DFMS = 0
WDCK (Word Clock)
PLRCK
PBCK
PDATA
DBCK
SCK
1
2
3
4
5
MS
MC
28
27
26
25
24
BCK
DATA
MDI
DSDL
DSDR
SCK
External Filter Device
DSD1791
DFMS = 1
WDCK (Word Clock)
BCK
PLRCK
PBCK
PDATA
DBCK
SCK
MS
MC
1
28
2
3
4
5
27
26
25
24
MDI
DSDL
DSDR
SCK
DSD1791
DATA_L
DATA_R
External Filter Device
Figure 35. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
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Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it
can provide improved stop-band attenuation when compared to the internal digital filter of the DSD1791.
The DSD1791 supports several external digital filters, including:
D Texas Instruments DF1704 and DF1706
D Pacific Microsonics PMD200 HDCD filter/decoder IC
D Programmable digital signal processors
The external digital filter application mode is accessed by programming the following bit in the corresponding control
register:
D DFTH = 1 (register 20)
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 35. The word clock (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, f .
S
Pin Assignments When Using the External Digital Filter Interface
D PLRCK (pin 1): WDCK as word clock input
D PBCK (pin 2): BCK as bit clock for audio data
D PDATA (pin 3): DATA as monaural audio data input when the DFMS bit is not set to 1
D DSDL (pin 25): DATAL as L-channel audio data input when the DFMS bit is set to 1
D DSDR (pin 26): DATAR as R-channel audio data input when the DFMS bit is set to 1
Audio Format
The DSD1791 in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit,
and 24-bit audio data, as shown in Figure 36. The audio format is selected by the FMT[2:0] bits of control register
18.
1/4 f or 1/8 f
S
S
WDCK
BCK
Audio Data Word = 16-Bit
DATA
15 16
1
2
3
4
8
5
9
6
7
8
9
10 11 12 13 14 15 16
LSB
DATAL
DATAR
MSB
Audio Data Word = 20-Bit
DATA
19 20
1
5
2
6
3
4
8
5
9
6
7
10 11 12 13 14 15 16 17 18 19 20
LSB
DATAL
DATAR
MSB
Audio Data Word = 24-Bit
DATA
23 24
1
2
3
4
7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LSB
DATAL
DATAR
MSB
Figure 36. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
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System Clock (SCK) and Interface Timing
The DSD1791 in an application using an external digital filter requires the synchronization of WDCK and the system
clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, DATA, DATAL,
and DATAR is shown in Figure 37.
WDCK
1.4 V
1.4 V
1.4 V
t
t
t
(LB)
(BCH)
(BCL)
BCK
t
t
(BCY)
(BL)
DATA
DATAL
DATAR
t
t
(DS)
(DH)
PARAMETER
MIN
20
7
MAX UNITS
t
t
t
t
t
t
t
BCK pulse cycle time
ns
ns
ns
ns
ns
ns
ns
(BCY)
(BCL)
(BCH)
(BL)
BCK pulse duration, LOW
BCK pulse duration, HIGH
7
BCK rising edge to WDCK falling edge
WDCK falling edge to BCK rising edge
DATA, DATAL, DATAR setup time
DATA, DATAL, DATAR hold time
5
5
(LB)
5
(DS)
5
(DH)
Figure 37. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
Functions Available in the External Digital Filter Mode
The external digital filter mode allows access to the majority of the DSD1791 mode control functions.
The following table shows the register mapping available when the external digital filter mode is selected, along with
descriptions of functions which are modified when using this mode selection.
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
–
B5
–
B4
–
B3
–
B2
–
B1
–
B0
–
Register 16 R/W
Register 17 R/W
Register 18 R/W
Register 19 R/W
Register 20 R/W
Register 21 R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
–
–
0
1
–
–
–
–
–
–
–
1
0
–
FMT2 FMT1 FMT0
–
–
–
–
1
1
REV
–
–
SRST
–
–
0
–
–
OPE MDOE DFMS
–
INZD
OS0
PCMZ
0
0
1
–
–
MONO CHSL OS1
0
1
–
–
–
–
–
–
Register 22
R
1
0
–
–
ZFGR ZFGL
NOTE: –: Function is disabled. No operation even if data bit is set
FMT[2:0]: Audio Data Format Selection
Default value: 000
FMT[2:0]
000
Audio Data Format Select
16-bit right-justified format (default)
20-bit right-justified format
24-bit right-justified format
N/A
001
010
Other
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OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
00
Operation Speed Select
8 times WDCK (default)
4 times WDCK
01
10
16 times WDCK
11
Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter and
the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×.
The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected
is 16× WDCK, the system clock frequency must be over 256 f .
S
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
PLRCK
PBCK
PDATA
DBCK
SCK
MS
MC
1
2
3
4
5
28
27
26
25
24
MDI
Bit Clock
DSDL
DSDR
1
System Clock
DATA_L
DATA_R
DSD Decoder
DSD1791
(1)
The system clock can be removed after the register setting to the DSD mode.
Figure 38. Connection Diagram in DSD Mode
Feature
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD) applications.
The DSD mode is available by programming the following bit in the corresponding control register:
D DSD = 1 (register 20)
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter structure.
Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
Pin Assignment When Using the DSD Format Interface
D DSDL (pin 25): L-channel DSD data input
D DSDR (pin 24): R-channel DSD data input
D DBCK (pin 4): Bit clock (BCK) for DSD data
Requirements for System Clock
The bit clock (DBCK) for the DSD mode is required at pin 4 of the DSD1791. The frequency of the bit clock may be
N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DSDL and DSDR is required to meet the setup and hold time
specifications shown in Figure 40.
The SCK is not necessary after the mode change to the DSD mode is done.
t = 1/(64 × 44.1 kHz)
DBCK
DSDL
D0
D1
D2
D3
D4
DSDR
Figure 39. Normal Data Output Form From DSD Decoder
t
t
(BCL)
(BCH)
1.4 V
1.4 V
DBCK
t
(BCY)
DSDL
DSDR
t
t
(DH)
(DS)
PARAMETER
MIN
MAX UNITS
(1)
t
DBCK pulse cycle time
DBCK high-level time
DBCK low-level time
85
ns
ns
ns
ns
ns
(BCY)
t
30
30
10
10
(BCH)
t
(BCL)
(DS)
(DH)
t
t
DSDL, DSDR setup time
DSDL, DSDR hold time
(1)
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified as a
sampling rate of DSD.)
Figure 40. Timing for DSD Audio Interface
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 185 kHz
c
(1)
Gain = –6.6 dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 41. DSD Filter-1, Low BW
Figure 42. DSD Filter-1, High BW
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 77 kHz
c
(1)
Gain = –6dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 43. DSD Filter-2, Low BW
Figure 44. DSD Filter-2, High BW
(1)
This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f ), and 50% modulation DSD data input, unless otherwise noted.
S
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED)
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 85 kHz
c
(1)
Gain = –1.5 dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 45. DSD Filter-3, Low BW
Figure 46. DSD Filter-3, High BW
GAIN
vs
GAIN
vs
FREQUENCY
FREQUENCY
0
−1
−2
−3
−4
−5
−6
0
−10
−20
−30
−40
−50
−60
f
= 94 kHz
c
(1)
Gain = –3.3 dB
0
50
100
150
200
0
500
1000
1500
f – Frequency – kHz
f – Frequency – kHz
Figure 47. DSD Filter-4, Low BW
Figure 48. DSD Filter-4, High BW
(1)
This gain is in comparison to PCM 0 dB, when the DSD input signal efficiency is 50%.
All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 f ), and 50% modulation DSD data input, unless otherwise noted.
S
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DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
DSD = 1 (Register 20, B5)
B15 B14 B13 B12 B11 B10
B9
0
B8
0
B7
B6
B5
–
B4
–
B3
–
B2
–
B1
–
B0
–
Register 16 R/W
Register 17 R/W
Register 18 R/W
Register 19 R/W
Register 20 R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
–
–
–
0
1
–
–
–
–
–
–
–
1
0
–
–
–
–
DMF1 DMF0
–
–
1
1
REV
–
–
SRST
–
–
OPE MDOE
–
–
–
0
0
1
–
–
–
MONO CHSL OS1
OS0
–
Register 21
Register 22
R
R
0
1
–
–
–
–
DZ1
–
DZ0
1
0
–
–
–
ZFGR ZFGL
NOTE: –: Function is disabled. No operation even if data bit is set
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0]
Analog FIR Performance Select
00
01
10
11
FIR-1 (default)
FIR-2
FIR-3
FIR-4
Plots for the four analog FIR filter responses are shown in the ANALOG FIR FILTER PERFORMANCE IN DSD
MODE section of this data sheet.
OS[1:0]: Analog FIR Operation Speed Selection
Default value: 00
OS[1:0]
00
Operation Speed Select
f
f
(default)
DBCK
DBCK
01
/2
10
Reserved
f /4
DBCK
11
The OS bits in the DSD mode select the operating rate of the analog FIR. The OS bits must be set before setting
the DSD bit to 1.
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TDMCA INTERFACE FORMAT
The DSD1791 supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host
control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any
programmable devices. The TDMCA format can transfer not only audio data but also command data, so that it can
be used together with any kind of device that supports the TDMCA format. The TDMCA frame consists of a command
field, extended command field, and some audio data fields. Those audio data are transported to IN devices (such
as a DAC) and/or from OUT devices (such as an ADC). The DSD1791 is an IN device. LRCK and BCK are used
with both IN and OUT devices so that the sample frequency of all devices in a system must be the same. The TDMCA
mode supports a maximum of 30 device IDs. The maximum number of audio channels depends on the BCK
frequency.
TDMCA Mode Determination
The DSD1791 recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration
of two BCK clocks. If TDMCA-mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 49 shows
the LRCK and BCK timing that determines the TDMCA mode. The DSD1791 enters the TDMCA mode after two
continuous TDMCA frames. Any TDMCA commands can be issued during the next TDMCA frame after the TDMCA
mode is entered.
Command
Accept
Pre-TDMCA Frame
TDMCA Frame
LRCK
2 BCK
BCK
Figure 49. LRCK and BCK Timing for Determination of TDMCA Mode
TDMCA Terminals
TDMCA requires six signals, four of which are for command and audio data interface, and one pair of signals which
are for daisy chaining. Those signals can be shared as in the following table. The DO signal has a 3-state output so
that it can be connected directly to other devices.
TERMINAL TDMCA
I/O
DESCRIPTION
NAME
PLRCK
PBCK
PDATA
MDI
NAME
LRCK
BCK
DI
input
input
input
TDMCA frame start signal. It must be the same as the sampling frequency.
TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK cycle.
TDMCA command and audio data input signal
DO
output TDMCA command data 3-state output signal
input TDMCA daisy-chain input signal
output TDMCA daisy-chain output signal
MC
DCI
MS
DCO
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Device ID Determination
The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can
simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM
devices. The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device. The IN device
has an input port to receive audio data, the OUT device has an output port to supply audio data, the IN/OUT device
has both input and output ports for audio data, and the NO device has no port for audio data but needs command
data from the host. A DAC is an IN device, an ADC is an OUT device, a codec is an IN/OUT device, and a PLL is
a NO device. The DSD1791 is an IN device. For the host controller to distinguish the devices, each device is assigned
its own device ID by the daisy chain. The devices obtain their own device IDs automatically by connecting their DCI
to the DCO of the preceding device and their DCO to the DCI of the following device in the daisy chain. The daisy
chains are categorized as the IN chain and the OUT chain, which are completely independent and equivalent.
Figure 50 shows an example daisy chain connection. If a system needs to chain the DSD1791 and a NO device in
the same IN or OUT chain, the NO device must be chained at the back end of the chain because it does not require
any audio data. Figure 51 shows an example of TDMCA system including an IN chain and an OUT chain with a TI
DSP. For a device to get its own device ID, the DID signal must be set to 1 (see the Command Field section for details),
and LRCK and BCK must be driven in the TDMCA mode for all PCM devices which are chained. The device at the
top of the chain knows its device ID is 1 because its DCI is fixed HIGH. Other devices count the BCK pulses and
observe their own DCI signal to determine their position and ID. Figure 52 shows the initialization of each device ID.
IN Chain
• • •
• • •
• • •
• • •
IN
IN
IN Device
IN Device
NO Device
NO Device
NO Device
NO Device
IN/OUT
Device
IN/OUT
Device
• • •
OUT Device
OUT Device
OUT
OUT
OUT Chain
Figure 50. Daisy Chain Connection
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DCII
LRCK
BCK
DI
IN/OUT
Device
(DIX1700)
DCOI
DCIO
DO
DCOO
Device ID = 1
LRCK
BCK
DI
DCI
IN Device
(DSD1791)
DCO
DO
Device ID = 2
LRCK
BCK
DI
DCI
NO Device
DCO
DO
Device ID = 3
•
•
•
FSX
FSR
CLKX
CLKR
LRCK
BCK
DI
DCI
OUT Device
DX
DCO
DR
DO
Device ID = 2
TI DSP
LRCK
BCK
DI
DCI
OUT Device
DCO
DO
Device ID = 3
•
•
•
Figure 51. IN Daisy Chain and OUT Daisy Chain Connection for a Multichip System
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SLES072B − MARCH 2003 − REVISED NOVEMBER 2006
LRCK
BCK
DID
Command Field
DI
Device ID = 1
Device ID = 2
DCO1
DCO1
DCI2
Device ID = 3
DCO2
DCI3
•
•
•
•
•
•
58 BCK
Device ID = 30 DCO29
DCI30
Figure 52. Device ID Determination Sequence
TDMCA Frame
In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields.
All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field. The
command field is always transferred as the first packet of the frame. The EMD field is transferred if the EMD flag of
the command field is HIGH. If any EMD packets are transferred, no audio data follows the EMD packets. This frame
is for quick system initialization. All devices of a daisy chain should respond to the command field and extended
command field. The DSD1791 has two audio channels that can be selected by OPE (register 19). If this OPE bit is
not set to HIGH, those audio channels are transferred. Figure 53 shows the general TDMCA frame. If some DACs
are enabled, but corresponding audio data packets are not transferred, the analog outputs are unpredictable.
1/f
S
LRCK
BCK
[For Initialization]
Don’t
Care
DI
EMD
CMD
CMD
EMD
EMD
CMD
EMD
EMD
32 Bits
DO
CMD
CMD
CMD
CMD
CMD
CMD
[For Operation]
Don’t
Care
Ch(n)
Ch2
Ch2
Ch4
Ch4
CMD
Ch1
Ch1
Ch3
Ch3
DI
DO
CMD
Ch(m)
Figure 53. General TDMCA Frame
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1/f (256 BCK Clocks)
S
7 Packets × 32 Bits
LRCK
BCK
Don’t
Care
DI
CMD
Ch2
IN and OUT Channel Orders are Completely Independent
Ch1 Ch2
Ch4
Ch5
Ch6
Ch1
CMD
Ch3
DO
CMD
Figure 54. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read
Command Field
The normal command field is defined as follows. When the DID bit (MSB) is 1, this frame is used only for device ID
determination, and all remaining bits in the field are ignored.
31
30
29
28
24
23
22
16 15
8
7
0
command
DID EMD DCS
device ID
R/W
register ID
data
not used
Bit 31: Device ID Enable Flag
The DSD1791 operates to get its own device ID for TDMCA initialization if this bit is HIGH.
Bit 30: Extended Command Enable Flag
An EMD packet is transferred if this bit is HIGH, otherwise skipped. Once it is HIGH, this frame does not contain any
audio data. This is for system initialization.
Bit 29: Daisy Chain Selection Flag
HIGH designates OUT-chain devices, LOW designates IN-chain devices. The DSD1791 is an IN device, so the DCS
bit must be set to LOW.
Bits[28:24]: Device ID
The device ID is 5 bits length, and it can be defined. These bits identify the order of a device in the IN or OUT daisy
chain. The top of the daisy chain defines device ID 1 and successive devices are numbered 2, 3, 4, etc. All devices
for which the DCI is fixed HIGH are also defined as ID 1. The maximum device ID is 30 each in the IN and OUT chains.
If a device ID of 0x1F is used, all devices are selected as broadcast when in the write mode. If a device ID of 0x00
is used, no device is selected.
Bit 23: Command Read/Write Flag
If this bit is HIGH, the command is a read operation.
Bits[22:16]: Register ID
It is 7 bits in length.
Bits[15:8]: Command Data
It is 8 bits in length. Any valid data can be chosen for each register.
Bits[7:0]: Not Used
These bits are never transported when a read operation is performed.
Extended Command Field
The extended command field is the same as the command field, except that it does not have a DID flag.
31
30
29
28
24
23
22
16 15
8
7
0
extended command rsvd EMD DCS
device ID
R/W
register ID
data
not used
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Audio Fields
The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with
0s as shown in the following example.
31
16
12
8
7
4 3
0
audio data MSB
24 bits
LSB
All 0s
TDMCA Register Requirements
TDMCA mode requires device ID and audio channel information, previously described. The OPE bit in register 19
indicates audio channel availability and register 23 indicates the device ID. Register 23 is used only in the TDMCA
mode. See the mode control register map (Table 4).
Register Write/Read Operation
The command supports register write and read operations. If the command requests to read one register, the read
data is transferred on DO during the data phase of the timing cycle. The DI signal can be retrieved at the positive
edge of BCK, and the DO signal is driven at the negative edge of BCK. DO is activated one BCK cycle early to
compensate for the output delay caused by high impedance. Figure 55 shows the TDMCA write and read timing.
Register ID Phase
Data Phase
BCK
Read Mode and Proper Register ID
Write Data Retrieved, if Write Mode
DI
Read Data Driven, if Read Mode
1 BCK Early
DO
DOEN
(Internal)
Figure 55. TDMCA Write and Read Operation Timing
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TDMCA-Mode Operation
DCO specifies the owner of the next audio channel in TDMCA-mode operation. When a device retrieves its own audio
channel data, DCO goes HIGH during the last audio channel period. Figure 56 shows the DCO output timing in
TDMCA-mode operation. The host controller ignores the behavior of DCI and DCO. DCO indicates the last audio
channel of each device. Therefore, DCI means the next audio channel is allocated.
1/f (384 BCK Clocks)
S
9 Packets × 32 Bits
LRCK
BCK
IN Daisy Chain
Ch2 Ch3 Ch4 Ch5
CMD Ch1
Ch6 Ch7 Ch8
Don’t Care
CMD
DI
DCI1
DID = 1
DID = 2
DCO1
DCI2
DCO2
DCI3
DID = 3
DID = 4
DCO3
DCI4
DCO4
Figure 56. DCO Output Timing for TDMCA Mode Operation
If some devices are skipped due to no active audio channel, the skipped devices must notify the next device that the
DCO is being passed through the next DCI. Figure 57 and Figure 58 show DCO timing with skip operation. Figure 59
shows the ac timing of the daisy chain signals.
1/f (256 BCK Clocks)
S
5 Packets × 32 Bits
LRCK
BCK
DI
CMD
Ch1
Ch2
Ch15
Ch16
Don’t Care
CMD
DCI
DID = 1
DID = 2
DCO
DCI
2 BCK Delay
14 BCK Delay
•
•
•
DCO
•
•
•
•
•
•
DCI
DID = 8
DCO
Figure 57. DCO Output Timing With Skip Operation
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Command Packet
LRCK
BCK
DI
DID EMD
DCO1
DCO2
•
•
•
Figure 58. DCO Output Timing With Skip Operation (for Command Packet 1)
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LRCK
t
t
(BL)
(LB)
BCK
t
t
t
(DH)
(BCY)
(DS)
DI
t
(DOE)
DO
t
t
(DH)
(DS)
DCI
DCO
t
(COE)
PARAMETER
MIN MAX UNITS
t
BCK pulse cycle time
LRCK setup time
LRCK hold time
DI setup time
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
(BCY)
t
t
t
t
t
t
(LB)
(BL)
(DS)
(DH)
(DS)
(DH)
3
0
DI hold time
3
DCI setup time
DCI hold time
0
3
(1)
DO output delay
t
8
6
(DOE)
(1)
DCO output delay
t
(COE)
(1)
Load capacitance is 10 pF.
Figure 59. AC Timing of Daisy Chain Signals
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THEORY OF OPERATION
0–62
Level
Upper 6 Bit
ICOB
Decoder
0–66
Current
Segment
DAC
Analog
Voltage
Output
Digital
Input
24 Bit
Advanced
DWA
I/V
Converter
rd
3 -Order
8 f
S
5-Level
Sigma-Delta
0–4
MSB and
Level
Lower 18 Bit
Figure 60. Advanced Segment DAC With I/V Converter
The DSD1791 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and
improved tolerance to clock jitter. The DSD1791 provides balanced voltage outputs.
Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted
to inverted complementary offset binary (ICOB) code. The lower 18 bits, in association with the MSB, are processed
by a five-level third-order delta-sigma modulator operated at 64 f by default. The 1 level of the modulator is equivalent
S
to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order
delta-sigma modulator are summed together to an up to 66-level digital code, and then processed by data-weighted
averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is
converted to an analog output in the differential-current segment section.
This architecture has overcome the various drawbacks of conventional multibit processing and also achieves
excellent dynamic performance.
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CONSIDERATIONS FOR APPLICATION CIRCUITS
PCB Layout Guidelines
A typical PCB floor plan for the DSD1791 is shown in Figure 61. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a split or cut in the circuit board. The DSD1791 must be
oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital
audio interface and control signals originating from the digital section of the board. Separate power supplies are
recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital
supply from contaminating the analog power supply and degrading the dynamic performance of the D/A converters.
In cases where a common 5 V supply would be used for the analog and digital sections, an inductance (RF choke,
ferrite bead) must be placed between the analog and digital 5-V supply connections to avoid coupling of the digital
switching noise into the analog circuitry. Figure 62 shows the recommended approach for single-supply applications.
Digital Power
+V DGND
Analog Power
AGND +5VA
+V
S
–V
S
D
REG
V
CC
Digital Logic
and
Audio
Processor
V
DD
DGND
Output
Circuits
DSD1791
AGND
Digital
Ground
Analog
Ground
Digital Section
Analog Section
Return Path for Digital Signals
Figure 61. Recommended PCB Layout
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Power Supplies
+5V AGND +V
RF Choke or Ferrite Bead
–V
S
S
REG
V
CC
V
DD
V
DD
DGND
Output
Circuits
DSD1791
AGND
Common
Ground
Digital Section
Analog Section
Figure 62. Single-Supply PCB Layout
Bypass and Decoupling Capacitor Requirements
Various-sized decoupling capacitors can be used, with no special tolerances being required. All capacitors must be
located as close as possible to the appropriate pins of the DSD1791 to reduce noise pickup from surrounding circuitry.
Aluminum electrolytic capacitors that are designed for hi-fi audio applications are recommended for larger values,
while metal film or monolithic ceramic capacitors are used for smaller values.
Post-LPF Design
By proper choice of the operational amplifier and resistors used in the post-LPF circuit, excellent performance of the
DSD1791 can be achieved. To obtain 0.001% THD+N, 113 dB signal-to-noise-ratio audio performance, the THD+N
and input noise performance of the operational amplifier should be considered. This is because the input noise of
the operational amplifier contributes directly to the output noise level of the application. The V
and the input resistor of the post-LPF circuit must be connected as closely as possible.
pin of the DSD1791
OUT
Out-of-band noise level and attenuated sampling spectrum level are much lower than for typical delta-sigma type
DACs due to the combination of a high-performance digital filter and advanced segment DAC architecture. The use
of a second-order or third-order post-LPF is recommended for the post-LPF of the DSD1791. The cutoff frequency
of the post-LPF depends on the application. For example, there are many sampling-rate operations such as
f = 44.1 kHz on CDDA, f = 96 kHz on DVD-M, f = 192 kHz on DVD-A, f = 64 f on DSD (SACD).
S
S
S
S
S
51
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
DSD1791DB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DSD1791DBG4
DSD1791DBR
DSD1791DBRG4
SSOP
SSOP
SSOP
DB
DB
DB
47 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
DSD1791DBR
SSOP
DB
28
2000
330.0
17.4
8.5
10.8
2.4
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Nov-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 28.6
DSD1791DBR
2000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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