DSLVDS1048PWR [TI]
3.3V LVDS 四通道高速差动线路接收器 | PW | 16 | -40 to 85;
| 型号： | DSLVDS1048PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V LVDS 四通道高速差动线路接收器 | PW | 16 | -40 to 85 |
| 文件： | 总25页 (文件大小：1072K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DSLVDS1048
ZHCSIV4 –SEPTEMBER 2018
DSLVDS1048 3.3V LVDS 四通道高速差动线路接收器
1 特性
EN 和 EN* 输入将接受 AND 运算并控制 TRI-STATE
1
输出。这些使能端由四个接收器共用。DSLVDS1048
和配套的 LVDS 线路驱动器（例如 DSLVDS1047）为
高速点对点接口应用提供了大功率 PECL/ECL 器件的
替代 产品。
•
•
•
•
•
•
•
•
•
•
•
旨在用于信号速率高达 400Mbps 的应用
直通引脚排列可简化 PCB 布局
150ps 通道到通道偏斜（典型值）
100ps 差动偏斜（典型值）
2.7ns 最大传播延迟
器件信息(1)
3.3V 电源设计
器件型号
封装
封装尺寸（标称值）
在断电模式下，LVDS 输入端具有高阻抗
低功耗设计（3.3V 静态条件下为 40mW）
能够与现有 5V LVDS 驱动器交互操作
接受小摆幅（350mV 典型值）差动信号电平
支持输入失效防护
DSLVDS1048
TSSOP (16)
5.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
图 1. 703A I2C
DSLVDS1048
–
开路、短路及终止失效防护
DSLVDS1047
•
•
•
•
0V 至 −100mV 阈值区域
RIN1+
RIN1-
DOUT1+
DOUT1-
工作温度范围：-40°C 至 +85°C
符合或超出 ANSI/TIA/EIA-644 标准
可采用 TSSOP 封装
DIN1
DIN2
DIN3
Driver
Driver
Driver
Receiver
Receiver
Receiver
ROUT1
2 应用
DOUT2+
DOUT2-
RIN2+
RIN2-
ROUT2
•
•
•
•
•
•
•
多功能打印机
板对板通信
测试和测量
打印机
DOUT3+
DOUT3-
RIN3+
RIN3-
数据中心互连
实验室仪表
超声波扫描仪
ROUT3
3 说明
DOUT4+
DOUT4-
RIN4+
RIN4-
DIN4
ROUT4
Driver
Receiver
DSLVDS1048 器件是一款四路 CMOS 直通差动线路
接收器，专为需要超低功耗和高数据速率的 应用 而设
计。该器件旨在使用低电压差动信号 (LVDS) 技术支持
超过 400Mbps (200MHz) 的数据速率。
EN
EN
EN*
EN*
DSLVDS1048 接受低电压（350mV 典型值）差动输入
信号，并将其转换为 3V CMOS 输出电平。该接收器
支持 TRI-STATE 功能，可用于对输出进行多路复用。
该接收器还支持开路、短路及终止 (100Ω) 输入失效防
护。该接收器的输出在所有失效防护条件下均为高电
平。DSLVDS1048 采用了直通引脚排列，可简化 PCB
布局。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS624
DSLVDS1048
ZHCSIV4 –SEPTEMBER 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 器件和文档支持 ..................................................... 16
12.1 接收文档更新通知 ................................................. 16
12.2 社区资源................................................................ 16
12.3 商标....................................................................... 16
12.4 静电放电警告......................................................... 16
12.5 术语表 ................................................................... 16
13 机械、封装和可订购信息....................................... 17
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 9 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Receiver enable pin: When EN is low, the receiver is disabled. When EN is high and EN* is low
or open, the receiver is enabled. If both EN and EN* are open circuit, then the receiver is
disabled.
EN
16
I
I
Receiver enable pin: When EN* is high, the receiver is disabled. When EN* is low or open and
EN is high, the receiver is enabled. If both EN and EN* are open circuit, then the receiver is
disabled.
EN*
9
GND
RIN+
RIN−
12
—
Ground pin
2, 3, 6, 7
1, 4, 5, 8
I
I
Noninverting receiver input pin
Inverting receiver input pin
Receiver output pin
10, 11, 14,
15
ROUT
VCC
O
13
—
Power supply pin, +3.3V ± 0.3V
6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)
See
MIN
–0.3
–0.3
–0.3
–0.3
MAX
4
UNIT
V
Supply voltage (VCC
Input voltage (RIN+, RIN−
Enable input voltage (EN, EN*)
Output voltage (ROUT
)
)
3.6
V
VCC + 0.3
VCC + 0.3
866
V
)
V
PW0016A package
mW
Maximum package power dissipation
at +25°C
Derate PW0016A
package
above +25°C
6.9
mW/°C
Lead temperature soldering
Maximum junction temperature
Storage temperature, Tstg
(4 s)
260
150
150
°C
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Copyright © 2018, Texas Instruments Incorporated
3
DSLVDS1048
ZHCSIV4 –SEPTEMBER 2018
www.ti.com.cn
6.2 ESD Ratings
VALUE
±10000
±1200
UNIT
Human-body model (HBM)
Machine model
V(ESD)
Electrostatic discharge(1)
V
(1) ESD Rating:
HBM (1.5 kΩ, 100 pF)
EIAJ (0 Ω, 200 pF)
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
Supply voltage, VCC
3.3
3.6
3
Receiver input voltage
GND
−40
V
Operating free air temperature, TA
25
85
°C
6.4 Thermal Information
DSLVDS1048
PW (TSSOP)
16 PINS
110.2
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
47
54.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
6.1
ψJB
54.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
PARAMETER
TEST CONDITIONS
VCM = +1.2 V, 0.05 V, 2.95 V(3)
VID = 200 mV peak to peak?(4)
PIN
MIN
TYP
MAX UNIT
VTH
Differential input high threshold
Differential input low threshold
Common-mode voltage range
100
mV
mV
V
VTL
−100
0.1
VCMR
2.3
10
10
20
RIN+
,
RIN−
VIN = +2.8 V
VCC = 3.6 V or 0 V
VIN = 0 V
−10
−10
–20
±5
±1
±1
IIN
Input current
μA
VIN = +3.6 V
VCC = 0 V
IOH = −0.4 mA, VID = +200 mV, input
terminated, input shorted
VOH
Output high voltage
2.7
3.3
V
VOL
IOS
IOZ
Output low voltage
IOL = 2 mA, VID = −200 mV
Enabled, VOUT = 0 V(5)
0.25
−100
10
V
ROUT
Output short-circuit current
Output TRI-STATE current
−15
−10
−47
mA
μA
Disabled, VOUT = 0 V or VCC
±1
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
(2) All typicals are given for: VCC = 3.3 V, TA = 25°C.
(3) VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range −0.2 V to VCC− VID/2. However, to
be compliant with AC specifications, the common voltage range is 0.1 V to 2.3 V.
(4) The VCMR range is reduced for larger VID. Example: if VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external
common-mode voltage applied. A VID up to VCC – 0 V may be applied to the RIN+/ RIN− inputs with the Common-Mode voltage set to
VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications
apply for 200 mV ≤ VID ≤ 800 mV over the common-mode range.
(5) Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only. Only one output should be shorted
at a time; do not exceed maximum junction temperature specification.
4
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
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ZHCSIV4 –SEPTEMBER 2018
Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
PARAMETER
Input high voltage
Input low voltage
Input current
TEST CONDITIONS
PIN
MIN
2
TYP
MAX UNIT
VIH
VIL
II
VCC
0.8
10
V
V
GND
−10
−1.5
EN,
EN*
VIN = 0 V or VCC, other Input = VCC or GND
±5
μA
V
VCL
Input clamp voltage
ICL = −18 mA
−0.8
No load supply current
receivers enabled
ICC
EN = VCC, inputs open
EN = GND, inputs open
9
1
15
5
mA
mA
VCC
No load supply current
receivers disabled
ICCZ
6.6 Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
1.2
TYP
2
MAX UNIT
tPHLD
tPLHD
tSKD1
Differential propagation delay high to low
2.7
2.7
0.4
ns
ns
ns
Differential propagation delay low to high
1.2
2
(5)
Differential pulse skew |tPHLD − tPLHD
|
0.1
Differential channel-to-channel skew; same
device(3)
CL = 15 pF
VID = 200 mV
tSKD2
0.15
0.5
ns
(Figure 16 and Figure 17)
tSKD3
tSKD4
tTLH
tTHL
tPHZ
tPLZ
Differential part-to-part skew(4)
Differential part-to-part skew(6)
Rise time
1
1.5
1
ns
ns
0.5
0.5
8
ns
Fall time
1
ns
Disable time high to Z
Disable time low to Z
Enable time Z to high
Enable time Z to low
Maximum operating frequency(7)
14
14
14
14
ns
RL = 2 kΩ
CL = 15 pF
(Figure 18 and Figure 19)
8
ns
tPZH
tPZL
9
ns
9
ns
fMAX
All channels switching
200
250
MHz
(1) All typicals are given for: VCC = 3.3 V, TA = 25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN
.
(3) tSKD2, channel-to-channel skew is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
(4) tSKD3, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC, and within 5°C of each other within the operating temperature range.
(5) tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel
(6) tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max−Min| differential
propagation delay.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05-V to 1.35-V peak to peak). Output criteria:
60 / 40% duty cycle, VOL (maximum 0.4 V), VOH (minimum 2.7 V), Load = 15 pF (stray plus probes).
Copyright © 2018, Texas Instruments Incorporated
5
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ZHCSIV4 –SEPTEMBER 2018
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6.7 Typical Characteristics
Figure 2. Output High Voltage vs Power Supply Voltage
Figure 3. Output Low Voltage vs Power Supply Voltage
Figure 5. Output TRI-STATE Current vs Power Supply
Voltage
Figure 4. Output Short-Circuit Current vs Power Supply
Voltage
Figure 6. Differential Transition Voltage vs Power Supply
Voltage
Figure 7. Power Supply Current vs Ambient Temperature
6
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
Typical Characteristics (continued)
Figure 9. Differential Propagation Delay vs Ambient
Temperature
Figure 8. Differential Propagation Delay vs Power Supply
Voltage
Figure 10. Differential Propagation Delay vs Differential
Input Voltage
Figure 11. Differential Propagation Delay vs Common-Mode
Voltage
Figure 12. Differential Skew vs Power Supply Voltage
Figure 13. Differential Skew vs Ambient Temperature
Copyright © 2018, Texas Instruments Incorporated
7
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ZHCSIV4 –SEPTEMBER 2018
www.ti.com.cn
Typical Characteristics (continued)
Figure 14. Transition Time vs Power Supply Voltage
Figure 15. Transition Time vs Ambient Temperature
8
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
7 Parameter Measurement Information
Figure 16. Receiver Propagation Delay and Transition Time Test Circuit
Figure 17. Receiver Propagation Delay and Transition Time Waveforms
CL includes load and test jig capacitance.
S1 = VCC for tPZL and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 18. Receiver TRI-STATE Delay Test Circuit
Figure 19. Receiver TRI-STATE Delay Waveforms
Copyright © 2018, Texas Instruments Incorporated
9
DSLVDS1048
ZHCSIV4 –SEPTEMBER 2018
www.ti.com.cn
8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
shown in Figure 20. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100 Ω. A termination resistor of 100 Ω (selected to match the media) is located as close to the receiver
input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is
detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects
of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise
margin limits, and total termination loading must be considered.
The DSLVDS1048 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V
common-mode range centered around +1.2 V. This is related to the driver offset voltage which is typically +1.2 V.
The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting
may be the result of a ground potential difference between the ground reference of the driver and the ground
reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to
+2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to VCC, but
exceeding VCC turns on the ESD protection circuitry, which clamps the bus voltages.
The DSLVDS1048 has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
8.2 Functional Block Diagram
10
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
8.3 Feature Description
8.3.1 Fail-Safe Feature
The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as
a valid signal.
The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing
fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver
inputs.
1. Open Input Pins. The DSLVDS1048 is a quad receiver device, and if an application requires only 1, 2, or 3
receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output
to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or
power-off condition, the receiver output is again in a HIGH state, even with the end of cable 100-Ω
termination resistor across the input pins. The unplugged cable can become a floating antenna which can
pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as
a valid signal and switch. To ensure that any noise is seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V
differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩ to 15-kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point must be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
Additional information on fail-safe biasing of LVDS devices may be found in AN-1194 Failsafe Biasing of LVDS
Interfaces (SNLA051).
8.4 Device Functional Modes
Table 1 lists the functional modes of the DSLVDS1048.
Table 1. Truth Table
ENABLES
INPUT
OUTPUT
EN
EN*
RIN+ − RIN−
VID ≥ 0 V
ROUT
H
L
VID ≤ −0.1 V
H
L or Open
Full Fail-safe
OPEN/SHORT or
Terminated
H
Z
All other combinations of ENABLE inputs
X
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ZHCSIV4 –SEPTEMBER 2018
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DSLVDS1048 has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
9.2 Typical Application
DSLVDS1048
DSLVDS1047
RIN1+
RIN1-
DOUT1+
DOUT1-
DIN1
DIN2
DIN3
Driver
Driver
Driver
Receiver
Receiver
Receiver
ROUT1
DOUT2+
DOUT2-
RIN2+
RIN2-
ROUT2
DOUT3+
DOUT3-
RIN3+
RIN3-
ROUT3
DOUT4+
DOUT4-
RIN4+
RIN4-
DIN4
ROUT4
Driver
Receiver
EN
EN
EN*
EN*
Figure 20. Balanced System Point-to-Point Application
12
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
Typical Application (continued)
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable
assemblies, and connectors. All components of the transmission media must have a matched differential
impedance of about 100 Ω. They must not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise
reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also
tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the
LVDS receiver.
For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M,
CAT5 (Category 5) twisted pair cable works well, is readily available, and relatively inexpensive.
Table 2. Design Requirements
DESIGN PARAMETERS
Receiver Supply Voltage (VCC
Receiver Output Voltage
Signaling Rate
EXAMPLE VALUE
3.0 to 3.6 V
0 to 3.6 V
0 to 400 Mbps
100 Ω
)
Interconnect Characteristic Impedance
Termination Resistance
100 Ω
Number of Receiver Nodes
1
Ground shift between driver and receiver
±1 V
9.2.2 Detailed Design Procedure
9.2.2.1 Probing LVDS Transmission Lines
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing gives deceiving results.
9.2.2.2 Threshold
The LVDS Standard (ANSI/TIA/EIA-644) specifies a maximum threshold of ±100 mV for the LVDS receiver. The
DSLVDS1048 supports an enhanced threshold region of −100 mV to 0 V. This is useful for fail-safe biasing. The
threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 21. The typical DSLVDS1048 LVDS
receiver switches at about −35 mV.
NOTE
With VID = 0 V, the output is in a HIGH state. With an external fail-safe bias of +25 mV
applied, the typical differential noise margin is now the difference from the switch point to
the bias point.
In the following example, this would be 60 mV of Differential Noise Margin (+25 mV − (−35 mV)). With the
enhanced threshold region of −100 mV to 0 V, this small external fail-safe biasing of +25 mV (with respect to
0 V) gives a DNM of a comfortable 60 mV. With the standard threshold region of ±100 mV, the external fail-safe
biasing would need to be +25 mV with respect to +100 mV or +125 mV, giving a DNM of 160 mV which is
stronger fail-safe biasing than is necessary for the DSLVDS1048. If more DNM is required, then a stronger fail-
safe bias point can be set by changing resistor values.
Copyright © 2018, Texas Instruments Incorporated
13
DSLVDS1048
ZHCSIV4 –SEPTEMBER 2018
www.ti.com.cn
Figure 21. VTC of the DSLVDS1048 LVDS Receiver
9.2.3 Application Curve
Figure 22. Power Supply Current vs Frequency
10 Power Supply Recommendations
Although the DSLVDS1047 draws very little power while at rest, its overall power consumption increases due to
a dynamic current component. The DSLVDS1048 power supply connection must take this additional current
consumption into consideration for maximum power requirements.
11 Layout
11.1 Layout Guidelines
•
•
Use at least 4 PCB layers (top to bottom): LVDS signals, ground, power, and TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. Best practice is to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
•
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
11.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high-frequency ceramic (surface mount is recommended)
0.1-μF and 0.001-μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple
vias must be used to connect the decoupling capacitors to the power planes. A 10-μF (35-V) or greater solid
tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply
and ground.
14
Copyright © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
Layout Guidelines (continued)
11.1.2 Differential Traces
Use controlled impedance traces that match the differential impedance of your transmission medium (that is,
cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they
leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than
traces 3 mm apart because magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals, which destroys the magnetic field cancellation benefits of differential signals and
EMI, results. Remember the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or
0.0118 in/ps.
Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities
in differential impedance. Minor violations at connection points are allowable.
11.1.3 Termination
Use a termination resistor that best matches the differential impedance or your transmission line. The resistor
must be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs must be minimized. The distance between the termination resistor and the receiver must be
< 10 mm (12 mm maximum).
11.2 Layout Example
DS90LV048A
DS90LV047A
1
2
3
16
15
14
13
12
11
10
9
1
2
3
16
15
14
13
12
11
10
9
DOUT1-
DOUT1+
DOUT2+
DOUT2-
DOUT3-
DOUT3+
RIN1-
RIN1+
RIN2+
RIN2-
RIN3-
RIN3+
EN
EN
DIN1
DIN2
Series Termination (optional)
ROUT1
ROUT2
LVCMOS
Inputs
LVCMOS
Outputs
Decoupling Cap
4
5
4
5
VCC
GND
VCC
GND
Decoupling Cap
6
7
6
7
ROUT3
ROUT4
EN*
DIN3
DIN4
EN*
DOUT4+
DOUT4-
RIN4+
RIN4-
Series Termination (optional)
8
8
Input Termination
(Required)
Figure 23. Layout Recommendation
版权 © 2018, Texas Instruments Incorporated
15
DSLVDS1048
ZHCSIV4 –SEPTEMBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
16
版权 © 2018, Texas Instruments Incorporated
DSLVDS1048
www.ti.com.cn
ZHCSIV4 –SEPTEMBER 2018
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DSLVDS1048PWR
DSLVDS1048PWT
ACTIVE
TSSOP
TSSOP
PW
16
16
2500 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
DSLVDS
1048
ACTIVE
PW
SN
DSLVDS
1048
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DSLVDS1048PWR
DSLVDS1048PWT
TSSOP
TSSOP
PW
PW
16
16
2500
1000
330.0
330.0
12.4
12.4
6.95
6.95
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DSLVDS1048PWR
DSLVDS1048PWT
TSSOP
TSSOP
PW
PW
16
16
2500
1000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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相关型号：
DSM-098-B-25-S-L-FB-FT
D Subminiature Connector, 25 Contact(s), Female, Solder Terminal, Socket
SAMTEC
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