ERJ-8GEYJ302V [TI]
This document contains the following chapters; 本文档包含以下章节
| 型号： | ERJ-8GEYJ302V |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | This document contains the following chapters |
| 文件： | 总26页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC7573, DAC6573, and
DAC5573 Evaluation Module
User’s Guide
January 2004
Data Acquisition
SLAU125
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V - VDD +0.3 V and the
output voltage range of 4.5 V and 18 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
100°C. The EVM is designed to operate properly with certain components above 100°C as
long as the input and output ranges are maintained. These components include but are not
limited to linear regulators, switching transistors, pass transistors, and current sense
resistors. These types of devices can be identified using the EVM schematic located in the
EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This user’s guide describes the characteristics, operation, and the use of the
DAC7573, DAC6573, DAC5573 Evaluation Module. It covers all pertinent
areas involved to properly use this EVM board along with the devices that it
supports. The physical PCB layout, schematic diagram and circuit
descriptions are included.
How to Use This Manual
This document contains the following chapters:
Chapter 1 – EVM Overview
Chapter 2 – PCB Design
Chapter 3 – EVM Operation
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
iii
Trademarks
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477–8924 or the Product
Information Center (PIC) at (972) 644–5580. When ordering, identify this
manual by its title and literature number. Updated documents can also be
obtained through our Web site at www.ti.com.
Data Sheets:
DAC7573
DAC6573
DAC5573
REF02
Literature Number:
SLAS398
SLAS402
SLAS401
SBVS-003A
PDS-998H
PDS-1309B
OPA627
OPA2132
Questions about this or other Data Converter EVMs?
If you have questions about this or other Texas Instruments Data Converter
evaluation modules, feel free to e-mail the Data Converter Application Team
at datacnvapps@list.ti.com Include in the subject heading the product you
have questions or concerns with.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It gen-
erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
2
I C is a trademark of Philips Corporation.
iv
Contents
1
EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.2 Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
2
3
PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
EVM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
3.3
3.4
Factory Default Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
EVM Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Output Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4.1 Unity Gain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.2 Output Gain of Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4.3 Capacitive Load Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.4.4 Optional Signal Conditioning Op Amp (U8B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Jumper Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5
3.6
v
Figures
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
EVM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Top Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Layer 1 (Top Signal Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Layer 2 (Ground Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Layer 3 (Power Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Layer 4 (Bottom Signal Plane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Bottom Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Drill Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Tables
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
Featured DAC Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
DACx573EVM Factory-Default Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
DACx573 Output Channel Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Unity Gain Output Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Gain of Two Output Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Capacitive-Load Drive Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Jumper Setting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
vi
Chapter 1
EVM Overview
This chapter gives a general overview of the DAC7573, DAC6573, and
DAC5573 evaluation module (EVM), and describes some of the factors that
must be considered in using this module.
Topic
Page
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-1
Features
1.1 Features
This EVM features the DAC7573, DAC6573 and DAC5573 family of
digital-to-analog converters. In this user’s guide, the EVM is referred to as the
DACx573 EVM to cover all supported DAC parts. The DACx573 EVM provides
a quick and easy way to evaluate the functionality and performance of these
2
12-bit, 10-bit, and 8-bit resolution, quad-channel, and serial I C-input DACs.
The following table shows the three DAC types this EVM supports. The EVM
2
also provides an I C serial interface to communicate with any host
microprocessor- or TI DSP-based system.
Table 1-1.Featured DAC Selections
EVM Version
Installed Device (DUT)
DAC7573IPW
DAC Channels Resolution
DAC7573 EVM
4
4
4
12-Bit
10-Bit
8-Bit
DAC6573 EVM
DAC6573IPW
DAC5573 EVM
DAC5573IPW
1.2 Power Requirements
This section describes the power requirements of this EVM.
1.2.1 Supply Voltage
The power supply requirement for the digital section (V ) of this EVM is
DD
typically 5 V, connected via J5-1 or J6-10 when used with another EVM or
interface card. It is referenced to ground through the J5-2 and J6-5 terminals.
The power supply requirements for the analog section of this EVM are as
follows:
V
CC
and V range from 15.75 V to -15.75 V maximum, and connects
SS
through J1-3 and J1-1 respectively, or through the J6-1 and J6-2 termi-
nals.
The 5-VA supply connects through J5-3 or J6-3 and the 3.3-VA supply con-
nects through J6-8.
All analog power supplies are referenced to analog ground through the
J1-2 and J6-6 terminals.
The analog power supply for the device under test (DUT), U1, can be supplied
by either 5 VA or 3.3 VA via jumper W1. This allows the DACx573 analog
section to operate from either supply while the I/O and digital section is
powered by 5 V, V
.
DD
The V
supply is mainly used as the positive rail of the external output
CC
operational amplifier (op amp), U2, the reference chip, U3, and the reference
buffer, U8. The negative rail of the output op amp, U2, can be selected between
V
SS
and AGND via jumper W5. The external op amp is installed as an option
to provide output signal conditioning, to boost capacitive load drive (via W15),
and for other output-mode requirements.
1-2
EVM Basic Functions
Caution
To avoid potential damage to the EVM board, make sure that the
correct cables are connected to their respective terminals as
labeled on the EVM board.
Stresses above the maximum listed voltage ratings may cause
permanent damage to the device.
1.2.2 Reference Voltage
The 5-V precision voltage reference is provided to supply the external voltage
reference for the DAC through REF02, U3, via jumper W4 by shorting pins 1
and 2. The reference voltage goes through 100-kΩ potentiometer R11 in
series with 20-kΩ R10 to allow the user to adjust the reference voltage to a
desired level. The voltage reference is then buffered through U8A to the DUT.
Test points TP1, TP2, and TP5 are also provided, as well as J4-18 and J4-20,
to allow the user to connect another external reference source if the onboard
reference circuit is not used. The external voltage reference must not exceed
5 Vdc.
The REF02 precision reference is powered by V (15 V) through the J1-3
CC
or J6-1 terminal.
Caution
When applying an external voltage reference through TP1 or J4-20,
make sure that it does not exceed 5 V maximum. Otherwise, this
can permanently damage the installed device under test (DUT).
1.3 EVM Basic Functions
The DACx573 EVM is a functional-evaluation platform to demonstrate the
operation of the DACx573 family of digital-to-analog converters. Functional
evaluation of the DAC device can be conducted with any microprocessor, TI
DSP, or a waveform generator.
Header connectors J2 and P2 allow control signals and data from a host
processor or waveform generator to interface with the DACx573 EVM using
a custom-built cable.
Specific adapter interface boards are also available for many TI DSP Starter
Kits (DSKs). Specify the correct adapter interface board for the TI DSP Starter
Kit to be used. In addition, an MSP430-based platform (HPA449) that uses the
MSP430F449 microprocessor is available that directly interfaces with this
EVM. For more information regarding the adapter-interface board or the
HPA449 platform, please call Texas Instruments or send email to
dataconvapps@list.ti.com.
EVM Overview
1-3
EVM Basic Functions
The DAC outputs can be monitored through the J4 header connector. All the
outputs can be switched by their respective jumpers W2, W11, W12, and W13
for stacking. Stacking allows eight DAC channels to be used, provided that the
2
I C address is unique for each EVM board stacked.
In addition, one DAC output can be fed to the noninverting side of output op
amp U2 by installing a jumper across the appropriate pins of J4. Output op amp
U2 must first be configured correctly for the desired waveform characteristic.
Refer to Chapter 3 of this user’s guide for more information.
A block diagram of the EVM is shown in Figure 1-1.
Figure 1-1. EVM Block Diagram
VCC
VSS
VCC
GND
VSS
GND
VDD
(J1)
(J5)
(J6)
(P6)
3.3 VA
VDD
5 VA
External
Reference
Module
W4
A0
A1
A2
A3
TP1
(J2)
(P2)
V
H
REF
W2
W11
W12
W13
(J4)
(P4)
DAC Out
TP3
DAC Module
SDA
SCL
LDAC
Output
4 CH
Buffer
8 CH
VREF
V
L
REF
A0 A1 A2 A3
W8 W9
W3
Module
W10
TP2
W7
H
W15
W6
TP5
W5
VSS
1-4
Chapter 2
PCB Design
This chapter describes the physical and mechanical characteristics of the
EVM. The bill of materials is also included in this chapter.
Topic
Page
2.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-1
PCB Layout
2.1 PCB Layout
The DACx573 EVM demonstrates the performance of the installed DAC
device under test, as specified in the data sheet. Careful analysis of the
physical restrictions and performance-degrading factors of the EVM is vital to
a successful design implementation. The obvious attributes that can cause
poor performance of the EVM can be avoided during schematic design by
proper component selection and correct circuit-design practices. The circuit
must include adequate bypassing, identifying, and managing the analog and
digital signals and understanding the mechanical attributes of the
components.
The less obvious part of the design lies in the PCB layout. The main concerns
are component placement and proper signal routing. The bypass capacitors
must be placed as close as possible to the pins and the analog and digital
signals must be properly separated from each other. The power and ground
planes are very important and require careful consideration. A solid plane is
preferred, but sometimes impractical. When solid planes are not possible, a
well-designed split plane can suffice. When considering a split-plane design,
analyze the component placement and carefully divide the board into its
analog and digital sections starting from the device under test. The ground
plane plays an important role in controlling noise and other effects that can
contribute to DAC output error. To ensure that return currents are handled
properly, route the appropriate signals only in their respective sections. Route
analog traces only directly above or below the analog section, and the digital
traces in the digital section. Minimize trace length, but use the widest possible
trace allowable in the design. These design practices are demonstrated in
subsequent figures in this section.
The DACx573 EVM board is constructed on a four-layer printed circuit board
using a copper-clad FR-4 laminate material. The printed circuit board has a
dimension of 43,1800 mm (1.7000 inch) X 82,5500 mm (3.2500 inch), and the
board thickness is 1,5748 mm (0.0620 inch). Figure 2-1 through Figure 2-6
show the individual artwork layers.
2-2
PCB Layout
Figure 2-1. Top Silkscreen
DACx573
REV A
LAYER SILKSCREEN
TOP
Figure 2-2. Layer 1 (Top Signal Plane)
DACx573
REV A
LAYER 1 TOP SIGNAL LAYER
Figure 2-3. Layer 2 (Ground Plane)
DACx573 REV A
LAYER 2 SPLIT GND PLANE
PCB Design
2-3
PCB Layout
Figure 2-4. Layer 3 (Power Plane)
DACx5/3 REV A
LAYER 3 SPLIT POWER PLANE
Figure 2-5. Layer 4 (Bottom Signal Plane)
DACx573
REV A
LAYER 4
BOTTOM SIGNAL LAYER
Figure 2-6. Bottom Silkscreen
DACx573
REV A
LAYER
SILKSCREEN BOTTOM
2-4
PCB Layout
Figure 2-7. Drill Drawing
PCB Design
2-5
Bill of Materials
2.2 Bill of Materials
Table 2-1.Parts List
Item #
Qty Designator
Mfr.
Part Number
Description
1
2
C9 C10
Panasonic
ECUV1H105JCH
1-µF, 1206 multilayer-ceramic
capacitor
2
3
4
5
4
C1 C2 C3 C7
C12
Panasonic
Panasonic
Kemet
ECJ3VB1C104K
ECUV1H102JCH
C1210C106K8PAC
ERJ-8GEY0R00V
0.1-µF, 1206 multilayer-ceramic
capacitor
1
1-nF, 1206 multilayer ceramic
capacitor
3
C5 C6 C11
10-µF, 1210 multilayer ceramic X5R
capacitor
17
R8 R17 R25
R26 R27 R28
R29 R30 R31
R32 R33 R34
R35 R36 R37
R38 R39
Panasonic
0-Ω, 1/4-W 1206 chip resistor
6
7
8
9
2
1
1
6
R15 R16
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-8GEYJ431V
ERJ-8GEYJ101V
ERJ-8ENF2002V
ERJ-8GEYJ302V
430-Ω, 1/4-W 1206 chip resistor
100-Ω,1/4-W 1206 chip resistor
20-kΩ,1/4-W 1206 chip resistor
3-kΩ, 1/4-W 1206 chip resistor
R13
R10
R1 R2 R3 R4
R5 R7
10
11
3
1
R6 R12 R14
R9
Panasonic
Bourns
ERJ-8ENF1002V
3214W-203E
10-kΩ,, 1/4-W 1206 chip resistor
20-kΩ, BOURNS_32X4W series 5T
pot
12
13
14
15
1
1
2
2
R11
J6
Bourns
Samtec
Samtec
3214W-104E
100-kΩ, BOURNS_32X4W series 5T
pot
TSM-105-01-T-DV
TSM-110-01-S-DV-M
ED555/3DS
5X2X0.1, 10-pin 3 A isolated power
socket
J2 J4
J1 J5
10X2X.1, 20 Pin 0.025” sq SMT
socket
On-Shore
3-pin terminal connector
Technology
2
DAC7573IPW
DAC6573IPW
DAC5573IPW
12-bit, quad output, I C DAC
2
10-bit, quad output, I C DAC
16
1
U1
Texas Instruments
2
8-bit, quad output, I C DAC
17
18
1
1
U2
U3
Texas Instruments OPA627AU
Texas Instruments REF02AU
8-SOP(D) precision op amp
5-V, 8-SOP(D) precision voltage
reference
19
20
1
7
U8
Texas Instruments OPA2132UA
8-SOP(D) Dual Precision Op Amp
Turret terminal test point
TP1 TP2 TP3 Mill-max
TP4 TP5 TP6
TP7
2348-2-01-00-00-07-0
21
2
P2 P4
(see Note)
Samtec
SSW-110-22-S-D-VS-P 20-pin 0.025” square SMT
terminal strips
22
23
1
6
P6 (see Note) Samtec
SSW-105-F-D-VS-K
22-03-2021
3-A isolated 10-pin power header
2 position jumper, 0.1” spacing
W3 W7 W8
Molex
W9 W10 W15
24
8
W1 W2 W4
W5 W6 W11
W12 W13
Molex
22-03-2031
3 position jumper, 0.1” spacing
Note: P2, P4, and P6 parts are not shown in the schematic diagram. All the P-designated parts are installed on the bottom side
of the PC board opposite the J-designated counterpart. Example, J2 is installed on the top side while P2 is installed in the
bottom side opposite of J2. Not all parts listed in the BOM are installed in the EVM as they are specific to the DUT installed.
2-6
Chapter 3
EVM Operation
This chapter details the operation of the EVM to guide the user in evaluating
the onboard DAC and in interfacing the EVM to a host processor.
Refer to the specific DAC data sheet, as listed in the Related Documentation
From Texas Instruments section in the Preface of this user’s guide for more
information about the DAC serial interface and other related topics.
The EVM board is factory-configured to operate in the unipolar output mode.
Topic
Page
3.1 Factory Default Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3 EVM Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4 The Output Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.5 Jumper Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.6 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-1
Factory Default Setting
3.1 Factory Default Setting
The EVM board is factory-configured to operate in unipolar 5-V output mode.
Table 3-1.DACx573EVM Factory-Default Jumper Configuration
DACx573 EVM CONFIGURATION
Jumper
Reference
W1
Function
Position
1-2
Analog supply for the DACx573 is 5 VA.
DAC output A (VOUTA) is routed to J4-2.
W2
1-2
W3
Open
VREFH is not routed to the inverting input of the op
amp.
W4
1-2
Onboard external buffered reference U3 is routed to
V
REFH.
W5
1-2
Negative supply rail of U2 op amp is supplied by V
VREFL is tied to AGND.
SS.
W6
1-2
W7
Closed
Closed
Closed
Closed
1-2
A0 pin is tied to DGND.
W8
A1 pin is tied to DGND.
W9
A3 pin is tied to DGND.
W10
W11
W12
W13
W15
J4
A2 pin is tied to DGND.
DAC output B (VOUTB) is routed to J4-4.
DAC output C (VOUTC) is routed to J4-6.
DAC output D (VOUTD) is routed to J4-8.
Output op amp U2 is configured for a gain of 2.
1-2
1-2
Closed
1-2
DAC output A (VOUTA) is connected to the noninvert-
ing input of output op amp U2.
3.2 Host Processor Interface
Because the host processor controls the DAC, proper operation depends on
the correct interface of the host processor and the EVM board. Properly written
code is also required to operate the DAC.
A host-platform-specific cable assembly can be made to connect the EVM to
2
the host processor through J2 for the I C serial control and data signals. The
output is monitored through J4.
An interface adapter board is available for specific TI DSP starter kits as well
as for an MSP430-based microprocessor as mentioned in section 1.3. Using
the interface board alleviates the tedious task of building custom cables and
allows easy configuration of a simple evaluation system.
2
This DACx573 EVM interfaces with any host processor capable of I C
protocols or the popular TI DSP. For more information regarding the serial
interface of the particular DAC installed, refer to the specific DAC data sheet,
as listed in the Related Documentation From Texas Instruments section in the
Preface of this user’s guide.
3-2
EVM Stacking
3.3 EVM Stacking
EVM stacking enables the designer to evaluate two DACx573s in tandem to
yield an eight-channel output. A maximum of two DACx573 EVMs are allowed
because the output terminal, J4, dictates the number of DAC channels that can
be connected without colliding. Table 3-2 shows how the DAC output
channels are mapped to the output terminal, J4, with respect to the jumper
positions of W2, W11, W12, and W13.
Table 3-2.DACx573 Output Channel Mapping
Jumper
Reference
Function
Position
W2
1-2
DAC output A (VOUTA) is routed to J4-2.
DAC output A (VOUTA) is routed to J4-10.
DAC output B (VOUTB) is routed to J4-4.
DAC output B (VOUTB) is routed to J4-12.
DAC output C (VOUTC) is routed to J4-6.
DAC output C (VOUTC) is routed to J4-14.
DAC output D (VOUTD) is routed to J4-8.
DAC output D (VOUTD) is routed to J4-16.
2-3
1-2
2-3
1-2
2-3
1-2
2-3
W11
W12
W13
2
Each DAC EVM in a stacked configuration must have a unique I C address.
This is accomplished by configuring address jumpers W7 and W8 (refer to the
2
data sheet for I C addressing).
The LDAC signal can be shared to have a synchronous DAC-output update
and can be hardware-driven by GPIO0. If software control of the LDAC is
desired, the GPIO0 signal must be set low through software or J2-pin 2 can
be strapped to DGND.
3.4 Output Op Amp
The EVM includes an optional signal conditioning circuit for the DAC output
through an external operational amplifier, U2. Only one DAC output channel
can be monitored at any given time because the odd numbered pins (J4-1 to
J4-7) are tied together. The output op amp gain is configured at two by default.
The unbuffered outputs of the DAC can be probed through the even pins of J4,
the output terminal, which also provides mechanical stability when stacking or
plugging into an interface board. J4 also provides easy access for monitoring
up to eight DAC channels when stacking two EVMs together, as described in
section 3.3.
The following sections describe various configurations of the output amplifier,
U2.
EVM Operation
3-3
Output Op Amp
3.4.1 Unity Gain Output
The buffered output configuration can be used to prevent loading the DAC.
However, it may present some slight distortion because of the feedback
resistor and capacitor. The user can tailor the feedback circuit to closely match
the desired wave shape by simply removing R7 and C11 and replacing them
with the desired values. R7 can be replaced with a zero-ohm resistor and C11
can be left open, if desired.
Table 3-3 shows the jumper settings for the unity gain configuration of the
output buffer in unipolar or bipolar supply mode.
Table 3-3.Unity Gain Output Jumper Settings
Jumper Setting
Reference
Function
Unipolar
Bipolar
Disconnects TP2 input or AGND from the in-
verting input of the op amp
W3
W5
Open
2-3
Open
Supplies VSS to the negative rail of the op amp
or ties it to AGND
1-2
Disconnects negative input of the op amp
from AGND
W15
Open
Open
3.4.2 Output Gain of Two
Table 3-4 shows the proper jumper settings of the EVM for the 2× gain output
of the DAC.
Table 3-4.Gain of Two Output Jumper Settings
Jumper Setting
Reference
Function
Unipolar
Bipolar
Inverting input of output op amp U2 is con-
nected to VREFH for use as its offset voltage
with a gain of 2. Jumper W15 must be open.
Closed
Open
2-3
Closed
W3
VREFH is disconnected from the inverting in-
put of output op amp U2. Jumper W15 must
be closed.
Open
1-2
Supplies power, VSS, to the negative rail of op
amp U2 for bipolar supply mode, or ties it to
AGND for unipolar supply mode
W5
Configures op amp U2 for a gain of 2 output
without an offset voltage. Jumper W3 must be
open.
Closed
Open
Closed
Open
W15
Inverting input of op amp U2 is disconnected
from AGND. Jumper W3 must be closed.
3-4
Output Op Amp
3.4.3 Capacitive Load Drive
Another output configuration option is to drive a wide range of capacitive loads.
All op amps under certain conditions may become unstable depending on
configuration, gain, and load value. In unity gain, the OPA627 op amp performs
well with large capacitive loads. Increasing the gain and adding a load resistor
further improves the capacitive load drive capability.
Table 3-5 shows the proper jumper settings of the EVM for the 2× gain output
of the DAC.
Table 3-5.Capacitive-Load Drive Jumper Settings
Jumper Setting
Reference
Function
Unipolar
Bipolar
VREFH is disconnected from the inverting in-
put of output op amp U2.
W3
Open
Open
Supplies power, VSS, to the negative rail of op
amp U2 for bipolar supply, or ties it to AGND
for unipolar supply.
W5
2-3
1-2
Capacitive load drive output of DAC is routed
to jumper-W15 pin 1, and this pin can be used
as the output terminal.
W15
Open
Open
3.4.4 Optional Signal Conditioning Op Amp (U8B)
One device of the dual-op amp OPA2132 (U8) is used for reference buffering
(U8A), while the other is unused. This unused op amp (U8B) is available for
user-configured circuitry. The 1206-package resistor and capacitor footprints
associated with the U8B op amp are unpopulated and available for easy
configuration. TP6 and TP7 test points are not installed for maximum flexibility
of input-signal configuration. No test point is available for the output due to
space restrictions, but a wire can be simply soldered to the output of the op
amp via the unused component pads connected to it.
Once the op amp circuit design is determined, it is easily implemented by
simply populating the desired components and leaving unused component
footprints unpopulated.
EVM Operation
3-5
Jumper Setting
3.5 Jumper Setting
Table 3-6 shows the function of each specific jumper setting of the EVM.
Table 3-6.Jumper Setting Function
Jumper
Reference
Function
Setting
1
1
1
1
3
3
3
3
5-V analog supply is selected for AVDD
.
+3.3-V analog supply is selected for AVDD
Routes VOUTA to J4-2
W1
.
W2
W3
W4
Routes VOUTA to J4-10
Disconnects VREFH to the inverting input of output op amp U2.
Connects VREFH to the inverting input of output op amp U2.
1
1
1
1
1
1
3
3
3
3
3
3
Routes the adjustable, buffered, onboard 5-V reference to the VREFH input of the
DACx573.
Routes the user supplied reference from TP1 or J4-20 to the VREFH input of the
DACx573.
Negative supply rail of the output op amp U2 is powered by VSS for bipolar operation.
Negative supply rail of the output op amp U2 is tied to AGND for unipolar operation.
VREFL is tied to AGND.
W5
W6
Routes the user-supplied negative reference from TP2 or J4-18 to the VREFL input of
the DACx573. This voltage must be within the range of 0V to VREFH.
A0 is set high through pullup-resistor R4. A0 can be driven by GPIO5.
A0 is set low.
W7
W8
A1 is set high through pullup-resistor R3. A1 can be driven by GPIO4.
A1 is set low.
A3 is set high through pullup-resistor R2. A3 can be driven by GPIO1.
LDAC pin is set low and DAC update is accomplished via software.
A2 is set high through pullup-resistor R1. A2 can be driven by GPIO3.
A2 pin is set low.
W9
W10
1
1
3
3
Routes VOUTB to J4-4
Routes VOUTB to J4-12
W11
3-6
Schematic
Jumper
Setting
Reference
Function
1
1
1
1
3
3
3
3
Routes VOUTC to J4-6
Routes VOUTC to J4-14
Routes VOUTD to J4-8
Routes VOUTD to J4-16
W12
W13
Disconnects the inverting input of output op amp U2 from AGND.
W15
Connects the inverting input of output op amp U2 to AGND for gain of 2.
Legend:
Indicates the corresponding pins that are shorted or closed.
3.6 Schematic
The schematic is on the following page.
EVM Operation
3-7
1
2
3
4
5
6
Revision History
+5VA
+3.3VA
REV
ECN Number
Approved
W1
AVDD
VDD
VDD
R1
R2
R3
10K
R4
R5
3K
R7
3K
C1
C5
10K
10K
10K
0.1µF
10µF
C6
C2
VCC
10µF
0.1µF
C9
D
C
B
A
R25
R26
D
C
B
A
GPIO0
GPIO1
(LDAC)
(A3)
1µF
0
0
U1
AVDD
4
12
3
R8
IO_V/DVDD
VrefH
U2_+IN
3
2
U2
R27
R28
GPIO2
GPIO3
OUT_A1
(EN)
(A2)
R13
100
TP3
0
6
U2_OUT
0
0
VrefH
VrefL
16
15
14
13
OUT_A
OUT_B
W2
VOUT
A3/LDAC
A2/EN
A1
W3
U2_-IN
Op Amp
OUT_A2
OUT_B1
5
VrefL
R38
R39
GPIO4
GPIO5
(A1)
(A0)
0
0
W11
J4
R14
10K
A0
VSS
2
1
3
5
7
9
OUT_B2
OUT_C1
4
R15 440/0
R16 440/0
SDI
SCLK
R29
11
10
9
SDA/Din
6
W9
W8
W7
W10
1
2
7
8
VoutA
VoutB
VoutC
VoutD
8
SCL/SCLK
LDAC/SYNC
10
W5
C10
12 11
14 13
16 15
18 17
20 19
FSX
(SYNC)
(LDAC)
OUT_C
OUT_D
W12
W13
1µF
0
R30
0
-REFin
+REFin
GPIO0
6
OUT_C2
R6
GND
DAC7573/6573/5573
10K
OUTPUT HEADER
C12
OUT_D1
OUT_D2
DAC7573 = 12-Bit
DAC6573 = 10-Bit
DAC5573 = 8-Bit
1nF
W15
VCC
R9
20K
2
R12
10K
U3
VCC
5
2
8
7
6
3
1
TRIM OUT
V+ TEMP
TP4
C7
0.1µF
NC
NC
NC
C8
NI
C11
Tantalum
10µF
R11
REF02AU(8)
2
3
2
C3
R18
R22
1
NI
0.1µF
J2
100K
NI
NI
W4
GPIO0
(LDAC)
U8A
OPA2227UA
TP6
1
3
5
7
9
2
1
R31
CLKX
CLKR
FSX
FSR
DX
VrefH
+Vin
4
6
U8B
GPIO1
GPIO2
(A3)
(EN)
0
0
0
3
R20
R21
R32
R33
5
8
R24
NI
7
NI
NI
R10
20K
TP1
10
+REFin
-REFin
6
GPIO3
GPIO4
SCL
(A2)
(A1)
EXTERNAL
11 12
13 14
15 16
17 18
19 20
DR
REFERENCE
OPA2227UA
TP5
TP7
-Vin
NOTE: Voltage range of -REFin input should not exceed
R17
0
0 - VrefH.
R23
R19
NI
GPIO5
SDA
(A0)
W6
Serial Header
R36
0
VrefL
DX
C13
NI
R34
SDI
SCLK
0
R35
TP2
0
R37
0
CLKX
J1
J5
+3.3VD+1.8VD +5VA VCC
VSS -5VA +3.3VA VDD
J6
1
3
5
7
9
2
4
6
8
VSS
VCC
VDD
+5VA
10
VCC = +15V Analog
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog
ti
DACx573 EVM
12500 TI Boulevard. Dallas, Texas 75243
Title:
Engineer:
J. PARGUIAN
DOCUMENTCONTROL #
REV:
A
6456605
Drawn By:
FILE:
DATE:
SIZE:
1-Dec-2003
SHEET:
OF:
DAC7573 RevA.Sch
1
1
2
3
4
5
6
相关型号：
©2020 ICPDF网 联系我们和版权申明