ESD204 [TI]
适用于 USB 和 HDMI 且具有 5.5A 浪涌额定值的四路 0.55pF、±3.6V、±30kV ESD 保护二极管;
| 型号： | ESD204 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 和 HDMI 且具有 5.5A 浪涌额定值的四路 0.55pF、±3.6V、±30kV ESD 保护二极管 二极管 |
| 文件： | 总19页 (文件大小：1185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
ESD204 4 通道低电容浪涌和 ESD 保护二极管
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
ESD204 是一种双向 TVS ESD 保护二极管阵列，可为
HDMI 和 USB 提供高达 5.5A (8/20μs) 的浪涌保护。
ESD204 的额定 ESD 冲击消散值达到了 IEC 61000-4-
2（4 级）国际标准中规定的最高水平。
–
–
±30kV 接触放电
±30kV 气隙放电
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
–
ESD204 提供低钳位和高差分带宽，使器件可干净地
传输高速信号，并且为下游器件提供强大的保护。该器
件每通道具有 0.55pF 的低电容值，这使其非常适合用
于保护速率高达 6Gbps 的高速接口（例如 HDMI
2.0、HDMI 1.4、USB 3.0 和以太网 1G）。低动态电
阻和低钳位电压确保系统级抗瞬变事件保护。
–
–
5.5A (8/20μs)
低浪涌钳位电压
在 5.5A IPP 下为 8.5V
•
IO 电容：
–
0.55pF（典型值）
ESD204 采用符合行业标准的 USON-10 (DQA) 封
装。该封装 采用 直通布线，其引脚间距为 0.5mm，能
够简化实现并缩短设计时间。
•
•
•
•
•
•
符合 HDMI 2.0 标准
直流击穿电压：5.5V（最小值）
超低泄漏电流：10nA（最大值）
支持速率最高达 6Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
简易直通布线封装
器件信息(1)
器件型号
ESD204
封装
USON (10)
封装尺寸（标称值）
2.50mm x 1.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
•
终端设备
典型应用原理图
–
–
IP 网络摄像机
数字视频录像机 (DVR) 和网络视频录像机
TMDS D2+
(NVR)
TMDS D2œ
ESD204
–
–
–
–
–
以太网交换机和路由器
便携式计算机和台式机
机顶盒
TMDS GND
TMDS D1+
TMDS D1œ
电视和监视器
TMDS D0+
手机和平板电脑
TMDS D0œ
ESD204
•
接口
TMDS GND
To System
TMDS CLK+
–
–
–
–
–
–
HDMI 2.0
TMDS CLKœ
HDMI 1.4
USB 3.0
CEC
显示端口 1.3
UTILITY
TPD4E05U06
PCI Express 3.0总线接口
以太网 10/100/1000Mbps
DDC_CLK
DDC_DAT
GND
P 5V0
HOTPLUG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSEE2
ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
目录
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 8
8.1 Application Information.............................................. 8
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 10
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings -JEDEC Specifications ........................ 4
6.3 ESD Ratings - IEC Specifications............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
8
9
10 Layout................................................................... 10
10.1 Layout Guidelines ................................................. 10
10.2 Layout Examples ................................................. 11
11 器件和文档支持 ..................................................... 12
11.1 接收文档更新通知 ................................................. 12
11.2 社区资源................................................................ 12
11.3 商标....................................................................... 12
11.4 静电放电警告......................................................... 12
11.5 术语表 ................................................................... 12
12 机械、封装和可订购信息....................................... 12
7
4 修订历史记录
Changes from Original (February 2018) to Revision A
Page
•
已更改 将“高级信息”更改为“生产数据” ................................................................................................................................... 1
2
版权 © 2018, Texas Instruments Incorporated
ESD204
www.ti.com.cn
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
5 Pin Configuration and Functions
DQA Package
10-Pin USON
Top View
IO1
IO2
1
2
3
4
5
10 NC
9
8
7
6
NC
GND
IO3
GND
NC
IO4
NC
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
NO.
3
Ground
I/O
Ground. Connect to ground
GND
IO1
IO2
IO3
IO4
NC
8
1
2
ESD protected channel. Connect to the line being protected.
4
5
6
NC
7
Not connected internally; Can be connected to line being protected for optional flow-
through routing. Can also be left floating or grounded
NC
NC
9
NC
10
Copyright © 2018, Texas Instruments Incorporated
3
ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Electrical Fast
IEC 61000-4-4 Peak Current at 25°C
Transient
80
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25°C
Peak Pulse
50
W
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25°C
5.5
TA
Operating free-air temperature
Storage temperature
-40
-65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings -JEDEC Specifications
VALUE
UNIT
Human body model (HBM), per
±2500
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
UNIT
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air Discharge, all pins
±30000
±30000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
-3.6
-40
NOM
MAX
UNIT
V
VIN
TA
Input voltage
3.6
Operating Free Air Temperature
125
°C
6.5 Thermal Information
ESD204
THERMAL METRIC(1)
DQA (USON)
10 PINS
262.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
184.6
138.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
41.8
ΨJB
137.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
ESD204
www.ti.com.cn
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIO < 10 nA, across operating
temperature range
VRWM
VBRF
Reverse stand-off voltage
-3.6
3.6
V
Positive Breakdown Voltage, Each IO
IIO = 1 mA
5
7.9
-5
V
(1)
Pin to GND
Negative Breakdown Voltage, Each IO
VBRR
IIO = -1 mA,
-7.9
V
V
(1)
Pin to GND
VHOLD
Positive Holding Voltage, Each IO pin IIO = 1 mA
6.2
(2)
to GND
Negative Holding Voltage, Each IO
pin to GND
VHOLD-NEG
IIO = -1 mA
-6.2
8.5
V
V
V
V
(2)
Surge IPP = 5.5 A, Each IO pin to
GND, GND to Each IO pin, tp=8/20 μs
TLP IPP = 5 A, Each IO pin to GND,
GND to Each IO pin, tp=10/100 ns
VCLAMP
Clamping voltage
8.2
TLP IPP = 16 A, Each IO pin to GND,
GND to Each IO pin, tp=10/100 ns
11.5
0.3
Each IO Pin to GND, TLP tp=10/100
ns
RDYN
Dynamic resistance
Ω
GND to Each IO Pin, TLP tp=10/100
ns
0.3
0.55
0.02
0.25
CLINE
Line capacitance, any IO to GND
Variation of line capacitance
Line-to-line capacitance
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
0.65
0.07
0.35
pF
pF
pF
CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30
mV, f = 1 MHz
ΔCLINE
CCROSS
VIO = 0 V, Vrms = 30 mV, f = 1 MHz
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback
state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
版权 © 2018, Texas Instruments Incorporated
5
ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6.7 Typical Characteristics
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
-5
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Voltage (V)
Voltage (V)
D001
D002
图 1. Positive TLP Curve, IO pin to GND (tp = 100 ns)
图 2. Negative TLP Curve, GND to IO pin (tp=100 ns; Plotted
as Positive TLP Curve from GND to IO pin)
6
5.5
5
55
50
45
40
35
30
25
20
15
10
5
110
100
90
80
70
60
50
40
30
20
10
0
Current (A)
Power (W)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
-10
-20
-5
0
20
40
60
80 100 120 140 160 180 200
Time (us)
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
D006
D003
图 3. Surge Curve (tp = 8/20 µs), any IO pin to GND
图 4. 8-kV IEC 61000-4-2 Clamping Voltage Waveform, IO pin
to GND
20
10
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-10
0
10
20
30
40
50
60
70
80
90
0
0.5
1
1.5
2
2.5
3
3.5
4
Time (ns)
Bias Voltage (V)
D004
D008
图 5. –8-kV IEC 61000-4-2 Clamping Voltage Waveform, GND
图 6. Capacitance vs Bias Voltage
pin to IO
6
版权 © 2018, Texas Instruments Incorporated
ESD204
www.ti.com.cn
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
Typical Characteristics (接下页)
2.1
0.001
0.0005
0
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.0005
-0.001
-40
-20
0
20
40
60
80
100 120 140
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
Temperature (èC)
Voltage (V)
D007
D005
图 7. Leakage Current vs Temperature, IO pin to GND at 3.6
图 8. DC Voltage Sweep I-V Curve, IO pin to GND
V Bias
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.1
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0.2 0.3
0.5 0.7
1
2
3
4 5 6 7 8 10
Frequency (GHz)
Frequency (Ghz)
EDS0D120
D009
图 9. Capacitance vs Frequency
图 10. Differential Insertion Loss
版权 © 2018, Texas Instruments Incorporated
7
ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ESD204 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD
strikes up to 30kV (Contact/Air) level specified by the IEC 61000-4-2 International Standard. Additionally,
ESD204 dissipates 5.5 A of surge current (8/20 µs waveform) per IEC 61000-4-5 standard. The ultra-low
capacitance makes this device capable of supporting any super high-speed signal pins.
7.2 Functional Block Diagram
IO1
IO2
IO3
IO4
GND
7.3 Feature Description
ESD204 provides ESD protection up to ±30-kV contact and ±30-kV air gap per IEC61000-4-2 standard. During
an ESD event, ESD diode connected to the IO pin turns on and diverts the ESD current to ground. Additionally,
ESD204 also provides protection against IEC 61000-4-5 surge currents up to 5.5 A (8/20 µs waveform) and up to
80 A per IEC 61000-4-4 electrical fast transient (EFT) standard. Please see the Application Note on IEC61000-4-
x standard based tests. ESD204 provides a very low clamping voltage of 11.5 V at 16 A 100 ns TLP current and
8.5 V at 5.5 A surge current (8/20 µs waveform).
The capacitance between each I/O pin to ground is 0.55 pF (typical) and 0.65 pF (maximum). This device
supports data rates up to 6 Gbps. The DC breakdown voltage of each I/O pin is a minimum of ±5 V. This ensures
that sensitive equipment is protected from surges above the reverse standoff voltage of ±3.6 V. The I/O pins
feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±3.6 V.
7.4 Device Functional Modes
The ESD204 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During
ESD events, voltages as high as ±30 kV (contact/air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of ESD204 (usually within 10s of nano-
seconds) the device reverts to passive.
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ESD204 is a diode type TVS array which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between an interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8
版权 © 2018, Texas Instruments Incorporated
ESD204
www.ti.com.cn
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
8.2 Typical Application
TMDS D2+
TMDS D2œ
TMDS GND
ESD204
TMDS D1+
TMDS D1œ
TMDS D0+
TMDS D0œ
ESD204
TMDS GND
TMDS CLK+
TMDS CLKœ
To System
CEC
UTILITY
TPD4E05U06
DDC_CLK
DDC_DAT
GND
P 5V0
HOTPLUG
图 11. ESD204 Protecting the HDMI Interface
8.2.1 Design Requirements
In this design example, two ESD204 devices and one TPD4E05U06 device are used to protect an HDMI 2.0
interface. For HDMI 2.0 application design parameters listed in 表 1 are known.
表 1. Design Parameters
DESIGN PARAMETER
VALUE
0 to 3.6 V
Signal range on high speed differential data
lines
Operating frequency of high speed data lines
3 GHz (First Harmonic)
0 to 5 V
Signal range on control lines (CEC, UTILITY,
DDC_CLK and DDC_DAT)
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
ESD204 supports signal ranges between –3.6 V and 3.6 V, which supports the high-speed lines on the HDMI 2.0
application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports the HDMI control
lines.
8.2.2.2 Operating Frequency
The ESD204 has a 0.55 pF (typical) capacitance, which supports the HDMI 2.0 rate of 6 Gbps. The
TPD4E05U06 has a typical capacitance of 0.5 pF, which easily support the control lines. The ESD204 has 4
identical protection channels for the differential HDMI high-speed signal lines. The symmetrical pin out of the
device with a ground pin between the two differential signal pins makes it suitable for this application.
版权 © 2018, Texas Instruments Incorporated
9
ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
8.2.3 Application Curves
图 13. HDMI 2.0 6 Gbps Eye Diagram with ESD204
图 12. HDMI 2.0 6 Gbps EYE Diagram (Bare Board)
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10
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ESD204
www.ti.com.cn
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
10.2 Layout Examples
图 14. HDMI Type-A Transmitter Port Layout
版权 © 2018, Texas Instruments Incorporated
11
ESD204
ZHCSHP1A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD204DQAR
ACTIVE
USON
DQA
10
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CEG
CEY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD204DQAR
ESD204DQAR
USON
USON
DQA
DQA
10
10
3000
3000
180.0
180.0
8.4
9.5
1.23
1.18
2.7
0.6
4.0
4.0
8.0
8.0
Q1
Q1
2.68
0.72
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESD204DQAR
ESD204DQAR
USON
USON
DQA
DQA
10
10
3000
3000
203.2
189.0
196.8
185.0
33.3
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DQA0010A
USON - 0.55 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
0.55 MAX
SEATING PLANE
(0.13) TYP
0.08 C
0.05
0.00
5
6
4X 0.5
(R0.125)
2X
2
0.45
0.35
2X
0.1
C A
B
0.05
1
10
0.25
0.15
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A
B
0.43
0.30
10X
C
4220328/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
SYMM
2X (0.4)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220328/A 12/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
METAL
TYP
SYMM
2X (0.36)
8
3
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 3 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220328/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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