ESD224 [TI]
适用于 USB 和 HDMI 且具有 8V、16A TLP 钳位的四路 0.5pF、±3.6V、±12kV ESD 保护二极管;
| 型号： | ESD224 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 和 HDMI 且具有 8V、16A TLP 钳位的四路 0.5pF、±3.6V、±12kV ESD 保护二极管 二极管 |
| 文件： | 总22页 (文件大小：2051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
用于 HDMI 接口的 ESD224 低钳位 4 通道 ESD 保护器件
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
ESD224 是一款适用于高速 应用 （如 USB 3.0 和
HDMI 2.0）的双向 TVS ESD 保护二极管阵列。
ESD224 的额定 ESD 冲击消散值达到了 IEC 61000-4-
2（4 级）国际标准中规定的最高水平。ESD224 采用
片上差分匹配的串联元件提高下行 ESD 钳位性能，同
时能够保持高速接口的信号符合性。ESD224 片上
ESD 保护网络提供超低钳位性能和高差分带宽，使器
件符合 HDMI 2.0 标准，并且为下行 HDMI 器件提供稳
健的保护。
–
–
±12kV 接触放电
±15kV 气隙放电
•
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
2A (8/20µs)
IO 电容：
–
–
–
0.5pF（典型值）
•
•
•
符合 HDMI 2.0 标准
ESD224 采用符合行业标准的 USON-10 (DQA) 封
装。该封装 采用 0.5mm 引脚间距，能够简化实现并缩
短设计时间。
超低泄漏电流：0.1nA（典型值）
超低 ESD 钳位电压：在 16A TLP 下为 8V（系统
侧）
器件信息(1)
•
•
•
支持速率最高达 6Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
行业标准 DQA 封装
器件型号
ESD224
封装
封装尺寸（标称值）
USON (10) 2.50mm x 1.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
终端设备
典型应用原理图
–
–
–
–
机顶盒
电视和监视器
TMDS D2+
TMDS D2-
ESD224
便携式计算机和台式机
DVD、蓝光、多媒体播放器
TMDS D1+
TMDS D1-
•
接口
–
–
–
HDMI 2.0/1.4
TMDS D0+
TMDS D0-
以太网 10/100/1000Mbps
ESD224
To System
USB 3.0
TMDS CLK+
TMDS CLK-
TPD4E05U06
CEC
UTILITY
DDC_CLK
DDC_DAT
GND
P 5V0
HOTPLUG
TPD1E05U06
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSEB4
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings -JEDEC Specifications ........................ 4
6.3 ESD Ratings - IEC Specifications............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Parameter Measurement Setup ............................ 8
9
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Examples ................................................. 14
12 器件和文档支持 ..................................................... 15
12.1 文档支持 ............................................................... 15
12.2 接收文档更新通知 ................................................. 15
12.3 社区资源................................................................ 15
12.4 商标....................................................................... 15
12.5 静电放电警告......................................................... 15
12.6 术语表 ................................................................... 15
13 机械、封装和可订购信息....................................... 15
7
8
7.1 IEC 61000-4-2 System Level ESD Test Setup with
HDMI Driver for Clamping Voltage Measurement ..... 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
4 修订历史记录
Changes from Original (February 2018) to Revision A
Page
•
已更改 将产品状态从“预告信息”更改成了“生产数据” ............................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
5 Pin Configuration and Functions
DQA Package
10-Pin USON
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
NO.
3
Ground
Ground. Connect to ground. These pins are shorted internally.
ESD protected channel to be connected to the connector
GND
8
IO1_C
IO2_C
IO3_C
IO4_C
1
2
Connector Side I/O
4
5
System Side I/O Pin
corresponding to
IO4_C
IO4_S
IO3_S
IO2_S
IO1_S
6
7
System Side I/O Pin
corresponding to
IO3_C
To be connected to the system side
System Side I/O Pin
corresponding to
IO2_C
9
System Side I/O Pin
corresponding to
IO1_C
10
Copyright © 2018, Texas Instruments Incorporated
3
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Electrical Fast
IEC 61000-4-4 Peak Current at 25°C
Transient
80
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25°C
Peak Pulse
17
2
W
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25°C
TA
Operating free-air temperature
Storage temperature
-40
-65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings -JEDEC Specifications
VALUE
UNIT
Human body model (HBM), per
±2500
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
UNIT
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air Discharge, all pins
±12000
±15000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
-3.6
-40
NOM
MAX
UNIT
V
VIN
TA
Input voltage
3.6
Operating Free Air Temperature
125
°C
6.5 Thermal Information
ESD224
THERMAL METRIC(1)
DQA (USON)
10 PINS
173.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
109.6
77.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
14.3
ΨJB
77.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIO < 10 nA, across operating
temperature range
VRWM
VBRF
Reverse stand-off voltage
-3.6
3.6
V
Breakdown voltage, Pin 1, 2, 4, 5 to 3
IIO = 1 mA
5
7.9
-5
V
(1)
(GND)
Reverse breakdown voltage, pin 1, 2,
VBRR
IIO = -1 mA
IIO = 1 mA
-7.9
V
V
(1)
4, 5 to 3 (GND)
VHOLD
Holding voltage, pin1, 2, 4, 5 to 3
(GND) and 3 (GND) to pin 1, 2, 4, 5
6.3
(2)
Breakdown voltage, pin1, 2, 4, 5 to 3
(GND)
VHOLD-NEG
IIO = -1 mA
-6.3
7
V
V
V
V
(2)
IPP = 1 A, pin 1, 2, 4, 5 to 3 or
8(GND), GND to pin 1, 2, 4, 5
IPP = 5 A, pin 1, 2, 4, 5 to 3 or
8(GND), GND to pin 1, 2, 4, 5
VCLAMP
TLP Clamping voltage (Intrinsic)
9
IPP = 16 A, pin 1, 2, 4, 5 to 3 or
8(GND), GND to pin 1, 2, 4, 5
14
8-kV Contact discharge on pin 1, 2, 4,
5 with pin3 grounded. Voltage
waveform measured at pin 6, 7, 9, 10
with respect to GND
8
V
IEC 61000-4-2 30 ns Clamping
voltage (system side) assuming
system draws at least 3 A of current at
8 V. See measurement setup.
VCLAMP-IEC-
SYS
-8-kV Contact discharge on pin 1, 2, 4,
5 with pin3 grounded. Voltage
waveform measured at pin 6, 7, 9, 10
with respect to GND
-5
V
Pin 1, 2, 4, 5 to GND, 100 ns TLP
GND to Pin 1, 2, 4, 5 , 100 ns TLP
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
0.5
0.5
0.5
RDYN
Dynamic resistance
Ω
CLINE
Line capacitance, any IO to GND
Variation of line capacitance
0.6
pF
pF
CLINE1 - CLINE2, VIO = 0 V, Vp-p = 30
mV, f = 1 MHz
ΔCLINE
0.02
0.07
Line-to-line capacitnace between one
differential pair to another differnetial
pair
CCROSS
VIO = 0 V, Vrms = 30 mV, f = 1 MHz
0.28
pF
DC insertion loss at Ch1, Ch2, Ch3,
Ch4
S21DC
DC Insertion Loss
Leakage Current
0.3
0.1
dB
nA
Ileakage
VIO=±3.6 V, Pin 1,2,4,5 to Pin 3
10
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the
snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
版权 © 2018, Texas Instruments Incorporated
5
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
6.7 Typical Characteristics
32
28
24
20
16
12
8
32
28
24
20
16
12
8
4
4
0
0
-4
-4
0
2
4
6
8
10 12 14 16 18 20 22
Voltage (V)
0
2
4
6
8
10 12 14 16 18 20 22
Voltage (V)
D001
D002
图 1. Positive TLP Curve, Connector side IO Pin to GND
图 2. Negative TLP Curve, Connector side IO Pin to GND
(tp=100ns)
(Plotted as positive TLP from GND to IO, tp=100ns )
30
0
150
Voltage on Connector Side (V)
Voltage on System Side (V)
120
90
60
30
0
-30
-60
-90
-120
Voltage on Connector Side (V)
Voltage on System Side (V)
-30
-20 -10
-150
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
D003
D004
图 3. Clamping voltage waveform for +8kV IEC 61000-4-2
stress. See 图 11 for details.
图 4. Clamping voltage waveform for -8kV IEC 61000-4-2
stress. See 图 11 for details.
0.6
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
17.5
Current (A)
Power (W)
15
12.5
10
7.5
5
0.5
0.4
0.3
0.2
0.1
0
2.5
0
-0.3
-2.5
-20
0
20
40
60
80 100 120 140 160 180
Time (ms)
0
0.5
1
1.5
2
2.5
3
3.5
4
Bias Voltage (V)
EDS0D025
D009
图 5. IEC 61000-4-5 Surge Waveform (tp=8/20 µs)
图 6. Capacitance vs. Bias Voltage at 25 degree Celsius
6
版权 © 2018, Texas Instruments Incorporated
ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
Typical Characteristics (接下页)
2.2
2
0.00125
0.001
1.8
1.6
1.4
1.2
1
0.00075
0.0005
0.00025
0
0.8
0.6
0.4
0.2
0
-0.00025
-0.0005
-0.00075
-0.001
-0.2
-8
-6
-4
-2
0
2
4
6
8
-40
-20
0
20
40
60
80
100
120
Voltage (V)
Temperature èC
D007
D008
图 7. DC Voltage Sweep I-V Curve, IO Pin to GND
图 8. Leakage Current vs Temperature, IO Pin to GND, at 2.5
V Bias
0
-1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.01
0.1
Frequency (GHz)
1
10
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
Frequency (GHz)
D011
D010
图 9. Differential Insertion Loss
图 10. Capacitance vs Frequency
版权 © 2018, Texas Instruments Incorporated
7
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
7 Parameter Measurement Setup
7.1 IEC 61000-4-2 System Level ESD Test Setup with HDMI Driver for Clamping Voltage
Measurement
图 11 shows the setup used to perform System Level ESD test to evaluate the clamping performance of ESD224
in real-world applications where the device is protecting a downstream HDMI driver System-on-Chip. IEC 61000-
4-2 8kV Contact stress was applied at the connector pin and the voltage waveform on the system-side pin was
captured to look at the clamping voltage presented by ESD224 to the down stream HDMI driver.
SMA
Connector
0 Ω
IO1_C
IO2_C
GND
IO1_S
IO2_S
GND
ESD224
HDMI Driver
IO3_C
IO4_C
IO3_S
IO4_S
图 11. System Level IEC 61000-4-2 ESD Test Setup with ESD224 protecting an HDMI driver chip
8
版权 © 2018, Texas Instruments Incorporated
ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
8 Detailed Description
8.1 Overview
The ESD224 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate ESD
strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low
capacitance makes this device ideal for protecting any super high-speed signal pins.
8.2 Functional Block Diagram
IO1_C
IO1_S
IO2_S
IO3_S
IO2_C
IO3_C
IO4_C
IO4_S
Copyright © 2018, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. The ESD-surge clamp diverts
the current to ground.
8.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). The ESD-surge clamp diverts the current to ground.
8.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). The ESD-surge clamp diverts
this current to ground.
8.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.5 pF (typical). This device supports data rates up to 6
Gbps.
8.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of ±3.6 V.
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9
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
Feature Description (接下页)
8.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V.
8.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8 V (IPP = 16 A TLP) on the system
side pins when the system draws at least 3 A.
8.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 6 Gbps, because of the extremely low IO
capacitance.
8.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
8.4 Device Functional Modes
The ESD224 is a passive integrated circuit that triggers when voltages are above VBRF or below VBRR. During
ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. When the
voltages on the protected line fall below the trigger levels of ESD224 (usually within 100s of nano-seconds) the
device reverts to passive.
10
版权 © 2018, Texas Instruments Incorporated
ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ESD224 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-
speed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. Part of this voltage drop across the diode drops
across the series element between the connector side pin and the system-side pin. Therefore, the effective
voltage drop across the protected IC is smaller than the voltage drop across the diode. It is recommended to
avoid through-routing for this ESD diode (single trace connecting both the connector side pin and the system
side pin) for the best ESD performance.
9.2 Typical Application
TMDS D2+
TMDS D2-
ESD224
TMDS D1+
TMDS D1-
TMDS D0+
TMDS D0-
ESD224
To System
TMDS CLK+
TMDS CLK-
TPD4E05U06
CEC
UTILITY
DDC_CLK
DDC_DAT
GND
P 5V0
HOTPLUG
TPD1E05U06
Copyright © 2018, Texas Instruments Incorporated
图 12. ESD224 Protecting the HDMI Interface
版权 © 2018, Texas Instruments Incorporated
11
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
Typical Application (接下页)
9.2.1 Design Requirements
In this design example, two ESD224 devices, one TPD4E05U06 and one TPD1E05U06 device are used to
protect an HDMI 2.0 interface. For HDMI 2.0 application design parameters listed in 表 1 are known.
表 1. Design Parameters
DESIGN PARAMETER
VALUE
0 to 3.6 V
Signal range on high speed differential data lines
Operating frequency of high speed data lines
3 GHz (First Harmonic)
Signal range on control lines (CEC, UTILITY, DDC_CLK and
DDC_DAT)
0 to 5 V
9.2.2 Detailed Design Procedure
9.2.2.1 Signal Range
ESD224 supports signal ranges between –3.6 V and 3.6 V, which supports the high-speed lines on the HDMI 2.0
application. The TPD4E05U06 and TPD1E05U06 support signal ranges between 0 V and 5.5 V, which supports
the HDMI control lines.
9.2.2.2 Operating Frequency
The ESD224 has a 0.5 pF (typical) capacitance, which supports the HDMI 2.0 rate of 6 Gbps. The TPD4E05U06
and TPD1E05U06 have a typical capacitance of 0.5 pF and 0.42 pF respectively, which easily support the control
lines. The ESD224 has 4 identical protection channels for the differential HDMI high-speed signal lines. The
symmetrical pin out of the device with a ground pin between the two differential signal pins makes it suitable for
this application.
9.2.3 Application Curves
图 13. HDMI 2.0 6 Gbps Eye Diagram (Bare Board)
图 14. HDMI 2.0 6 Gbps Eye Diagram with ESD224
12
版权 © 2018, Texas Instruments Incorporated
ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
10 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (–3.6 V to 3.6 V) to ensure the device functions properly.
11 Layout
11.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
For the best ESD performance, do not use through-routing for the data channels. Connecting pins 1 and 10, 2
and 9, 4 and 7, 5 and 6 together with through routing will reduce the clamping voltage performance of
ESD224.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
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13
ESD224
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
www.ti.com.cn
11.2 Layout Examples
图 15. HDMI Type-A Transmitter Port Layout
注
There is no Through-Routing for the ESD224 Pins Connecting to the High Speed Data
Lines.
14
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ESD224
www.ti.com.cn
ZHCSHL9A –FEBRUARY 2018–REVISED MARCH 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：:
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD224DQAR
ACTIVE
USON
DQA
10
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1AR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD224DQAR
USON
DQA
10
3000
180.0
8.4
1.23
2.7
0.6
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
USON DQA 10
SPQ
Length (mm) Width (mm) Height (mm)
203.2 196.8 33.3
ESD224DQAR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DQA0010A
USON - 0.55 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
0.55 MAX
SEATING PLANE
(0.13) TYP
0.08 C
0.05
0.00
5
6
4X 0.5
(R0.125)
2X
2
0.45
0.35
2X
0.1
C A
B
0.05
1
10
0.25
0.15
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A
B
0.43
0.30
10X
C
4220328/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
SYMM
2X (0.4)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220328/A 12/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
METAL
TYP
SYMM
2X (0.36)
8
3
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 3 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220328/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
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