ESD2CANFD24 [TI]
具有 8/20µS 浪涌的双通道 2.5pF、±24V、±25kV ESD 保护二极管;
| 型号： | ESD2CANFD24 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8/20µS 浪涌的双通道 2.5pF、±24V、±25kV ESD 保护二极管 二极管 |
| 文件： | 总21页 (文件大小：1597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD2CANFD24
ZHCSR82 –NOVEMBER 2022
ESD2CANFD24 用于车载网络的24V、2 通道ESD 保护二极管
1 特性
3 说明
• IEC 61000-4-2 4 级ESD 保护：
ESD2CANFD24 是一款用于控制器局域网 (CAN) 接口
保护的双向 ESD 保护二极管。ESD2CANFD24 的额
定消散接触 ESD 冲击能力超过了 IEC 61000-4-2 标准
所规定的最高水平（±25kV 接触放电，±25kV 气隙放
电）。低动态电阻和低钳位电压支持针对瞬态事件提供
系统级保护。这种保护很关键，因为系统对安全应用的
稳健性和可靠性要求很高。
– ±25kV 接触放电
– ±25kV 气隙放电
• 经测试符合IEC 61000-4-5
• 24V 工作电压
• 双向ESD 保护
• 2 通道器件通过单个组件实现完整的ESD 保护
• 低钳位电压可保护下游组件
• I/O 电容= 2.5pF（典型值）
• SOT-23 (DBZ) 小型、标准、通用封装
• 引线式封装，用于自动光学检测(AOI)
该器件具有每通道低 IO 电容和引脚排列，以便适合两
条 CAN 总线（CANH 和 CANL），防止因静电放电
(ESD) 和其他瞬变造成损坏。此外，ESD2CANFD24
的 2.5pF（典型值）或更小线路电容适合 CAN、
CANFD、CAN SiC 和支持高达 10Mbps 数据速率的
CAN-XL 应用。
2 应用
• 工业控制网络：
ESD2CANFD24 采用引线式封装，以便轻松实现直通
式路由。
– DeviceNet IEC 62026-3
– CANopen –CiA 301/302-2 和EN 50325-4
封装信息(1)
封装尺寸（标称值）
器件型号
封装
ESD2CANFD24
DBZ（SOT-23，3） 2.92mm × 1.30mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
CANH
TXD
RT/2
Application
CAN
CAN
Bus
(for example,
TRANSCEIVER
MCU I/O)
RT/2
RXD
CANL
1
2
C
G
ESD2CANFD24
3
ESD2CANFD24 典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSH12
ESD2CANFD24
ZHCSR82 –NOVEMBER 2022
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Table of Contents
7.4 Device Functional Modes............................................9
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................12
10 Layout...........................................................................12
10.1 Layout Guidelines................................................... 12
10.2 Layout Example...................................................... 12
11 Device and Documentation Support..........................13
11.1 Documentation Support.......................................... 13
11.2 接收文档更新通知................................................... 13
11.3 支持资源..................................................................13
11.4 Trademarks............................................................. 13
11.5 Electrostatic Discharge Caution..............................13
11.6 术语表..................................................................... 13
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 绝对最大额定值...........................................................4
6.2 ESD 等级- JEDEC 规格............................................. 4
6.3 ESD 等级- IEC 规格...................................................4
6.4 建议运行条件.............................................................. 4
6.5 热性能信息..................................................................4
6.6 电气特性......................................................................5
6.7 Typical Characteristics –ESD2CANFD24.................6
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
Information.................................................................... 13
4 Revision History
DATE
REVISION
NOTES
November 2022
*
Initial Release
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5 Pin Configuration and Functions
IO
IO
1
2
3
GND
Not to scale
图5-1. DBZ Package, 3-Pin SOT-23 (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
IO
NO.
1, 2
3
I/O
G
ESD protected IO
Connect to ground.
GND
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
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6 Specifications
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
参数
器件
最小值
最大值
单位
PPP
IPP
TA
133
3.5
W
25°C 时的IEC 61000-4-5 功率(tp –8/20µs)
A
25°C 时的IEC 61000-4-5 电流(tp –8/20µs)
ESD2CANFD24
-55
-55
-65
150
150
155
自然通风工作温度
结温
TJ
°C
Tstg
贮存温度
(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条
件下能够正常运行。如果超出建议运行条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、
功能和性能并缩短器件寿命。
6.2 ESD 等级- JEDEC 规格
参数
测试条件
值
单位
人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001 标准(1)
充电器件模型(CDM)，符合JEDEC 规范JS-002(2)
± 2500
V(ESD)
V
静电放电
± 1000
(1) JEDEC 文档JEP155 指出：500V HBM 时能够在标准ESD 控制流程下安全生产。
(2) JEDEC 文档JEP157 指出：250V CDM 时能够在标准ESD 控制流程下安全生产。
6.3 ESD 等级- IEC 规格
在TA = 25°C 条件下（除非另有说明）
参数
测试条件
器件
值
单位
±25000
IEC 61000-4-2 接触放电，所有引脚
IEC 61000-4-2 空气间隙放电，所有引脚
V(ESD)
ESD2CANFD24
V
静电放电
±25000
6.4 建议运行条件
在自然通风条件下的工作温度范围内测得（除非另有说明）
参数
最小值
-24
标称值
最大值
24
单位
V
VIN
TA
输入电压
-55
150
°C
自然通风工作温度
6.5 热性能信息
ESD2CANFD24
DBZ (SOT-23)
3 引脚
热指标(1)
单位
RθJA
316.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
RθJC(top)
RθJB
170.7
结至外壳（顶部）热阻
结至电路板热阻
156.2
45.9
ΨJT
结至顶部特征参数
155.1
ΨJB
结至电路板特征参数
结至外壳（底部）热阻
RθJC(bot)
不适用
(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标应用报告。
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6.6 电气特性
在TA = 25°C 条件下（除非另有说明）(1)
参数
测试条件
器件
最小值 典型值 最大值 单位
VRWM
ESD2CANFD24
24
35.5
V
V
V
V
–24
25.5
反向关断电压
击穿电压(2)
击穿电压(2)
钳位电压(3)
IIO = 10mA、IO 至GND
VBRF
ESD2CANFD24
ESD2CANFD24
ESD2CANFD24
VBRR
-35.5
-25.5
IIO = –10mA、IO 至GND
VCLAMP
37
36
IPP = 3.5A，tp = 8/20µs，IO 到GND
IPP = 16A、TLP、IO 至GND 或GND 至
IO
钳位电压(4)
VCLAMP
ESD2CANFD24
V
ILEAK
RDYN
CL
ESD2CANFD24
ESD2CANFD24
ESD2CANFD24
ESD2CANFD24
-50
5
0.45
2.5
50
nA
VIO = ±24V、IO 至GND
IO 至GND 或GND 至IO
VIO = 0V、f = 1MHz、Vpp = 30mV
TLP
漏电流
动态电阻(4)
Ω
pF
V
线路电容(5)
4.2
VHold
30
快速复位后的保持电压
(1) 在每个IO 通道上进行的测量
(2) BRF 和VBRR 被定义为在器件锁存到快速复位状态之前，分别在正向和负向方向上施加±10mA 的电压
V
(3) 根据IEC 61000-4-5 器件承受8/20μs 指数衰减波形的应力
(4) 非重复电流脉冲、传输线路脉冲(TLP)；方波脉冲；ANSI / ESD STM5.5.1-2008
(5) 在每个通道上从IO 测量到GND
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6.7 Typical Characteristics –ESD2CANFD24
30
27
24
21
18
15
12
9
30
27
24
21
18
15
12
9
6
6
3
3
0
0
-3
-3
0
5
10
15
20 25
Vclamp (V)
30
35
40
45
0
5
10
15
20 25
Vclamp (V)
30
35
40
45
tp = 100 ns, Transmission Line Pulse (TLP)
tp = 100 ns, Transmission Line Pulse (TLP)
图6-2. Negative TLP Curve
图6-1. Positive TLP Curve
175
150
125
100
75
Vclamp_ESD at 30ns = 27.3V
50
25
0
-25
-100
0
100
200
300
400
500
600
700
Time(ns)
图6-3. +8-kV Clamped IEC Waveform
图6-4. −8-kV Clamped IEC Waveform
10
8
2.3
2.28
2.26
2.24
2.22
2.2
6
4
2
2.18
2.16
2.14
2.12
2.1
2.08
2.06
2.04
2.02
2
0
-2
-4
-6
-8
-10
-25 -20 -15 -10
-5
0
VR (V)
5
10
15
20
25
TA = 150 ꢀC
ILEAK is less than 1 nA at -55 ꢀC and 25 ꢀC.
-25 -20 -15 -10
-5
0
5
10
15
20
25
VR (V)
图6-5. Capacitance vs. Bias Voltage
图6-6. Leakage Current vs. Bias Voltage Across Temperature
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6.7 Typical Characteristics –ESD2CANFD24 (continued)
40
4
Voltage (V)
Current (A)
36
32
28
24
20
16
12
8
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
4
0
-5
0
5
10
15
20
25
30
35
40
45
Time (ꢀs)
图6-7. 8/20 μs Surge Response at 3.5 A
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7 Detailed Description
7.1 Overview
The ESD2CANFD24 is a dual-channel ESD TVS diode in SOT-23 leaded package which is convenient for
automatic optical inspection. This product offers IEC 61000-4-2 ±25-kV air-gap, ±25-kV contact ESD protection,
and has a clamp circuit with a back-to-back TVS diode for bidirectional signal support. The 2.5 pF (typical) or
less line capacitance of this ESD protection diode is suitable for CAN, CANFD, CAN SiC, and CAN-XL
applications that can support data rates up to 10 Mbps. A typical application for this product is ESD circuit
protection for CAN transceivers.
7.2 Functional Block Diagram
1
2
3
7.3 Feature Description
The ESD2CANFD24 is a bidirectional TVS with a high ESD protection level. This device protects the circuit from
ESD strikes up to ±25-kV contact and ±25-kV air-gap specified in the IEC 61000-4-2 standard. The device can
also handle up to 3.5 A surge current (IEC 61000-4-5 8/20 µs). The I/O capacitance of 2.5-pF (typical) supports
a data rate up to 10 Mbps. This clamping device has a small dynamic resistance, which makes the clamping
voltage low when the device is actively protecting other circuits. For example, the clamping voltage is only 37 V
when the device is taking 3.5 A transient surge current. The breakdown is bidirectional so this protection device
is a good fit for CAN which is a differential signal. Low leakage allows the diode to conserve power when working
below the VRWM. The temperature range of −55°C to +150°C makes this ESD device work at extensive
temperatures in most environments. The leaded SOT-23 package is good for applications requiring automatic
optical inspection (AOI).
7.3.1 Temperature Range
This device is qualified to operate from –55°C to +150°C.
7.3.2 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events of at least ±25-kV contact and ±25-kV air-gap in the leaded SOT-23
package according to the IEC 61000-4-2 standard. An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 3.5 A (8/20 µs waveform). An ESD-surge clamp diverts this
current to ground.
7.3.4 IO Capacitance
The capacitance between the I/O pins is 2.5 pF (typical) or less. This capacitance supports data rates for CAN,
CANFD, CAN SiC, and CAN-XL up to 10 Mbps.
7.3.5 Dynamic Resistance
The IO pins feature an ESD clamp that has a low RDYN of 0.45 Ω (Pin 1 or Pin 2 to Pin 3) and 0.45 Ω (Pin 3 to
Pin 1 or Pin 2) or less which prevents system damage during ESD events.
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7.3.6 DC Breakdown Voltage
The DC breakdown voltage between the IO pins is a minimum of ± 25.5 V. This protects sensitive equipment
from surges above the reverse standoff voltage of ± 24 V.
7.3.7 Ultra Low Leakage Current
The IO pins feature an ultra-low leakage current of ± 50 nA (maximum) with a bias of ± 24 V.
7.3.8 Clamping Voltage
The IO pins feature an ESD clamp that is capable of clamping the voltage to 37 V (IPP = 3.5 A) and 36 V (IPP
16 A for TLP).
=
7.3.9 Industry Standard Leaded Packages
This device features an industry standard SOT-23 (DBZ) leaded package for automatic optical inspection (AOI).
7.4 Device Functional Modes
The ESD2CANFD24 is a dual channel passive clamp that has low leakage during normal operation when the
voltage between pin 1 or pin 2 and pin 3 is below VRWM, and activates when the voltage between pin 1 or pin 2
and pin 3 goes above VBR. During IEC 61000-4-2 ESD events, transient voltages as high as ±25 kV can be
clamped on either channel. When the voltages on the protected lines fall below the VHOLD, the device reverts
back to the low leakage passive state.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ESD2CANFD24 is a dual channel TVS diode which is used to provide a path to ground for dissipating ESD
events on differential CAN signal lines. As the current from ESD passes through the TVS, only a small voltage
drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered
TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
CANH
TXD
RT/2
Application
(for example,
MCU I/O)
CAN
Bus
CAN
TRANSCEIVER
RT/2
RXD
CANL
1
2
C
G
ESD2CANFD24
3
图8-1. ESD2CANFD24 Typical Application
8.2.1 Design Requirements
For this design example, the ESD2CANFD24 is used to provide ESD protection for a CAN transceiver. 表 8-1
lists the known design parameters for this application.
表8-1. Design Parameters for the ESD2CANFD24 Typical Application
Design Parameter
Diode configuration
VIO differential signal range
VRWM
Value
Bidirectional
> ±1.5 V
±24 V
Data rate
Up to 10 Mbps
60 Ω
RT/2
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8.2.2 Detailed Design Procedure
The ESD2CANFD24 has a VRWM of ±24 V. The bidirectional characteristic enables the signal integrity of the
differential CAN lines to not be impacted by the diode. The low capacitance of 2.5 pF (typical) or less enables
data rates up to 10 Mbps, which allows the designer to meet the requirements for CAN, CANFD, CAN SiC, and
CAN-XL. The 60 Ω split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines.
8.2.3 Application Curves
175
150
125
100
75
Vclamp_ESD at 30ns = 27.3V
50
25
0
-25
-100
0
100
200
300
400
500
600
700
Time(ns)
图8-2. +8-kV Clamped IEC Waveform
图8-3. −8-kV Clamped IEC Waveform
40
36
32
28
24
20
16
12
8
4
Voltage (V)
Current (A)
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
4
0
-5
0
5
10
15
20
Time (ꢀs)
25
30
35
40
45
图8-4. 8/20 µs Surge Response at 3.5 A
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9 Power Supply Recommendations
This device is a passive TVS diode-based ESD protection device, therefore there is no requirement to power it.
Ensure that the maximum voltage specifications for each pin are not violated.
10 Layout
10.1 Layout Guidelines
• The optimum placement of the device is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
• If pin 3 is connected to ground, use a thick and short trace for this return path.
10.2 Layout Example
This example is typical of a dual channel differential data pair application, such as CAN.
IO1
GND
IO2
= VIA to GND
图10-1. Routing with DBZ Package
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, ESD Layout Guide user's guide
• Texas Instruments, ESD Protection Diodes EVM user's guide
• Texas Instruments, Generic ESD Evaluation Module user's guide
• Texas Instruments, Reading and Understanding an ESD Protection data sheet
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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13
Product Folder Links: ESD2CANFD24
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD2CANFD24DBZR
ACTIVE
SOT-23
DBZ
3
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-50 to 150
2QO8
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ESD2CANFD24 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2022
Automotive : ESD2CANFD24-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD2CANFD24DBZR
SOT-23
DBZ
3
3000
180.0
8.4
2.9
3.35
1.35
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBZ
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
ESD2CANFD24DBZR
3
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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