ESD321DPYR [TI]
适用于 USB 2.0、采用 0402 封装且具有 6.8V、16A TLP 钳位的 0.8pF、3.3V、±30kV ESD 保护二极管 | DPY | 2 | -40 to 125;
| 型号： | ESD321DPYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 2.0、采用 0402 封装且具有 6.8V、16A TLP 钳位的 0.8pF、3.3V、±30kV ESD 保护二极管 | DPY | 2 | -40 to 125 局域网 光电二极管 |
| 文件： | 总25页 (文件大小：1438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD321
ZHCSIK7A –JULY 2018 –REVISED DECEMBER 2022
ESD321 采用0402 和SOD-523 封装的
低电容（小于1pF）单通道30kV ESD 保护二极管
1 特性
3 说明
• IEC 61000-4-2 级4 ESD 保护
ESD321 是一款单向 TVS ESD 保护二极管，具有低动
态电阻和低钳位电压。ESD321 的额定 ESD 冲击消散
值高达±30kV，符合IEC 61000-4-2 国际标准（高于4
级）。
– ±30kV 接触放电
– ±30kV 空气间隙放电
• IEC 61000-4-4 EFT 保护
– 80A (5/50ns)
• IEC 61000-4-5 浪涌保护
– 6A (8µs/20µs)
• IO 电容：0.9pF（典型值）
• 直流击穿电压：4.5V（最小值）
• 低漏电流：0.1nA（典型值）
• 极低ESD 钳位电压
超低动态电阻 (0.13Ω) 和极低钳位电压（16A TLP 时
为 6.8V）可针对瞬态事件提供系统级保护。该器件具
有0.9pF 的低IO 电容，适合用于保护USB 2.0 和以太
网10/100/1000Mbps 等接口。
ESD321 采用业界通用的 0402 (DPY/DFN1006P2) 和
SOD-523 (DYA) 封装。
封装信息(1)
– 在16A TLP 下为6.8V（I/O 至GND）
– RDYN：0.13Ω（I/O 至GND）
封装尺寸（标称值）
器件型号
封装
• 工业温度范围：–40°C 至+125°C
• 业界通用的0402 (DFN1006P2) 和SOD-523 封装
DPY（X1SON，2） 0.60mm x 1.00mm
ESD321
DYA（SOD-532，
2）
0.80mm × 1.20mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 终端设备：
– 可穿戴设备
– 工业和服务机器人
– 便携式计算机和台式机
– 手机和平板电脑
– 机顶盒
– DVR 和NVR
– 电视和监视器
– EPOS（电子销售点）
• 接口：
– USB 2.0/1.1
– 通用输入/输出(GPIO)
– 以太网10/100/1000Mbps
– 按钮
– 音频
5-V Source
VBUS
Dœ
USB Transceiver
D+
1
1
GND
2
2
USB 2.0 典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEN8
ESD321
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ZHCSIK7A –JULY 2018 –REVISED DECEMBER 2022
Table of Contents
7.4 Device Functional Modes............................................8
8 Application and Implementation....................................9
8.1 Application Information............................................... 9
8.2 Typical Application...................................................... 9
9 Power Supply Recommendations................................11
10 Layout...........................................................................12
10.1 Layout Guidelines................................................... 12
10.2 Layout Example...................................................... 12
11 Device and Documentation Support..........................13
11.1 Documentation Support.......................................... 13
11.2 接收文档更新通知................................................... 13
11.3 支持资源..................................................................13
11.4 Trademarks............................................................. 13
11.5 Electrostatic Discharge Caution..............................13
11.6 术语表..................................................................... 13
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings –JEDEC Specifications.......................4
6.3 ESD Ratings –IEC Specifications.............................4
6.4 Recommended Operating Conditions.........................4
6.5 Thermal Information....................................................4
6.6 Electrical Characteristics.............................................5
6.7 Typical Characteristics................................................6
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
Information.................................................................... 13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2018) to Revision A (December 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 向数据表添加了DYA 封装.................................................................................................................................. 1
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5 Pin Configuration and Functions
1
2
图5-1. DPY Package, 2-Pin X1SON (Top View)
ID Area
1
2
图5-2. DYA Package, 2-Pin SOD-523 (Top View)
表5-1. Pin Functions
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DPY
DYA
IO
1
2
2
1
I/O
ESD Protected Channel. Connect to the line being protected.
Connect to ground
GND
GND
(1) I = input, O = output, GND = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Electrical Fast
IEC 61000-4-4 Peak Current at 25 °C
Transient
80
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25 °C
Surge Pulse
40
6
W
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25 °C
TA
Operating free-air temperature
Storage temperature
125
155
°C
°C
–40
–65
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings –JEDEC Specifications
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings –IEC Specifications
VALUE
UNIT
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air Discharge, all pins
±30000
±30000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
UNIT
V
VIN
TA
Input voltage
3.6
Operating Free Air Temperature
125
°C
–40
6.5 Thermal Information
ESD321
THERMAL METRIC (1)
DYA (SOD-523)
2 Pins
774.7
DPY (X1SON)
2 Pins
437.8
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
462.3
249.5
541.1
169.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
164.4
99.3
534.6
168.6
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIO < 50 nA, across operating
temperature range
VRWM
Reverse stand-off voltage
3.6
V
ILEAKAGE
VBRF
Leakage current at 3.6 V
VIO = 3.6 V, I/O to GND
IIO = 1 mA
0.1
10
nA
V
Breakdown voltage, I/O to GND (1)
Forward Voltage, GND to I/O (1)
Holding voltage, I/O to GND (2)
4.5
7.5
VFWD
IIO = 1 mA
0.8
5.1
6.3
6.8
4.7
V
VHOLD
IIO = 1 mA
V
IPP = 6 A (8/20 µs Surge), I/O to GND
IPP = 16 A (100 ns TLP), I/O to GND
IPP = 16 A (100 ns TLP), GND to I/O
V
VCLAMP
Clamping voltage
V
V
I/O to GND, 100 ns TLP, between 10
to 20 A IPP
0.13
RDYN
Dynamic resistance
Ω
GND to I/O , 100 ns TLP, between 10
to 20 A IPP
0.2
0.9
CLINE
Line capacitance, IO to GND
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
1.1
pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the
snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
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6.7 Typical Characteristics
32
28
24
20
16
12
8
4
0
-4
-8
-12
-16
-20
-24
-28
-32
4
0
-4
0
1
2
3
4
5
Volatge (V)
6
7
8
9
10
-8
-7
-6
-5
-4
Voltage (V)
-3
-2
-1
0
D001
D002
D001_TLP_IO_GND.grf
D002_TLP_GND_IO.grf
图6-1. TLP I-V Curve, I/O Pin to GND (tp = 100 ns)
图6-2. TLP I-V Curve, GND to I/O Pin (tp = 100 ns)
60
10
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-10
-10
0
10
20
30
40
Time (ns)
50
60
70
80
90
-10
0
10
20
30
40
Time (ns)
50
60
70
80
90
D003
D004
D003_8kV_pos.grf
D004_8kV_neg.grf
图6-3. 8-kV IEC 61000-4-2 Clamping Voltage Waveform, I/O Pin 图6-4. 8-kV IEC 61000-4-2 Clamping Voltage Waveform, GND to
to GND I/O Pin
0.001
0.0005
0
45
40
35
30
25
20
15
10
5
Current (A)
Power (W)
-0.0005
-0.001
0
-5
-1
0
1
2
3
Voltage (V)
4
5
6
7
-20
0
20
40
60
80 100 120 140 160 180
Time (ms)
D005
D006
D005_DC_Plot.grf
D006_Surge.grf
图6-5. DC Voltage Sweep I-V Curve, I/O Pin to GND
图6-6. Surge Curve (IEC 61000-4-5, tp=8/20 µs), I/O Pin to GND
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6.7 Typical Characteristics (continued)
2
20
18
16
14
12
10
8
-40
25
85
1.6
1.2
0.8
0.4
0
6
4
2
0
0
0.4 0.8 1.2 1.6
2
Bias Voltage (V)
2.4 2.8 3.2 3.6
4
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D007
D008
D007_Cap_Bias.grf
D008_Leakage_Temp.grf
图6-7. Capacitance vs. Bias Voltage For Different Temperatures 图6-8. Leakage Current (at 3.6 V Bias) Across Temperature, I/O
(°C)
Pin to GND
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
0.1
0.2 0.3
0.5 0.7 1
Frequency (GHz)
2
3
4 5 6 7 8 10
D009
D009_S21.grf
图6-9. Insertion Loss vs. Frequency
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7 Detailed Description
7.1 Overview
The ESD321 is a low capacitance uni-directional ESD Protection Diode with a low clamping voltage. This device
can dissipate ESD strikes up to ±30 kV (Contact and Air) per the IEC 61000-4-2 Standard. The low clamping
makes this device suitable for protecting any ESD sensitive devices.
7.2 Functional Block Diagram
7.3 Feature Description
ESD321 provides ESD protection up to ±30-kV contact and ±30-kV air gap per IEC 61000-4-2 standard. During
an ESD event, ESD diode connected to the I/O pin turns on and diverts the current to ground. Additionally,
ESD321 also provides protection against IEC 61000-4-5 Surge currents up to 6 A (8/20 µs waveform) and up to
80 A per IEC 61000-4-4 (5/50 ns waveform, 4 kV with 50-Ω impedance) electrical fast transient (EFT) standard.
The capacitance between the I/O pin and ground is 0.9 pF (typical) and 1.1 pF (maximum). The device features
a low leakage current of 0.1 nA (typical) and 50 nA (maximum, across operating temperature range) with a bias
of 3.6 V. The ESD diode at the I/O pin protects the ESD-sensitive devices by clamping the voltage to a low value
of 6.8 V (IPP = 16 A 100 ns TLP ). The layout of this device makes it simple and easy to add protection to an
existing layout. The package offers flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The ESD321 is a passive integrated circuit that triggers when voltages are above VBRF or below VFWD. During
ESD events, voltages as high as ±30 kV (contact or air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of ESD321 (usually within 10s of nano-
seconds) the device reverts to passive.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The ESD321 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-
speed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
5-V Source
VBUS
Dœ
USB Transceiver
D+
GND
1
2
1
2
图8-1. USB 2.0 ESD Schematic
8.2.1 Design Requirements
For this design example, two ESD321 devices are being used in a USB 2.0 application. This provides a
complete ESD protection scheme.
Given the USB 2.0 application, the parameters listed in 表8-1 are known.
表8-1. Design Parameters
DESIGN PARAMETER
Signal range on DP-DM lines
VALUE
0 V to 3.6 V
up to 240 MHz
Operating frequency on DP-DM lines
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The ESD321 supports signal ranges between 0 V and 3.6 V, which supports the USB 2.0 signal pair on the USB
2.0 application.
8.2.2.2 Operating Frequency
The ESD321 has a 0.9 pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps.
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8.2.3 Application Curve
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
0.1
0.2 0.3
0.5 0.7 1
Frequency (GHz)
2
3
4 5 6 7 8 10
D009
D009_S21.grf
图8-2. Insertion Loss Vs. Frequency
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9 Power Supply Recommendations
The ESD321 is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (0 V to 3.6 V) to ensure the device functions properly.
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10 Layout
10.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
VBUS
To power supply
ESD321
D-
To USB transceiver
D+
ESD321
Legend
Pin to GND
GND
USB2.0 Connector
图10-1. USB 2.0 ESD Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Generic ESD Device Evaluation Module
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD321DPYR
ESD321DYAR
ACTIVE
ACTIVE
X1SON
DPY
DYA
2
2
10000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-3-260C-168 HR
-40 to 125
-55 to 150
(A5, DD)
1L8
Samples
Samples
SOT-5X3
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD321DPYR
ESD321DYAR
X1SON
DPY
2
2
10000
3000
178.0
178.0
8.4
9.5
0.7
0.5
1.15
1.94
0.47
0.73
2.0
2.0
8.0
8.0
Q1
Q1
SOT-5X3 DYA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESD321DPYR
ESD321DYAR
X1SON
DPY
DYA
2
2
10000
3000
205.0
210.0
200.0
200.0
33.0
42.0
SOT-5X3
Pack Materials-Page 2
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
1.3
1.1
0.3
0.1
0.7
0.5
B
2X
TYP
0.77 MAX
C
SEATING PLANE
0.05 C
0.15
2X
0.08
SYMM
SYMM
0.35
0.25
2X
0.1
0.05
C A B
0.4
0.2
2X
4224978/B 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEITA SC-79 registration except for package height
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224978/B 09/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/B 09/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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