ESD351 [TI]
适用于 USB 2.0、采用 0402 封装且具有 6.5V、16A TLP 钳位的 1.8pF、3.3V、±30kV ESD 保护二极管;
| 型号： | ESD351 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 2.0、采用 0402 封装且具有 6.5V、16A TLP 钳位的 1.8pF、3.3V、±30kV ESD 保护二极管 二极管 |
| 文件： | 总20页 (文件大小：868K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ESD351
ZHCSIK8 –JULY 2018
采用 0402 封装的低钳位电压 ESD351 单通道 30kV ESD
保护二极管
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
ESD351 是一种单向 TVS ESD 保护二极管，具有低动
态电阻 RDYN 和低钳位电压。ESD351 的额定 ESD 冲
击消散值高达 30kV（接触放电和空气放电），级别符
合 IEC 61000-4-2 标准。超低动态电阻 (0.1Ω) 和极低
钳位电压（16A TLP 时为 6.5V）可针对瞬变事件提供
系统级保护。该器件的电容为 1.8pF（典型值），因此
非常适用于保护 USB 2.0 等接口。
–
–
±30kV 接触放电
±30kV 气隙放电
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
6A (8µs/20µs)
–
–
•
•
•
•
IO 电容：1.8pF（典型值）
直流击穿电压：4.5V（最小值）
低泄漏电流 0.1nA（典型值）
极低 ESD 钳位电压
ESD351 采用符合行业标准的 0402
(DPY/DFN1006P2) 封装。
器件信息(1)
器件编号
ESD351
封装
X1SON (2)
封装尺寸（标称值）
–
–
在 16A TLP 下为 6.5V（I/O 引脚至 GND）
DYN：0.1Ω（I/O 引脚至 GND）
0.60mm x 1.00mm
R
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
•
•
工业温度范围：-40°C 至 +125°C
行业标准的 0402 封装 (DFN1006P2)
典型的 USB 2.0 应用原理图
2 应用
5-V Source
•
终端设备
VBUS
–
–
–
–
–
–
可穿戴产品
Dœ
工业和服务机器人
便携式计算机和台式机
手机和平板电脑
机顶盒
USB Transceiver
D+
GND
1
2
1
2
数字视频录像机 (DVR) 和网络视频录像机
(NVR)
–
–
电视和监视器
EPOS（电子销售终端）
•
接口
–
–
–
–
USB 2.0/1.1
通用输入/输出 (GPIO)
按钮
音频
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEO3
ESD351
ZHCSIK8 –JULY 2018
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 11
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings -JEDEC Specifications ........................ 4
6.3 ESD Ratings - IEC Specifications............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
10 Layout................................................................... 11
10.1 Layout Guidelines ................................................. 11
10.2 Layout Example .................................................... 11
11 器件和文档支持 ..................................................... 12
11.1 文档支持................................................................ 12
11.2 接收文档更新通知 ................................................. 12
11.3 社区资源................................................................ 12
11.4 商标....................................................................... 12
11.5 静电放电警告......................................................... 12
11.6 术语表 ................................................................... 12
12 机械、封装和可订购信息....................................... 12
7
4 修订历史记录
日期
修订版本
说明
2018 年 7 月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
ESD351
www.ti.com.cn
ZHCSIK8 –JULY 2018
5 Pin Configuration and Functions
DPY Package
2-Pin X1SON
Top View
1
2
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
IO
1
2
I/O
ESD Protected Channel. Connect this pin to the line being protected.
Connect this pin to Ground
GND
GND
Copyright © 2018, Texas Instruments Incorporated
3
ESD351
ZHCSIK8 –JULY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Electrical Fast
IEC 61000-4-4 Peak Current at 25 °C
Transient
80
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Power at 25 °C
Surge Pulse
36
6
W
A
IEC 61000-4-5 Surge (tp 8/20 µs) Peak Current at 25 °C
TA
Operating free-air temperature
Storage temperature
–40
–65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings -JEDEC Specifications
VALUE
UNIT
Human body model (HBM), per
±2500
ANSI/ESDA/JEDEC JS-001, allpins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
UNIT
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air Discharge, all pins
±30000
±30000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
UNIT
V
VIN
TA
Input voltage
3.6
Operating Free Air Temperature
–40
125
°C
6.5 Thermal Information
ESD351
THERMAL METRIC(1)
DPY (X1SON)
2 PINS
409.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
216.8
140.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
81.4
ΨJB
140.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
ESD351
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ZHCSIK8 –JULY 2018
6.6 Electrical Characteristics
At TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIO < 50 nA, across operating
temperature range
VRWM
Reverse stand-off voltage
3.6
V
ILEAKAGE
VBRF
Leakage current at 3.6 V
VIO = 3.6 V, I/O to GND
IIO = 1 mA
0.1
10
nA
V
(1)
Breakdown voltage, I/O to GND
4.5
7.5
(1)
VFWD
Forward Voltage, GND to I/O
IIO = 1 mA
0.8
5.1
6.1
6.5
2.5
V
(2)
VHOLD
Holding voltage, I/O to GND
IIO = 1 mA
V
IPP = 6 A (8/20 µs Surge), I/O to GND
IPP = 16 A (100 ns TLP), I/O to GND
IPP = 16 A (100 ns TLP), GND to I/O
V
VCLAMP
Clamping voltage
V
V
I/O to GND, 100 ns TLP, between 10
to 20 A IPP
0.1
RDYN
Dynamic resistance
Ω
GND to I/O , 100 ns TLP, between 10
to 20 A IPP
0.08
1.8
CLINE
Line capacitance, IO to GND
VIO = 0 V, Vp-p = 30 mV, f = 1 MHz
2.2
pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback
state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.
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ZHCSIK8 –JULY 2018
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6.7 Typical Characteristics
32
28
24
20
16
12
8
4
0
-4
-8
-12
-16
-20
-24
-28
-32
4
0
-4
0
1
2
3
4
5
6
7
8
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
Voltage (V)
Voltage (V)
D001
D002
D001_Positive_TLP.grf
D002_Negative_TLP.grf
图 1. TLP I-V Curve, I/O Pin to GND (tp = 100 ns)
图 2. TLP I/V Curve, GND to I/O Pin (tp = 100 ns)
40
35
30
25
20
15
10
5
5
0
-5
-10
-15
-20
-25
-30
0
-5
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
Time (ns)
Time (ns)
D003
D004
D003_Positive_IEC.grf
D004_Negative_IEC.grf
图 3. 8-kV IEC 61000-4-2 Clamping Voltage, I/O pin to GND
图 4. 8-kV IEC 61000-4-2 Clamping Voltage, GND to I/O Pin
45
0.001
0.0008
0.0006
0.0004
0.0002
0
Current (A)
Power (W)
40
35
30
25
20
15
10
5
-0.0002
-0.0004
-0.0006
-0.0008
-0.001
0
-5
-20
0
20
40
60
80 100 120 140 160 180
Time (ms)
-1
0
1
2
3
4
5
6
7
Voltage (V)
D005
D006
D005_Surge.grf
D006_DC.grf
图 5. Surge Curve (IEC 61000-4-5, tp = 8/20 µs), I/O Pin to
图 6. DC IV-Curve, I/O Pin to GND
GND
3.5
3
3.2
2.8
2.4
2
-40
25
85
125
2.5
2
1.5
1
1.6
1.2
0.8
0.4
0.5
0
-40
-20
0
20
40
60
80
100 120 140
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
Temperature (°C)
Bias Voltage (V)
D007
D008
D007_Leakage.grf
D008_Cap.grf
图 7. Leakage Current at 3.6 V Bias Voltage Across
图 8. Capacitance Vs. Bias Voltage at Different
Temperature, I/O Pin to GND
Temperatures (°C)
6
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ESD351
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ZHCSIK8 –JULY 2018
Typical Characteristics (接下页)
0
-1
-2
-3
-4
-5
-6
-7
0.1
0.2 0.3 0.4 0.5 0.7
1
2
3
4
5
Frequency (GHz)
D009
D009_InsertionLoss.grf
图 9. Insertion Loss Vs. Frequency
版权 © 2018, Texas Instruments Incorporated
7
ESD351
ZHCSIK8 –JULY 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ESD351 is a uni-directional ESD Protection Diode with 30 kV IEC 61000-4-2 level (Contact and Air) with
ultra-low clamping voltage in a 1 mm × 0.6 mm package. The ultra-low clamping makes this device capable of
protecting any ESD-sensitive pins.
7.2 Functional Block Diagram
7.3 Feature Description
ESD351 provides ESD protection up to ±30-kV contact and ±30-kV air gap per IEC 61000-4-2 standard. During
an ESD event, ESD diode connected to the I/O pin turns on and diverts the current to ground. Additionally,
ESD351 also provides protection against IEC 61000-4-5 Surge currents up to 6 A (8/20µs waveform) and up to
80 A per IEC 61000-4-4 (5/50 ns waveform, 4 kV with 50-Ω impedance) electrical fast transient (EFT) standard.
The capacitance between the I/O pin and ground is 1.8 pF (typical) and 2.2 pF (maximum). The device features
a low leakage current of 0.1 nA (typical) and 50 nA (maximum, across operating temperature range) with a bias
of 3.6 V. The ESD diode at the I/O pin protects the ESD-sensitive devices by clamping the voltage to a low value
of 6.5 V (IPP = 16 A 100 ns TLP ). The layout of this device makes it simple and easy to add protection to an
existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The ESD351 is a passive integrated circuit that triggers when voltages are above VBRF or below VFWD. During
ESD events, voltages as high as ±30 kV (contact or air) can be directed to ground via the internal diode network.
When the voltages on the protected line fall below the trigger levels of ESD351 (usually within 10s of nano-
seconds) the device reverts to passive.
8
版权 © 2018, Texas Instruments Incorporated
ESD351
www.ti.com.cn
ZHCSIK8 –JULY 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ESD351 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on high-
speed signal lines between a human interface connector and a system. As the current from ESD passes through
the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
5-V Source
VBUS
Dœ
USB Transceiver
D+
GND
1
2
1
2
图 10. USB 2.0 ESD Schematic
8.2.1 Design Requirements
For this design example, two ESD351 devices are being used in a USB 2.0 application. This provides a complete
ESD protection scheme.
Given the USB 2.0 application, the parameters listed in 表 1 are known.
表 1. Design Parameters
DESIGN PARAMETER
Signal range on DP-DM lines
VALUE
0 V to 3.6 V
up to 240 MHz
Operating frequency on DP-DM lines
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The ESD351 supports signal ranges between 0 V and 3.6 V, which supports the USB 2.0 signal pair on the USB
2.0 application.
8.2.2.2 Operating Frequency
The ESD351 has a 1.8 pF (typical) capacitance, which supports the USB 2.0 data rates of 480 Mbps.
版权 © 2018, Texas Instruments Incorporated
9
ESD351
ZHCSIK8 –JULY 2018
www.ti.com.cn
8.2.3 Application Curve
0
-1
-2
-3
-4
-5
-6
-7
0.1
0.2 0.3 0.4 0.5 0.7
1
2
3
4
5
Frequency (GHz)
D009
D009_InsertionLoss.grf
图 11. Insertion Loss
10
版权 © 2018, Texas Instruments Incorporated
ESD351
www.ti.com.cn
ZHCSIK8 –JULY 2018
9 Power Supply Recommendations
The ESD351 is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification (0 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
VBUS
To power supply
ESD351
D-
To USB transceiver
D+
ESD351
Legend
Pin to GND
GND
USB2.0 Connector
图 12. USB 2.0 ESD Layout
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ZHCSIK8 –JULY 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
《通用 ESD 器件评估模块》，SLVUBG5
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
12
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD351DPYR
ACTIVE
X1SON
DPY
2
10000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(A5, DE)
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD351DPYR
X1SON
DPY
2
10000
178.0
8.4
0.7
1.15
0.47
2.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
X1SON DPY
SPQ
Length (mm) Width (mm) Height (mm)
205.0 200.0 33.0
ESD351DPYR
2
10000
Pack Materials-Page 2
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号：
ESD351DPYR
适用于 USB 2.0、采用 0402 封装且具有 6.5V、16A TLP 钳位的 1.8pF、3.3V、±30kV ESD 保护二极管 | DPY | 2 | -40 to 125
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