ESD751 [TI]
适用于 LIN 和车载网络的 2.5pF、±24V、±22kV ESD 保护二极管;
| 型号： | ESD751 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 LIN 和车载网络的 2.5pF、±24V、±22kV ESD 保护二极管 二极管 |
| 文件： | 总24页 (文件大小：1532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD751, ESD761
ZHCSR66C –NOVEMBER 2022 –REVISED DECEMBER 2022
ESD751 和ESD761 24V 单通道ESD 保护二极管
1 特性
3 说明
• IEC 61000-4-2 4 级ESD 保护：
ESD751 和 ESD761 是适用于 USB 电力输送 (USB-
PD) 的单通道低电容双向 ESD 保护器件。这些器件旨
在耗散超过 IEC 61000-4-2 国际标准所规定最高水平
（分别为 ±22kV 接触放电、±22kV 气隙放电，以及
±15kV 接触放电、±15kV 气隙放电）的接触 ESD 冲
击。低动态电阻和低钳位电压有助于保护系统免受瞬态
事件的影响。这种保护至关重要，因为工业系统对鲁棒
性和可靠性的要求很高。
– ±22kV 或±15kV 接触放电
– ±22kV 或±15kV 气隙放电
• 强大的浪涌保护：
– IEC 61000-4-5 (8/20µs)：2.8A 或1.8A
• 24V 工作电压
• 双向ESD 保护
• 低钳位电压可保护下游元件
封装信息(1)
• 温度范围：–55°C 至+150°C
• I/O 电容= 1.6pF 或1.1pF（典型值）
• 采用标准引线式封装和0402 尺寸封装：SoD-523
(DYA) 和X1SON (DPY)
器件型号
ESD751
ESD761
封装
封装尺寸（标称值）
1.60mm × 0.80mm
1.00mm × 0.60mm
DYA（SOD-523，2）
DPY（X1SON，2）
• 引线式封装，用于自动光学检测(AOI)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
• USB 电力传输(USB-PD)
– VBUS 保护
– I/O 保护
• 工业控制网络：
– DeviceNet
– 智能配电系统
– 4/20mA 电路
– PLC 浪涌保护
– ADC 浪涌保护
USB
Connector
VBUS
CC1
USB PD
Controller
Over Voltage
Protection
CC2
SBU1
SBU2
D+
D-
ESD751 ESD751
ESD751 ESD751 ESD751
ESD761 ESD761
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSH10
ESD751, ESD761
ZHCSR66C –NOVEMBER 2022 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes............................................8
8 Application and Implementation....................................9
8.1 Application Information............................................... 9
8.2 Typical Application...................................................... 9
9 Power Supply Recommendations................................10
10 Layout...........................................................................11
10.1 Layout Guidelines................................................... 11
10.2 Layout Example...................................................... 11
11 Device and Documentation Support..........................12
11.1 Documentation Support.......................................... 12
11.2 接收文档更新通知................................................... 12
11.3 支持资源..................................................................12
11.4 Trademarks............................................................. 12
11.5 Electrostatic Discharge Caution..............................12
11.6 术语表..................................................................... 12
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—JEDEC Specification...........................4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 Recommended Operating Conditions.........................4
6.5 Thermal Information....................................................5
6.6 Electrical Characteristics.............................................5
6.7 Typical Characteristics –ESD751.............................6
6.8 Typical Characteristics - ESD761............................... 7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
Information.................................................................... 12
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (December 2022) to Revision C (December 2022)
Page
• Updated Thermal Information table.................................................................................................................... 5
Changes from Revision A (November 2022) to Revision B (December 2022)
Page
• 将ESD761 器件的状态从预告信息更改为“量产数据”.................................................................................. 1
Changes from Revision * (November 2022) to Revision A (November 2022)
Page
• 将ESD751 器件的状态从预告信息更改为“量产数据”.................................................................................. 1
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5 Pin Configuration and Functions
1
2
图5-1. DPY Package, 2-Pin X1SON (Top View)
ID Area
1
2
图5-2. DYA Package, 2-Pin SOD523 (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
IO
1
I/O
G
ESD protected IO
Connect to ground.
GND
2
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
DEVICE
MIN
MAX
UNIT
ESD751
102
65
PPP
IEC 61000-4-5 Power (tp - 8/20 µs) at 25°C
IEC 61000-4-5 current (tp - 8/20 µs) at 25°C
W
ESD761
ESD751
ESD761
2.8
1.8
150
150
155
IPP
A
TA
Operating free-air temperature
Junction temperature
-55
-55
-65
TJ
°C
Tstg
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings—JEDEC Specification
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
± 2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JS-002(2)
± 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard
ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard
ESD control process.
6.3 ESD Ratings—IEC Specification
DEVICE
ESD751
ESD761
VALUE
UNIT
±22000
±15000
±22000
±15000
IEC 61000-4-2 Contact Discharge, all pins
IEC 61000-4-2 Air-gap Discharge, all pins
V(ESD)
Electrostatic discharge
V
ESD751
ESD761
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
-24
-55
NOM
MAX
24
UNIT
V
VIN
TA
Input voltage
Operating free-air temperature
150
°C
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6.5 Thermal Information
ESD751
ESD761
DPY (X1SON)
2 PINS
282.3
THERMAL METRIC(1)
DYA (SOD-523)
2 PINS
746.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
301.2
150.6
509.6
98.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
81.8
9.6
ΨJT
503.0
97.7
ΨJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
over TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
MIN
–24
TYP
MAX
24
UNIT
VRWM
VBRF
VBRR
Reverse stand-off voltage
V
IIO = 10 mA, IO to GND
25.5
35.5
Breakdown voltage(1)
Clamping voltage(2)
V
V
IIO = –10 mA, IO to GND
–35.5
–25.5
IPP = 2.8 A, tp = 8/20 µs, IO to GND and
GND to IO
ESD751
36.5
36.3
IPP = 1.8 A, tp = 8/20 µs, IO to GND and
GND to IO
ESD761
VCLAMP
ESD751
ESD761
41.5
42.5
1
Clamping voltage(3)
Leakage current
IPP = 16 A, TLP, IO to GND and GND to IO
VIO = ±24 V, IO to GND
V
ILEAK
RDYN
-50
50
nA
Ω
ESD751
ESD761
ESD751
ESD761
0.6
0.53
1.6
1.1
Dynamic resistance(3)
2.7
1.8
VIO = 0 V, f = 1 MHz, Vpp = 30 mV, IO to
GND
CL
Line capacitance
pF
(1) VBRF and VBRR are defined as the voltage when ±10 mA is applied in the positive-going direction, before the device latches into the
snapback state.
(2) Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.
(3) Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008
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6.7 Typical Characteristics –ESD751
32
30
28
26
24
22
20
18
16
14
12
10
8
32
30
28
26
24
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
35
40
45
0
5
10
15
20
25
30
35
40
45
Vclamp (V)
Vclamp (V)
图6-1. Positive TLP Curve
图6-2. Negative TLP Curve
图6-4. -8-kV Clamped IEC Waveform
图6-3. +8-kV Clamped IEC Waveform
2.17
2.165
2.16
12
11
10
9
2.155
2.15
8
2.145
2.14
7
2.135
2.13
6
5
2.125
2.12
4
3
2.115
2.11
2
1
2.105
2.1
0
0
2.5
5
7.5
10 12.5 15 17.5 20 22.5 25
VR (V)
-50 -30 -10
10
30
50
70
90 110 130 150
Temperature (ꢀC)
图6-5. Capacitance vs. Bias Voltage
图6-6. Leakage Current vs. Temperature
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6.8 Typical Characteristics - ESD761
图6-7. Positive TLP Curve
图6-8. Negative TLP Curve
图6-9. Capacitance vs. Bias Voltage
图6-10. DC Voltage Sweep I-V Curve
图6-11. Insertion Loss
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7 Detailed Description
7.1 Overview
The ESD751 and ESD761 are single-channel bidirectional ESD diodes. These devices can dissipate ESD
strikes above the maximum level specified by the IEC 61000-4-2 standard. The low capacitance between the I/O
pins makes these devices suitable for slower speed signals such as USB-PD or industrial I/O applications. The
surge current capability is suitable for VBUS protection or industrial I/Os requiring 2.8 A of surge current
protection.
7.2 Functional Block Diagram
1
2
7.3 Feature Description
These clamping devices have a small dynamic resistance, which makes the clamping voltage low when the
devices are actively protecting other circuits. The breakdown is bidirectional so these protection devices are a
good fit for applications requiring postive and negative polarity protection. Low leakage allows the diode to
conserve power when working below the VRWM. The temperature range of −55°C to +150°C makes these ESD
devices work at extensive temperatures in most environments. The leaded SOD-523 package is good for
applications requiring autmotic optical inspection (AOI).
7.3.1 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.8 A and 1.8 A (8/20 µs waveform) for the ESD751 and ESD761
respectively.
7.3.2 I/O Capacitance
The capacitance between the I/O pins is 1.6 pF and 1.1 pF for the ESD751 and ESD761 respectively. The
capacitance of these devices support data rates up to 1 Gbps.
7.4 Device Functional Modes
The ESD751 and ESD761 are single channel passive clamps that have low leakage during normal operation
when the voltage between I/O and GND is below VRWM, and activate when the voltage between I/O and GND
goes above VBR. When the voltages on the protected lines fall below the VHOLD, the device reverts back to the
low leakage passive state
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ESD751 and ESD761 are single channel TVS diodes which are used to provide a path to ground for
dissipating ESD events on USB-PD or industrial I/O lines. As the current from ESD passes through the TVS,
only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low
RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
USB
Connector
VBUS
CC1
USB PD
Controller
Over Voltage
Protection
CC2
SBU1
SBU2
D+
D-
ESD751 ESD751
ESD751 ESD751 ESD751
ESD761 ESD761
图8-1. Typical Application
8.2.1 Design Requirements
For this design example, the ESD751 and ESD761 are used to provide ESD protection on a USB-PD connector.
表8-1 lists the known design parameters for this application.
表8-1. Design Parameters for Typical Applications
Design Parameter
Diode configuration
VBUS Voltage
Value
Bidirectional
+ 20 V
VIO differential signal range
VRWM
±3.3 V
±24 V
Short to VBUS event on VIO
Data rate
±20 V
Up to 480 Mbps
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8.2.2 Detailed Design Procedure
The ESD751 and ESD761 have a VRWM of ±24 V to protect the diode from being damaged during a short event
that can occur when one of the USB-PD slower speed lines (CC1, CC2, SBU1, SBU2, D+, and D-) is shorted to
VBUS. The bidirectional characteristic ensures both positive and negative polarity are protected. The low
capacitance of 1.7 pF or less permits data rates up to 480 Mbps, which allows the designer to meet the
requirements for the D+ and D- signals. These devices have an IPP = 2.8 A and 1.8 A (8/20 µs), respectively.
The surge current capability of these devices is suitable for protecting the VBUS power rail.
8.2.2.1 Application Curves
图8-3. −8-kV Clamped IEC Waveform
图8-2. +8-kV Clamped IEC Waveform
9 Power Supply Recommendations
These devices are passive TVS diode-based ESD protection devices, therefore there is no requirement to power
them. Ensure that the maximum voltage specifications for each pin is not violated.
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10 Layout
10.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
• If pin 1 or 2 is connected to ground, use a thick and short trace for this return path.
10.2 Layout Example
VBUS
CC1
To power supply
ESD751
CC2
ESD751
ESD751
SBU1
SBU2
D+
ESD751
ESD761
D-
ESD761
Legend
Pin to GND
GND
图10-1. Layout Recommendation
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, ESD Layout Guide application reports
• Texas Instruments, Generic ESD Evaluation Module user's guide
• Texas Instruments, Picking ESD Diodes for Ultra High-Speed Data Lines application reports
• Texas Instruments, Reading and Understanding an ESD Protection data sheet
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD751DYAR
ESD761DPYR
ACTIVE
ACTIVE
SOT-5X3
X1SON
DYA
DPY
2
2
8000 RoHS & Green
10000 RoHS & Green
SN
Level-3-260C-168 HR
Level-1-260C-UNLIM
-55 to 150
-50 to 150
1MN
NE
Samples
Samples
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2022
OTHER QUALIFIED VERSIONS OF ESD751, ESD761 :
Automotive : ESD751-Q1, ESD761-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD751DYAR
ESD761DPYR
SOT-5X3 DYA
X1SON DPY
2
2
8000
178.0
178.0
9.5
8.4
0.5
0.7
1.94
1.15
0.73
0.47
2.0
2.0
8.0
8.0
Q1
Q1
10000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESD751DYAR
ESD761DPYR
SOT-5X3
X1SON
DYA
DPY
2
2
8000
210.0
205.0
200.0
200.0
42.0
33.0
10000
Pack Materials-Page 2
PACKAGE OUTLINE
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
1.3
1.1
0.3
0.1
0.7
0.5
B
2X
TYP
0.77 MAX
C
SEATING PLANE
0.05 C
0.15
2X
0.08
SYMM
SYMM
0.35
0.25
2X
0.1
0.05
C A B
0.4
0.2
2X
4224978/B 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEITA SC-79 registration except for package height
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224978/B 09/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/B 09/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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