ESD762DBZR [TI]
具有 8/20µS 浪涌的双通道 1.75pF、±24V、±20kV ESD 保护二极管 | DBZ | 3 | -50 to 150;
| 型号： | ESD762DBZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8/20µS 浪涌的双通道 1.75pF、±24V、±20kV ESD 保护二极管 | DBZ | 3 | -50 to 150 二极管 |
| 文件： | 总25页 (文件大小：1941K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD752, ESD762
ZHCSQM5B –MAY 2022 –REVISED NOVEMBER 2022
ESD752 and ESD762 采用SOT-23 和SOT-323/SC-70 封装且具有5.7A 8/20µs
浪涌保护的24V、双通道ESD 保护二极管
1 特性
3 说明
• 强大的浪涌保护：
– IEC 61000-4-5 (8/20µs)：5.7 A 或2.5 A
• IEC 61000-4-2 4 级ESD 保护：
– ±30kV 或±20kV 接触放电
– ±30kV 或±20kV 气隙放电
• 24V 工作电压
ESD752 and ESD762 是用于 USB 电力传输 (USB-
PD) 和工业接口的双向 ESD 保护二极管。ESD752
and ESD762 旨在耗散达到或超出 IEC 61000-4-2 4 级
标准所规定最大电平（±30kV 或 ±20kV 接触和 ±30kV
或 ±20kV 气隙）的接触式 ESD。低动态电阻和低钳位
电压支持针对瞬态事件提供系统级保护。这种保护至关
重要，因为工业系统对鲁棒性和可靠性的要求很高。
• 双向ESD 保护
• 双通道器件通过单个元件提供全面的ESD 和浪涌保
护
这些器件具有每通道低 IO 电容和提供两条 IO 线路的
引脚排列，可防止因静电放电 (ESD) 和其他瞬变造成
损坏。ESD752 的 IPP = 5.7A（8/20µs 浪涌波形）能
力使其适用于保护 USB VBUS 和工业 I/O 线路免受瞬
态浪涌事件的影响。此外，ESD752 和 ESD762 的
3pF 或 1.7pF 线路电容适用于保护 USB 电力传输的低
速信号和工业应用的IO 信号。
• 低钳位电压可保护下游元件
• I/O 电容= 3pF 或1.7pF（典型值）
• SOT-23 (DBZ) 小型、标准、通用封装
• SOT-323/SC-70 (DCK) 超小、标准、节省空间的通
用封装
• 引线式封装，用于自动光学检测(AOI)
ESD752 and ESD762 采用两种引线式封装，可轻松实
现直通式布线。
2 应用
• USB 电力传输(USB-PD)：
– VBUS 保护
封装信息(1)
封装尺寸（标称值）
器件型号
封装
– IO 保护（耐受VBUS 短路）
• 工业控制网络：
DCK
2.00mm × 1.25mm
（SOT-323/SC-70，
3）
ESD752
– 智能配电系统(SDS)
– DeviceNet IEC 62026-3
– CANopen –CiA 301/302-2 和EN 50325-4
– 4/20mA 电路
DBZ（SOT-23，3） 2.92mm × 1.30mm
DBZ（SOT-23，3） 2.92mm × 1.30mm
ESD762
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
– PLC 浪涌保护
– ADC 浪涌保护
USB
Connector
VBUS
CC1
USB PD
Controller
Over Voltage
Protection
CC2
SBU1
SBU2
D+
D-
2
1
2
1
1
2
1
3
ESD752
3
ESD752
2
ESD7x1
3
ESD762
USB Power Delivery Applica on
USB 电力传输典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGX0
ESD752, ESD762
ZHCSQM5B –MAY 2022 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes............................................9
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................12
10 Layout...........................................................................13
10.1 Layout Guidelines................................................... 13
10.2 Layout Example...................................................... 13
11 Device and Documentation Support..........................14
11.1 Documentation Support.......................................... 14
11.2 接收文档更新通知................................................... 14
11.3 支持资源..................................................................14
11.4 Trademarks............................................................. 14
11.5 Electrostatic Discharge Caution..............................14
11.6 术语表..................................................................... 14
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—JEDEC Specification...........................4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 Recommended Operating Conditions.........................4
6.5 Thermal Information....................................................4
6.6 Electrical Characteristics.............................................5
6.7 Typical Characteristics –ESD752.............................6
6.8 Typical Characteristics –ESD762.............................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
Information.................................................................... 14
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (August 2022) to Revision B (November 2022)
Page
• 在数据表添加了ESD762 规格。........................................................................................................................ 1
• Added the Application Curves section..............................................................................................................12
Changes from Revision * (May 2022) to Revision A (August 2022)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
IO
IO
1
2
3
GND
Not to scale
图5-1. DCK and DBZ Package,
3-Pin SOT-323 / SC-70 and SOT-23
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1, 2
3
IO
I/O
G
ESD protected IO
Connect to ground.
GND
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
DEVICE
ESD752
ESD762
ESD752
ESD762
MIN
MAX UNIT
210
90
W
W
A
IEC 61000-4-5 Power (tp –8/20 µs) at 25°C
Ppp
IEC 61000-4-5 Power (tp –8/20 µs) at 25°C
5.7
2.5
150
150
155
IEC 61000-4-5 current (tp –8/20 µs) at 25°C
Ipp
A
IEC 61000-4-5 current (tp –8/20 µs) at 25°C
TA
Operating free-air temperature
Junction temperature
-55
-55
-65
°C
°C
°C
TJ
Tstg
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings—JEDEC Specification
PARAMETER
TEST CONDITION
VALUE
± 2500
± 1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged device model (CDM), per JEDEC specification JS-002 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufactuuring with a standard ESD control proccess.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufactuuring with a standard ESD control proccess.
6.3 ESD Ratings—IEC Specification
over TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITION
DEVICE
ESD752
ESD762
ESD752
ESD762
VALUE
±30000
±20000
±30000
±20000
UNIT
V
V
V
V
IEC 61000-4-2 Contact Discharge, all pins
V(ESD)
Electrostatic discharge
IEC 61000-4-2 Air Discharge, all pins
6.4 Recommended Operating Conditions
PARAMETER
MIN
-24
-55
NOM
MAX
24
UNIT
VIN
TA
Input voltage
V
Operating free-air temperature
150
°C
6.5 Thermal Information
ESD752
ESD762
THERMAL METRIC(1)
DBZ (SOT-23)
3 PINS
291.5
DCK (SOT-323 / SC-70)
DBZ (SOT-23)
3 PINS
325.3
UNIT
3 PINS
283.0
164.1
105.1
67.1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
147.1
178.8
RθJB
ΨJT
Junction-to-board thermal resistance
131.1
165.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
32.0
52.4
130.2
104.4
164.4
ΨJB
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6.5 Thermal Information (continued)
ESD752
ESD762
THERMAL METRIC(1)
DBZ (SOT-23)
3 PINS
DCK (SOT-323 / SC-70)
DBZ (SOT-23)
3 PINS
UNIT
3 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
over TA = 25°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
DEVICE
MIN
–24
TYP
MAX UNIT
VRWM Reverse stand-off voltage
24
35.5
V
V
VBRF
VBRR
Forward breakdown voltage(2)
Reverse breakdown voltage(2)
IIO = 10 mA, IO to GND
25.5
V
IIO = –10 mA, IO to GND
–35.5
–25.5
IPP = 5.7 A, tp = 8/20 µs, IO to GND
IPP = 2.5 A, tp = 8/20 µs, from IO to GND
ESD752
ESD762
ESD752
ESD762
ESD752
ESD762
37
36
V
VCLAMP Clamping voltage(3)
VCLAMP Clamping voltage(4)
V
35
V
IPP = 16 A, TLP, IO to GND or GND to IO
38
V
30
V
VHold
ILEAK
RDYN
Holding voltage after snapback(5) TLP
30
V
Leakage current
VIO = ±24 V, IO to GND
-50
5
50
nA
ESD752
ESD762
ESD752
ESD762
0.35
0.57
3
Ω
Ω
Dynamic resistance(4)
IO to GND and GND to IO
5
pF
pF
CL
Line capacitance(6)
VIO = 0 V, f = 1 MHz, Vpp = 30 mV
1.7
2.8
(1) Measurements made on each IO channel.
(2) VBRF and VBRR are defined as the voltage when +/- 10 mA is applied in the positive or negative direction respectively, before the device
latches into the snapback state.
(3) Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.
(4) Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008
(5) VHOLD is defined as the lowest voltage on the TLP plot once the trigger threshold is reached and the device snapbacks and begins
clamping the voltage.
(6) Measured from IO to GND on each channel.
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6.7 Typical Characteristics –ESD752
28
26
24
22
20
18
16
14
12
10
8
28
26
24
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
5
10
15
20 25
Vclamp (V)
30
35
40
5
10
15
20 25
Vclamp (V)
30
35
40
tp = 100 ns, Transmission Line Pulse (TLP)
tp = 100 ns, Transmission Line Pulse (TLP)
图6-1. Positive TLP Curve
图6-2. Negative TLP Curve
150
25
0
125
100
75
-25
Vclamp_ESD at 30ns = -32.9V
-50
-75
50
Vclamp_ESD at 30ns = 28V
-100
-125
-150
-175
25
0
-25
-100
0
100
200
300
400
500
600
700
-100
0
100
200
300
400
500
600
700
Time(ns)
Time(ns)
图6-3. +8-kV Clamped IEC Waveform
图6-4. −8-kV Clamped IEC Waveform
10
8
3.2
3.1
3
6
4
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2
0
-2
-4
-6
-8
-10
-25 -20 -15 -10
-5
0
VR (V)
5
10
15
20
25
Frequency = 1MHz, Vpp = 30 mV
TA = 150 ꢀC
ILEAK is less than 1 nA at -55 ꢀC and 25 ꢀC.
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VR (V)
图6-5. Capacitance vs. Bias Voltage
图6-6. Leakage Current vs. Bias Voltage Across Temperature
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6.7 Typical Characteristics –ESD752 (continued)
6
5.5
5
60
Current
Voltage
55
50
45
40
35
30
25
20
15
10
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
-5
0
5
10
15
20
25
30
35
40
Time (ꢀs)
图6-7. 8/20 µs Surge Response at 5.7 A
6.8 Typical Characteristics –ESD762
200
175
150
125
100
50
25
0
-25
Vclamp_ESD at 30ns = -29.3V
-50
-75
75
Vclamp_ESD at 30ns = 27.7V
-100
-125
-150
-175
-200
50
25
0
-25
-100
0
100
200
300
400
500
600
700
-100
0
100
200
300
400
500
600
700
Time(ns)
Time(ns)
图6-8. +8-kV Clamped IEC Waveform
图6-9. −8-kV Clamped IEC Waveform
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7 Detailed Description
7.1 Overview
The ESD752 and ESD762 are dual-channel ESD TVS diodes in SOT-23 and SOT-323 (SC-70) leaded packages
which are convenient for automatic optical inspection. This product offers IEC 61000-4-2 ±30-kV or ±20-kV air-
gap, ±30-kV or ±20-kV contact ESD protection respectively, and has a clamp circuit with a back-to-back TVS
diode for bidirectional signal support.
A typical application of this product is the ESD protection for USB-PD slower speed signals (CC1, CC2, SBU1,
SBU2, D+, and D-). The IPP = 5.7 A (8/20 µs surge waveform) capability of the ESD752 makes it suitable for
protecting VBUS. The ESD752 device is also a good fit for protecting industrial IOs requiring 5.7 A or less of
surge current protection. The 3 pF or 1.7 pF line capacitance of these ESD protection diodes are suitable for
USB-PD slower speed signals and industrial IO applications.
7.2 Functional Block Diagram
1
2
3
7.3 Feature Description
The ESD752 and ESD762 are bidirectional TVS diodes with a high ESD protection level. This device protects
the circuit from ESD strikes up to ±30-kV or ±20-kV contact and ±30-kV or ±20-kV air-gap respectively as
specified in the IEC 61000-4-2 standard. The ESD752 and ESD762 can also handle up to 5.7 A or 2.5 A of
surge current (IEC 61000-4-5 8/20 µs) respectively. The I/O capacitance of 3 pF or 1.7 pF (typical) are suitable
for USB power delivery slower speed signals and industrial applications. These clamping devices have a small
dynamic resistance, which makes the clamping voltage low when the device is actively protecting other circuits.
For example, the ESD752 clamping voltage is only 37 V when the device is taking 5.7 A transient current. The
breakdown is bidirectional so these protection devices are a good fit for applications requiring postive and
negative polarity protection. Low leakage allows these diodes to conserve power when working below the VRWM
.
The temperature range of −55°C to +150°C makes this ESD device work at extensive temperatures in most
environments. The leaded SOT-23 and SOT-323 (SC-70) packages are good for applications requiring automatic
optical inspection (AOI).
7.3.1 Temperature Range
These devices are qualified to operate from –55°C to +150°C.
7.3.2 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 5.7 A and 2.5 A (8/20 µs waveform) for the ESD752 and ESD762
respectively. An ESD-surge clamp diverts this current to ground.
7.3.3 IO Capacitance
The capacitance between the I/O pins is 3 pF and 1.7 pF for the ESD752 and ESD762 respectively. These
capacitances are suitable for USB power delivery slower speed signals and industrial applications.
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7.3.4 Dynamic Resistance
The IO pins feature an ESD clamp that has a low RDYN of 0.35 Ω for the ESD752 device, and 0.57 Ω for the
ESD762 device, which prevents system damage during ESD events.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage between the IO pins is a minimum of ± 25.5 V. This protects sensitive equipment is
protected from surges above the reverse standoff voltage of ± 24 V.
7.3.6 Ultra Low Leakage Current
The IO pins feature an ultra-low leakage current of 50 nA (maximum) with a bias of ± 24 V.
7.3.7 Clamping Voltage
The IO pins feature an ESD clamp that is capable of clamping the voltage to 37 V (IPP = 5.7 A for 8/20 μs surge
waveform), 35 V (IPP = 16 A for TLP), 36 V (IPP = 2.5 A for 8/20 μs surge waveform), and 38 V (IPP = 16 A for
TLP) for the ESD752 and ESD762, respectively.
7.3.8 Industry Standard Leaded Packages
These devices feature industry standard SOT-23 (DBZ) and SC-70 (DCK) leaded packages for automatic optical
inspection (AOI).
7.4 Device Functional Modes
The ESD752 and ESD762 are dual channel passive clamp devices that have low leakage during normal
operation when the voltage between IO and GND is below VRWM, and activate when the voltage between IO and
GND goes above VBR. During IEC 61000-4-2 ESD events, transient voltages as high as ±30 kV can be clamped
on either channel. When the voltages on the protected lines fall below the VHOLD, the device reverts back to the
low leakage passive state.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ESD752 and ESD762 are dual channel TVS diodes which are used to provide a path to ground for
dissipating ESD events on USB-PD or industrial IO signal lines. As the current from the ESD passes through the
TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC.
The low RDYN of the triggered TVS holds this voltage (VCLAMP) to a safe level for the protected IC.
8.2 Typical Application
USB
Connector
VBUS
CC1
USB PD
Controller
Over Voltage
Protection
CC2
SBU1
SBU2
D+
D-
2
1
2
1
1
2
1
3
ESD752
3
ESD752
2
ESD7x1
3
ESD762
USB Power Delivery Applica on
图8-1. USB Power Delivery Typical Application
8.2.1 Design Requirements
For this design example, the ESD752 and ESD762 are used to provide ESD protection on a USB-PD connector.
表8-1 lists the known design parameters for this application.
表8-1. Design Parameters for the USB Power Delivery Typical Application
Design Parameter
Diode configuration
VBUS Voltage
Value
Bidirectional
+ 20 V
VIO signal range
+ 3.3 V
VRWM
± 24 V
Short to VBUS event on VIO
± 20 V
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表8-1. Design Parameters for the USB Power Delivery Typical Application (continued)
Design Parameter
Value
Data rate
Up to 480 Mbps
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8.2.2 Detailed Design Procedure
The ESD752 and ESD762 has a VRWM of ± 24 V to prevent the diode from being damaged during a short event
that can occur when one of the USB-PD slower speed lines (CC1, CC2, SBU1, SBU2, D+, and D-) is shorted to
VBUS. The bidirectional characteristic protects both positive and negative polarity. The low 1.7 pF capacitance of
the ESD762 device enables data rates up to 480 Mbps, which allows the designer to meet the requirements for
the D+ and D- signals. The ESD752 has an IPP = 5.7 A (8/20 µs) surge current capability making it suitable for
protecting the VBUS power rail.
8.2.3 Application Curves
图8-3. −8-kV Clamped IEC Waveform
图8-2. +8-kV Clamped IEC Waveform
9 Power Supply Recommendations
These are passive TVS diode-based ESD protection devices; therefore, there is no requirement to power it.
Ensure that the maximum voltage specifications for each pin are not violated.
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10 Layout
10.1 Layout Guidelines
• The optimum placement of the device is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
• If pin 3 is connected to ground, use a thick and short trace for this return path.
10.2 Layout Example
This is a typical example of a dual channel IO routing.
IO1
GND
IO2
= VIA to GND
图10-1. Routing with DBZ and DCK Package
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: ESD752 ESD762
ESD752, ESD762
ZHCSQM5B –MAY 2022 –REVISED NOVEMBER 2022
www.ti.com.cn
11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, ESD Layout Guide user's guide
• Texas Instruments, ESD and Surge Protection for USB Interfaces application note
• Texas Instruments, ESD Protection Diodes EVM user's guide
• Texas Instruments, Generic ESD Evaluation Module user's guide
• Texas Instruments, Reading and Understanding an ESD Protection data sheet
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ESD752DBZR
ESD752DCKR
ESD762DBZR
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBZ
DCK
DBZ
3
3
3
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-1-260C-UNLIM
-55 to 150
-55 to 150
-50 to 150
2RP8
1MP
Samples
Samples
Samples
NIPDAU
NIPDAU
SOT-23
2RK8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ESD752DBZR
ESD752DCKR
ESD762DBZR
SOT-23
SC70
DBZ
DCK
DBZ
3
3
3
3000
3000
3000
180.0
178.0
180.0
8.4
9.0
8.4
2.9
2.4
2.9
3.35
2.5
1.35
1.2
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
SOT-23
3.35
1.35
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ESD752DBZR
ESD752DCKR
ESD762DBZR
SOT-23
SC70
DBZ
DCK
DBZ
3
3
3
3000
3000
3000
210.0
180.0
210.0
185.0
180.0
185.0
35.0
18.0
35.0
SOT-23
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0003A
SOT-SC70 - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR SC70
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
0.65
1.3
2.15
1.85
3
0.30
3X
0.15
C A B
0.1
0.0
0.1
(0.9)
TYP
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
TYP
TYP
0
SEATING PLANE
4220745/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
3
(1.3)
(0.65)
2
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220745/C 06/2021
NOTES: (continued)
3. Publication IPC-7351 may have alternate designs.
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
3
(1.3)
(0.65)
2
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4220745/C 06/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
6. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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