F28M35H20B1_1110 [TI]

Concerto Microcontrollers; 协奏曲微控制器


型号：	F28M35H20B1_1110
厂家：	TEXAS INSTRUMENTS
描述：	Concerto Microcontrollers 协奏曲微控制器微控制器
文件：	总104页 (文件大小：801K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Concerto Microcontrollers

1 F28M35x ( Concerto™) MCUs

1.1 Features

12345

• Master Subsystem — ARM^®Cortex™-M3

– 100 MHz

• Control Subsystem — TMS320C28x™ 32-Bit

CPU

– 150 MHz

– Embedded Memory

•

Up to 512KB Flash (ECC)

Up to 32KB RAM (ECC/Parity)

Up to 64KB Shared RAM

2KB IPC Message RAM

•

Up to 512KB Flash (ECC)

Up to 36KB RAM (ECC/Parity)

Up to 64KB Shared RAM

2KB IPC Message RAM

– 5 Universal Asynchronous

Receiver/Transmitters (UARTs)

– 4 Synchronous Serial Interfaces (SSIs)/

– IEEE-754 Single-Precision Floating-Point

Unit (FPU)

Serial Peripheral Interface (SPI)

– 2 Inter-integrated Circuits (I2Cs)

– Universal Serial Bus On-the-Go (USB-OTG) +

– Viterbi, Complex Math, CRC Unit (VCU)

– Serial Communications Interface (SCI)

– Serial Peripheral Interface (SPI)

PHY

– Inter-integrated Circuit (I2C)

– 10/100 ENET 1588 MII

– 6-Channel Direct Memory Access (DMA)

– 2 Controller Area Networks (CANs)

– 32-Channel Direct Memory Access (μDMA)

– 9 Enhanced Pulse Width Modulator (ePWM)

Modules

– Dual Security Zones (128-Bit Password per

•

18 Outputs (16 High-Resolution)

Zone)

– 6 32-Bit Enhanced Capture (eCAP) Modules

– External Peripheral Interface (EPI)

– 3 32-Bit Enhanced Quadrature Encoder

– Micro Cyclic Redundancy Check (µCRC)

(eQEP) Modules

Module

– Multi-Channel Buffered Serial Port (McBSP)

– One Security Zone (128-Bit Password)

– 3 32-Bit Timers

– 4 General-Purpose Timers

– 2 Watchdog Timer Modules

– Endianness: Little Endian

• Clocking

– Endianness: Little Endian

– On-chip Crystal Oscillator/External Clock

• Analog Subsystem

Input

– Dual 12-Bit Analog-to-Digital Converters

(ADCs)

– Up to 2.88 MSPS

– Dynamic PLL Ratio Changes Supported

• 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design

– Up to 20 Channels

– 4 Sample-and-Hold (S/H) Circuits

– Up to 6 Comparators With 10-Bit

• Interprocessor Communications (IPC)

– 32 Handshaking Channels

– 4 Channels Generate IPC Interrupts

Digital-to-Analog Converter (DAC)

– Can be Used to Coordinate Transfer of Data

– On-chip Temperature Sensor

Through IPC Message RAMs

• Package

• Up to 74 Individually Programmable,

– 144-Pin RFP PowerPAD™ Thermally

Multiplexed GPIO Pins

Enhanced Thin Quad Flatpack (HTQFP)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Concerto, TMS320C28x, PowerPAD, C28x, C2000, Piccolo, Delfino, TMS320C2000, XDS are trademarks of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Ltd or its subsidiaries.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative

or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right

to change or discontinue these products without notice.

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

1.2 Description

The Concerto™ family is a multi-core system-on-chip microcontroller (MCU) with independent

communication and real-time control subsystems. The F28M35x is the first series in the Concerto family.

The communications subsystem is based on the industry-standard 32-bit ARM^®Cortex™-M3 CPU and

features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, CAN,

UART, SSI, I2C, and an external interface.

The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x™ Floating-Point

CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault

protection, and encoders and captures—all as implemented by TI’s C2000™ Piccolo™ and Delfino™

families. In addition, the C28-CPU has been enhanced with the addition of the Viterbi, Complex Math,

CRC Unit (VCU) instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs

and CRC algorithms.

A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage

regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code

(ECC), Parity, and Code Secure Memory, as well as documentation to assist with system-level industrial

safety certification.

F28M35x ( Concerto™) MCUs

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

1.3 Functional Block Diagram

SECURE

1.8V

1.2V

GPIO_MUX1

RAM

8 KB

RAM

8 KB

VREG

SECURE

FLASH

(ECC)

(parity)

BOOT

ROM

SECURE

512 KB

(ECC)

RAM

8 KB

RAM

8 KB

64 KB

(ECC)

(parity)

APB BUS

REGS

ONLY

AHB BUS

uDMA BUS

TEMP

ADC

INPUTS

SENS

BUS

BRIDGE

MPU

NVIC

uDMA

M3 CPU

ADC_1

MODULE

I-CODE BUS

D-CODE BUS

COMP

INPUTS

M3 SYSTEM BUS

INTER-PROCESSOR

COMMUNICATIONS

CLOCKS

RESETS

NMI

COMP-

ARATOR

+ DAC

UNITS

MTOC

CTOM

MSG

RAM

8 KB

MSG

RAM

IPC

8 KB

(parity)

2 KB

(parity)

2 KB

COMP

OUTPUTS

DEBUG

S0 - S7 SHARED RAM (parity)

INTER-PROCESSOR

COMMUNICATIONS

C28 DMA BUS

COMP

INPUTS

C28

CPU

C28

DMA

C28

VCU

C28

FPU

ADC_2

PIE

MODULE

ADC

INPUTS

C28 MEMORY BUS

ANALOG

SUBSYSTEM

16-BIT

PF2

32-BIT

PF1

32-BIT

PF3

16/32-BIT

PF0

BOOT

ROM

SECURE

RAM

8 KB

(ECC)

RAM

8 KB

(parity)

RAM

2 KB

64 KB

SECURE

FLASH

(ECC)

SECURE

512 KB

(ECC)

RAM

8 KB

RAM

8 KB

RAM

2 KB

GPIO_MUX1

66 PINS

(ECC)

(parity)

(ECC)

Figure 1-1. Functional Block Diagram

F28M35x ( Concerto™) MCUs

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

F28M35x ( Concerto™) MCUs ........................ 1

1.1 Features .............................................. 1

1.2 Description ........................................... 2

1.3 Functional Block Diagram ............................ 3

Device Pins ............................................. 63

3.1 Pin Assignments .................................... 63

3.2 Terminal Functions ................................. 64

Device Operating Conditions ....................... 82

4.1 Absolute Maximum Ratings ........................ 82

4.2 Recommended Operating Conditions .............. 82

Revision History .............................................. 5

Device Overview ........................................ 8

2.1 Device Characteristics ............................... 9

2.2 Memory Maps ...................................... 11

2.3 Master Subsystem .................................. 21

2.4 Control Subsystem ................................. 26

2.5 Analog Subsystem .................................. 31

4.3 Electrical Characteristics ........................... 83

Peripheral Information and Timings ............... 84

5.1 Master Subsystem Peripherals ..................... 84

5.2 Control Subsystem Peripherals .................... 85

5.3 Analog/Shared Peripherals ......................... 88

2.6 Master Subsystem NMIs ........................... 34

5.4 Current Consumption ............................... 94

5.5 Power Sequencing ................................. 96

Device and Documentation Support ............... 97

6.1 Device Support ..................................... 97

2.7 Control Subsystem NMIs ........................... 34

2.8 Resets .............................................. 36

2.9 Master Subsystem Clocking ........................ 41

2.10 Control Subsystem Clocking ....................... 44

2.11 Analog Subsystem Clocking ........................ 46

2.12 Shared Resources Clocking ........................ 47

2.13 GPIOs and Other Pins .............................. 47

6.2 Documentation Support ............................ 98

6.3 Community Resources ............................. 98

Mechanical Packaging and Orderable

Information .............................................. 99

7.1 Packaging Information .............................. 99

Contents

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data sheet revision history highlights the technical changes made to the SPRS742A device-specific

data sheet to make it an SPRS742B revision.

Scope:

Added Section 4.1, Absolute Maximum Ratings.

Added Section 4.2, Recommended Operating Conditions.

Added Section 4.3, Electrical Characteristics.

Restructured Section 2, Device Overview.

Added Section 6, Device and Documentation Support.

See table below.

LOCATION

ADDITIONS, DELETIONS, AND MODIFICATIONS

Master Subsystem — ARM® Cortex™-M3:

Section 1.1

Features:

•

–

Changed "Universal Serial Bus On-the-Go (USB-OTB) + PHY" to "Universal Serial Bus On-the-Go

(USB-OTG) + PHY"

–

Added "Endianness: Little Endian"

•

Control Subsystem — TMS320C28x™ 32-Bit CPU:

–

Embedded Memory:

Added "Up to 64KB Shared RAM"

Added "Endianness: Little Endian"

•

–

Figure 1-1

Section 2

Updated "Functional Block Diagram"

Device Overview:

•

Added NOTE about color-coding

Table 2-1

Table 2-8

Hardware Features:

•

"Product status" row: Changed "TMX" to "xF28M35..."

Updated footnote about product status

Control Subsystem Flash, ECC, OTP, Boot ROM:

•

Sector N: Added "(not available for 256KB Flash configuration)"

Sector M: Added "(not available for 256KB Flash configuration)"

Sector L: Added "(not available for 256KB Flash configuration)"

Sector K: Added "(not available for 256KB Flash configuration)"

Sector J: Added "(not available for 256KB Flash configuration)"

Sector I: Added "(not available for 256KB Flash configuration)"

Sector H: Added "(not available for 256KB Flash configuration)"

Table 2-9

Master Subsystem Flash, ECC, OTP, Boot ROM:

•

Sector I: Added "(not available for 256KB Flash configuration)"

Sector H: Added "(not available for 256KB Flash configuration)"

Sector G: Added "(not available for 256KB Flash configuration)"

Sector F: Added "(not available for 256KB Flash configuration)"

Table 2-11

Master Subsystem Peripherals:

•

4000 1000 – 4000 1FFF: Added "Watchdog Timer 1 Registers"

400F B900 – 400F B93F: Added "0000 0880 – 0000 0890 (Read Only)" in "C Address (x16 Aligned)"

column

Section 2.3.1

Figure 2-1

Updated "Cortex™-M3 CPU" section

Updated "Master Subsystem" figure

Section 2.3.3

Section 2.3.4

Section 2.3.5

Section 2.3.7

Figure 2-2

Added "Cortex™-M3 Interrupts" section

Added "Cortex™-M3 Vector Table" section

Updated "Cortex™-M3 Local Peripherals" section

Updated "Cortex™-M3 Accessing Shared Resources and Analog Peripherals" section

Updated "Control Subsystem" figure

Table 2-16

Added "PIE Peripheral Interrupts" table

Contents

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

LOCATION

Section 2.4.4

ADDITIONS, DELETIONS, AND MODIFICATIONS

Updated "C28x Local Peripherals" section

Section 2.4.6

Section 2.5

Section 2.5.1

Section 2.5.2

Figure 2-3

Updated "C28x Accessing Shared Resources and Analog Peripherals" section

Updated "Analog Subsystem" section

Updated "ADC1" section

Updated "ADC2" section

Updated "Analog Subsystem" figure

Section 2.5.3

Section 2.5.4

Section 2.6

Section 2.7

Figure 2-4

Updated "Analog Comparator + DAC" section

Updated "Analog Common Interface Bus (ACIB)" section

Updated "Master Subsystem NMIs" section

Updated "Control Subsystem NMIs" section

Updated "Cortex™-M3 NMI and C28x NMI" figure

Updated "Resets" section

Section 2.8

Section 2.8.1

Figure 2-5

Updated "Cortex™-M3 Resets" section

Updated "Resets" figure

Section 2.8.4

Section 2.9

Table 2-19

Added "Device Boot Sequence" section

Updated "Master Subsystem Clocking" section

Added "Master Subsystem Low-Power Modes" table

Updated "Cortex™-M3 Clocks and Low-Power Modes" figure

Updated "Cortex™-M3 Run Mode" section

Figure 2-6

Section 2.9.1

Section 2.9.2

Section 2.9.3

Section 2.10

Table 2-20

Updated "Cortex™-M3 Sleep Mode" section

Updated "Cortex™-M3 Deep Sleep Mode" section

Updated "Control Subsystem Clocking" section

Added "Control Subsystem Low-Power Modes" table

Updated "C28x Clocks and Low-Power Modes" figure

Updated "C28x Normal Mode" section

Figure 2-7

Section 2.10.1

Section 2.10.3

Section 2.11

Section 2.12

Section 2.13

Section 2.13.1

Figure 2-8

Updated "C28x Standby Mode" section

Updated "Analog Subsystem Clocking" section

Added "Shared Resources Clocking" section

Changed section title from "GPIOs" to "GPIOs and Other Pins"

Updated "GPIOs and Other Pins" section

Updated "GPIO_MUX1" section

Updated "GPIOs and Other Pins" figure

Figure 2-9

Added "GPIO_MUX1 Block" figure

Figure 2-10

Table 2-21

Added "GPIO_MUX1 Pin Mapping Through Register Set A" figure

Added "GPIO_MUX1 Pin Assignments (M3 Primary Modes)" table

Added "GPIO_MUX1 Pin Assignments (M3 Alternate Modes)" table

Added "GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)" table

Updated "GPIO_MUX2" section

Table 2-22

Table 2-23

Section 2.13.2

Table 2-24

Added "GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)" table

Added "Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2" figure

Updated "AIO_MUX1" section

Figure 2-11

Section 2.13.3

Table 2-25

Added "AIO_MUX1 Pin Assignments (C28x AIO Modes)" table

Updated "AIO_MUX2" section

Section 2.13.4

Table 2-26

Added "AIO_MUX2 Pin Assignments (C28x AIO Modes)" table

144-Pin RFP PowerPAD™ HTQFP (Top View):

Figure 3-1

•

Pin 135: Changed signal name from "ADC2V_REFLO" to "ADC2V_REFLO, V_SSA2"

Contents

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

LOCATION

Table 3-1

ADDITIONS, DELETIONS, AND MODIFICATIONS

Terminal Functions:

•

Pin 118, ADC1V_REFLO, V_SSA1: Added "ADC1 Ground" to DESCRIPTION

Pin 135: Changed signal name from "ADC2V_REFLO" to "ADC2V_REFLO, V_SSA2

Pin 135, ADC2V_REFLO, V_SSA2: Added "ADC2 Ground" to DESCRIPTION

Pin 23: Removed M_OFSD2N

Pin 104: Removed M_IID

Pin 103: Removed M_ISESSEND

Pin 82: Removed M_IAVALID

Pin 81: Removed M_IVBUSVALID. Added BOOT_2.

Pin 48: Removed M_IXRCV

Pin 51: Removed M_IDM

Pin 69: Removed M_IDP

Pin 50: Removed M_ODISCHRGVBUS

Pin 71: Removed M_OCHRGVBUS

Pin 78:

–

Removed M_ODMPULLDN

Added BOOT_0

•

Pin 72: Removed M_OLSD2N

Pin 70: Removed M_OLSD1N

Pin 52:

–

Removed M_OIDPULLUP

Added BOOT_1

•

Pin 41: Removed M_OSPEED

Pin 42: Removed M_OSUSPEND

Pin 36: Removed M_OOE

Pin 35: Removed M_ODMSE0

Pin 46: Removed M_ODPDAT

Added "Boot Pins" group

Changed "FLASH" pin group heading to "Test Pins"

Added footnote about color-coding

Added footnote about output from the Concerto ePWM

Section 4

Added "Device Operating Conditions" section

Added "Absolute Maximum Ratings" section

Added "Recommended Operating Conditions" section

Added "Electrical Characteristics" section

Section 4.1

Section 4.2

Section 4.3

Section 5

Changed section title from "Peripheral and Electrical Specifications" to "Peripheral Information and Timings"

Added "Master Subsystem Peripherals" section

Section 5.1

Section 5.2

Figure 5-1

Figure 5-2

Section 5.3

Figure 5-3

Figure 5-4

Figure 5-5

Table 5-1

Added "Control Subsystem Peripherals" section

Added "ePWM, eQEP, eCAP" figure

Added "ePWM/HRPWM" figure

Added "Analog/Shared Peripherals" section

Added "ADC" figure

Added "Comparator + DAC Units" figure

Added "Interprocessor Communications (IPC)" figure

Updated "F28M35Hx Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK" table

Added "Power Sequencing" section

Section 5.5

Section 5.5.1

Table 5-2

Added "Power Management and Supervisory Circuit Solutions" section

Added "Power Management and Supervisory Circuit Solutions" table

Added "Device and Documentation Support" section

Section 6

Contents

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

2 Device Overview

The Concerto™ microcontroller (MCU) comprises three subsystems: the Master Subsystem, the Control

Subsystem, and the Analog Subsystem. While the Master and Control Subsystem each have dedicated

local memories and peripherals, they can also share data and events through shared memories and

peripherals. The Analog Subsystem has two ADC converters and six Analog Comparators. Both the

Master and Control Subsystems access the Analog Subsystem through the Analog Common Interface

Bus (ACIB). The NMI Blocks force communication of critical events to the Master and Control Subsystem

processors and their Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset,

External Reset, and other events to initialize subsystem processors and the rest of the chip to a known

state. The Clocking Blocks support multiple low-power modes where clocks to the processors and

peripherals can be slowed down or stopped in order to manage power consumption.

NOTE

Throughout this document, the Master Subsystem is denoted by the color "blue"; the Control

Subsystem is denoted by the color "green"; and the Analog Subsystem is denoted by the

color "orange".

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.1 Device Characteristics

Table 2-1 lists the features of the F28M35Hx devices.

Table 2-1. Hardware Features

FEATURE

TYPE⁽¹⁾

H20B1

H20C1

H22B1

H22C1

H32B1

H32C1

H50B1

H50C1

H52B1

H52C1

Master Subsystem — ARM^®Cortex™-M3

Speed (MHz)

Flash (KB)

–

100⁽²⁾

256

100⁽²⁾

256

100⁽²⁾

256

100⁽²⁾

256

100⁽²⁾

256

100⁽²⁾

512

100⁽²⁾

512

100⁽²⁾

512

100⁽²⁾

512

100⁽²⁾

512

RAM ECC (KB)

RAM Parity (KB)

IPC Message RAM Parity (KB)

Security Zones

10/100 ENET 1588 MII

USB OTG FS

Yes

Synchronous Serial Interface (SSI)/

Serial Peripheral Interface (SPI)

Universal Asynchronous Receiver/Transmitter (UART)

Inter-integrated circuit (I2C)

–

Controller Area Network (CAN)

Direct Memory Access (µDMA)

32-ch

External Peripheral Interface (EPI)

Micro Cyclic Redundancy Check (µCRC) Module

General-Purpose Timers

Watchdog Timer Modules

Control Subsystem — C28x Floating-Point Unit (FPU)/Viterbi, Complex Math, CRC Unit (VCU)

Speed (MHz)

150

256

150

256

150

256

150

256

150

512

150

256

150

512

150

512

150

512

150

512

Flash (KB)

RAM ECC (KB)

RAM Parity (KB)

IPC Message RAM Parity (KB)

Security Zones

Enhanced Pulse Width Modulator (ePWM) modules

High-Resolution PWM outputs

9: 18 outputs

16 outputs

Enhanced Capture (eCAP) modules/

PWM outputs

6 (32-bit)

3 (32-bit)

Enhanced Quadrature Encoder (eQEP) modules

Fault Trip Zones

–

12 on any of 64 GPIO pins

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the

basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the

peripheral reference guides.

(2) An integer divide ratio must be maintained between the C28x and Cortex™-M3 clock frequencies; thus, when the C28x is configured to run at maximum frequency of 150 MHz, the fastest

allowable frequency for the Cortex™-M3 will be 75 MHz.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-1. Hardware Features (continued)

FEATURE

TYPE⁽¹⁾

H20B1

H20C1

H22B1

H22C1

H32B1

H32C1

H50B1

H50C1

H52B1

H52C1

Multi-Channel Buffered Serial Port (McBSP)/

Serial Peripheral Interface (SPI)

Serial Communications Interface (SCI)

Serial Peripheral Interface (SPI)

Inter-integrated circuit (I2C)

Direct Memory Access (DMA)

32-Bit Timers

–

6-ch

Shared

Supplemental RAM (KB)

MSPS

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

Conversion Time

12-Bit ADC 1

Channels

Temperature Sensor

Sample-and-Hold (S/H)

MSPS

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

2.88

350 ns

Conversion Time

Channels

12-Bit ADC 2

Sample-and-Hold (S/H)

Comparators with Integrated DACs

Voltage Regulator and Monitor

Clocking

3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC)

4–20 MHz input, Clock fail or out-of-specification, 10-MHz/32-kHz Limp Mode

Additional Safety

Master Subsystem

Control Subsystem

Shared

2 Watchdogs, NMI Watchdog: CPU, Memory

NMI Watchdog: CPU, Memory

Critical Register and I/O Function Lock Protection; RAM Fetch Protection

Packaging

144-Pin RFP PowerPAD™

HTQFP

Package Type

Available at Prototype Sampling

Yes Yes

T: –40°C to 105°C

S: –40°C to 125°C

Q: –40°C to 125°C⁽³⁾

–

Yes

Temperature options

Product status⁽⁴⁾

No 125ºC for ENET/USB

xF28M35...

(3) "Q" refers to Q100 qualification for automotive applications.

(4) The "xF28M35..." product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. See Section 6.1.2, Device

Nomenclature, for descriptions of device stages.

Device Overview

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.2 Memory Maps

Section 2.2.1 shows the Control Subsystem Memory Map. Section 2.2.2 shows the Master Subsystem

Memory Map.

2.2.1 Control Subsystem Memory Map

Table 2-2. Control Subsystem M0, M1 RAM

C Address

Size

(Bytes)

C DMA Access⁽¹⁾

Control Subsystem M0, M1 RAM

(x16 Aligned)⁽¹⁾

0000 0000 – 0000 03FF

0000 0400 – 0000 07FF

M0 RAM (ECC)

M1 RAM (ECC)

(1) The letter "C" refers to the Control Subsystem.

Table 2-3. Control Subsystem Peripheral Frame 0 (Includes Analog)

C Address

Control Subsystem Peripheral Frame 0

(Includes Analog)

Size

(Bytes)

C DMA Access⁽¹⁾

(x16 Aligned)⁽¹⁾

0000 0800 – 0000 087F

Reserved

Control Subsystem Device Configuration Registers (Read

Only)

0000 0880 – 0000 0890

0000 0891 – 0000 0ADF

0000 0AE0 – 0000 0AEF

0000 0AF0 – 0000 0AFF

0000 0B00 – 0000 0B0F

0000 0B10 – 0000 0B3F

0000 0B40 – 0000 0B4F

0000 0B50 – 0000 0BFF

0000 0C00 – 0000 0C07

0000 0C08 – 0000 0C0F

0000 0C10 – 0000 0C17

0000 0C18 – 0000 0CDF

0000 0CE0 – 0000 0CFF

0000 0D00 – 0000 0DFF

0000 0E00 – 0000 0EFF

0000 0F00 – 0000 0FFF

0000 1000 – 0000 11FF

0000 1200 – 0000 16FF

0000 1700 – 0000 177F

0000 1780 – 0000 3FFF

Reserved

C28x CSM Registers

Reserved

yes

ADC1 Result Registers

Reserved

ADC2 Result Registers

Reserved

CPU Timer 0

CPU Timer 1

CPU Timer 2

Reserved

PIE Registers

PIE Vector Table

PIE Vector Table Copy (Read Only)

Reserved

512

C28x DMA Registers

Reserved

Analog Subsystem Control Registers

Reserved

256

(1) The letter "C" refers to the Control Subsystem.

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F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

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Table 2-4. Control Subsystem Peripheral Frame 3

C Address

Control Subsystem

Peripheral Frame 3

Size

(Bytes)

M Address

µDMA

Access

C DMA Access⁽¹⁾

(x16 Aligned)⁽¹⁾

(Byte-Aligned)⁽²⁾

0000 4000 – 0000 4181

0000 4182 – 0000 42FF

C28x Flash Control Registers

Reserved

772

C28x Flash ECC Error Log

Registers

0000 4300 – 0000 4323

0000 4324 – 0000 43FF

0000 4400 – 0000 443F

0000 4440 – 0000 48FF

0000 4900 – 0000 497F

0000 4980 – 0000 49FF

Reserved

M Clock Control Registers⁽²⁾

128

256

400F B800 – 400F B87F

400F B200 – 400F B2FF

Reserved

RAM Configuration Registers

Reserved

RAM ECC/Parity/Access Error

Log Registers

0000 4A00 – 0000 4A7F

256

400F B300 – 400F B3FF

400F B700 – 400F B77F

0000 4A80 – 0000 4DFF

0000 4E00 – 0000 4E3F

0000 4E40 – 0000 4FFF

0000 5000 – 0000 503F

0000 5040 – 0000 50FF

0000 5100 – 0000 517F

0000 5180 – 0000 51FF

0000 5200 – 0000 527F

0000 5280 – 0000 52FF

0000 5300 – 0000 537F

0000 5380 – 0000 53FF

0000 5400 – 0000 547F

0000 5480 – 0000 54FF

0000 5500 – 0000 557F

0000 5580 – 0000 57FF

Reserved

CtoM and MtoC IPC Registers

Reserved

128

yes

McBSP-A

Reserved

yes

EPWM1 (Hi-Resolution)

EPWM2 (Hi-Resolution)

EPWM3 (Hi-Resolution)

EPWM4 (Hi-Resolution)

EPWM5 (Hi-Resolution)

EPWM6 (Hi-Resolution)

EPWM7 (Hi-Resolution)

EPWM8 (Hi-Resolution)

EPWM9

256

Reserved

(1) The letter "C" refers to the Control Subsystem.

(2) The letter "M" refers to the Master Subsystem.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-5. Control Subsystem Peripheral Frame 1

C Address

Size

(Bytes)

C DMA Access⁽¹⁾

Control Subsystem Peripheral Frame 1

Reserved

(x16 Aligned)⁽¹⁾

0000 5800 – 0000 59FF

0000 5A00 – 0000 5A1F

0000 5A20 – 0000 5A3F

0000 5A40 – 0000 5A5F

0000 5A60 – 0000 5A7F

0000 5A80 – 0000 5A9F

0000 5AA0 – 0000 5ABF

0000 5AC0 – 0000 5AFF

0000 5B00 – 0000 5B3F

0000 5B40 – 0000 5B7F

0000 5B80 – 0000 5BBF

0000 5BC0 – 0000 5F7F

0000 5F80 – 0000 5FFF

0000 6000 – 0000 63FF

0000 6400 – 0000 641F

0000 6420 – 0000 643F

0000 6440 – 0000 645F

0000 6460 – 0000 647F

0000 6480 – 0000 649F

0000 64A0 – 0000 64BF

0000 64C0 – 0000 6F7F

0000 6F80 – 0000 6FFF

ECAP1

ECAP2

ECAP3

ECAP4

ECAP5

ECAP6

Reserved

EQEP1

128

EQEP2

EQEP3

Reserved

C GPIO Group 1 Registers⁽¹⁾

256

Reserved

COMP1 Registers

COMP2 Registers

COMP3 Registers

COMP4 Registers

COMP5 Registers

COMP6 Registers

Reserved

C GPIO Group 2 Registers and AIO Mux Registers⁽¹⁾

256

(1) The letter "C" refers to the Control Subsystem.

Table 2-6. Control Subsystem Peripheral Frame 2

C Address

Size

(Bytes)

C DMA Access⁽¹⁾

Control Subsystem Peripheral Frame 2

Reserved

(x16 Aligned)⁽¹⁾

0000 7000 – 0000 70FF

0000 7010 – 0000 702F

0000 7030 – 0000 703F

0000 7040 – 0000 704F

0000 7050 – 0000 705F

0000 7060 – 0000 706F

0000 7070 – 0000 707F

0000 7080 – 0000 70FF

C28x System Control Registers

Reserved

SPI-A

SCI-A

NMI Watchdog Interrupt Registers

External Interrupt Registers

Reserved

ADC1 Configuration Registers

(Only 16-bit read/write access supported)

0000 7100 – 0000 717F

0000 7180 – 0000 71FF

256

ADC2 Configuration Registers

(Only 16-bit read/write access supported)

0000 7200 – 0000 78FF

0000 7900 – 0000 793F

0000 7940 – 0000 7FFF

Reserved

I2C-A

128

Reserved

(1) The letter "C" refers to the Control Subsystem.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-7. Control Subsystem RAMs

C Address

Size

(Bytes)

M Address

µDMA

Access

C DMA Access⁽¹⁾

Control Subsystem RAMs

(x16 Aligned)⁽¹⁾

(Byte-Aligned)⁽²⁾

0000 8000 – 0000 8FFF

0000 9000 – 0000 9FFF

0000 A000 – 0000 AFFF

0000 B000 – 0000 BFFF

0000 C000 – 0000 CFFF

0000 D000 – 0000 DFFF

0000 E000 – 0000 EFFF

0000 F000 – 0000 FFFF

0001 0000 – 0001 0FFF

0001 1000 – 0001 1FFF

0001 2000 – 0001 2FFF

0001 3000 – 0001 3FFF

0001 4000 – 0003 F7FF

L0 RAM (ECC, Secure)

L1 RAM (ECC, Secure)

L2 RAM (Parity, Interleaving)

L3 RAM (Parity, Interleaving)

S0 RAM (Parity, Shared)

S1 RAM (Parity, Shared)

S2 RAM (Parity, Shared)

S3 RAM (Parity, Shared)

S4 RAM (Parity, Shared)

S5 RAM (Parity, Shared)

S6 RAM (Parity, Shared)

S7 RAM (Parity, Shared)

Reserved

yes

2000 8000 – 2000 9FFF

2000 A000 – 2000 BFFF

2000 C000 – 2000 DFFF

2000 E000 – 2000 FFFF

2001 0000 – 2001 1FFF

2001 2000 – 2001 3FFF

2001 4000 – 2001 5FFF

2001 6000 – 2001 7FFF

yes

read only

yes

0003 F800 – 0003 FBFF

0003 FC00 – 0003 FFFF

CtoM MSG RAM (Parity)

MtoC MSG RAM (Parity)

2007 F000 – 2007 F7FF

2007 F800 – 2007 FFFF

yes

read only

yes

0004 0000 – 0004 7FFF

0004 8000 – 0004 8FFF

0004 9000 – 0004 9FFF

0004 A000 – 0004 AFFF

0004 B000 – 0004 BFFF

0004 C000 – 0004 CFFF

0004 D000 – 0004 DFFF

0004 E000 – 0004 EFFF

0004 F000 – 0004 FFFF

0005 0000 – 0005 0FFF

0005 1000 – 0005 1FFF

0005 2000 – 0005 2FFF

0005 3000 – 0005 3FFF

0005 4000 – 0007 EFFF

0007 F000 – 0007 F3FF

0007 F400 – 0007 F7FF

0007 F800 – 0007 FBFF

0007 FC00 – 0007 FFFF

0008 0000 – 0009 FFFF

Reserved

L0 RAM - ECC Bits

L1 RAM - ECC Bits

L2 RAM - Parity Bits

L3 RAM - Parity Bits

S0 RAM - Parity Bits

S1 RAM - Parity Bits

S2 RAM - Parity Bits

S3 RAM - Parity Bits

S4 RAM - Parity Bits

S5 RAM - Parity Bits

S6 RAM - Parity Bits

S7 RAM - Parity Bits

Reserved

2008 8000 – 2008 9FFF

2008 A000 – 2008 BFFF

2008 C000 – 2008 DFFF

2008 E000 – 2008 FFFF

2009 0000 – 2009 1FFF

2009 2000 – 2009 3FFF

2009 4000 – 2009 5FFF

2009 6000 – 2009 7FFF

M0 RAM - ECC Bits

M1 RAM - ECC Bits

CtoM MSG RAM - Parity Bits

MtoC MSG RAM - Parity Bits

Reserved

200F F000 – 200F F7FF

200F F800 – 200F FFFF

(1) The letter "C" refers to the Control Subsystem.

(2) The letter "M" refers to the Master Subsystem.

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-8. Control Subsystem Flash, ECC, OTP, Boot ROM

C Address

Size

(Bytes)

C DMA Access⁽¹⁾

Control Subsystem Flash, ECC, OTP, Boot ROM

(x16 Aligned)⁽¹⁾

0010 0000 – 0010 1FFF

0010 2000 – 0010 3FFF

0010 4000 – 0010 5FFF

0010 6000 – 0010 7FFF

0010 8000 – 0010 FFFF

0011 0000 – 0011 7FFF

0011 8000 – 0011 FFFF

0012 0000 – 0012 7FFF

0012 8000 – 0012 FFFF

0013 0000 – 0013 7FFF

0013 8000 – 0013 9FFF

0013 A000 – 0013 BFFF

0013 C000 – 0013 DFFF

Sector N (not available for 256KB Flash configuration)

16K

64K

16K

Sector M (not available for 256KB Flash configuration)

Sector L (not available for 256KB Flash configuration)

Sector K (not available for 256KB Flash configuration)

Sector J (not available for 256KB Flash configuration)

Sector I (not available for 256KB Flash configuration)

Sector H (not available for 256KB Flash configuration)

Sector G

Sector F

Sector E

Sector D

Sector C

Sector B

Sector A

0013 E000 – 0013 FFFF

0014 0000 – 001F FFFF

0020 0000 – 0020 7FFF

16K

(CSM password in the high address)

Reserved

Flash - ECC Bits

(1/8 of Flash used = 64 KBytes)

64K

0020 8000 – 0024 01FF

0024 0200 – 0024 03FF

0024 0400 – 003F 7FFF

003F 8000 – 003F FFFF

Reserved

TI OTP

Reserved

C28x Boot ROM (64 KBytes)

64K

(1) The letter "C" refers to the Control Subsystem.

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

2.2.2 Master Subsystem Memory Map

Table 2-9. Master Subsystem Flash, ECC, OTP, Boot ROM

M Address

Size

(Bytes)

µDMA Access

Master Subsystem Flash, ECC, OTP, Boot ROM

(Byte-Aligned)⁽¹⁾

Boot ROM - Dual-mapped to 0x0100 0000

(Both maps access same physical location.)

0000 0000 – 0000 FFFF

0001 0000 – 001F FFFF

0020 0000 – 0020 3FFF

64K

Reserved

Sector N

16K

(Zone 1 CSM password in the low address.)

0020 4000 – 0020 7FFF

0020 8000 – 0020 BFFF

0020 C000 – 0020 FFFF

0021 0000 – 0021 FFFF

0022 0000 – 0022 FFFF

0023 0000 – 0023 FFFF

0024 0000 – 0024 FFFF

0025 0000 – 0025 FFFF

0026 0000 – 0026 FFFF

0027 0000 – 0027 3FFF

0027 4000 – 0027 7FFF

0027 8000 – 0027 BFFF

Sector M

16K

64K

16K

Sector L

Sector K

Sector J

Sector I (not available for 256KB Flash configuration)

Sector H (not available for 256KB Flash configuration)

Sector G (not available for 256KB Flash configuration)

Sector F (not available for 256KB Flash configuration)

Sector E

Sector D

Sector C

Sector B

Sector A

0027 C000 – 0027 FFFF

0028 0000 – 005F FFFF

0060 0000 – 0060 FFFF

16K

(Zone 2 CSM password in the high address.)

Reserved

Flash - ECC Bits

(1/8 of Flash used = 64 KBytes)

64K

0061 0000 – 0068 047F

0068 0480 – 0068 07FF

0068 0800

Reserved

TI OTP

896

OTP – Security Lock

Reserved

0068 0804

0068 0808

Reserved

0068 080C

OTP – Zone 2 Flash Start Address

OTP – EMAC Address 0

OTP – EMAC Address 1

Reserved

0068 0810

0068 0814

0068 0818 – 0070 00FF

OTP – ECC Bits – Application Use

(1/8 of OTP used = 3 Bytes)

0070 0100 – 0070 0102

0070 0103 – 00FF FFFF

0100 0000 – 0100 FFFF

0101 0000 – 03FF FFFF

Reserved

Boot ROM – Dual-mapped to 0x0000 0000

(Both maps access same physical location.)

64K

Reserved

ROM/Flash/OTP/Boot ROM – Mirror-mapped

(Read cycles from this space cause the µCRC peripheral

to continuously update data checksum inside a register,

when reading a block of data.)

0400 0000 – 07FF FFFF

0800 0000 – 1FFF FFFF

64M

Reserved

(1) The letter "M" refers to the Master Subsystem.

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-10. Master Subsystem RAMs

µDMA

Access

M Address

Size

(Bytes)

C Address

Master Subsystem RAMs

C DMA Access⁽²⁾

(Byte-Aligned)⁽¹⁾

(x16 Aligned)⁽²⁾

2000 0000 – 2000 1FFF

2000 2000 – 2000 3FFF

2000 4000 – 2000 5FFF

2000 6000 – 2000 7FFF

2000 8000 – 2000 9FFF

2000 A000 – 2000 BFFF

2000 C000 – 2000 DFFF

2000 E000 – 2000 FFFF

2001 0000 – 2001 1FFF

2001 2000 – 2001 3FFF

2001 4000 – 2001 5FFF

2001 6000 – 2001 7FFF

2001 8000 – 2007 EFFF

C0 RAM (ECC, Secure)

C1 RAM (ECC, Secure)

C2 RAM (Parity)

yes

C3 RAM (Parity)

S0 RAM (Parity, Shared)

S1 RAM (Parity, Shared)

S2 RAM (Parity, Shared)

S3 RAM (Parity, Shared)

S4 RAM (Parity, Shared)

S5 RAM (Parity, Shared)

S6 RAM (Parity, Shared)

S7 RAM (Parity, Shared)

Reserved

0000 C000 – 0000 CFFF

0000 D000 – 0000 DFFF

0000 E000 – 0000 EFFF

0000 F000 – 0000 FFFF

0001 0000 – 0001 0FFF

0001 1000 – 0001 1FFF

0001 2000 – 0001 2FFF

0001 3000 – 0001 3FFF

yes

read only

2007 F000 – 2007 F7FF

2007 F800 – 2007 FFFF

CtoM MSG RAM (Parity)

MtoC MSG RAM (Parity)

0003 F800 – 0003 FBFF

0003 FC00 – 0003 FFFF

yes

read only

yes

2008 0000 – 2008 1FFF

2008 2000 – 2008 3FFF

2008 4000 – 2008 5FFF

2008 6000 – 2008 7FFF

2008 8000 – 2008 9FFF

2008 A000 – 2008 BFFF

2008 C000 – 2008 DFFF

2008 E000 – 2008 FFFF

2009 0000 – 2009 1FFF

2009 2000 – 2009 3FFF

2009 4000 – 2009 5FFF

2009 6000 – 2009 7FFF

2009 8000 – 200F EFFF

200F F000 – 200F F7FF

200F F800 – 200F FFFF

2010 0000 – 21FF FFFF

C0 RAM - ECC Bits

C1 RAM - ECC Bits

C2 RAM - Parity Bits

C3 RAM - Parity Bits

S0 RAM - Parity Bits

S1 RAM - Parity Bits

S2 RAM - Parity Bits

S3 RAM - Parity Bits

S4 RAM - Parity Bits

S5 RAM - Parity Bits

S6 RAM - Parity Bits

S7 RAM - Parity Bits

Reserved

0004 C000 – 0004 CFFF

0004 D000 – 0004 DFFF

0004 E000 – 0004 EFFF

0004 F000 – 0004 FFFF

0005 0000 – 0005 0FFF

0005 1000 – 0005 1FFF

0005 2000 – 0005 2FFF

0005 3000 – 0005 3FFF

CtoM MSG RAM - Parity Bits

MtoC MSG RAM - Parity Bits

Reserved

0007 F800 – 0007 FBFF

0007 FC00 – 0007 FFFF

Bit Banded RAM Zone

(Dedicated address for each

RAM bit of Cortex™-M3 RAM

blocks above)

yes

2200 0000 – 23FF FFFF

32M

64M

All RAM Spaces –

Mirror-Mapped

(Read cycles from this space

cause the µCRC peripheral to

continuously update data

checksum inside a register

when reading a block of data.)

2400 0000 – 27FF FFFF

2800 0000 – 3FFF FFFF

Reserved

(1) The letter "M" refers to the Master Subsystem.

(2) The letter "C" refers to the Control Subsystem.

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-11. Master Subsystem Peripherals

µDMA

Access

M Address

Master Subsystem

Peripherals

Size

(Bytes)

C Address

C DMA Access⁽²⁾

(Byte-Aligned)⁽¹⁾

(x16 Aligned)⁽²⁾

yes

4000 0000 – 4000 0FFF

4000 1000 – 4000 1FFF

4000 2000 – 4000 3FFF

4000 4000 – 4000 4FFF

4000 5000 – 4000 5FFF

4000 6000 – 4000 6FFF

4000 7000 – 4000 7FFF

4000 8000 – 4000 8FFF

4000 9000 – 4000 9FFF

4000 A000 – 4000 AFFF

4000 B000 – 4000 BFFF

4000 C000 – 4000 CFFF

4000 D000 – 4000 DFFF

4000 E000 – 4000 EFFF

4000 F000 – 4000 FFFF

4001 0000 – 4001 0FFF

4001 1000 – 4001 FFFF

4002 0000 – 4002 07FF

4002 0800 – 4002 0FFF

4002 1000 – 4002 17FF

4002 1800 – 4002 1FFF

4002 2000 – 4002 3FFF

4002 4000 – 4002 4FFF

4002 5000 – 4002 5FFF

4002 6000 – 4002 6FFF

4002 7000 – 4002 7FFF

4002 8000 – 4002 FFFF

4003 0000 – 4003 0FFF

4003 1000 – 4003 1FFF

4003 2000 – 4003 2FFF

4003 3000 – 4003 3FFF

4003 4000 – 4003 CFFF

4003 D000 – 4003 DFFF

4003 E000 – 4003 FFFF

4004 8000 – 4004 8FFF

4004 9000 – 4004 FFFF

4005 0000 – 4005 0FFF

4005 1000 – 4005 7FFF

4005 8000 – 4005 8FFF

4005 9000 – 4005 9FFF

4005 A000 – 4005 AFFF

4005 B000 – 4005 BFFF

4005 C000 – 4005 CFFF

4005 D000 – 4005 DFFF

4005 E000 – 4005 EFFF

Watchdog Timer 0 Registers

Watchdog Timer 1 Registers

Reserved

M GPIO Port A (APB Bus)⁽¹⁾

M GPIO Port B (APB Bus)⁽¹⁾

M GPIO Port C (APB Bus)⁽¹⁾

M GPIO Port D (APB Bus)⁽¹⁾

SSI0

yes

SSI1

SSI2

SSI3

UART0

UART1

UART2

UART3

UART4

Reserved

I2C0 Master

I2C0 Slave

I2C1 Master

I2C1 Slave

Reserved

yes

M GPIO Port E (APB Bus)⁽¹⁾

M GPIO Port F (APB Bus)⁽¹⁾

M GPIO Port G (APB Bus)⁽¹⁾

M GPIO Port H (APB Bus)⁽¹⁾

Reserved

yes

GP Timer 0

GP Timer 1

GP Timer 2

GP Timer 3

Reserved

M GPIO Port J (APB Bus)⁽¹⁾

yes

Reserved

ENET MAC0

Reserved

USB MAC0

Reserved

yes

M GPIO Port A (AHB Bus)⁽¹⁾

M GPIO Port B (AHB Bus)⁽¹⁾

M GPIO Port C (AHB Bus)⁽¹⁾

M GPIO Port D (AHB Bus)⁽¹⁾

M GPIO Port E (AHB Bus)⁽¹⁾

M GPIO Port F (AHB Bus)⁽¹⁾

M GPIO Port G (AHB Bus)⁽¹⁾

(1) The letter "M" refers to the Master Subsystem.

(2) The letter "C" refers to the Control Subsystem.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-11. Master Subsystem Peripherals (continued)

µDMA

Access

M Address

Master Subsystem

Peripherals

Size

(Bytes)

C Address

C DMA Access⁽²⁾

(Byte-Aligned)⁽¹⁾

(x16 Aligned)⁽²⁾

yes

4005 F000 – 4005 FFFF

4006 0000 – 4006 0FFF

4006 1000 – 4006 FFFF

4007 0000 – 4007 3FFF

4007 4000 – 4007 7FFF

4007 8000 – 400C FFFF

400D 0000 – 400D 0FFF

400D 1000 – 400F 9FFF

400F A000 – 400F A303

400F A304 – 400F A5FF

M GPIO Port H (AHB Bus)⁽¹⁾

M GPIO Port J (AHB Bus)⁽¹⁾

Reserved

CAN0

16K

CAN1

Reserved

EPI0 (Registers only)

Reserved

M Flash Control Registers⁽¹⁾

772

Reserved

M Flash ECC Error Log

Registers⁽¹⁾

400F A600 – 400F A647

400F A648 – 400F B1FF

400F B200 – 400F B2FF

Reserved

RAM Configuration Registers

256

0000 4900 – 0000 497F

0000 4A00 – 0000 4A7F

RAM ECC/Parity/Access Error

Log Registers

400F B300 – 400F B3FF

400F B400 – 400F B5FF

400F B600 – 400F B67F

400F B680 – 400F B6FF

400F B700 – 400F B77F

400F B780 – 400F B7FF

400F B800 – 400F B87F

400F B880 – 400F B8BF

400F B8C0 – 400F B8FF

M CSM Registers⁽¹⁾

512

128

µCRC

Reserved

CtoM and MtoC IPC Registers

Reserved

M Clock Control Registers⁽¹⁾

M LPM Control Registers⁽¹⁾

M Reset Control Registers⁽¹⁾

128

0000 4E00 – 0000 4E3F

0000 4400 – 0000 443F

128

0000 0880 – 0000 0890

400F B900 – 400F B93F

Device Configuration Registers

(Read Only)

400F B940 – 400F B97F

400F B980 – 400F B9FF

400F BA00 – 400F BA7F

400F BA80 – 400F EFFF

400F F000 – 400F FFFF

4010 0000 – 41FF FFFF

Reserved

M Write Protect Registers⁽¹⁾

M NMI Registers⁽¹⁾

Reserved

128

µDMA Registers

Reserved

Bit Banded Peripheral Zone

(Dedicated address for each

peripherals above.)

yes

4200 0000 – 43FF FFFF

4400 0000 – 4FFF FFFF

32M

Reserved

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

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Table 2-12. Master Subsystem Analog and EPI

µDMA

Access

M Address

Size

(Bytes)

Master Subsystem Analog and EPI

(Byte-Aligned)⁽¹⁾

5000 0000 – 5000 15FF

5000 1600 – 5000 161F

5000 1620 – 5000 167F

5000 1680 – 5000 169F

5000 16A0 – 5FFF FFFF

Reserved

yes

ADC1 Result Registers

Reserved

ADC2 Result Registers

Reserved

EPI0

yes

6000 0000 – DFFF FFFF

(External Peripheral/Memory Interface)

(1) The letter "M" refers to the Master Subsystem.

Table 2-13. Cortex™-M3 Private Bus

µDMA

Access

Cortex™-M3 Address

Size

(Bytes)

Cortex™-M3 Private Bus

(Byte-Aligned)

E000 0000 – E000 0FFF

E000 1000 – E000 1FFF

E000 2000 – E000 2FFF

E000 3000 – E000 E007

E000 E008 – E000 E00F

E000 E010 – E000 E01F

E000 E020 – E000 E0FF

E000 E100 – E000 E4EF

E000 E4F0 – E000 ECFF

E000 ED00 – E000 ED3F

E000 ED40 – E000 ED8F

E000 ED90 – E000 EDB8

E000 EDB9 – E000 EEFF

E000 EF00 – E000 EF03

E000 EF04 – FFFF FFFF

Reserved

DWT (Data Watchpoint and Trace)

FPB (Flash Patch and Breakpoint)

Reserved

System Control Block

System Timer

Reserved

Nested Vectored Interrupt Controller (NVIC)

Reserved

1008

System Control Block

Reserved

Memory Protection Unit

Reserved

Nested Vectored Interrupt Controller (NVIC)

Reserved

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.3 Master Subsystem

The Master Subsystem includes the Cortex™-M3 CPU, µDMA, Nested Vectored Interrupt Controller

(NVIC), Cortex™-M3 Peripherals, and Local Memory. Additionally, the Cortex™-M3 CPU and µDMA can

access the Control Subsystem through Shared Resources (IPC, Message RAM, Shared RAM), and talk to

the Analog Peripherals via the Analog Common Interface Bus. The Master Subsystem can also receive

events from the NMI block and send events to the Resets block.

Figure 2-1 shows the Master Subsystem.

2.3.1 Cortex™-M3 CPU

The 32-bit Cortex™-M3 processor offers high performance, fast interrupt handling, and access to a variety

of communication peripherals (including Ethernet and USB). The Cortex™-M3 features a Memory

Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus

bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses

that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex™-M3 System

Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also

accessible by the Control Subsystem) and to the Analog Subsystem through the Analog Common

Interface Bus (ACIB). Another bus bridge allows bus cycles from both the Cortex™-M3 System Bus and

those of the µDMA bus to access the Master Subsystem peripherals (via the APB bus or the AHP bus).

Most of the interrupts to the Cortex™-M3 CPU come from the Nested Vectored Interrupt Controller

(NVIC), which manages the interrupt requests from peripherals and assigns handling priorities. There are

also several exceptions generated by Cortex™-M3 CPU that can return to the Cortex™-M3 as interrupts

after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts,

there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to

M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned

to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned

to level-1 priority, and it is caused by one of the error condition exceptions (Memory Management, Bus

Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not properly serviced.

The Cortex™-M3 CPU has two low-power modes: Sleep and Deep Sleep.

2.3.2 Cortex™-M3 DMA and NVIC

The Cortex™-M3 direct memory access (µDMA) module provides a hardware method of transferring data

between peripherals and/or memory without intervention from the Cortex™-M3 CPU. The Nested

Vectored Interrupt Controller (NVIC) manages and prioritizes interrupt handling for the Cortex™-M3 CPU.

The Cortex™-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the

µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the

data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the

Cortex™-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral,

REQ/DONE will directly drive IRQ to the NVIC so that the Cortex™-M3 CPU can transfer the data. For

those peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing

the DMA. This is the case for both Watchdogs, CANs, I2Cs, and the Analog-to-Digital Converters sending

ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the

µDMA or the NVIC (only to the Resets block).

Device Overview

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

M3PORRST

M3SYSRST

M3 NMI

RESETS

FIXED

PRIORITY

INTERRUPTS

M3NMIINT

M3HRDFLT

M3NMIINT

M3NMI

M3NMIINT

M3NMIRST

M3WDRST (1:0)

NVIC

M3 PERIPHERALS

PERIPHERAL

I/O s

M3SWRST

M3DBGRST

APB BUS

AHB BUS

GPTA/B

CPU

USB

MAC

REQ

EMAC RX

EMACTX

REQ

UART

(5:1)

REQ

(3:0)

REQ

SSI

(3:0)

REQ

EPI

REQ

BUS

uDMA

BRIDGE

DMA INTRS

USAGE FAULT

SVCALL

CAN0/1

(1:0)

ADC

INT

GPIO

(H:A)

IRQ

USB

MAC

IRQ

I2C

UART

(1:5)

IRQ

SSI

GPTA/B DMA

DMA

IRQ

WDT

(1:0)

IRQ

(1:0)

IRQ

(0:3)

IRQ

(3:0)

IRQ

ERR

IRQ

EPI

EMAC

IRQ

(1:0)

IRQ

DBG MONITOR

PENDING SV

SYS TICK

(8:1)

IRQ

EXCEPTIONS

FROM M3 CORE

NVIC

(NESTED VECTORED INTERRUPT CONTROLLER)

PROGRAM-

MABLE

INTERRUPTS

PRIORITY

INTERRUPTS

CTOM IPC (4:1)

FLSINGER

FLFSM

RAMSINGERR

APB BUS (REG ACCESS ONLY)

MEM

MNGMT

uDMA BUS

M3 uDMA BUS

M3 SYSTEM BUS

LOCAL MEMORY

S0-S7

SHARED

RAM

MTOC

MSG

CTOM

MSG

SECURE

FLASH

(ECC)

SECURE

C0/C1

RAM

C2/C3

RAM

DATA

IPC

BOOT

ROM

MPU /

BRIDGE

REGS

INSTRUCTIONS

RAM

(parity)

RAM

(parity)

(ECC)

SHARED RESOURCES

I-CODE BUS

D-CODE BUS

RAMUNCERR

FLASHUNCERR

BUS CNTRL/FAULT LOGIC

RAMACCVIOL

RAMUNCERR

BUSFAULT

C28x SUBSYSTEM

Figure 2-1. Master Subsystem

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.3.3 Cortex™-M3 Interrupts

Table 2-14 shows all interrupt assignments for the Cortex™-M3 processor. Most interrupts (16–107) are

associated with interrupt requests from Cortex™-M3 peripherals. The first 15 interrupts (1–15) are

processor exceptions generated by the Cortex™-M3 core itself. These processor exceptions are detailed

in Table 2-15.

Table 2-14. Interrupts from NVIC to Cortex™-M3

Interrupt Number

(Bit in Interrupt Registers)

Vector Number

Vector Address or Offset

Description

–

0–15

0x0000.0000–0x0000.003C

0x0000.0040

0x0000.0044

0x0000.0048

0x0000.004C

0x0000.0050

0x0000.0054

0x0000.0058

0x0000.005C

0x0000.0060

–

Processor exceptions

GPIO Port A

GPIO Port B

GPIO Port C

GPIO Port D

GPIO Port E

UART0

UART1

SSI0

I2C0

9–17

25–27

38–41

48–52

55–56

25–33

Reserved

0x0000.0088

0x0000.008C

0x0000.0090

0x0000.0094

0x0000.0098

0x0000.009C

0x0000.00A0

–

Watchdog Timers 0 and 1

Timer 0A

Timer 0B

Timer 1A

Timer 1B

Timer 2A

Timer 2B

41–43

Reserved

0x0000.00B0

0x0000.00B4

0x0000.00B8

0x0000.00BC

0x0000.00C0

0x0000.00C4

0x0000.00C8

0x0000.00CC

0x0000.00D0

0x0000.00D4

–

System Control

Flash State Machine

GPIO Port F

GPIO Port G

GPIO Port H

UART2

SSI1

Timer 3A

Timer 3B

I2C1

54–57

Reserved

0x0000.00E8

0x0000.00F0

–

Ethernet Controller

USB

Reserved

0x0000.00F8

0x0000.00FC

–

µDMA Software

µDMA Error

Reserved

64–68

0x0000.0114

0x0000.0118

–

EPI

GPIO Port J

Reserved

71–72

0x0000.0124

0x0000.0128

SSI 2

SSI 3

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-14. Interrupts from NVIC to Cortex™-M3 (continued)

Interrupt Number

(Bit in Interrupt Registers)

Vector Number

Vector Address or Offset

Description

0x0000.012C

UART3

0x0000.0130

–

UART4

61–63

77–79

Reserved

0x0000.0140

0x0000.0144

0x0000.0148

0x0000.014C

–

CAN1 INT0

CAN1 INT1

CAN1 INT0

CAN1 INT1

Reserved

68–71

84–87

0x0000.0160

0x0000.0164

0x0000.0168

0x0000.016C

0x0000.0170

0x0000.0174

0x0000.0178

0x0000.017C

0x0000.0180

0x0000.0184

0x0000.0188

0x0000.018C

–

ADCINT1

ADCINT2

ADCINT3

ADCINT4

ADCINT5

ADCINT6

ADCINT7

ADCINT8

CTOMIPC1

CTOMIPC2

CTOMIPC3

CTOMIPC4

Reserved

84–87

100–103

104

1–5

106

107

0x0000.01A0

0x0000.01A4

0x0000.01A8

0x0000.01AC

RAM Single Error

System / USB PLL Out of Lock

M3 Flash Single Error

Reserved

Table 2-15. Exceptions from Cortex™-M3 Core to NVIC

Vector Address or

Offset⁽²⁾

Exception Type

Priority⁽¹⁾

Vector Number

Activation

Stack top is loaded from

the first entry of the vector

table on reset.

–

0x0000.0000

0x0000.0004

Reset

–3 (highest)

Asynchronous

On Concerto devices

activated by clock fail

condition, C28 PIE error,

external M3GPIO NMI

input signal, and C28 NMI

WD timeout reset.

Non-Maskable Interrupt

(NMI)

–2

0x0000.0008

Hard Fault

–1

0x0000.000C

0x0000.0010

–

Memory Management

programmable⁽³⁾

Synchronous

(1) 0 is the default priority for all the programmable priorities

(2) See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto F28M35x

Technical Reference Manual (literature number SPRUH22).

(3) See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual (literature number

SPRUH22).

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-15. Exceptions from Cortex™-M3 Core to NVIC (continued)

Vector Address or

Offset⁽²⁾

Exception Type

Priority⁽¹⁾

Vector Number

Activation

Synchronous when

precise and asynchronous

when imprecise.

On Concerto devices

activated by memory

access errors and RAM

and flash uncorrectable

data errors.

Bus Fault

programmable⁽³⁾

0x0000.0014

Usage Fault

–

programmable⁽³⁾

–

0x0000.0018

–

Synchronous

Reserved

7–10

SVCall

programmable⁽³⁾

–

0x0000.002C

0x0000.0030

–

Synchronous

Reserved

Debug Monitor

–

PendSV

SysTick

Interrupts

programmable⁽³⁾

0x0000.0038

0x0000.003C

Asynchronous

(4)

programmable

16 and above

0x0000.0040 and above Asynchronous

(4) See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual (literature number

SPRUH22).

2.3.4 Cortex™-M3 Vector Table

Each peripheral interrupt of Table 2-14 is assigned an address offset containing the location of the

peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers

16–107).

Similarly, each exception interrupt of Table 2-15 (including Reset) is also assigned an address offset

containing the location of the exception interrupt handler (relative to the vector table base) for that

particular interrupt (vector numbers 1–15).

In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table

location 0.

Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can

write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different

memory location, in the range 0x0000 0200 to 0x3FFF FE00. Note that when configuring the VTABLE

2.3.5 Cortex™-M3 Local Peripherals

The Cortex™-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose

Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB +

PHY, EPI, and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus

(Advanced High-Performance Bus). The remaining peripherals are accessible through the APB Bus

(Advanced Peripheral Bus). The APB and AHB bus cycles originate from the CPU System Bus or the

µDMA Bus via a bus bridge.

While the Cortex™-M3 CPU has access to all the peripherals, the µDMA has access to most, with the

exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The

Cortex™-M3 peripherals connect to the Concerto™ device pins via GPIO_MUX1. Most of the peripherals

also generate event signals for the µDMA and/or the NVIC. The Watchdogs receive M3SWRST from the

NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI

Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets

block.

See Section 5.1 for more information on the Cortex™-M3 peripherals.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

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2.3.6 Cortex™-M3 Local Memory

The Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure C0/C1

RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both

accessible through the I-CODE and D-CODE Buses. Flash registers can also be accessed by the

Cortex™-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex™-M3 CPU; the

C2/C3 RAM is also accessible by the µDMA.

Two types of error correction events can be generated during access of the Local Memory: uncorrectable

errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a

Bus Fault Exception to the Cortex™-M3 CPU. The less critical single errors go to the NVIC where they

can result in maskable interrupts to the Cortex™-M3 CPU.

2.3.7 Cortex™-M3 Accessing Shared Resources and Analog Peripherals

There are several memories, digital peripherals, and analog peripherals that can be accessed by both the

Master and Control Subsystems. They are grouped into Shared Resources block and the Analog

Subsystem.

The Shared Resources block includes Inter-Processor Communications (IPC) registers, MTOC Message

RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks. The RAMs of the

Shared Resources block have Parity Error Checking.

The Message RAMs and the Shared RAMs can be accessed by the Cortex™-M3 CPU and µDMA. The

MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem,

having r/w access for the Cortex™-M3/µDMA and read-only access for the C28x/DMA. The CTOM

Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having

r/w access for the C28x/DMA and read-only access for the Cortex™-M3/µDMA.

The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the

Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the

Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays

associated with polling).

The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;

however, the direction of the data flow can be individually set for each block to be from Master to Control

Subsystem or from Control to Master Subsystem.

The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed by

both the Cortex™-M3 and C28x Subsystems through the Analog Common Interface Bus. The

Cortex™-M3 CPU accesses the ACIB through the System Bus, and the µDMA through the µDMA Bus.

The ACIB arbitrates for access to the ADC and Analog Comparator registers between CPU/DMA bus

cycles of the Master Subsystem with those of the Control Subsystem. In addition to managing bus cycles,

the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem (as well as to the

Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources from ADC2 are

AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations in both the

Master Subsystem and the Control Subsystem.

See Section 5.3 for more information on shared resources and analog peripherals.

2.4 Control Subsystem

The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block,

DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared

Resources (IPC, Message RAM, Shared RAM), and to Analog Peripherals via the Analog Common

Interface Bus.

Figure 2-2 shows the Control Subsystem.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

RAMUNCERR

GPIO_MUX1

M3 SUBSYSTEM

C28x NMI

ECCDBLERR

FLASHUNCERR

QUAL

SHARED RESOURCES

C28x LOCAL MEMORY

S0-S7

SHARED

RAM

MTOC

MSG

CTOM

MSG

SECURE

L0/L1

RAM

M0/M1

RAM

SECURE

L2/L3

RAM

IPC

BOOT

ROM

LPMWAKE

RAM

FLASH

(ECC)

REGS

(ECC)

(parity)

(ECC)

(parity)

MTOCIPC (4:1)

LVF

LUF

RAMACCVIOL

FLSINGERR

FLFSM

RAMSINGERR

C28x

FPU

PIE (PERIPHERAL INTERRUPT EXPANSION)

PIEINTRS (12:1)

DINTCH (6:1)

ADCINT (8:1)

ADCINT (4:1)

MXINTA, MRINTA

TINT 0,1,2

I2C

SCIRXINTA

SCITXINTA

SPI

C28x

CPU

C28x

TINT 0,1,2

XINT 2

DMA

EQEP(3:1)INT

EPWM(9:1)INT

EPWM(9:1)TZINT

ECAP(6:1)INT

XINT 1,2,3

SOCA (9:1), SOCB(9:1)

C28 DMA BUS

C28 CPU BUS

TINT1

TINT2

C28x

VCU

C28x PERIPHERALS

PERIPHERAL

I/O s

EQEP

ERR

C28NMI

C28NMIINT

ECCDBLERR

EMUSTOP

PIENMIERR

GPTRIP

(12:1)

GPTRIP

(12:7)

GPTRIP

(6:4)

CLOCKFAIL

C28NMIRST

SOCAO

SOCBO

SYNCO

GPIO_MUX1

M3 CLOCKS

RESETS

M3 NMI

C28x NMI

Figure 2-2. Control Subsystem

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

2.4.1 C28x CPU/FPU/VCU

The F28M35x Concerto™ MCU family is a member of the TMS320C2000™ MCU platform. The

Concerto™ C28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Piccolo™ MCUs,

combined with a single-precision (32-bit) IEEE 754 floating-point unit (FPU) of TI’s existing Delfino™

MCUs. It is a very efficient C/C++ engine, enabling users to develop their system control software in a

high-level language. It also enables math algorithms to be developed using C/C++. The device is as

efficient at DSP math tasks as it is at system control tasks. The 32 x 32-bit MAC 64-bit processing

capabilities enable the controller to handle higher numerical resolution problems efficiently. With the

addition of the fast interrupt response with automatic context save of critical registers, the device is

capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep

protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds

without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the

latency for conditional discontinuities. Special conditional store operations further improve performance.

The VCU extends the capabilities of the C28x CPU and C28x+FPU processors by adding additional

instructions to accelerate Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms. No changes have

been made to existing instructions, pipeline, or memory bus architecture. Therefore, programs written for

the C28x are completely compatible with the C28x+VCU.

There are two events generated by the FPU block that go to the C28x Peripheral Interrupt Expansion

(PIE): LVF and LUV. Inside PIE, these and other events from C28x peripherals and memories result in 12

PIE interrupts PIEINTS[12:1] into the C28x CPU. The C28x CPU also receives three additional interrupts

directly (instead of through PIE) from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block

(C28uNMIINT).

The C28x has two low-power modes: Idle and Standby.

2.4.2 C28x Peripheral Interrupt Expansion (PIE)

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The

PIE block can support up to 96 peripheral interrupts. On the F28M35x, 70 of the possible 96 interrupts are

used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines

(INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the

96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The

vector is automatically fetched by the CPU on servicing the interrupt. It takes eight CPU clock cycles to

fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt events.

Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled

or disabled within the PIE block.

See Table 2-16 for PIE interrupt assignments.

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-16. PIE Peripheral Interrupts⁽¹⁾

PIE INTERRUPTS

CPU INTERRUPTS

INTx.8

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

C28.LPMWAKE

(C28LPM)

TINT0

(TIMER 0)

0x0D4C

Reserved

–

0x0D4A

XINT2

–

0x0D48

XINT1

–

0x0D46

Reserved

–

0x0D44

ADCINT2

(ADC)

0x0D42

ADCINT1

(ADC)

0x0D40

INT1

0x0D4E

EPWM8_TZINT

(ePWM8)

EPWM7_TZINT

(ePWM7)

EPWM6_TZINT

(ePWM6)

EPWM5_TZINT

(ePWM5)

EPWM4_TZINT

(ePWM4)

EPWM3_TZINT

(ePWM3)

EPWM2_TZINT

(ePWM2)

EPWM1_TZINT

(ePWM1)

INT2

INT3

INT4

INT5

INT6

INT7

INT8

INT9

INT10

INT11

INT12

0x0D5E

0x0D5C

0x0D5A

0x0D58

0x0D56

0x0D54

0x0D52

0x0D50

EPWM8_INT

(ePWM8)

0x0D6E

EPWM7_INT

(ePWM7)

0x0D6C

EPWM6_INT

(ePWM6)

0x0D6A

EPWM5_INT

(ePWM5)

0x0D68

EPWM4_INT

(ePWM4)

0x0D66

EPWM3_INT

(ePWM3)

0x0D64

EPWM2_INT

(ePWM2)

0x0D62

EPWM1_INT

(ePWM1)

0x0D60

EPWM9_TZINT

(ePWM9)

Reserved

–

0x0D7C

ECAP6_INT

(eCAP6)

0x0D7A

ECAP5_INT

(eCAP5)

0x0D78

ECAP4_INT

(eCAP4)

0x0D76

ECAP3_INT

(eCAP3)

0x0D74

ECAP2_INT

(eCAP2)

0x0D72

ECAP1_INT

(eCAP1)

0x0D70

0x0D7E

EPWM9_INT

(ePWM9)

0x0D8E

Reserved

–

0x0D8C

Reserved

–

0x0D8A

Reserved

–

0x0D88

Reserved

–

0x0D86

EQEP3_INT

(eQEP3)

0x0D84

EQEP2_INT

(eQEP2)

0x0D82

EQEP1_INT

(eQEP1)

0x0D80

Reserved

–

0x0D9E

Reserved

–

0x0D9C

MXINTA

(McBSPA)

0x0D9A

MRINTA

(McBSPA)

0x0D98

Reserved

–

0x0D96

Reserved

–

0x0D94

SPITXINTA

(SPIA)

0x0D92

SPIRXINTA

(SPIA)

0x0D90

Reserved

–

0x0DAE

Reserved

–

0x0DAC

DINTCH6

(C28 DMA)

0x0DAA

DINTCH5

(C28 DMA)

0x0DA8

DINTCH4

(C28 DMA)

0x0DA6

DINTCH3

(C28 DMA)

0x0DA4

DINTCH2

(C28 DMA)

0x0DA2

DINTCH1

(C28 DMA)

0x0DA0

Reserved

–

0x0DBE

Reserved

–

0x0DBC

Reserved

–

0x0DBA

Reserved

–

0x0DB8

Reserved

–

0x0DB6

Reserved

–

0x0DB4

I2CINT2A

(I2CA)

0x0DB2

I2CINT1A

(I2CA)

0x0DB0

Reserved

–

0x0DCE

Reserved

–

0x0DCC

Reserved

–

0x0DCA

Reserved

–

0x0DC8

Reserved

–

0x0DC6

Reserved

–

0x0DC4

SCITXINTA

(SCIA)

0x0DC2

SCIRXINTA

(SCIA)

0x0DC0

ADCINT8

(ADC)

0x0DDE

ADCINT7

(ADC)

0x0DDC

ADCINT6

(ADC)

0x0DDA

ADCINT5

(ADC)

0x0DD8

ADCINT4

(ADC)

0x0DD6

ADCINT3

(ADC)

0x0DD4

ADCINT2

(ADC)

0x0DD2

ADCINT1

(ADC)

0x0DD0

Reserved

–

0x0DEE

Reserved

–

0x0DEC

Reserved

–

0x0DEA

Reserved

–

0x0DE8

MTOCIPCINT4

(IPC)

0x0DE6

MTOCIPCINT3

(IPC)

0x0DE4

MTOCIPCINT2

(IPC)

0x0DE2

MTOCIPCINT1

(IPC)

0x0DE0

LUF

(C28FPU)

0x0DFE

LVF

(C28FPU)

0x0DFC

Reserved

–

0x0DFA

C28RAMACCVIOL C28RAMSINGERR

C28FLFSM

(Memory)

0x0DF4

C28FLSINGERR

(Memory)

XINT3

(Ext. Int. 3)

0x0DF0

(Memory)

0x0DF8

(Memory)

0x0DF6

0x0DF2

(1) Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is

being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while

modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

1) No peripheral within the group is asserting interrupts.

2) No peripheral interrupts are assigned to the group (example PIE group 11).

2.4.3 C28x DMA

The C28x direct memory access (DMA) module provides a hardware method of transferring data between

peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other

system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is

transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into

blocks for optimal CPU processing. The interrupt trigger source for each of the six DMA channels can be

configured separately and each channel contains its own independent PIE interrupt to let the CPU know

when a DMA transfer has either started or completed. Five of the six channels are exactly the same, while

Channel 1 has one additional feature: the ability to be configured at a higher priority than the others.

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2.4.4 C28x Local Peripherals

The C28x local peripherals include NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI,

McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals are accessible

by the C28x CPU via the C28x Memory Bus. Additionally, the McBSP and ePWM are accessible by the

C28x DMA Bus. The Serial Port Peripherals and the Control Peripherals connect to Concerto’s pins via

the GPIO_MUX1 block. Internally, the C28x peripherals generate events to the PIE block, C28x DMA, and

the Analog Subsystem. The C28x NMI Watchdog receives a C28NMI event from the NMI block and sends

a counter timeout event to the Cortex™-M3 NMI block and the Resets block to flag a potentially critical

condition.

The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and

EPWMxB. These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and

EMUSTOP events from the C28x CPU, and up to 12 trips from GPIO_MUX1.

See Section 5.2 for more information on C28x peripherals.

2.4.5 C28x Local Memory

The C28x Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure

L0/L1 RAM with ECC; L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories

are accessible from the C28x CPU; the L2/L3 RAM is also accessible by the C28x DMA. Two types of

error correction events can be generated during access of the C28x Local Memory: uncorrectable errors

and single errors. The uncorrectable errors propagate to the NMI block where they can become the

C28NMI to the C28x NMI Watchdog and the C28NMIINT non-maskable interrupt to the C28x CPU. The

less critical single errors go to the PIE block where they can become maskable interrupts to the C28x

CPU.

2.4.6 C28x Accessing Shared Resources and Analog Peripherals

There are several memories, digital peripherals, and analog peripherals that can be accessed by both the

Master and Control Subsystems. They are grouped into the Shared Resources block and the Analog

Subsystem.

The Shared Resources block includes Inter-Processor Communications (IPC) registers, MTOC Message

RAM, CTOM Message RAM, and eight individually configurable Shared RAM blocks.

The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have

Parity-Error Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem

to the Control Subsystem, having r/w access for the Cortex™-M3/µDMA and read-only access for the

C28x/DMA. The CTOM Message RAM is intended for sending data from the Control Subsystem to the

Master Subsystem, having r/w access for the C28x/DMA and read-only access for the

Cortex™-M3/µDMA.

The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the

Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the

Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays

associated with polling).

The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;

however, the direction of the data flow can be individually set for each block to be from Master to Control

Subsystem or from Control to Master Subsystem.

See Section 5.3 for more information on shared resources and analog peripherals.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.5 Analog Subsystem

The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed

by both the Master Subsystem and Control Subsystem via the Analog Common Interface Bus. The C28x

CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through the C28x DMA Bus.

The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles

of the C28x Subsystem with those of the Cortex™-M3 Subsystem. In addition to managing bus cycles, the

ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion

ADC interrupts to both the Master Subsystem and the Control Subsystem.

There are 22 possible SOC (Start-Of-Conversion) sources from the C28x Subsystem that are mapped to a

total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).

Going the other way, eight EOC (End-Of-Conversion) sources from ADC1 and eight EOC sources from

ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control

Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same

eight go to the C28x DMA.

The Concerto™ MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1,

ADC2); six Analog Comparators + DAC units; and an Analog Common Interface Bus (ACIB) to facilitate

analog data communications with Concerto’s two digital subsystems (Cortex™-M3 and C28x).

Figure 2-3 shows the Analog Subsystem.

2.5.1 ADC1

The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which

10 are currently pinned out. One of the not-pinned-out channels is assigned to the internal temperature

sensor. The analog channels are internally pre-assigned to two Sample-and-Hold (S/H) units A and B,

both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in ADC1 result

registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional

channels or channel pairs are converted sequentially. Start-of-Conversion (SOC) triggers from the Control

Subsystem initiate analog-to-digital conversions. End-of-Conversion (EOC) interrupts from ADCs notify the

Master and Control Subsystems that the conversion results are ready to be read from ADC1 result

registers.

See Section 5.3.1 for more information on ADC peripherals.

2.5.2 ADC2

The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which

10 are currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H)

units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored

in the ADC2 result registers. The two S/H units enable simultaneous sampling of two analog signals at a

time. Additional channels or channel pairs are converted sequentially. Start-of-Conversion (SOC) triggers

from the Control Subsystem initiate analog-to-digital conversions. End-of-Conversion (EOC) interrupts

from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read

from ADC2 result registers.

See Section 5.3.1 for more information on ADC peripherals.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

AIO_MUX1

GPIO

MUX

ANALOG

COMMON

INTERFACE

BUS

ADC1INA0

ADC1INA1

ADC1INA3

ADC1INA4

ADC1INA6

ADC1INA7

ADC1INB0

ADC1INB3

ADC1INB4

ADC1INB7

ANALOG BUS

MCIBSTATUS REG

CPU

uDMA

ADC

TRIGS (8:1)

SYSTEM

BUS

uDMA

BUS

COMPA1

COMPA2

COMPA3

COMPB2

EOC

INTER-

RUPTS

(8:1)

ADC1INT (8:1)

ADC2INT (8:1)

VDDA

(3.3V)

ADCINT(8:1)

COMPARATOR

+ DAC UNITS

COMPOUT (6:1)

VSSA

(0V)

C28

CPU

BUS

C28

DMA

BUS

COMPA4

COMPA5

COMPA6

COMPB5

C28x

CPU

C28x

DMA

CCIBSTATUS REG

ADCINT

(4:1)

TRIGS (8:1)

ADC

SOC

TRIG-

GERS

(8:1)

TINT (2:0)

XINT2

ADC2INA0

ADC2INB0

ADC2INB3

ADC2INB4

ADC2INB7

ADC2INA2

ADC2INA3

ADC2INA4

ADC2INA6

ADC2INA7

SOC (9:1) A

SOC (9:1) B

TRIG8SEL REG

TRIG7SEL REG

. . .

GPIO

MUX

TIMER

(3)

XINT2

EPWM

(9)

TRIG2SEL REG

TRIG1SEL REG

AIO_MUX2

Figure 2-3. Analog Subsystem

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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2.5.3 Analog Comparator + DAC

There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs,

resulting in six digital comparison outputs. The external analog inputs that are being compared in the

comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared

against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual

Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be

mapped to six out of eight available pins.

Note that in order to use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first

routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before

they can be assigned to selected 12 ePWM Trip Inputs.

See Section 5.3.2 for more information on the analog comparator + DAC.

2.5.4 Analog Common Interface Bus (ACIB)

The ACIB bus links the Master and Control Subsystems with the Analog Subsystem. It enables the

Cortex™-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC

Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The

Cortex™-M3 uses its System Bus and the µDMA Bus to read from and write to Analog Subsystem

registers. The C28x uses its Memory Bus and the DMA bus to access the same Analog Subsystem

registers. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the

Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the

Analog Subsystem side.

Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger

destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC

interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems.

The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC

interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines

because it is unlikely that any application would need all 16 interrupts at the same time.

Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22

possible trigger sources to each SOC trigger.

There are two registers that provide status of ACIB to the Master Subsystem and to the Control

Subsystem.

The Cortex™-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly

powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and

interrupts are correctly propagating between the Master, Control, and Analog subsystems.

The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered

up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are

correctly propagating between the Master, Control, and Analog subsystems.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

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2.6 Master Subsystem NMIs

The Cortex™-M3 NMI Block generates an M3NMIINT non-maskable interrupt to the Cortex™-M3 CPU

and an M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or

outside the Concerto™ MCU. When able to respond to the M3NMIINT interrupt, the Cortex™-M3 CPU

may address the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out

and an M3NMIRST reset signal is sent to the Resets block.

The inputs to the Cortex™-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR,

VREGWARN and EXTGPIO signals. The C28NMIRST comes from the C28x NMI Watchdog and it

indicates that the C28x was not able to prevent the C28x NMI Watchdog counter from counting out.

PIENMIERR indicates that an error condition was generated during the NMI vector fetch from the C28x

Peripheral Interrupt Expansion (PIE) block. The CLOCKFAIL input comes from the Master Clocks Block,

announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition

inside the Analog Common Interface Bus. The VREGWARN input communicates a power anomaly.

EXTGPIO comes from the GPIO_MUX1 to announce an external emergency.

The Cortex™-M3 NMI block can be accessed via the Cortex™-M3 NMI configuration registers—including

the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources,

clear the flags, and force the flags to active state, respectively.

Figure 2-4 shows the Cortex™-M3 NMI and C28x NMI.

2.7 Control Subsystem NMIs

The C28x NMI Block generates a C28NMIINT non-maskable interrupt to the C28x CPU and a C28NMI

event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the

Concerto™ MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI

condition and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the

C28NMIRST reset signal is sent to the Resets block and the Cortex™-M3 NMI Block, where it can

generate an NMI to the Cortex™-M3 processor.

The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR,

and PIENMIERR signals. The CLOCKFAIL input comes from the Clocks Block, announcing a missing

clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common

Interface Bus. The RAMUCERR and FLASHUNCERR announce the occurrence of uncorrectable error

conditions during access to the Flash or RAM (local or shared). PIENMIERR indicates that an error

condition was generated during NMI vector fetch from the C28x Peripheral Interrupt Expansion (PIE)

block.

The C28x NMI block can be accessed via the C28x NMI configuration registers—including the CNMIFLG,

CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags,

and force the flags to active state, respectively.

Figure 2-4 shows the Cortex™-M3 NMI and C28x NMI.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

1.2V

VREG

M3 NMI

WDOG

M3 WDOG

(2)

VREGWARN

M3NMI

M3NMIRST

M3WDRST (1:0)

NMI

M3NMI

M3EXTNMI

M3NMIINT

GPIO_MUX

M3 NMI

M3 CPU

C28NMIRST

ACIBERR

ANALOG

SUBSYSTEM

M3WDRST (1:0)

M3NMIRST

RESETS

C28NMIRST

CLOCKFAIL

CLOCKS

PIENMIERR

C28NMIINT

C28NMI

C28x CPU

RAMUNCERR

C28x NMI

SHARED RAM

C28x LOCAL

RAM

FLASHUNCERR

C28NMI

C28NMIRST

C28x

FLASH

C28x NMI

WDOG

Figure 2-4. Cortex™-M3 NMI and C28x NMI

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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2.8 Resets

The Concerto™ MCU has two external reset pins: XRS for the Master and Control Subsystems, and ARS

for the Analog Subsystem. It is recommended that these two pins be externally tied together with a board

signal trace.

The XRS pin can receive an external reset signal from outside into the chip, and it can drive a reset signal

out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control

Subsystems. A reset pulse can also be driven out of the XRS pin by the voltage monitoring block of the

Master and Control Subsystems. A reset pulse can be driven out of the XRS pin when the two

Cortex™-M3 Watchdogs or the Cortex™-M3 NMI Watchdog time out.

The ARS pin can receive an external reset signal from outside into the chip, and it can drive a reset signal

out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A reset

pulse can be driven out of the ARS pin by the voltage monitoring block of the Analog Subsystem.

Figure 2-5 shows the resets.

2.8.1 Cortex™-M3 Resets

The Cortex™-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR

(Power-On Reset) or the M3SYSRST reset signal. In both cases, the Cortex™-M3 CPU restarts program

execution from the address provided by the reset entry in the vector table. A register can later be

referenced to determine the source of the reset. The M3SYSRST signal also propagates to the

Cortex™-M3 peripherals and the rest of the Cortex™-M3 Subsystem.

The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The

M3WDOGS is set in response to time-out conditions of the two Cortex™-M3 Watchdogs or the

Cortex™-M3 NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The

M3DBGRS is a debugger-generated reset that is also output by the NVIC. In addition to driving

M3SYSRST, these two resets also propagate to the C28x Subsystem and the Analog Subsystem.

The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from

the Cortex™-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface

Bus. In addition to driving reset signals to other parts of the chip, the Cortex™-M3 can also detect a

C28SYSRST reset being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS

Cortex™-M3 software can also set bits in the SRCR register to selectively reset individual Cortex™-M3

peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause

VMON/POR/BOR, Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC.

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

M3 WDOG (1)

M3 WDOG (0)

M3WDOGS

CRESSTS REG

CRESCNF REG

JTAG

CONTROLLER

( SETS DEFAULT VALUES ) XRS

SOFTWARE

POR

M3PORRST

VOLTAGE

REGULATION

AND

NVIC

CPU

NMI

MONITORING

XRS

WDOG

M3SYSRST

XRS

FLASH PUMP

M3SYSRST

M3SWRST

PERIPHERAL SOFTWARE RESETS

SRCR REG

M3DBGRST

SUBSYSTEM

MRESC REG

DC REG

CONTAINS RESET CAUSES

GLOBAL PERIPHERAL ENABLES

ARS

ACIBRST

SRXRST

ANALOG

SUBSYSTEM

XRS

GPIO_MUX

SHARED

RESOURCES

M3WDOGS

POR

C28x

SUBSYSTEM

‘0’

XRS

C28RSTIN

XRS

C28SYSRST

C28x

CPU

SYNC

DEGLITCH

M3SSCLK

C28x

NMI

XRS

WDOG

RESET INPUT SIGNAL STATUS

C28NMIWD

DEVICECNF REG

Figure 2-5. Resets

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2.8.2 C28x Resets

The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x

Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the

address provided at the top of the Boot ROM Vector Table.

The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the

M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The

M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated

reset that is also output by the NVIC. These two resets must be first enabled by the Cortex™-M3

processor in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex™-M3

Subsystem to selectively reset the C28x Subsystem from Cortex™-M3 software.

The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin

by reading the DEVICECNF register.

2.8.3 Analog Subsystem and Shared Resources Resets

Both the Analog Subsystem and the resources shared between the C28x and Cortex™-M3 subsystems

(IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog

Subsystem is also reset by the internal ACIBRST signal from the Cortex™-M3 Subsystem and the

external ARS pin (which should be externally tied to the XRS pin).

The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a

software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also

output by the NVIC. These two resets must be first enabled by the Cortex™-M3 processor in order to

propagate to the Analog Subsystem and the Shared Resources.

2.8.4 Device Boot Sequence

Concerto’s boot sequence is used to configure the Master Subsystem and the Control Subsystem for

execution of application code. It involves both internal resources, and resources external to the device.

These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-programmed inside

the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code (C-Bootloader)

factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); three GPIO_MUX1 pins for

Master boot mode selection; internal Flash and RAM memories; and selected Cortex™-M3 and C28x

peripherals for loading the application code into the Master and Control Subsystems.

The boot sequence starts when the Master Subsystem comes out of reset. This can be caused by device

power up, external reset, debugger reset, software reset, Cortex™-M3 watchdog reset, or Cortex™-M3

NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and

then both bootloaders work in tandem to configure the device, load application code for both processors (if

not already in the Flash), and branch the execution of each processor to a selected location in the

application code.

Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive

state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until

the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level

functions, then it initializes the Master Subsystem. Next, the M-Bootloader takes the Control Subsystem

and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out of reset, its own

C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the Control Subsystem,

the C-Bootloader enters the C28x processor into the idle mode (to wait for the M-Bootloader to wake it up

later via the MTOCIPC1 interrupt). Next, the M-Bootloader reads three GPIO pins (see Table 2-17) to

determine the boot mode for the rest of the M-Bootloader operation.

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-17. Master Subsystem Boot Mode Selection

PF3_GPIO35

(BOOT_2)

PG7_GPIO47

(BOOT_1)

PG3_GPIO43

(BOOT_0)

Boot Mode #

Master Subsystem Boot Modes

Boot from Parallel GPIO

Boot to Master Subsystem RAM

Boot from Master Subsystem serial

peripherals (UART0/SSI0/I2C0)

Boot from Master Subsystem CAN interface

Boot from Master Subsystem Ethernet

interface

Not supported (Defaults to Boot-to-Flash)

Boot to Master Subsystem Flash memory

Boot Mode 7 causes the Master program to branch execution to the application in the Master Flash

memory. This requires that the Master Flash be already programmed with valid code; otherwise, a hard

fault exception is generated and the Cortex™-M3 goes back to the above reset sequence. (Therefore, for

a factory-fresh device, the M-Bootloader will be in a continuous reset loop until the emulator is connected

and a debug session started.) If the Master Subsystem Flash has already been programmed, the

application code will start execution. Typically, the Master Subsystem application code will then establish

data communication with the C28x [through the IPC (Interprocessor Communications peripheral)] to

coordinate the rest of the boot process with the Control Subsystem. Boot Mode 7 typically does not

require any external signals to drive the three boot mode pins, as by default, all three pins are internally

pulled up to logic 1 (111b).

Boot Mode 1 causes the Master boot program to branch to Cortex™-M3 RAM, where it starts executing

code that has been preloaded earlier. Typically, this mode is used during development of application code

meant for Flash, but which has to be first tested running out of RAM. In this case, the user would typically

load the application code into RAM using the debugger, and then issue a debugger reset, while setting the

three boot pins to 001b. From that point on, the rest of the boot process on the Master Subsystem side is

controlled by the application code.

Boot Modes 0, 2, 3, and 4 are used to load the Master application code from an external peripheral before

branching to it. This is different from Boot Modes 7 and 1, where the application code was either already

programmed in Flash or loaded into RAM by the emulator. If the boot mode selection pins are set to 000b,

the M-Bootloader (running out of M-Boot ROM) will start uploading the Master application code from

preselected Parallel GPIO_MUX1 pins. If the boot pins are set to 010b, the application code will be loaded

from the Master Subsystem UART0, SSI0, or I2C0 peripheral. If the boot pins are set to 011b, the

application code will be loaded from the Master Subsystem CAN interface. Furthermore, if the boot pins

are set to 100b, the application code will be loaded through the Master Subsystem Ethernet interface.

Regardless of the type of boot mode selected, once the Master application code is resident in Master

Flash or RAM, the next step for the M-Bootloader is to branch to it. At that point, the application code

takes over control from the M-Bootloader, and the boot process continues as prescribed by the application

code. At this stage, the Master application program typically establishes communication with the

C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the C28x to

go into Idle mode. To wake the Control Subsystem out of Idle mode, the Master application issues the

Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1) . Once the data communication has been established

through the IPC, the boot process can now also continue on the Control Subsystem side.

The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing

IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and

acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be

established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except

for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through

the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts

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accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to

branch to preloaded code in RAM (development mode), or to upload the Control application code from

one of several available peripherals (see Table 2-18). As before, once the Control application is in place

(in Flash or RAM), the C-Bootloader branches to it, and from that point on, the application code takes

over.

Table 2-18. Control Subsystem Boot Mode Selection

Control Subsystem

Boot Modes

MTOCIPCBOOTMODE

Description

Upon receiving this command from the Master Subsystem, C-Boot

ROM will branch to the Control Subsystem RAM entry point location

and start executing code from there.

BOOT_FROM_RAM

0x0000 0001

0x0000 0002

Upon receiving this command, C-Boot ROM will branch to the

Control Subsystem FLASH entry point and start executing code from

there.

BOOT_FROM_FLASH

Upon receiving this command, C-Boot ROM will boot from the

Control Subsystem SCI peripheral.

BOOT_FROM_SCI

BOOT_FROM_SPI

0x0000 0003

0x0000 0004

0x0000 0005

0x0000 0006

Upon receiving this command, C-Boot ROM will boot from the

Control Subsystem SPI interface.

Upon receiving this command, C-Boot ROM will boot from the

Control Subsystem I2C interface.

BOOT_FROM_I2C

Upon receiving this command, C-Boot ROM will boot from the

Control Subsystem GPIO.

BOOT_FROM_PARALLEL

The boot process can be considered completed once the Cortex™-M3 and C28x are both running out of

their respective application programs. Note that following the boot sequence, the C-Bootloader is still

available to interpret and act upon an assortment of IPC commands that can be issued from the Master

Subsystem to perform a variety of configuration, housekeeping, and other functions. See the Concerto

F28M35x Technical Reference Manual (literature number SPRUH22) for additional information on

Concerto boot modes, IPC commands, and the underlying boot philosophy.

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2.9 Master Subsystem Clocking

The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a

divided-down output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the

SYSPLLCTL register.

There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The

10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source

to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the

10MHZCLK for the PLLSYSCLK. CLKFAIL signal is also sent to the NMI Block and the Control

Subsystem where it can trip the ePWM peripherals.

The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex™-M3 Subsystem as possible

sources for the Deep Sleep Clock.

There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and

SYSDIVSEL. Typically, the Cortex™-M3 processor writes to these registers, while the C28x processor has

read access. The C28x can request write access to the above registers through the CLKREQEST register.

Cortex™-M3 can regain write ownership of these registers through the MCLKREQUEST register.

The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode.

Table 2-19 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and

peripherals. Figure 2-6 shows the Cortex™-M3 clocks and the Master Subsystem low-power modes.

Table 2-19. Master Subsystem Low-Power Modes

Used to

Gate Clocks Main

Cortex™-M3

Low-Power Cortex™-M3

State of

Clock to

Cortex™-M3

Peripherals

Clock to

Analog

Subsystem

USB

PLL

Clock to Shared

Resources

Clock to C28x

PLL

Mode

CPU

Cortex™-M3

Peripherals

Run

Active

M3SSCLK⁽¹⁾

RCGC

PLLSYSCLK⁽²⁾

ASYSCLK⁽³⁾

RCGC or

SCGC⁽⁴⁾

Sleep

Stopped

RCGC or

DCGC⁽⁴⁾

Deep Sleep

Stopped

M3DSDIVCLK⁽⁵⁾

Off

(1) PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes

10MHZCLK divided-down per the M3SSDIVSEL register.

(2) PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the

PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is

substituted for the PLLSYSCLK.

(3) PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK.

(4) Depends on the ACG bit of the RCC register.

(5) 32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL

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M3 CPU

ASSERT ANY INTERRUPT

NVIC

INTR

TO EXIT SLEEP OR DEEP SLEEP

execution of WFI or WFE instr

activates low power modes

SELECTS TYPE

OF WAKEUP

ACCESS

SLEEPONEXIT

ACCESS

FCLK

HCLK

M3CLKENBx

M3SSCLK

PERIPH

LOGIC

SYSCTRL REG

M3SSCLK

OSCCLK

WDOG 1

SELECTS BETWEEN SLEEP

AND DEEP SLEEP MODES

SLEEPDEEP

WDOG 0

RCC REG

ENABLE

CLOCK MODE

ENTER A LOW POWER MODE

PERIPH

LOGIC

M3SSCLK

OSCCLK

XCLKIN

uCRC

NMI WDOG

GP TIMER (4)

SSI (4)

CAN

1,2

ACG (Auto Clock Gate)

CLOCKS

M3RUN

PERIPHERAL

CLOCK

ENABLES

M3CLKENBx

M3SLEEP

USB + PHY

(OTG)

M3DEEPSLEEP

USBPLLCLK

RCGC REG

( CLOCK GATING– RUN )

( CLOCK GATING– SLEEP )

SCGC REG

DCGC REG

DC REG

M3DEEPSLEEP

PLL

DIS

USB

PLL

( CLOCK GATING– DEEP SLEEP )

UART (5)

I2C (2)

DSLPCLKCFG REG

DSOSCSRC

M3SSDIVSEL REG

OSCCLK

XCLKIN

( GLOBAL PERIPHERAL ENABLES )

DSDIVOVRIDE

M3SSDIVSEL

32KHZCLK

10MHZCLK

OSCCLK

M3DSDIVCLK

M3SSCLK

OSCCLK

…

/16

EMAC

XCLKIN

GPIO_MUX1

EPI

MCLKREQUEST REG

SYSDIVSEL REG

SYSPLLSTAT REG

SYSPLLMULT REG

SYSPLLCTL REG

uDMA

32KHZCLK

10MHZCLK

OSCCLK

IPC

SYSDIVSEL

MAIN OSC

OFF

OSCCLK

SHARED

RAMS

PLLSYSCLK

INTERNAL

OSC

MISSING

CLK DETECT

PLL

DIS

MAIN

PLL

MSG

RAMS

10MHZCLK

CLOCKFAIL

CLPMSTAT REG

CLOCKFAIL

M3 NMI

SHARED

10MHZCLK

CLOCKFAIL

OSCCLK

RESOURCES

CONTROL SUBSYSTEM

Figure 2-6. Cortex™-M3 Clocks and Low-Power Modes

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2.9.1 Cortex™-M3 Run Mode

In Run Mode, the Cortex™-M3 processor, memory, and most of the peripherals are clocked by the

M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from

a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of

two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is

accomplished via corresponding peripheral configuration registers. Clock gating for individual peripherals

is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to

peripherals that are enabled in a corresponding DC (Device Configuration) register.

Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex™-M3 CPU and

forces the Cortex™-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of

the SLEEPDEEP bit of the Cortex™-M3 SYSCTRL register. To come out of a low-power mode, any

properly configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex™-M3

processor/subsystem to Run Mode.

2.9.2 Cortex™-M3 Sleep Mode

In Sleep Mode, the Cortex™-M3 processor and memory are prevented from clocking, and thus the code is

no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC

Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS

clock-gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral

clock frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode.

Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode

depends on the Sleeponexit bit of the SYSCTRL register. When the Sleeponexit bit is 1, the processor will

temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the

processor goes back to Sleep Mode. When the Sleeponexit bit is 0, the processor wakes up permanently

(for the ISR and thereafter).

2.9.3 Cortex™-M3 Deep Sleep Mode

In Deep Sleep Mode, the Cortex™-M3 processor and memory are prevented from clocking and thus the

code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input

clock to the C28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may

change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as

defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from

the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a

corresponding DC register.

Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run

Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected

with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to

DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further

divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If

32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates

OSCCLK) is turned off.

The Cortex™-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is

already in the Standby mode. Typically, just before entering the Standby mode, the C28x will record in the

CLPMSTAT that it is about to do so. The Cortex™-M3 processor can read the CLPMSTAT register to

check if the C28x is in Standby mode, and only then should it go into Deep Sleep. The reason for this is

that the Deep Sleep mode shuts down the clock to C28x and its peripherals, and if this is not expected by

the C28x, it could result in unintended consequences for some of its control peripherals.

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Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep

Mode depends on the Sleeponexit bit of the SYSCTRL register. When the Sleeponexit bit is 1, the

processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up.

After that, the processor goes back to Deep Sleep Mode. When the Sleeponexit bit is 0, the processor

wakes up permanently (for the ISR and thereafter).

2.10 Control Subsystem Clocking

The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1

external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT,

SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex™-M3 processor writes to these registers, while the

C28x processor has read access. The C28x can request write access to the above registers through the

CLKREQEST register. The Cortex™-M3 can regain write ownership of these registers through the

MCLKREQUEST register.

Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals. This is

done via the CPCLKCR0,2,3 registers.

The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK.

The Control Subsystem operates in one of three modes: Normal Mode, Idle Mode, or Standby Mode.

Table 2-20 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and

peripherals. Figure 2-7 shows the Control Subsystem clocks and low-power modes.

Table 2-20. Control Subsystem Low-Power Modes⁽¹⁾

Registers Used to Gate

C28x Low-Power Mode

State of C28x CPU

C28CPUCLK⁽²⁾

C28SYSCLK⁽³⁾

Clocks to C28x

Peripherals

Normal

Idle

Active

Off

CPCLKCR0,1,3

N/A

Stopped

Standby

(1) The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem

enters the Deep Sleep mode.

(2) C28CPUCLK is an output from the C28x CPU and it clocks the C28x FPU, VCU, and PIE.

(3) C28SYSCLK is an output from the C28x CPU and it clocks C28x peripherals.

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GPIO_MUX1

C28x NMI

MASTER SUBSYSTEM

ACIBRST

ASYSRST

SRXRST

CCLKCTL REG

CLKDIV

CLOCKFAIL

SYSDIVSEL REG

SYSPLLSTAT REG

SYSPLLMULT REG

SYSPLLCTL REG

CLPMSTAT REG

10MHZCLK

OSCCLK

OFF

HISPCP REG

HSPCLK

ASYSCLK

CCLKREQUEST REG

PULSE

C28HSPCLK

PLLSYSCLK

C28SYSCLK

XPLLCLKCFG REG

XPLLCLKOUTDIV

STRETCH

…

/14

C28SYSCLK

XCLKOUT

GPIO_MUX1

LOSPCP REG

LSPCLK

CLKOFF REG

EPWM (9)

C28CLKINDIS

‘0’

TINT2

TINT 1

TIMER 2

TIMER 1

C28LSPCLK

STANDBY

MODE

C28CLKIN

McBSP

SCI

…

/14

C28x CPU

TIMER 0

EXIT

STANDBY

MODE

EXIT

IDLE

MODE

execution of IDLE instruction

activates the IDLES signal

SPI

C28 XINT(3)

PIEINTRS (1)

I2C

PIEINTRS (12:1)

C28NMIINT

ENTER

STANDBY

MODE

IDLES

ENTER

IDLE

MODE

C28x

PIE

MTOCIPC(1)

C28 DMA

C28 FPU/VCU

C28x

PIE

LPM(1)

LPM(0)

EQEP (3)

ECAP (6)

CLPMCR0 REG

C28CPUCLK

C28SYSCLK

CLKCTL REG

LPMWAKE

CPCLKCR3 REG

CPCLKCR1 REG

CPCLKCR0 REG

QUAL

CTMR2CLK

PRESCALE

STDBY

(7:2)

TMR2CLKSRCSEL

OSC

CLK

QUAL

GPI (63:0)

GPIO_MUX1

C28SYSCLK

OSCCLK

C28CLKENBx

C28x NMI

IPC

/16

10MHZCLK

Figure 2-7. C28x Clocks and Low-Power Modes

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

2.10.1 C28x Normal Mode

In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the

C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and

PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be

clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK,

OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can

be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals; and

the HISPCP register can be programmed to provide a dedicated clock (C28HSPCLK) to stretch three

outputs from ePWM peripherals.

Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the

IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES

signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into Idle mode

or Standby Mode.

2.10.2 C28x Idle Mode

In Idle Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The

C28SYSCLK continues to run. Exit from Idle Mode is accomplished by any enabled interrupt or the

C28NMIINT (C28x non-maskable interrupt).

Upon exit from Idle Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE

ISR is executed. Next, the C28x processor starts fetching instructions from a location immediately

following the IDLE instruction that originally triggered the Idle Mode.

2.10.3 C28x Standby Mode

In Standby Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK, and

C28SYSCLK are turned off. Exit from Standby Mode is accomplished by one of 66 GPIOs from the

GPIO_MUX1 block, or MTOCIPCINT1 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected

inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the

Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the

CPCLKCR0 register) before propagating into the wake request logic.

Cortex™-M3 should use CLPMSTAT register bits to tell the C28x to go into Standby mode before going

into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control

software is not expecting it to shut off. When the device is in Deep Sleep/Standby mode, wake-up should

happen only from the Master Subsystem, since all C28x clocks are off (C28CLKIN, C28CPUCLK,

C28SYSCLK), thus preventing the C28x from waking up first.

Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the

LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching

instructions from a location immediately following the IDLE instruction that originally triggered the Standby

Mode.

2.11 Analog Subsystem Clocking

The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as

defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the

C28x processor, it is reset by ASYSRST, which is derived from two Analog Subsystem resets—ACIBRST

and SRXRST. Therefore, while normally the C28x controls the frequency of ASYSCLK, it is possible for

the Cortex™-M3 software to restore the ASYSCLK to its default value by resetting the Analog Subsystem.

The ASYSCLK is shut down when the Cortex™-M3 processor enters the Deep Sleep mode.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.12 Shared Resources Clocking

All Shared Resources (IPC, Shared RAMs, and Message RAMs) are clocked by PLLSYSCLK. The

PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In

case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL

2.13 GPIOs and Other Pins

Most Concerto external pins are shared among many internal peripherals. This is accomplished through

several I/O muxes where a specific physical pin can be assigned to selected signals of internal

peripherals.

Most of the I/O pins of the Concerto™ MCU can also be configured as programmable GPIOs. Exceptions

include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and

VREG18EN internal voltage regulator enables; and five JTAG pins. The 74 primary GPIOs are grouped in

2 programmable blocks: GPIO_MUX1 block (66 pins) and GPIO_MUX2 block (8 pins). Additionally, eight

secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins).

Figure 2-8 shows the GPIOs and other pins.

2.13.1 GPIO_MUX1

The 66 pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers

to all Cortex™-M3 peripherals, all C28x peripherals, 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External

Interrupts to the C28x PIE, the C28x Standby Mode Wakeup signal (LMPWAKE), 64 General-Purpose

Inputs or 64 General-Purpose Outputs, or a mixture of all of the above. Additionally, each GPIO_MUX1

pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled on reset, and

all pins of the GPIO_MUX1 block are mapped to Cortex™-M3 peripherals (and not to C28x peripherals).

Figure 2-9 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem

side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center,

Pin-Level Mux, is where the 66 GPIO_MUX1 pins are individually assigned between the two subsystems,

based on how the configuration registers are programmed in the blue and green blocks (see Figure 2-10

for the configuration registers).

Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or

GPIOs to the 66 Concerto pins. In addition to connecting peripheral I/Os of the two subsystems to pins,

the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[H:A] IRQ signals to

the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN

carries a clock from an external pin to USB PLL and CAN modules. The eight GPIO[H:A] IRQ signals are

interrupt requests from selected external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1]

signals carry trip events from selected external pins to C28x control peripherals—ePWM, eCAP, and

eQEP. The 64 GPI[63:0] signals go to the C28x QUAL block, where any one of them can be selected and

qualified to wake up the C28x CPU from Standby Low-Power Mode.

The configuration registers for the muxing of Master Subsystem peripherals are organized in nine sets

(A–J), with each set being responsible for up to eight pins. These registers are programmable by the

Cortex™-M3 CPU via the AHB bus or the APB bus. The configuration register for the muxing of Control

Subsystem peripherals are organized in three sets (A–C), with each set being responsible for up to

32 pins. These registers are programmable by the C28x CPU via the C28x CPU bus. Figure 2-10 shows

set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem registers,

and the muxing logic for one GPIO pin as driven by these registers.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

AIO_MUX1

GPIO

MUX

ADC1INA0

ADC1INA2

ADC1INA3

ADC1INA4

ADC1INA6

ADC1INA7

ADC1INB0

ADC1INB3

ADC1INB4

ADC1INB7

USB

PLL

EPI

USB

EMAC

UART

(5)

CAN

SSI

(4)

I2C

(2)

NVIC

NMI

(2)

COMPA1

COMPA2

COMPA3

ADC

COMPB2

VDDA

(3.3V)

GPIO

GPIO_MUX1

MUX

COMPARATOR

+ DAC UNITS

GPI (63:0)

COMPOUT (6:1)

VSSA

(0V)

QUAL

LPMWAKE

C28X

CPU

EPWM

(9)

XINT

(3)

ECAP

(6)

EQEP

(3)

SPI

I2C

SCI

COMPA4

COMPA5

COMPA6

ADC

COMPB5

McBSP

ADC2INA0

ADC2INA2

ADC2INA3

ADC2INA4

ADC2INA6

ADC2INA7

ADC2INB0

ADC2INB3

ADC2INB4

ADC2INB7

VREGS

DEBUG

RESETS

CLOCKS

NMI

GPIO

MUX

AIO_MUX2

Figure 2-8. GPIOs and Other Pins

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

M3 AHB BUS

M3 APB BUS

BUS BRIDGE

XCLKIN

CAN

USB

PLL

UART

(5)

SSI

(4)

I2C

(2)

USB

EPI

EMAC

(2)

uDMA

CPU

NMI

EXT

NMI

INTERRUPTS

M3 PERIPHERAL SIGNAL ROUTING

NVIC

M3 MUX A

M3 MUX B

M3 MUX D

M3 MUX E

M3 MUX F

M3 MUX G

M3 MUX H

M3 MUX J

M3 MUX C

XCLKIN

GPIO

(H:A)

IRQ

PIN - LEVEL MUX

GPIO

PINS

GPTRIP

(12:1)

GPI

(63:0)

C28 MUX A

C28 MUX B

C28 MUX C

C28 PERIPHERAL SIGNAL ROUTING

QUAL

LPM

WAKE

C28x

DMA

C28x

CPU

EQEP

(3)

ECAP

(6)

EPWM

(9)

XINT

(3)

McBSP

SCI

SPI

I2C

GPTRIP (12:7)

GPTRIP (12:1)

GPTRIP (6:4)

C28 CPU BUS

C28 DMA BUS

Figure 2-9. GPIO_MUX1 Block

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

PERIPHERALS 1-15 REPRESENT A SET OF UP TO

15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN

TO/FROM M3 PERIPH 1-11

TO/FROM M3 PERIPH 12-15

M3 CLOCKS

A-H INTR REQUESTS TO M3

BLUE REGISTER SET A

BREPRESENTS 8 OF 66

DEVICE I/Os. REMAINING

58 I/Os ARE CONTROLLED

BY SIMILAR REGISTER

SETS B, C, D, E, F, I, J, H

GPIO63 XCLKIN

ONLY

GPIO (A)

IRQ

GPIOPCTL REG

PRIMARY

ALT

M3 REG SET A

GPIOAMSEL REG

GPIOIS REG

GPIOIBE REG

GPIOIEV REG

GPIOIM REG

GPIORIS REG

GPIOMIS REG

GPIOICR REG

M3 REG SET A

GREY LOGIC IS SPECIFIC

TO ONE DEVICE I/O PIN

PRIMARY

AT RESET

GPIOAPSEL REG

(USB ANALOG SIGNALS)

DISABLED

AT RESET

M3 REG SET A

ENB

GPIODATA REG

GPIODIR REG

XRS

GPIOPUR REG

M3 REG SET A

GPIOODR REG

GPIOCSEL REG

GPIODEN REG

GPIOAFSEL REG

GPIOLOCK REG

GPIOCR REG

M3 REG SET A

NORMAL

AT RESET

SELECT M3

AT RESET

I/O DISABLED

AT RESET

GPIO MODE

AT RESET

‘1’

PULL UP

INPUT

OUTPUT

‘0’

(4 PINS ONLY)

ANALOG USB

SIGNALS

(M3 GPIO)

ONE OF 66

GPIO_MUX1

PINS

OUTPUT

DISABLED

OPEN

DRAIN

LOGIC

GPIOAMSEL REG

AFTER RESET

‘1’

ASYNC INPUT

ORANGE LOGIC SHOWS

USB ANALOG FUNCTIONS

(APPLIES TO 4 PINS

ONLY)

XRS

SYNC INPUT

SYNC

C28 REG SET A

GPACTRL REG

QUAL

GREEN REGISTER SET A

SHOWN REPRESENTS 32

OF 66 DEVICE I/Os. THE

REMAINING 34 I/Os ARE

CONTROLLED BY SIMILAR

(C28 GPIO)

C28SYSCLK

C28 REG SET A

6 SAMPLES

3 SAMPLES

GPASET REG

GPACLEAR REG

GPATOGGLE REG

GPADIR REG

OUTPUTS

GPASEL1 REG

GPASEL2 REG

SYNC INPUT

AT RESET

GPIO

SEL(1:0)

AT RESET

C28 REG SET A

GPADAT REG

EACH I/O PIN HAS A

DEDICATED PAIR OF

BITS FOR MUX SELECT

GPAMUX1 REG

GPAMUX2 REG

EACH I/O PIN HAS A

DEDICATED PAIR OF

BITS FOR MUX SELECT

SEL(1:0)

INPUTS

N/C AT RESET

TO XINT,

ECAP, EPWM

C28x CPU WAKE-UP FROM

A LOW POWER MODE

C28 REG SET A

N/C

PERIPHERALS 1 3 REPRESENT A SET OF UP TO

THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN

FROM C28 PERIPH 1-3

GPI (63:0)

TO C28 PERIPH 1-3

GPTRIP (12:1)

Figure 2-10. GPIO_MUX1 Pin Mapping Through Register Set A

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

For each of the 8 pins in set A of the Cortex™-M3 GPIO registers, register GPIOPCTL selects between

1 of 11 possible primary Cortex™-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals.

pin. The input takes the reverse path. See Table 2-21 and Table 2-22 for the mapping of Cortex™-M3

peripheral pins to the 66 pins of GPIO_MUX1.

Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral

signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along

the muxing chain towards a given pin. The input takes the reverse path. See Table 2-23 for the mapping

of C28x peripheral pins to the 66 pins of GPIO_MUX1.

In addition to passing mostly digital signals, a few GPIO_MUX1 pins can also be assigned to analog

signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB

signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes

USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, the corresponding pins

are not available for digital GPIO_MUX1 options as described above.

Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin

PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. It is always

available at these modules where it can be selected through local registers.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-21. GPIO_MUX1 Pin Assignments (M3 Primary Modes)⁽¹⁾

Analog

Mode

(USB Pins)

Primary

Mode 1

Primary

Mode 2

Primary

Mode 3

Primary

Mode 4

Primary

Mode 5

Primary

Mode 6

Primary

Mode 7

Primary

Mode 8

Primary

Mode 9

Primary

Mode 10

Primary

Mode 11

Device

Pin Name

–

PA0_GPIO0

PA1_GPIO1

PA2_GPIO2

PA3_GPIO3

PA4_GPIO4

PA5_GPIO5

PA6_GPIO6

PA7_GPIO7

PB0_GPIO8

PB1_GPIO9

PB2_GPIO10

PB3_GPIO11

PB4_GPIO12

PB5_GPIO13

PB6_GPIO14

PB7_GPIO15

PD0_GPIO16

PD1_GPIO17

PD2_GPIO18

PD3_GPIO19

PD4_GPIO20

PD5_GPIO21

PD6_GPIO22

PD7_GPIO23

PE0_GPIO24

PE1_GPIO25

PE2_GPIO26

PE3_GPIO27

PE4_GPIO28

PE5_GPIO29

PE6_GPIO30

PE7_GPIO31

U0RX

U0TX

SSI0CLK

SSI0FSS

SSI0RX

SSI0TX

I2C1SCL

I2C1SDA

CCP0

CCP2

I2C0SCL

I2C0SDA

–

I2C1SCL

U1RX

–

I2C1SDA

U1TX

–

MMI_TXD2

–

MMI_TXD1

–

MMI_TXD0

–

CAN0RX

–

MMI_RXDV

–

CAN0TX

–

CCP1

MMI_RXCK

–

CAN0RX

–

USB0EPEN

U1CTS

–

CCP4

MMI_RXER

–

CAN0TX

CCP3

USB0PFLT

U1DCD

–

U1RX

–

CCP1

U1TX

–

CCP3

CCP0

–

USB0EPEN

–

USB0PFLT

–

U2RX

CAN0RX

–

U1RX

EPI0S23

–

CCP5

CCP7

–

CCP6

CCP0

CAN0TX

CCP2

U1TX

EPI0S22

–

CCP1

–

CCP5

–

NMI

–

MII_RXD1

–

PWM0

PWM1

U1RX

U1TX

CCP0

CCP2

Fault0

IDX0

CAN0RX

CAN0TX

CCP6

CCP7

CCP3

CCP4

–

U2RX

U1RX

CCP6

MII_RXDV

–

U1CTS

–

U2TX

U1TX

CCP7

MII_TXER

–

U1DCD

CCP2

–

CCP5

–

EPI0S20

–

CCP0

–

EPI0S21

–

MII_TXD3

–

U1RI

EPI0S19

–

MII_TXD2

–

U2RX

EPI0S28

–

MII_TXD1

–

U2TX

EPI0S29

–

CCP1

MII_TXD0

–

U1DTR

EPI0S30

PWM4

PWM5

CCP4

CCP1

CCP3

CCP5

–

SSI1CLK

SSI1FSS

SSI1RX

SSI1TX

–

CCP3

–

EPI0S8

USB0PFLT

–

CCP2

CCP6

CCP2

CCP7

U2TX

–

EPI0S9

–

EPI0S24

–

EPI0S25

–

CCP2

MII_RXD0

–

U1CTS

U1DCD

–

(1) Blank fields represent Reserved functions.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-21. GPIO_MUX1 Pin Assignments (M3 Primary Modes)⁽¹⁾(continued)

Analog

Mode

(USB Pins)

Primary

Mode 1

Primary

Mode 2

Primary

Mode 3

Primary

Mode 4

Primary

Mode 5

Primary

Mode 6

Primary

Mode 7

Primary

Mode 8

Primary

Mode 9

Primary

Mode 10

Primary

Mode 11

Device

Pin Name

–

PF0_GPIO32

PF1_GPIO33

PF2_GPIO34

PF3_GPIO35

PF4_GPIO36

PF5_GPIO37

PF6_GPIO38

CAN1RX

CAN1TX

–

MII_RXCK

–

U1DSR

U1RTS

SSI1CLK

SSI1FSS

SSI1RX

SSI1TX

–

MII_RXER

–

CCP3

–

MII_PHYINTR

MII_MDC

MII_MDIO

MII_RXD3

MII_RXD2

–

CCP0

CCP2

CCP1

EPI0S12

EPI0S15

–

USB0VBUS

U1RTS

PF7_GPIO39

(no pin)

–

PG0_GPIO40

PG1_GPIO41

PG2_GPIO42

PG3_GPIO43

U2RX

U2TX

–

I2C1SCL

I2C1SDA

MII_COL

MII_CRS

–

USB0EPEN

EPI0S13

–

USB0DM

–

EPI0S14

–

PG4_GPIO44

(no pin)

–

USB0DP

PG5_GPIO45

PG6_GPIO46

PG7_GPIO47

PH0_GPIO48

PH1_GPIO49

PH2_GPIO50

PH3_GPIO51

PH4_GPIO52

PH5_GPIO53

PH6_GPIO54

PH7_GPIO55

PJ0_GPIO56

PJ1_GPIO57

PJ2_GPIO58

PJ3_GPIO59

PJ4_GPIO60

PJ5_GPIO61

PJ6_GPIO62

CCP5

–

MII_TXEN

–

U1DTR

–

USB0ID

–

MII_TXCK

–

U1RI

–

MII_TXER

–

CCP5

EPI0S31

–

CCP6

MII_PHYRST

–

EPI0S6

EPI0S7

EPI0S1

EPI0S0

EPI0S10

EPI0S11

EPI0S26

EPI0S27

EPI0S16

EPI0S17

EPI0S18

EPI0S19

EPI0S28

EPI0S29

EPI0S30

–

CCP7

–

MII_TXD3

MII_TXD2

MII_TXD1

MII_TXD0

MII_RXDV

–

USB0EPEN

–

USB0PFLT

–

SSI1CLK

–

SSI1FSS

–

SSI1RX

MII_RXCK

SSI1TX

MII_RXER

–

I2C1SCL

–

USB0PFLT

CCP0

–

I2C1SDA

–

U1CTS

U1DCD

U1DSR

U1RTS

CCP6

CCP4

CCP2

CCP1

PJ7_GPIO63/

XCLKIN

–

U1DTR

CCP0

–

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-21. GPIO_MUX1 Pin Assignments (M3 Primary Modes)⁽¹⁾(continued)

Analog

Mode

(USB Pins)

Primary

Mode 1

Primary

Mode 2

Primary

Mode 3

Primary

Mode 4

Primary

Mode 5

Primary

Mode 6

Primary

Mode 7

Primary

Mode 8

Primary

Mode 9

Primary

Mode 10

Primary

Mode 11

Device

Pin Name

PC0_GPIO64

(no pin)

–

PC1_GPIO65

(no pin)

PC2_GPIO66

(no pin)

PC3_GPIO67

(no pin)

–

PC4_GPIO68

PC5_GPIO69

PC6_GPIO70

PC7_GPIO71

CCP5

CCP1

CCP3

CCP4

–

MII_TXD3

–

CCP2

CCP3

U1RX

U1TX

CCP4

USB0EPEN

CCP0

–

EPI0S2

EPI0S3

EPI0S4

EPI0S5

CCP1

–

USB0PFLT

CCP0

USB0PFLT

–

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-22. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)⁽¹⁾

Alternate

Mode 12

Alternate

Mode 13

Alternate

Mode 14

Alternate

Mode 15

Analog Mode

(USB Pins)

Device Pin Name

–

PA0_GPIO0

PA1_GPIO1

PA2_GPIO2

PA3_GPIO3

PA4_GPIO4

PA5_GPIO5

PA6_GPIO6

PA7_GPIO7

PB0_GPIO8

PB1_GPIO9

PB2_GPIO10

PB3_GPIO11

PB4_GPIO12

PB5_GPIO13

PB6_GPIO14

PB7_GPIO15

PD0_GPIO16

PD1_GPIO17

PD2_GPIO18

PD3_GPIO19

PD4_GPIO20

PD5_GPIO21

PD6_GPIO22

PD7_GPIO23

PE0_GPIO24

PE1_GPIO25

PE2_GPIO26

PE3_GPIO27

PE4_GPIO28

PE5_GPIO29

PE6_GPIO30

PE7_GPIO31

PF0_GPIO32

PF1_GPIO33

PF2_GPIO34

PF3_GPIO35

PF4_GPIO36

PF5_GPIO37

PF6_GPIO38

–

SSI1FSS

–

U1CTS

U1DCD

U1DSR

U1RTS

U1DTR

U1RI

CAN1TX

–

SSI1CLK

–

MII_RXD1

–

SSI2TX

SSI2RX

SSI2CLK

SSI2FSS

–

U4TX

–

CAN1RX

U1RX

CAN1TX

CAN1RX

U1TX

U1RX

CAN1TX

CAN1RX

U1TX

U1RX

U3TX

U3RX

I2C1SDA

I2C1SCL

CAN0RX

CAN0TX

U2RX

U2TX

–

U4RX

–

SSI1TX

SSI1RX

SSI1CLK

SSI1FSS

USB0EPEN

USB0PFLT

CAN0RX

CAN0TX

CAN1TX

CAN1RX

U1TX

U1RX

SSI1TX

SSI1RX

SSI1CLK

SSI1FSS

USB0EPEN

USB0PFLT

–

MII_CRS

I2C0SDA

I2C0SCL

SSI0TX

SSI0RX

SSI0CLK

SSI0FSS

–

MII_RXD2

–

MII_COL

–

SSI3TX

SSI3RX

SSI3CLK

SSI3FSS

U0RX

U0TX

CAN0RX

CAN0TX

I2C0SDA

I2C0SCL

–

MII_TXER

–

MII_MDIO

–

MII_RXD3

–

XCLKOUT

–

U0TX

U0RX

–

USB0VBUS

–

PF7_GPIO39

(no pin)

–

(1) Blank fields represent Reserved functions.

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-22. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)⁽¹⁾(continued)

Alternate

Mode 12

Alternate

Mode 13

Alternate

Mode 14

Alternate

Mode 15

Analog Mode

(USB Pins)

Device Pin Name

–

PG0_GPIO40

PG1_GPIO41

PG2_GPIO42

PG3_GPIO43

MII_RXD2

MII_RXD1

–

U4RX

U4TX

–

USB0DM

–

MII_RXDV

–

PG4_GPIO44

(no pin)

–

USB0DP

PG5_GPIO45

PG6_GPIO46

PG7_GPIO47

PH0_GPIO48

PH1_GPIO49

PH2_GPIO50

PH3_GPIO51

PH4_GPIO52

PH5_GPIO53

PH6_GPIO54

PH7_GPIO55

PJ0_GPIO56

PJ1_GPIO57

PJ2_GPIO58

PJ3_GPIO59

PJ4_GPIO60

PJ5_GPIO61

PJ6_GPIO62

–

USB0ID

–

MII_RXD0

–

SSI3TX

SSI3RX

SSI3CLK

SSI3FSS

U3TX

–

U3RX

–

MII_TXEN

MII_TXCK

–

SSI0TX

SSI0RX

SSI0CLK

SSI0FSS

SSI0CLK

SSI0FSS

SSI1CLK

SSI1FSS

U2RX

–

MII_RXDV

MII_RXCK

MII_MDC

MII_COL

MII_CRS

MII_PHYINTR

–

U0TX

U0RX

–

PJ7_GPIO63/

XCLKIN

–

MII_PHYRST

U2TX

–

PC0_GPIO64

(no pin)

–

PC1_GPIO65

(no pin)

PC2_GPIO66

(no pin)

PC3_GPIO67

(no pin)

–

PC4_GPIO68

PC5_GPIO69

PC6_GPIO70

PC7_GPIO71

–

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 2-23. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)⁽¹⁾

C28x

Peripheral

Mode 0

C28x

Peripheral

C28x

Peripheral

Mode 2

C28x

Peripheral

Mode 3

Analog Mode

(USB Pins)

Devices Pin Name

Mode 1

EPWM1A

EPWM1B

EPWM2A

EPWM2B

EPWM3A

EPWM3B

EPWM4A

EPWM4B

EPWM5A

EPWM5B

EPWM6A

EPWM6B

EPWM7A

EPWM7B

EPWM8A

EPWM8B

SPISIMOAO

SPISOMIAO

SPICLKAO

SPISTEAO

EQEP1A

EQEP1B

EQEP1SO

EQEP1IO

ECAP1

–

PA0_GPIO0

PA1_GPIO1

PA2_GPIO2

PA3_GPIO3

PA4_GPIO4

PA5_GPIO5

PA6_GPIO6

PA7_GPIO7

PB0_GPIO8

PB1_GPIO9

PB2_GPIO10

PB3_GPIO11

PB4_GPIO12

PB5_GPIO13

PB6_GPIO14

PB7_GPIO15

PD0_GPIO16

PD1_GPIO17

PD2_GPIO18

PD3_GPIO19

PD4_GPIO20

PD5_GPIO21

PD6_GPIO22

PD7_GPIO23

PE0_GPIO24

PE1_GPIO25

PE2_GPIO26

PE3_GPIO27

PE4_GPIO28

PE5_GPIO29

PE6_GPIO30

PE7_GPIO31

PF0_GPIO32

PF1_GPIO33

PF2_GPIO34

PF3_GPIO35

PF4_GPIO36

PF5_GPIO37

PF6_GPIO38

GPIO0

–

GPIO1

ECAP6

–

GPIO2

–

GPIO3

ECAP5

–

GPIO4

–

GPIO5

MFSRAO

ECAP1

–

GPIO6

–

EPWMSYNCO

–

GPIO7

MCLKRAO

ECAP2

–

GPIO8

–

ADCSOCAO

–

GPIO9

–

ECAP3

–

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

GPIO35

GPIO36

GPIO37

GPIO38

–

ADCSOCBO

–

ECAP4

–

MDXA

–

MDRA

–

MCLKXAO

–

MFSXAO

–

EQEP2A

–

ECAP2

EQEP2B

–

ECAP3

EQEP2IO

–

ECAP4

EQEP2SO

–

SCIRXDA

SCITXDA

–

EPWM9A

–

EPWM9B

–

SDAAOC

SCLAOC

ECAP1

SCIRXDA

ADCSOCAO

–

EPWMSYNCO

ADCSOCBO

–

SCIRXDA

XCLKOUT

–

SCITXDA

SCIRXDA

ECAP2

–

USB0VBUS

–

PF7_GPIO39

(no pin)

–

GPIO39

–

(1) Blank fields represent Reserved functions.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 2-23. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)⁽¹⁾(continued)

C28x

Peripheral

Mode 0

C28x

Peripheral

Mode 1

C28x

Peripheral

Mode 2

C28x

Peripheral

Mode 3

Analog Mode

(USB Pins)

Devices Pin Name

–

PG0_GPIO40

PG1_GPIO41

PG2_GPIO42

PG3_GPIO43

GPIO40

GPIO41

GPIO42

GPIO43

–

USB0DM

–

PG4_GPIO44

(no pin)

–

GPIO44

–

USB0DP

PG5_GPIO45

PG6_GPIO46

PG7_GPIO47

PH0_GPIO48

PH1_GPIO49

PH2_GPIO50

PH3_GPIO51

PH4_GPIO52

PH5_GPIO53

PH6_GPIO54

PH7_GPIO55

PJ0_GPIO56

PJ1_GPIO57

PJ2_GPIO58

PJ3_GPIO59

PJ4_GPIO60

PJ5_GPIO61

PJ6_GPIO62

GPIO45

GPIO46

GPIO47

GPIO48

GPIO49

GPIO50

GPIO51

GPIO52

GPIO53

GPIO54

GPIO55

GPIO56

GPIO57

GPIO58

GPIO59

GPIO60

GPIO61

GPIO62

–

USB0ID

–

ECAP5

ECAP6

EQEP1A

EQEP1B

EQEP1SO

EQEP1IO

SPISIMOAO

SPISOMIAO

SPICLKAO

SPISTEAO

MCLKRAO

MFSRAO

–

EQEP3A

EQEP3B

EQEP3SO

EQEP3IO

EPWM7A

EPWM7B

EPWM8A

EPWM8B

EPWM9A

–

PJ7_GPIO63/

XCLKIN

–

GPIO63/XCLKIN

GPIO64

–

EPWM9B

PC0_GPIO64

(no pin)

–

PC1_GPIO65

(no pin)

GPIO65

PC2_GPIO66

(no pin)

GPIO66

PC3_GPIO67

(no pin)

GPIO67

–

PC4_GPIO68

PC5_GPIO69

PC6_GPIO70

PC7_GPIO71

GPIO68

GPIO69

GPIO70

GPIO71

–

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.13.2 GPIO_MUX2

The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight

General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each

GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are

configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed

through a separate set of registers from those used to program GPIO_MUX1.

The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set E.

They are accessible by the C28x CPU only. The middle portion of Figure 2-11 shows set E of Control

Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPEMUX1 register

selects one of six possible digital output signals from analog comparators, or one of eight general-purpose

GPIO digital outputs. The GPEPUD register disables pullups for the GPIO_MUX2 pins when a

corresponding bit of that register is set to “1”. Other registers of set E allow reading and writing of the eight

GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 2-24 for the

mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2.

Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPIOEMUX1 register to “00”,

“01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPIOEMUX1 register to “00”

(Peripheral Mode 0) assigns pin GPIO130 to internal signal GPIO130 (digital GPIO). Setting bits 5–4 of

the GPIOEMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO130 to internal signal COMP6OUT

coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently

available.

Table 2-24. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)⁽¹⁾

C28x

Peripheral

Mode 0

C28x

Peripheral

Mode 1

C28x

Peripheral

Mode 2

C28x

Peripheral

Mode 3

Device Pin Name

GPIO128

GPIO129

GPIO130

GPIO131

GPIO132

GPIO133

GPIO134

GPIO135

GPIO128

GPIO129

GPIO130

GPIO131

GPIO132

GPIO133

GPIO134

GPIO135

–

COMP1OUT

COMP6OUT

COMP2OUT

COMP3OUT

COMP4OUT

–

COMP5OUT

(1) Blank fields represent Reserved functions.

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

ADC1INA0

ADC1INA1

ADC1INA3

ADC1INA4

ADC1INA6

ADC1INA7

ADC1INB0

ADC1INB3

ADC1INB4

ADC1INB7

ADC

ONE OF 10

AIO_MUX1

PINS

AIOMUX1 REG

AIOSET REG

AIOCLEAR REG

AIOTOGGLE REG

AIODIR REG

AIO2

AIO4

AIO6

AIO12

AIODIR REG

AIODAT REG

COMPB2 COMPA1

COMPA2

COMPA3

COMPOUT1

DISABLED

COMPOUT2

AT RESET

COMPARATOR

+ DAC UNITS

COMPOUT3

DIS

ARS

COMPOUT4

COMPOUT5

COMPOUT6

GGPPIEOPPUUDR RREEGG

C28

CPU

BUS

COMPB5 COMPA4

COMPA5

ANALOG BUS

C28x

CPU

GPIO128

GPIO129

GPIO130

GPIO131

GPIO132

GPIO133

GPIO134

GPIO135

GPIO_MUX2

COMPA6

‘1’

PULL UP

GPEMUX1 REG

GPEDIR REG

GPESET REG

GPECLEAR REG

GPETOGGLE REG

GPEDIR REG

ONE OF 8

GPIO_MUX2

PINS

GPEDAT REG

ANALOG

COMMON

INTERFACE

BUS

ADC2INA0

ADC2INA1

ADC2INA3

ADC2INA4

ADC2INA6

ADC2INA7

ADC2INB0

ADC2INB3

ADC2INB4

ADC2INB7

ADC

ONE OF 10

AIO_MUX2

PINS

AIO_MUX2

AIOSET REG

AIOCLEAR REG

AIOTOGGLE REG

AIODIR REG

AIOMUX2 REG

AIODIR REG

AIO18

AIO20

AIO22

AIO28

AIODAT REG

Figure 2-11. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

2.13.3 AIO_MUX1

The ten pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to ten analog

inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or

four General-Purpose Outputs. Note that while AIO_MUX1 has been named after the analog signals

passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in

the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the

AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1

block is programmed through a separate set of registers from those used to program AIO_MUX2.

The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU

only. The top portion of Figure 2-11 shows Control Subsystem registers and muxing logic for the

associated ten AIO pins. The AIOMUX1 register selects one of ten possible analog input signals or one of

four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as

setting the direction for each of the bits (read or write). See Table 2-25 for the mapping of analog inputs

and AIOs to the ten pins of AIO_MUX1.

AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen

by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1

enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are

“don’t cares”.

Table 2-25. AIO_MUX1 Pin Assignments (C28x AIO Modes)⁽¹⁾⁽²⁾

Device Pin Name

ADC1INA0

ADC1INA2

ADC1INA3

ADC1INA4

ADC1INA6

ADC1INA7

ADC1INB0

ADC1INB3

ADC1INB4

ADC1INB7

C28x AIO Mode 0⁽³⁾

C28x AIO Mode 1⁽⁴⁾

ADC1INA0

–

AIO2

–

ADC1INA2, COMPA1

ADC1INA3

AIO4

AIO6

–

ADC1INA4, COMPA2

ADC1INA6, COMPA3

ADC1INA7

–

ADC1INB0

–

ADC1INB3

AIO12

–

ADC1INB4, COMPB2

ADC1INB7

(1) Blank fields represent Reserved functions.

(2) For each field with two pins (e.g., ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be disabled.

Use registers inside the respective destination analog peripherals to enable or disable these inputs.

(3) AIO Mode 0 represents digital general-purpose inputs or outputs.

(4) AIO Mode 1 represents analog inputs for ADC1 or the Comparator module.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

2.13.4 AIO_MUX2

The ten pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to ten analog

inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or

four General-Purpose Outputs. Note that while AIO_MUX2 has been named after the analog signals

passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in

the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the

AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2

block is programmed through a separate set of registers from those used to program AIO_MUX1.

The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU

only. The bottom portion of Figure 2-11 shows Control Subsystem registers and muxing logic for the

associated ten AIO pins. The AIOMUX2 register selects one of ten possible analog input signals or one of

four general-purpose AIO inputs. Other registers allow reading and writing of the four AIO bits, as well as

setting the direction for each of the bits (read or write). See Table 2-26 for the mapping of analog inputs

and AIOs to the ten pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available.

AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen

by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2

enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are

“don’t cares”.

Table 2-26. AIO_MUX2 Pin Assignments (C28x AIO Modes)⁽¹⁾⁽²⁾

Device Pin Name

ADC2INA0

ADC2INA2

ADC2INA3

ADC2INA4

ADC2INA6

ADC2INA7

ADC2INB0

ADC2INB3

ADC2INB4

ADC2INB7

C28x AIO Mode 0⁽³⁾

C28x AIO Mode 1⁽⁴⁾

ADC2INA0

–

AIO18

ADC2INA2, COMPA4

ADC2INA3

–

AIO20

ADC2INA4, COMPA5

ADC2INA6, COMPA6

ADC2INA7

AIO22

–

ADC2INB0

–

AIO28

–

ADC2INB3

ADC2INB4, COMPB5

ADC2INB7

(1) Blank fields represent Reserved functions.

(2) For each field with two pins (e.g., ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be disabled.

Use registers inside the respective destination analog peripherals to enable or disable these inputs.

(3) AIO Mode 0 represents digital general-purpose inputs or outputs.

(4) AIO Mode 1 represents analog inputs for ADC2 or the Comparator module.

Device Overview

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

3 Device Pins

3.1 Pin Assignments

Figure 3-1 shows the 144-pin RFP PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) pin

assignments.

PG5_GPIO45

PG2_GPIO42

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

GPIO135/COMP5OUT

GPIO134

GPIO133/COMP4OUT

GPIO132/COMP3OUT

VREG18EN

PG6_GPIO46

PF6_GPIO38

PD7_GPIO23

V_DDIO

ADC1INB7

ADC1INB4

V_DD12

PD4_GPIO20

PD5_GPIO21

PJ0_GPIO56

PJ1_GPIO57

ADC1INB3

ADC1INB0

ADC1V_REFLO, V_SSA1

V_DDA1

ADC1V_REFHI

ADC1INA0

ADC1INA2

ADC1INA3

ADC1INA4

ADC1INA6

ADC1INA7

ADC2INA7

ADC2INA6

PJ2_GPIO58

PJ3_GPIO59

V_DDIO

V_DD12

PJ4_GPIO60

PJ5_GPIO61

V_DD12

V_DDIO

PJ6_GPIO62

PG7_GPIO47

PF5_GPIO37

PG1_GPIO41

PG0_GPIO40

PF4_GPIO36

PH5_GPIO53

PH4_GPIO52

PE1_GPIO25

V_DDIO

PE0_GPIO24

PH1_GPIO49

PH0_GPIO48

PC7_GPIO71

PC6_GPIO70

PC5_GPIO69

PC4_GPIO68

ADC2INA4

ADC2INA3

ADC2INA2

ADC2INA0

ADC2V_REFHI

V_DDA2

ADC2V_REFLO, V_SSA2

ADC2INB0

ADC2INB3

ADC2INB4

ADC2INB7

GPIO128

GPIO129/COMP1OUT

GPIO130/COMP6OUT

GPIO131/COMP2OUT

ARS

A. See Table 3-1, Terminal Functions, for the complete multiplexed signal names.

Figure 3-1. 144-Pin RFP PowerPAD™ HTQFP (Top View)

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

3.2 Terminal Functions

Table 3-1 describes the signals.

Table 3-1. Terminal Functions⁽¹⁾

TERMINAL

I/O/Z⁽²⁾

RFP

DESCRIPTION

NAME

PIN #

ADC 1 Inputs, Analog Comparator Inputs, AIO Group 1

ADC1 External High Reference – only used when in ADC external reference

mode.

ADC1V_REFHI

120

118

ADC1V_REFLO

V_SSA1

ADC1 External Low Reference – only used when in ADC external reference

mode, ADC1 Ground.

ADC1INA0

ADC1INA2

COMPA1

AIO2

121

122

ADC1 Group A, Channel 0 input

ADC1 Group A, Channel 2 input

Comparator Input A1

I/O

Digital AIO2

ADC1INA3

ADC1INA4

COMPA2

AIO4

123

124

ADC1 Group A, Channel 3 input

ADC1 Group A, Channel 4 input

Comparator Input A2

I/O

Digital AIO4

ADC1INA6

COMPA3

AIO6

125

ADC1 Group A, Channel 6 input

Comparator Input A3

I/O

Digital AIO6

ADC1INA7

ADC1INB0

ADC1INB3

ADC1INB4

COMPB2

AIO12

126

117

116

115

ADC1 Group A, Channel 7 input

ADC1 Group B, Channel 0 input

ADC1 Group B, Channel 3 input

ADC1 Group B, Channel 4 input

Comparator Input B2

I/O

Digital AIO12

ADC1INB7

114

ADC1 Group B, Channel 7 input

ADC 2 Inputs, Analog Comparator Inputs, AIO Group 2

ADC2 External High Reference – only used when in ADC external reference

mode.

ADC2V_REFHI

133

135

ADC2V_REFLO

V_SSA2

ADC2 External Low Reference – only used when in ADC external reference

mode, ADC2 Ground.

ADC2INA0

ADC2INA2

COMPA4

AIO18

132

131

ADC2 Group A, Channel 0 input

ADC2 Group A, Channel 2 input

Comparator Input A4

I/O

Digital AIO18

ADC2INA3

ADC2INA6

COMPA6

AIO22

130

128

ADC2 Group A, Channel 3 input

ADC2 Group A, Channel 6 input

Comparator Input A6

I/O

Digital AIO22

ADC2INA4

COMPA5

AIO20

129

ADC2 Group A, Channel 4 input

Comparator Input A5

I/O

Digital AIO20

(1) Throughout this table, Master Subsystem signals are denoted by the color "blue"; Control Subsystem signals are denoted by the color

"green"; and Analog Subsystem signals are denoted by the color "orange".

(2) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

ADC2INA7

ADC2INB0

ADC2INB3

ADC2INB4

COMPB5

AIO28

127

136

137

138

ADC2 Group A, Channel 7 input

ADC2 Group B, Channel 0 input

ADC2 Group B, Channel 3 input

ADC2 Group B, Channel 4 input

Comparator Input B5

I/O

Digital AIO28

ADC2INB7

139

ADC2 Group B, Channel 7 input

Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only)

GPIO128

140

141

I/O

General-purpose input/output 128

GPIO129

General-purpose input/output 129

COMP1OUT

GPIO130

Compare result from Analog Comparator 1

General-purpose input/output 130

142

143

112

111

I/O

COMP6OUT

GPIO131

Compare result from Analog Comparator 6

General-purpose input/output 131

I/O

COMP2OUT

GPIO132

Compare result from Analog Comparator 2

General-purpose input/output 132

I/O

COMP3OUT

GPIO133

Compare result from Analog Comparator 3

General-purpose input/output 133

I/O

COMP4OUT

GPIO134

Compare result from Analog Comparator 4

General-purpose input/output 134

110

109

I/O

GPIO135

General-purpose input/output 135

COMP5OUT

Compare result from Analog Comparator 5

GPIO Group 1 and Peripheral Signals

PA0_GPIO0

M_U0RX

I/O/Z

General-purpose input/output 0

UART-0 receive data

M_I2C1SCL

M_U1RX

I/OD

I2C-1 clock open-drain bidirectional port

UART-1 receive data

C_EPWM1A

PA1_GPIO1

M_U0TX

Enhanced PWM-1 output A

General-purpose input/output 1

UART-0 transmit data

I/O/Z

M_I2C1SDA

M_U1TX

I/OD

I2C-1 data open-drain bidirectional port

UART-1 data transmit

M_SSI1FSS

C_EPWM1B

C_ECAP6

I/O

SSI-1 frame

Enhanced PWM-1 output B

Enhanced Capture-6 input/output

General-purpose input/output 2

SSI-0 clock

I/O

I/O/Z

I/O

PA2_GPIO2

M_SSI0CLK

M_MIITXD2

M_U1CTS

C_EPWM2A

EMAC MII transmit data bit 2

UART-1 clear-to-send modem status

Enhanced PWM-2 output A

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PA3_GPIO3

PIN #

I/O/Z

General-purpose input/output 3

SSI-0 frame

M_SSI0FSS

M_MIITXD1

M_U1DCD

M_SSI1CLK

C_EPWM2B

C_ECAP5

I/O

EMAC MII transmit data bit 1

UART-1 data carrier detect

SSI-1 clock

I/O

Enhanced PWM-2 output B

Enhanced Capture-5 input/output

General-purpose input/output 4

SSI-0 clock

I/O

PA4_GPIO4

M_SSI0RX

M_MIITXD0

M_CAN0RX

M_U1DSR

C_EPWM3A

PA5_GPIO5

M_SSI0TX

M_MIIRXDV

M_CAN0TX

M_U1RTS

I/O/Z

I/O

EMAC MII transmit data bit 0

CAN-0 receive data

UART-1 data set ready

Enhanced PWM-3 output A

General-purpose input/output 5

SSI-0 transmit data

I/O/Z

EMAC MII receive data valid

CAN-0 transmit data

UART-1 request-to-send

Enhanced PWM-3 output B

McBSP-A receive frame sync

Enhanced Capture-1 input/output

General-purpose input/output 6

C_EPWM3B

C_MFSRA

C_ECAP1

I/O

PA6_GPIO6

M_I2C1SCL

M_CCP1

I/O/Z

I/OD

I2C-1 clock open-drain bidirectional port

Capture/Compare/PWM-1 (General-purpose Timer)

EMAC MII receive clock

I/O

M_MIIRXCK

M_CAN0RX

M_USB0EPEN

M_U1CTS

CAN-0 receive data

USB-0 external power enable (optionally used in host mode

UART-1 clear-to-send modem status

UART-1 data terminal ready

M_U1DTR

C_EPWM4A

Enhanced PWM-4 output A

C_EPWMSYNCO

PA7_GPIO7

M_I2C1SDA

M_CCP4

Enhanced PWM-4 external sync pulse

General-purpose input/output 7

I/O/Z

I/OD

I2C-1 data open-drain bidirectional port

Capture/Compare/PWM-4 (General-purpose Timer)

EMAC MII receive error

I/O

M_MIIRXER

M_CAN0TX

M_CCP3

I/O

CAN-0 transmit data

Capture/Compare/PWM-3 (General-purpose Timer)

USB-0 external power error state (optionally used in the host mode)

UART-1 data carrier detect

M_USB0PFLT

M_U1DCD

M_MII_RXD1

M_U1RI

EMAC MII receive data 1

UART-1 ring indicator status

C_EPWM4B

C_MCLKRA

C_ECAP2

Enhanced PWM-4 output B

McBSP-A receive clock

I/O

Enhanced Capture-1 input/output

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

PB0_GPIO8

M_CCP0

I/O/Z

I/O

General-purpose input/output 8

Capture/Compare/PWM-0 (General-purpose Timer)

UART-1 data receive data

M_U1RX

M_SSI2TX

M_CAN1TX

M_U4TX

SSI-2 transmit data

CAN-1 transmit data

UART-4 transmit data

C_EPWM5A

C_ADCSOCAO

PB1_GPIO9

M_CCP2

Enhanced PWM-5 output A

ADC start-of-conversion A

I/O/Z

I/O

General-purpose input/output 9

Capture/Compare/PWM-2 (General-purpose Timer)

Capture/Compare/PWM-1 (General-purpose Timer)

UART-1 transmit data

M_CCP1

M_U1TX

M_SSI2RX

C_EPWM5B

C_ECAP3

SSI-2 receive data

Enhanced PWM-5 output B

I/O

I/O/Z

I/OD

I/O

Enhanced Capture-3 input/output

General-purpose input/output 10

I2C-0 clock open-drain bidirectional port

Capture/Compare/PWM-3 (General-purpose Timer)

Capture/Compare/PWM-0 (General-purpose Timer)

USB-0 external power enable (optionally used in the host mode)

SSI-2 clock

PB2_GPIO10

M_I2C0SCL

M_CCP3

M_CCP0

M_USB0EPEN

M_SSI2CLK

M_CAN1RX

M_U4RX

I/O

CAN-1 receive data

UART-4 receive data

C_EPWM6A

C_ADCSOCBO

PB3_GPIO11

M_I2C0SDA

M_USB0PFLT

M_SSI2FSS

M_U1RX

Enhanced PWM-6 output A

ADC start-of-conversion B

I/O/Z

I/OD

General-purpose input/output 11

I2C-0 data open-drain bidirectional port

USB-0 external power error state (optionally used in the host mode)

SSI-2 frame

I/O

UART-1 receive data

C_EPWM6B

C_ECAP4

Enhanced PWM-6 output B

I/O

I/O/Z

Enhanced Capture-4 input/output

General-purpose input/output 12

UART-2 receive data

PB4_GPIO12

M_U2RX

M_CAN0RX

M_U1RX

CAN-0 receive data

UART-1 receive data

M_EPIOS23

M_CAN1TX

M_SSI1TX

C_EPWM7A

I/O

EPI-0 signal 23

CAN-1 transmit data

SSI-1 transmit data

Enhanced PWM-7 output A

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PB5_GPIO13

PIN #

I/O/Z

I/O

General-purpose input/output 13

M_CCP5

Capture/Compare/PWM-5 (General-purpose Timer)

Capture/Compare/PWM-6 (General-purpose Timer)

Capture/Compare/PWM-0 (General-purpose Timer)

CAN-0 transmit data

M_CCP6

M_CCP0

M_CAN0TX

M_CCP2

I/O

Capture/Compare/PWM-2 (General-purpose Timer)

UART-1 transmit data

M_U1TX

M_EPI0S22

M_CAN1RX

M_SSI1RX

C_EPWM7B

PB6_GPIO14

M_CCP1

I/O

EPI-0 signal 22

CAN-1 receive data

SSI-1 receive data

Enhanced PWM-7 output B

I/O/Z

I/O

General-purpose input/output 14

Capture/Compare/PWM-1 (General-purpose Timer)

Capture/Compare/PWM-7 (General-purpose Timer)

Capture/Compare/PWM-5 (General-purpose Timer)

EMAC MII carrier sense

M_CCP7

M_CCP5

M_MIICRS

M_I2C0SDA

M_U1TX

I/OD

I2C-0 data open-drain bidirectional port

UART-1 transmit data

M_SSI1CLK

C_EPWM8A

PB7_GPIO15

M_EXTNMI

M_MIIRXD1

M_I2C0SCL

M_U1RX

I/O

EMAC MII carrier sense

Enhanced PWM-8 output A

I/O/Z

General-purpose input/output 15

Cortex™-M3 external non-maskable interrupt

EMAC MII receive data 1

I/OD

I2C-0 clock open-drain bidirectional port

UART-1 receive data

M_SSI1FSS

C_EPWM8B

PD0_GPIO16

M_CAN0RX

M_U2RX

I/O

SSI-1 frame

Enhanced PWM-8 output B

102

I/O/Z

General-purpose input/output 16

CAN-0 receive data

UART-2 receive data

M_U1RX

UART-1 receive data

M_CCP6

I/O

Capture/Compare/PWM-6 (General-purpose Timer)

EMAC MII receive data valid

M_MIIRXDV

M_U1CTS

M_MIIRXD2

M_SSI0TX

M_CAN1TX

M_USB0EPEN

C_SPISIMOA

UART-1 clear-to-send modem status

EMAC MII receive data 2

SSI-0 transmit data

CAN-1 transmit data

USB-0 external power enable (optionally used in the host mode)

SPI-A slave in, master out

I/O

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

PD1_GPIO17

M_CAN0TX

M_U2TX

I/O/Z

General-purpose input/output 17

CAN-0 transmit data

UART-2 transmit data

M_U1TX

UART-1 transmit data

M_CCP7

I/O

Capture/Compare/PWM-7 (General-purpose Timer)

EMAC MII transmit error

M_MIITXER

M_U1DCD

M_CCP2

UART-1 data carrier detect

Capture/Compare/PWM-2 (General-purpose Timer)

EMAC MII collision detect

I/O

M_MIICOL

M_SSI0RX

M_CAN1RX

M_USB0PFLT

C_SPISOMIA

PD2_GPIO18

M_U1RX

SSI-0 receive data

CAN-1 receive data

USB-0 external power error state (optionally used in the host mode)

SPI-A master in, slave out

I/O

I/O/Z

General-purpose input/output 18

UART-1 receive data

M_CCP6

I/O

Capture/Compare/PWM-6 (General-purpose Timer)

Capture/Compare/PWM-5 (General-purpose Timer)

EPI-0 signal 20

M_CCP5

M_EPI0S20

M_SSI0CLK

M_U1TX

SSI-0 clock

UART-1 transmit data

M_CAN0RX

C_SPICLKA

PD3_GPIO19

M_U1TX

CAN-0 receive data

I/O

I/O/Z

SPI-A clock

General-purpose input/output 19

UART-1 transmit data

M_CCP7

I/O

Capture/Compare/PWM-7 (General-purpose Timer)

Capture/Compare/PWM-0 (General-purpose Timer)

EPI-0 signal 21

M_CCP0

M_EPI0S21

M_SSI0FSS

M_U1RX

SSI-0 frame

UART-1 receive data

M_CAN0TX

C_SPISTEA

PD4_GPIO20

M_CCP0

CAN-0 transmit data

I/O

I/O/Z

I/O

SPI-A slave transmit enable

General-purpose input/output 20

Capture/Compare/PWM-0 (General-purpose Timer)

Capture/Compare/PWM-3 (General-purpose Timer)

EMAC MII transmit data 3

M_CCP3

M_MIITXD3

M_U1RI

UART-1 receive data

M_EPI0S19

M_U3TX

I/O

EPI-0 signal 19

UART-3 transmit data

M_CAN1TX

C_EQEP1A

C_MDXA

CAN-1 transmit data

Enhanced QEP-1 input A

McBSP-A transmit data

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PD5_GPIO21

PIN #

I/O/Z

I/O

General-purpose input/output 21

M_CCP2

Capture/Compare/PWM-2 (General-purpose Timer)

Capture/Compare/PWM-4 (General-purpose Timer)

EMAC MII transmit data 2

UART-2 receive data

M_CCP4

M_MIITXD2

M_U2RX

M_EPI0S28

M_U3RX

I/O

EPI-0 signal 28

UART-3 receive data

M_CAN1RX

C_EQEP1B

C_MDRA

CAN-1 receive data

Enhanced QEP-1 input B

McBSP-A receive data

PD6_GPIO22

M_MIITXD1

M_U2TX

I/O/Z

General-purpose input/output 22

EMAC MII transmit data 1

UART-2 transmit data

M_EPI0S29

M_I2C1SDA

M_U1TX

I/O

I/OD

EPI-0 signal 29

I2C-0 data open-drain bidirectional port

UART-1 transmit data

C_EQEP1S

C_MCLKXA

PD7_GPIO23

M_CCP1

I/O

Enhanced QEP-1 strobe

McBSP-A transmit clock

I/O/Z

I/O

General-purpose input/output 23

Capture/Compare/PWM-1 (General-purpose Timer)

EMAC MII transmit data 0

UART-1 data terminal ready

EPI-0 signal 30

M_MIITXD0

M_U1DTR

M_EPI0S30

M_I2C1SCL

M_U1RX

I/O

I/OD

I2C-1 clock open-drain bidirectional port

UART-1 receive data

C_EQEP1I

C_MFSXA

PE0_GPIO24

M_SSI1CLK

M_CCP3

I/O

Enhanced QEP-1 index

McBSP-A transmit frame sync

General-purpose input/output 24

SSI-1 clock

I/O/Z

I/O

Capture/Compare/PWM-3 (General-purpose Timer)

EPI-0 signal 8

M_EPI0S8

M_USB0PFLT

M_SSI3TX

M_CAN0RX

M_SSI1TX

C_ECAP1

C_EQEP2A

USB-0 external power error state (optionally used in the host mode)

SSI-3 transmit data

CAN-1 receive data

SSI-1 transmit data

I/O

Enhanced Capture-1 input/output

Enhanced QEP-2 input A

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

PE1_GPIO25

M_SSI1FSS

M_CCP2

I/O/Z

I/O

General-purpose input/output 25

SSI-1 frame

Capture/Compare/PWM-2 (General-purpose Timer)

Capture/Compare/PWM-6 (General-purpose Timer)

EPI-0 signal 9

M_CCP6

M_EPI0S9

M_SSI3RX

M_CAN0TX

M_SSI1RX

C_ECAP2

C_EQEP2B

PE2_GPIO26

M_CCP4

SSI-3 receive data

CAN-1 transmit data

SSI-1 transmit data

I/O

Enhanced Capture-2 input/output

Enhanced QEP-2 input B

I/O/Z

I/O

General-purpose input/output 26

Capture/Compare/PWM-4 (General-purpose Timer)

SSI-1 receive data

M_SSI1RX

M_CCP2

I/O

Capture/Compare/PWM-2 (General-purpose Timer)

EPI-0 signal 24

M_EPI0S24

M_SSI3CLK

M_U2RX

SSI-3 clock

UART-2 receive data

M_SSI1CLK

C_ECAP3

C_EQEP2I

PE3_GPIO27

M_CCP1

I/O

I/O/Z

I/O

SSI-1 clock

Enhanced Capture-3 input/output

Enhanced QEP-2 index

General-purpose input/output 27

Capture/Compare/PWM-1 (General-purpose Timer)

SSI-1 transmit data

M_SSI1TX

M_CCP7

I/O

Capture/Compare/PWM-7 (General-purpose Timer)

EPI-0 signal 25

M_EPI0S25

M_SSI3FSS

M_U2TX

SSI-3 frame

UART-2 transmit data

M_SSI1FSS

C_ECAP4

C_EQEP2S

PE4_GPIO28

M_CCP3

I/O

I/O/Z

I/O

SSI-1 frame

Enhanced Capture-4 input/output

Enhanced QEP-2 strobe

General-purpose input/output 28

Capture/Compare/PWM-3 (General-purpose Timer)

UART-2 transmit data

M_U2TX

M_CCP2

I/O

Capture/Compare/PWM-2 (General-purpose Timer)

EMAC MII receive data 0

M_MIIRXD0

M_U0RX

UART-0 receive data

M_USB0EPEN

C_SCIRXDA

PE5_GPIO29

M_CCP5

USB-0 external power enable (optionally used in the host mode)

SCI-A receive data

I/O/Z

I/O

General-purpose input/output 29

Capture/Compare/PWM-5 (General-purpose Timer)

EMAC MII transmit error

M_MIITXER

M_U0TX

UART-0 transmit data

M_USB0PFLT

C_SCITXDA

USB-0 external power error state (optionally used in the host mode)

SCI-A transmit data

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PE6_GPIO30

PIN #

I/O/Z

General-purpose input/output 30

M_U1CTS

UART-1 clear-to-send modem status

EMAC MII MDIO

M_MIIMDIO

M_CAN0RX

C_EPWM9A

PE7_GPIO31

M_U1DCD

M_MIIRXD3

M_CAN0TX

C_EPWM9B

PF0_GPIO32

M_CAN1RX

M_MIIRXCK

M_U1DSR

I/O

CAN-0 receive data

Enhanced PWM-9 output A

General-purpose input/output 31

UART-1 data carrier detect

EMAC MII receive data 3

I/O/Z

CAN-0 transmit data

Enhanced PWM-9 output B

General-purpose input/output 32

CAN-1 receive data

104

I/O/Z

EMAC MII receive clock

UART-1 data set ready

M_I2C0SDA

C_SDAA

I/OD

I2C-0 data open-drain bidirectional port

I2C-A data open-drain bidirectional port

SCI-A receive data

ADC start-of-conversion A⁽¹⁾

General-purpose input/output 33

CAN-1 transmit data

C_SCIRXDA

C_ADCSOCAO

PF1_GPIO33

M_CAN1TX

M_MIIRXER

M_U1RTS

103

I/O/Z

EMAC MII receive error

UART-1 request-to-send

M_CCP3

I/O

I/OD

Capture/Compare/PWM-3 (General-purpose Timer)

I2C-0 clock open-drain bidirectional port

I2C-A clock open-drain bidirectional port

Enhanced PWM sync out

ADC start-of-conversion B⁽¹⁾

General-purpose input/output 34

EMAC PHY MII interrupt

M_I2C0SCL

C_SCLA

C_EPWMSYNCO

C_ADCSOCBO

PF2_GPIO34

M_MIIPHYINTR

M_SSI1CLK

I/O/Z

I/O

SSI-1 clock

M_XCLKOUT

C_ECAP1

Main PLL clock (divided by 1, 2 or 4)

Enhanced Capture-1 input/output

SCI-A receive data

I/O

C_SCIRXDA

C_XCLKOUT

Main PLL clock (divided by 1, 2 or 4)

(1) Output from the Concerto ePWM is meant for the external ADC (if present).

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

PF3_GPIO35

M_MIIMDC

M_SSI1FSS

M_U0TX

I/O/Z

General-purpose input/output 35

EMAC PHY MII MDC

SSI-1 frame

I/O

UART-0 transmit data

SCI-A transmit data

Boot pin 2

C_SCITXDA

BOOT_2

PF4_GPIO36

M_CCP0

I/O/Z

General-purpose input/output 36

I/O

Capture/Compare/PWM-0 (General-purpose Timer)

EMAC MII MDIO

M_MIIMDIO

M_EPI0S12

M_SSI1RX

M_U0RX

I/O

EPI-0 signal 12

SSI-1 receive data

UART-0 receive data

C_SCIRXDA

PF5_GPIO37

M_CCP2

I/O/Z

I/O

SCI-A receive data

General-purpose input/output 37

Capture/Compare/PWM-2 (General-purpose Timer)

EMAC MII receive data 3

M_MIIRXD3

M_EPI0S15

M_SSI1TX

C_ECAP2

I/O

EPI-0 signal 15

SSI-1 transmit data

I/O

I/O/Z

Analog

I/O

Enhanced Capture-2 input/output

General-purpose input/output 38

USB0 VBUS power

PF6_GPIO38

M_USB0VBUS

M_CCP1

Capture/Compare/PWM-1 (General-purpose Timer)

EMAC MII receive data 2

M_MIIRXD2

M_U1RTS

UART-1 request-to-send

PF7_GPIO39

PG0_GPIO40

M_U2RX

No Pin

I/O/Z

General-purpose input/output 39 is not pinned out.

General-purpose input/output 40

UART-2 receive data

M_I2C1SCL

M_USB0EPEN

M_EPI0S13

M_MIIRXD2

M_U4RX

I/OD

I2C-1 clock open-drain bidirectional port

USB-0 external power enable (optionally used in the host mode)

EPI-0 signal 13

I/O

EMAC MII receive data 2

UART-4 receive data

PG1_GPIO41

M_U2TX

I/O/Z

General-purpose input/output 41

UART-2 transmit data

M_I2C1SDA

M_EPI0S14

M_MIIRXD1

M_U4TX

I/OD

I/O

I2C-1 data open-drain bidirectional port

EPI-0 signal 14

EMAC MII receive data 1

UART-4 transmit data

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PG2_GPIO42

PIN #

I/O/Z

General-purpose input/output 42

USB0 data minus

M_USB0DM

M_MIICOL

PG3_GPIO43

M_MIICRS

M_MIIRXDV

BOOT_0

Analog

EMAC MII collision detect

General-purpose input/output 43

EMAC MII carrier sense

EMAC MII receive data valid

Boot pin 0

I/O/Z

PF7_GPIO44

PG5_GPIO45

M_USB0DP

M_CCP5

No Pin

I/O/Z

Analog

I/O

General-purpose input/output 44 is not pinned out.

General-purpose input/output 45

USB0 data plus

Capture/Compare/PWM-5 (General-purpose Timer)

EMAC MII transmit enable

UART-1 data terminal ready

General-purpose input/output 46

USB0 ID

M_MIITXEN

M_U1DTR

PG6_GPIO46

M_USB0ID

M_MIITCK

M_U1RI

I/O/Z

Analog

EMAC MII transmit clock

UART-1 receive data

PG7_GPIO47

M_MIITXER

M_EPI0S31

BOOT_1

I/O/Z

General-purpose input/output 47

EMAC MII transmit error

EPI-0 signal 31

I/O

Boot pin 1

PH0_GPIO48

M_CCP6

I/O/Z

I/O

General-purpose input/output 48

Capture/Compare/PWM-6 (General-purpose Timer)

EMAC PHY MII reset

M_MIIPHYRST

M_EPI0S6

M_SSI3TX

C_ECAP5

I/O

EPI-0 signal 6

SSI-3 transmit data

I/O

I/O/Z

I/O

Enhanced Capture-5 input/output

General-purpose input/output 49

Capture/Compare/PWM-7 (General-purpose Timer)

EPI-0 signal 7

PH1_GPIO49

M_CCP7

M_EPI0S7

M_MIIRXD0

M_SSI3RX

C_ECAP6

EMAC MII receive data 0

SSI-3 receive data

I/O

I/O/Z

I/O

Enhanced Capture-6 input/output

General-purpose input/output 50

EPI-0 signal 1

PH2_GPIO50

M_EPI0S1

M_MIITXD3

M_SSI3CLK

C_EQEP1A

EMAC MII transmit data 3

SSI-3 clock

I/O

Enhanced QEP-2 input B

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

PH3_GPIO51

M_USB0EPEN

M_EPI0S0

I/O/Z

General-purpose input/output 51

USB-0 external power enable (optionally used in the host mode)

EPI-0 signal 0

I/O

M_MIITXD2

M_SSI3FSS

C_EQEP1B

PH4_GPIO52

M_USB0FLT

M_EPI0S10

M_MIITXD1

M_SSI1CLK

M_U3TX

EMAC MII transmit data 2

SSI-3 frame

I/O

Enhanced QEP-1 input B

General-purpose input/output 52

USB-0 external power error state (optionally used in the host mode)

EPI-0 signal 10

I/O/Z

I/O

EMAC MII transmit data 1

SSI-1 clock

I/O

UART-3 transmit data

C_EQEP1S

PH5_GPIO53

M_EPI0S11

M_MIITXD0

M_SSI1FSS

M_U3RX

I/O

I/O/Z

I/O

Enhanced QEP-1 strobe

General-purpose input/output 53

EPI-0 signal 11

EMAC MII transmit data 0

SSI-1 frame

I/O

UART-3 receive data

C_EQEP1I

I/O

I/O/Z

I/O

Enhanced QEP-1 index

General-purpose input/output 54

EPI-0 signal 26

PH6_GPIO54

M_EPI0S26

M_MIIRXDV

M_SSI1RX

M_MIITXEN

M_SSI0TX

EMAC MII receive data valid

SSI-1 receive data

EMAC MII transmit enable

SSI-0 transmit data

C_SPISIMOA

C_EQEP3A

PH7_GPIO55

M_MIIRXCK

M_EPI0S27

M_SSI1TX

I/O

SPI-A slave in, master out

Enhanced QEP-1 input A

General-purpose input/output 55

EMAC MII receive clock

EPI-0 signal 27

I/O/Z

I/O

SSI-1 transmit data

M_MIITXCK

M_SSI0RX

C_SPISOMIA

C_EQEP3B

PJ0_GPIO56

M_MIIRXER

M_EPI016

EMAC MII transmit clock

SSI-0 receive data

I/O

SPI-A master in, slave out

Enhanced QEP-3 input B

General-purpose input/output 56

EMAC MII receive error

EPI-0 signal 16

I/O/Z

I/O

I/OD

I/O

M_I2C1SCL

M_SSI0CLK

C_SPICLKA

C_EQEP3S

I2C-1 clock open-drain bidirectional port

SSI-0 clock

SPI-A clock

Enhanced QEP-3 strobe

Device Pins

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PJ1_GPIO57

PIN #

I/O/Z

I/O

General-purpose input/output 57

EPI-0 signal 17

M_EPI0S17

M_USB0PFLT

M_I2C1SDA

M_MIIRXDV

M_SSI0FSS

C_SPISTEA

C_EQEP3I

PJ2_GPIO58

M_EPI0S18

M_CCP0

USB-0 external power error state (optionally used in the host mode)

I2C-1 data open-drain bidirectional port

EMAC MII receive data valid

SSI-0 frame

I/OD

I/O

I/O/Z

I/O

SPI-A slave transmit enable

Enhanced QEP-3 index

General-purpose input/output 58

EPI-0 signal 18

Capture/Compare/PWM-0 (General-purpose Timer)

EMAC MII receive clock

M_MIIRXCK

M_SSI0CLK

M_U0TX

I/O

SSI-0 clock

UART-0 transmit data

C_MCLKRA

C_EPWM7A

PJ3_GPIO59

M_EPI0S19

M_U1CTS

McBSP-A receive clock

Enhanced PWM-7 output A

General-purpose input/output 59

EPI-0 signal 19

I/O/Z

I/O

UART-1 clear-to-send

M_CCP6

I/O

Capture/Compare/PWM-6 (General-purpose Timer)

EMAC PHY MII MDC

M_MIIMDC

M_SSI0FSS

M_U0RX

I/O

SSI-0 frame

UART-0 receive data

C_MFSRA

C_EPWM7B

PJ4_GPIO60

M_EPI0S28

M_U1DCD

M_CCP4

McBSP-A receive frame sync

Enhanced PWM-7 output B

General-purpose input/output 60

EPI-0 signal 28

I/O/Z

I/O

UART-1 data carrier detect

Capture/Compare/PWM-4 (General-purpose Timer)

EMAC MII collision detect

SSI-1 clock

I/O

M_MIICOL

M_SSI1CLK

C_EPWM8A

PJ5_GPIO61

M_EPI0S29

M_U1DSR

M_CCP2

I/O

Enhanced PWM-8 output A

General-purpose input/output 61

EPI-0 signal 29

I/O/Z

I/O

UART-1 data set ready

I/O

Capture/Compare/PWM-2 (General-purpose Timer)

EMAC PHY MII CRS

M_MIICRS

M_SSI1FSS

C_EPWM8B

I/O

SSI-1 frame

Enhanced PWM-8 output B

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

PJ6_GPIO62

M_EPI0S30

M_U1RTS

M_CCP1

I/O/Z

General-purpose input/output 62

EPI-0 signal 30

I/O

UART-1 request-to-send

I/O

Capture/Compare/PWM-1 (General-purpose Timer)

EMAC PHY MII interrupt

M_MIIPHYINTR

M_U2RX

UART-2 receive data

C_EPWM9A

PJ7_GPIO63

M_U1DTR

M_CCP0

Enhanced PWM-9 output A

I/O/Z

General-purpose input/output 63

UART-1 data terminal ready

I/O

Capture/Compare/PWM-0 (General-purpose Timer)

EMAC PHY MII reset

M_MIIPHYRST

M_U2TX

UART-2 transmit data

C_EPWM9B

PC0_GPIO64

PC1_GPIO65

PC2_GPIO66

PC3_GPIO67

PC4_GPIO68

M_CCP5

Enhanced PWM-9 output B

No Pin

General-purpose input/output 64 is not pinned out

General-purpose input/output 65 is not pinned out

General-purpose input/output 66 is not pinned out

General-purpose input/output 67 is not pinned out

General-purpose input/output 68

No Pin

I/O/Z

Capture/Compare/PWM-5 (General-purpose Timer)

EMAC MII transmit data 3

M_MIITXD3

M_CCP2

Capture/Compare/PWM-2 (General-purpose Timer)

Capture/Compare/PWM-4 (General-purpose Timer)

EPI-0 signal 2

M_CCP4

M_EPI0S2

M_CCP1

I/O

Capture/Compare/PWM-1 (General-purpose Timer)

General-purpose input/output 69

PC5_GPIO69

M_CCP1

I/O/Z

Capture/Compare/PWM-1 (General-purpose Timer)

Capture/Compare/PWM-3 (General-purpose Timer)

USB-0 external power enable (optionally used in the host mode)

EPI-0 signal 3

M_CCP3

M_USB0EPEN

M_EPI0S3

PC6_GPIO70

M_CCP3

I/O

I/O/Z

General-purpose input/output 70

Capture/Compare/PWM-3 (General-purpose Timer)

UART-1 receive data

M_U1RX

M_CCP0

Capture/Compare/PWM-0 (General-purpose Timer)

USB-0 external power error state (optionally used in the host mode)

EPI-0 signal 4

M_USB0PFLT

M_EPI0S4

PC7_GPIO71

M_CCP4

I/O

I/O/Z

General-purpose input/output 71

Capture/Compare/PWM-4 (General-purpose Timer)

Capture/Compare/PWM-0 (General-purpose Timer)

UART-1 transmit data

M_CCP0

M_U1TX

M_USB0PFLT

M_EPI0S5

USB-0 external power error state (optionally used in the host mode)

EPI-0 signal 5

I/O

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

Reset

Digital Subsystem Reset (in) and Watchdog/Brown-out Reset (out). In most

applications, it is recommended that the XRS pin be tied with the ARS pin. The

Digital Subsystem has a built-in power-on-reset (POR) and brown-out-reset

(BOR) circuitry. As such, no external circuitry is needed to generate a reset

pulse. During a power-on or brown-out condition, this pin is driven low by the

Digital Subsystem. This pin is also driven low by the Digital Subsystem when a

watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the

watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry

may also drive this pin to assert device reset. In this case, it is recommended

that this pin be driven by an open-drain device. An R-C circuit must be

connected to this pin for noise immunity reasons. Regardless of the source, a

device reset causes the Digital Subsystem to terminate execution. The

Cortex™-M3 program counter points to the address contained at the location

0x00000004. The C28 program counter points to the address contained at the

location 0x3FFFC0. When reset is deactivated, execution begins at the location

designated by the program counter. The output buffer of this pin is an

open-drain with an internal pullup.

XRS

I/OD

Analog Subsystem Reset (in) and Brown-out Reset (out).In most applications, it

is recommended that the ARS pin be tied with the XRS pin. The Digital

Subsystem has a built-in brown-out-reset (BOR) circuitry. As such, no external

circuitry is needed to generate a reset pulse. During a power-on or brown-out

condition, this pin is driven low by the Analog Subsystem. If need be, an

external circuitry may also drive this pin to assert a device reset. In this case, it

is recommended that this pin be driven by an open-drain device. An R-C circuit

must be connected to this pin for noise immunity reasons. Regardless of the

source, the Analog Subsystem reset causes the digital logic associated with the

Analog Subsystem, to enter reset state. The output buffer of this pin is an

open-drain with an internal pullup.

ARS

144

I/OD

Clocks

On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a

ceramic resonator must be connected across X1 and X2. If this pin is not used,

it must be tied to GND.

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must

be connected across X1 and X2. If X2 is not used, it must be left unconnected.

see

PJ7_GPIO63

External oscillator input. This pin feeds a clock from an external 3.3-V oscillator

to internal USB PLL module and to the CAN peripherals.

XCLKIN

see

PF2_GPIO34

External oscillator output. This pin outputs a clock divided-down from the

internal PLL System Clock. The divide ratio is defined in the XCLKCFG register.

XCLKOUT

O/Z

Boot Pins

see

PG3_GPIO43

One of three boot mode pins. It selects a specific configuration source from

which the Concerto device boots on start-up.

BOOT_0

BOOT_1

BOOT_2

see

PG7_GPIO47

One of three boot mode pins. It selects a specific configuration source from

which the Concerto device boots on start-up.

see

PG3_GPIO35

One of three boot mode pins. It selects a specific configuration source from

which the Concerto device boots on start-up.

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan

system control of the operations of the device. If this signal is not connected or

driven low, the device operates in its functional mode, and the test reset signals

are ignored. NOTE: TRST is an active-high test pin and must be maintained low

during normal device operation. An external pull-down resistor is required on

this pin. The value of this resistor should be based on drive strength of the

debugger pods applicable to the design. A 2.2-kΩ resistor generally offers

adequate protection. Since this is application-specific, it is recommended that

each target board be validated for proper operation of the debugger and the

application. (↓)

TRST

TCK

TMS

JTAG test clock with internal pullup (↑)

JTAG test-mode select (TMS) with internal pullup. This serial control input is

clocked into the TAP controller on the rising edge of TCK. (↑)

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected

TDI

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) are shifted out of TDO on the falling edge of TCK. (8-mA

drive)

TDO

O/Z

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or

from the emulator system and is defined as input/output through the JTAG scan.

This pin is also used to put the device into boundary-scan mode. With the

EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising

edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z,

8 mA drive ↑)

NOTE: An external pullup resistor is required on this pin. The value of this

resistor should be based on the drive strength of the debugger pods applicable

to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is

application-specific, it is recommended that each target board be validated for

proper operation of the debugger and the application.

EMU0

I/O/Z

NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters

Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator

to connect to the device and to modify FLASH contents.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or

from the emulator system and is defined as input/output through the JTAG scan.

This pin is also used to put the device into boundary-scan mode. With the

EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising

edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z,

8 mA drive ↑)

NOTE: An external pullup resistor is required on this pin. The value of this

resistor should be based on the drive strength of the debugger pods applicable

to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is

application-specific, it is recommended that each target board be validated for

proper operation of the debugger and the application.

EMU1

I/O/Z

NOTE: If EMU0 is 0 and EMU1 is 1 when coming out of reset, the device enters

Wait-in-Reset mode. WIR suspends bootloader execution, allowing the Emulator

to connect to the device and to modify FLASH contents.

Device Pins

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

Test Pins

FLT1

FLT2

I/O

FLASH Test Pin 1. Reserved for TI. Must be left unconnected.

FLASH Test Pin 2. Reserved for TI. Must be left unconnected.

Internal Voltage Regulator Control

Internal 1.8-V VREG Enable/Disable for V_DD18. Pull low to enable the internal

1.8-V voltage regulator (VREG18), pull high to disable VREG18.

VREG18EN

VREG12EN

113

101

Internal 1.2-V VREG Enable/Disable for V_DD12. Pull low to enable the internal

1.2-V voltage regulator (VREG12), pull high to disable VREG12.

Analog, Digital, and I/O Power

3.3-V Analog Module 1 Power Pin. Tie with a 2.2-µF capacitor (typical) close to

the pin.

V_DDA1

V_DDA2

V_DDIO

119

134

107

3.3-V Analog Module 2 Power Pin. Tie with a 2.2-µF capacitor (typical) close to

the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

105

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

100

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

3.3-V Digital I/O and FLASH Power Pin. Tie with a 0.1-µF capacitor (typical)

close to the pin.

106

1.8-V Digital Logic Power Pins (associated with the Analog Subsytem) - no

supply needed when using internal VREG18. Tie with 1.2-µF (minimum)

ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher

value capacitors may be used but could impact supply-rail ramp-up time.

V_DD18

Device Pins

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

I/O/Z⁽²⁾

DESCRIPTION

RFP

NAME

PIN #

1.8-V Digital Logic Power Pins (associated with the Analog Subsytem) - no

supply needed when using internal VREG18. Tie with 1.2-µF (minimum)

ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher

value capacitors may be used but could impact supply-rail ramp-up time.

V_DD18

V_DD12

108

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

1.2-V Digital Logic Power Pins - no supply needed when using internal

VREG12. Tie with 422- nF (minimum) ceramic capacitor (10% tolerance) to

ground when using internal VREG. Higher value capacitors may be used but

could impact supply-rail ramp-up time.

V_SS

PWR PAD

Analog and Digital Ground Power Pad (located on the bottom of the chip).

Clock Oscillator Ground Pin

V_SSOSC

Device Pins

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

4 Device Operating Conditions

4.1 Absolute Maximum Ratings^{(1) (2)}

Supply voltage range, V_DDIO(I/O and Flash)

Supply voltage range, V_DD18

with respect to V_SS

with respect to V_SSA

–0.3 V to 4.6 V

–0.3 V to 2.5 V

–0.3 V to 1.5 V

–0.3 V to 4.6 V

±20 mA

Supply voltage range, V_DD12

Analog voltage range, V_DDA

Input voltage range, V_IN(3.3 V)

Output voltage range, V_O

(3)

Input clamp current, I_IK(V_IN< 0 or V_IN> V_DDIO

)

Output clamp current, I_OK(V_O< 0 or V_O> V_DDIO

)

±20 mA

(4)

Junction temperature range, T_J

–40°C to 150°C

–65°C to 150°C

(4)

Storage temperature range, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Continuous clamp current per pin is ± 2 mA.

(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for

TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).

4.2 Recommended Operating Conditions

MIN NOM

MAX

3.46

1.89

UNIT

(1)

Device supply voltage, I/O, V_DDIO

3.14

1.71

3.3

1.8

Device supply voltage, Analog Subsystem, V_DD18

(when internal VREG is disabled and 1.8 V is

supplied externally)

Device supply voltage, Master and Control

Subsystems, V_DD12

(when internal VREG is disabled and 1.2 V is

supplied externally)

1.14

3.14

1.2

1.26

3.47

Supply ground, V_SS

3.3

(1)

Analog supply voltage, V_DDA

Analog ground, V_SSA

Device clock frequency (system clock)

High-level input voltage, V_IH(3.3 V)

Low-level input voltage, V_IL(3.3 V)

High-level output source current, V_OH= V_OH(MIN), I_OHAll GPIO/AIO pins

Group 2⁽²⁾

MHz

V_DDIO* 0.7

V_DDIO+ 0.3

_SS– 0.3

V_DDIO* 0.3

–4

–8

Low-level output sink current, V_OL= V_OL(MAX), I_OL

All GPIO/AIO pins

Group 2⁽²⁾

(3)

Junction temperature, T_J

T version

–40

105

125

S version

°C

Q version (Q100 qualification)

(1) V_DDIOand V_DDAshould be maintained within ~0.3 V of each other.

(2) Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1,

PD0_GPIO16, AIO7, AIO4.

(3) T_A(Ambient temperature) is product- and application-dependent and can go up to the specified T_Jmax of the device.

Device Operating Conditions

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

4.3 Electrical Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

V_DDIO* 0.8

V_DDIO– 0.2

TYP

MAX UNIT

I_OH= I_OHMAX

I_OH= 50 μA

V_OH

V_OL

High-level output voltage

Low-level output voltage

I_OL= I_OLMAX

V_DDIO* 0.2

All GPIO/AIO

–140

–300

Pin with pullup

enabled

V_DDIO= 3.3 V, V_IN= 0 V

Input current

(low level)

XRS pin and ARS pin

I_IL

μA

Pin with pulldown

enabled

V_DDIO= 3.3 V, V_IN= 0 V

V_DDIO= 3.3 V, V_IN= V_DDIO

V_O= V_DDIOor 0 V

±2

Pin with pullup

enabled

Input current

(high level)

I_IH

μA

Pin with pulldown

enabled

Output current, pullup or

pulldown disabled

I_OZ

C_I

Input capacitance

2.78

V_DDIOBOR trip point

V_DDIOBOR hysteresis

Falling V_DDIO

Supervisor reset release

delay time

Time after BOR/POR/OVR event is removed to

XRS release

600

μs

VREG V_DD18output

VREG V_DD12output

Internal VREG18 on

Internal VREG12 on

1.8

1.2

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(V_DD) go out of range.

Device Operating Conditions

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

5 Peripheral Information and Timings

5.1 Master Subsystem Peripherals

Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the

Cortex™-M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB

peripherals include EMAC, two I2Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG,

and a µCRC module (Cyclic Redundancy Check).

5.1.1 External Peripheral Interface (EPI)

The External Peripheral Interface (EPI) is a high-speed parallel bus for external peripherals or memory. It

has several modes of operation to interface gluelessly to many types of external devices. The EPI is

similar to a standard microprocessor address/data bus, except that it must typically be connected to just

one type of external device. Enhanced capabilities include µDMA support, clocking control, and support

for external FIFO buffers.

The EPI supports three primary functional modes: Synchronous Dynamic Random-Access Memory

(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also provides

custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same way as a

communication mechanism and is speed-controlled using clocking.

Peripheral Information and Timings

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F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

5.2 Control Subsystem Peripherals

Control Subsystem peripherals are accessible from the C28x CPU via the C28x Memory Bus, and from

the C28x DMA via the C28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port

Peripherals (SCI, SPI, McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP, eCAP).

5.2.1 Pulse Width Modulator (PWM) Modules

There are nine PWM modules in the Concerto device. Eight of these are of the High-Resolution PWM

(HRPWM) type, and one is of the Enhanced PWM (ePWM) type. The HRPWM modules have all the

features of the ePWM plus they offer significantly higher PWM resolution (time granularity). Figure 5-1

shows the eight HRPWM modules (PWM 1–8) and the single ePWM module (PWM 9).

The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of

GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output

SYNCO1 comes from the HRPWM1 module and is stretched by 8 HSPCLK cycles before entering

GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from

GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR

signal from the C28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1),

EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x

CPU).

There are nine SOCA PWM outputs and nine SOCB PWM outputs—a pair from each PWM module. The

nine SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1

as a single SOCAO signal. The nine SOCB outputs are OR-ed together and stretched by 32 HSPCLK

cycles before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs also go to the

Analog Subsystem, where they can be selected to become conversion triggers to ADC modules.

The nine PWM modules also drive two other sets of outputs which can interrupt the C28x CPU via the

C28x PIE block. These are nine EPWMINT interrupts and nine EPWMTZINT trip-zone interrupts. See

Figure 5-2 for the internal structure of the ePWM and HRPWM modules. The green-colored blocks are

common to both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution

blocks.

Peripheral Information and Timings

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

SOCA (9:1)

SOCB(9:1)

PULSE STRETCH SOCAO

32 HSPCLK CYCLES

PULSE STRETCH SOCBO

32 HSPCLK CYCLES

GPTRIP6

SYNCI

EPWM

EPWM(9:1)A

GPTRIP1

GPTRIP2

GPTRIP3

GPTRIP4

GPTRIP5

GPTRIP6

GPTRIP7

GPTRIP8

GPTRIP9

GPTRIP10

GPTRIP11

GPTRIP12

‘0’

TRIPIN1

TRIPIN2

TRIPIN3

TRIPIN4

TRIPIN5

TRIPIN6

TRIPIN7

TRIPIN8

TRIPIN9

TRIPIN10

TRIPIN11

TRIPIN12

TRIPIN13

TRIPIN14

TRIPIN15

PWM

SYNCO

TZ1

TZ2

TZ3

TZ4

TZ5

TZ6

GPTRIP1

GPTRIP2

GPTRIP3

EQEPERR

CLOCKFAIL

EMUSTOP

PWM

ECCDBLERR

PIEERR

EPWM(9:1)B

TBCLKSYNC

EPWM(9:1)TZINT

EPWM(9:1)INT

PULSE STRETCH

8 HSPCLK CYCLES

SYNCO

SYNCO1

CPCLKCR0 REG

EQEP(3:1)INT

ECAP(6:1)INT

EQEP1A

EQEP1B

EQEP1S

EQEP1I

SYNCI

EQEP 1

ECAP

GPTRIP7

GPTRIP8

GPTRIP9

GPTRIP10

GPTRIP11

GPTRIP12

ECAP1INP

ECAP2INP

ECAP3INP

ECAP4INP

ECAP5INP

ECAP6INP

SYNCO

EQEP2A

EQEP2B

EQEP2S

EQEP2I

EQEP 2

ECAP

EQEP3A

EQEP3B

EQEP3S

EQEP3I

EQEP3

ECAP

EQEP

ECAP(6:1)

LEGEND:

PWM

1-8

EPWM +

HiRES PWM

GPTRIP(1-12)

GPIO_MUX1

ECCDBLERR

PIEERR

EMUSTOP

EQEPERR

CLOCKFAIL

PWM

EPWM

ONLY

C28x

CPU

CLOCKS

C28x LOCAL RAM

SHARED RAM

Figure 5-1. ePWM, eQEP, eCAP

Peripheral Information and Timings

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

C28SYSCLK

TBCLKSYNC

TRIPIN(15:1)

DCAEVT1.SYNC

DCBEVT1.SYNC

SYNCO

SYNCI

DCAEVT1.SOC

DCBEVT1.SOC

TIME BASE

(TB)

PHS

PRD

DIGITAL

TBCLK

CTR=ZER

CTR=PRD

COMPARE

CTR=

CMPB

(DC)

TBCTR

(15:0)

CTR=ZER

CTR=PRD

CTR_DIR

TBCTR

(15:0)

HiRES

CONTROL

TBCLK

CMPA

CMPB

CAL

CNTRL

DCAEVT1.FORCE DCBEVT1.FORCE

DCAEVT2.FORCE DCBEVT2.FORCE

COUNTER

COMPARE

DCAEVT1.SYNC

DCBEVT1.SYNC

RED

FED

DCAEVT1.INTER DCBEVT1.INTER

DCAEVT2.INTER DCBEVT2.INTER

(CC)

CTR=ZER

CTR=PRD

CTR_DIR

EPWM_A

EPWM_B

ACTION

DEAD

BAND

PWM

TRIP

HiRES

PWM

QUALIFIER

CHOPPER

ZONE

CTR=CMPA

CTR=CMPB

(AQ)

(DB)

(PC)

(TZ)

(HRPWM)

SWFSYNC

SYNCI

CTR=ZER

CTR=PRD

C28SYSCLK

CTR=CMPA

CTR=CMPB

CTR=CMPC

CTR=CMPD

DCAEVT1.SOC

DCBEVT1.SOC

EVENT

TRIGGER

SYNCI

(ET)

EPWM_TZINT

EPWM_INT

SOCA

SOCB

TZ (6:1)

Figure 5-2. ePWM/HRPWM

Peripheral Information and Timings

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

5.3 Analog/Shared Peripherals

Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem.

The Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six

Comparator + DAC (10-bit) modules. All ADC and Comparator registers are accessible by the

Cortex™-M3 CPU and C28x CPU, while ADC results registers are also accessible by the respective

DMAs of the two processors.

The Inter-Processor Communications (IPC) Peripheral is only accessible by the Cortex™-M3 CPU and by

the C28x CPU (not accessible by DMAs). IPC is used for sending and receiving synchronization events

between Master and Control subsystems to coordinate execution of software running on both processors,

or exchanging of data between the two processors.

5.3.1 Analog-to-Digital Converter (ADC)

Figure 5-3 shows the internal structure of each of the two ADC peripherals that are present on Concerto.

Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion

trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read

16 result registers. The 16 ADC channels can be used independently or in pairs, based on the

assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be

sampled simultaneously—thereby, increasing the overall conversion performance.

5.3.1.1 Sample Mode

Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital

conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For

example, if bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential

mode. This means that the SOC4CTL and SOC5CTL registers can both be programmed to configure

channels 4 and 5 to independently perform analog-to-digital conversions with results being stored in the

RESULT4 and RESULT5 registers. "Independently" means that channel 4 may use a different

Start-Of-Conversion (SOC) trigger, different analog input, and different sampling window than the trigger,

input, and window assigned to channel 5.

The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when

corresponding bits in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in

the SAMPLEMODE register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. This means

that the SOC4CTL register now contains configuration parameters for both channel 4 and channel 5, and

the SOC5CTL register is ignored. This means that while channel 4 and channel 5 are still using dedicated

analog inputs (now selected as pairs in the CHSEL field of SOC4CTL), they both share the same SOC

trigger and Sampling Window, with the results being stored in the RESULT4 and RESULT5 registers.

The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each

sample-and-hold unit has its own mux for selecting analog inputs (see Figure 5-3). By programming the

SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels,

8 channel pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous

pairs).

5.3.1.2 Start-of-Conversion (SOC) Triggers

There are eight external SOC triggers that go to each of the two ADC modules (from the Control

Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers

derived from End-Of-Conversion (EOC) interrupts inside each ADC module (ADCINT1 and ADCINT2).

Registers INTSOCSEL1 and 2 are used to configure each of the 16 ADC channels for internal or external

SOC sources. If internal SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select

whether the internal source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel,

the TRIGSEL field of the corresponding SOCxCTL register selects which of the eight external triggers is

used for SOC in that channel. One analog-to-digital conversion can be performed at a time by the 12-bit

ADC. The analog-to-digital conversion priority is managed according to the state of the PRICTL register.

Peripheral Information and Timings

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

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SPRS742B–JUNE 2011–REVISED OCTOBER 2011

ADC_INT(8:1)

TRIGS(8:1)

INTSOCSEL1 REG

INTSOCSEL2 REG

ADCINT1

ADCINT2

SOC0CTL REG

SOC1CTL REG

SOC2CTL REG

SOC3CTL REG

INTSEL1N2 REG

INTSEL3N4 REG

INTSEL5N6 REG

INTSEL7N8 REG

INTFLG REG

INTFLGCLR REG

INTOVF REG

SOCFLG REG

SOCFRC REG

SOCOVF REG

SOC4CTL REG

SOC5CTL REG

SOC6CTL REG

SOC7CTL REG

SOC8CTL REG

SOC9CTL REG

SOC10CTL REG

SOC11CTL REG

SOC12CTL REG

SOC13CTL REG

SOC14CTL REG

SOC15CTL REG

ADC INTERUPT

CONTROL

SOCx TRIGGER

CONTROL

INTOVFCLR REG

SOCOVFCLR REG

SOCPRICTL REG

EOC(15:0)

SOC(15:0)

SAMPLEMODE REG

ADC CONTROL

ASEL

SHSEL

SOC

REGSEL

ANALOG BUS

ADC_INA0

N/C

ADC_INA2

ADC_INA3

ADC_INA4

RESULT0 REG

RESULT1 REG

RESULT2 REG

RESULT3 REG

RESULT4 REG

RESULT5 REG

RESULT6 REG

RESULT7 REG

RESULT8 REG

RESULT9 REG

RESULT10 REG

RESULT11 REG

RESULT12 REG

RESULT13 REG

RESULT14 REG

RESULT15 REG

TEMP¹

ADC_INA6

ADC_INA7

S / H

TEMPCONV

ADCCTL1 REG

VREFLOCONV

STORE

RESULT

12-BIT ADC

CONVERTER

BSEL

S / H

ADC_INB0

N/C

ADC_INB3

ADC_INB4

ADCCTL1 REG

REFTRIM REG

OFFTRIM REG

REV REG

VREFLO²

N/C

ADC_INB7

(1) TEMPERATURE SENSOR IN ADC1 ONLY (N/C IN ADC2)

(2) CURRENTLY TIED TO ANALOG GROUND

Figure 5-3. ADC

Peripheral Information and Timings

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

5.3.1.3 Analog Inputs

Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group

having a dedicated mux and sample-and-hold unit (see Figure 5-3). Mux A selects one of seven possible

analog inputs—six external inputs via AIO MUX, and one from the internal temperature sensor (present on

ADC1 only). Mux B selects one of five possible analog inputs—four external inputs via AIO MUX, and one

from the internal VREFLO signal, which is currently tied to the Analog Ground. The Mux A and Mux B

inputs can be simultaneously or sequentially sampled by the two sample-and-hold units according to the

sampling window chosen in the SOCxCTL register for the corresponding channel.

5.3.1.4 ADC Result Registers and EOC Interrupts

Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for

ADC2). The 16 ADCx channels can be programmed via the INTSELxNy registers to trigger up to eight

ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts

from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both

the Master Subsystem and the Control Subsystem, announcing that the Result Registers are ready to be

read by a CPU or DMA (see Figure 2-3).

5.3.2 Comparator + DAC Units

Figure 5-4 shows the internal structure of the six analog Comparator + DAC units present in Concerto

devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of

the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The A inputs

come from AIO_MUX1 and AIO_MUX2, as do two of the six B inputs. The remaining four of the B inputs

are provided by 10-bit digital-to-analog units that are present in each comparator. In fact, all six B inputs

can be provided by the DACs, if so desired. The 10-bit value for each DAC unit is programmed in the

respective DACVAL register. Another comparator register, COMPCTL, can be programmed to select the

source of the B input, to enable/disable the comparator circuit, to invert comparator output, to synchronize

comparator output to C28x SYSCLK, and to select the qualification period (number of clock cycles). All six

output signals from the six comparators can be routed out to the device pins via GPIO_MUX2 pin mux.

Peripheral Information and Timings

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

AIO_MUX1

GPIO_MUX2

COMPOUT(1)

COMPA(1)

COMP1

DAC1

N/C

COMP2

COMPCTL REG

COMPSOURCE¹

COMPDACE

COMPINV

QUALSEL

SYNCSEL

COMPA(2)

COMPB(2)

COMPOUT(2)

COMP

SYNC / QUAL

VDDA

VSSA

10-BIT

DAC

C28SYSCLK

COMPSTS

COMPSTS REG

V = ( DACVAL * ( VDDA-VSSA ) ) / 1023

DACVAL(8:0)

DACVAL REG

COMP = 0 WHEN VOLTAGE A < VOLTAGE B

COMP = 1 WHEN VOLTAGE A > VOLTAGE B

COMPA(3)

COMPOUT(3)

COMP3

DAC3

N/C

AIO_MUX2

COMPA(4)

COMPOUT(4)

COMPOUT(5)

COMPOUT(6)

COMP4

COMP5

COMP6

DAC4

DAC5

DAC6

N/C

COMPA(5)

COMPB(5)

COMPA(6)

N/C

(1) COMPSOURCE BIT MUST BE SET TO“DAC” FOR COMP 1, 3, 4, AND 6 , AS THE CORRESPONDING COMPB INPUTS ARENOT CONNECTED

Figure 5-4. Comparator + DAC Units

Peripheral Information and Timings

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

5.3.3 Inter-Processor Communications (IPC)

Figure 5-5 shows the internal structure of the IPC peripheral used to synchronize program execution and

exchange of data between the Cortex™-M3 and the C28x CPU. IPC can be used by itself when

synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating

data transfers between processors. In either case, the operation of the IPC is the same. There are two

independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master).

The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. This is

typically accomplished using the following three registers: MTOCIPCSET, MTOCIPCFLG, and

MTOCIPCACK. Each of the 32 bits of these registers represents 32 independent channels through which

the Cortex™-M3 CPU can send up to 32 events to the C28x CPU via software handshaking. Additionally,

the first 4 bits of the MTOCIPC registers are supplemented with interrupts. To send an event via channel

2, for example, the Cortex™-M3 and C28x CPUs write to, and read from bit 2 of the MTOCIPCSET,

MTOCIPCFLG, MTOCIPCACK registers. The handshake starts with the Cortex™-M3 polling bit 2 of the

MTOCIPCFLG register to make sure it is ‘0’. Next, the Cortex™-M3 writes a ‘1’ into bit 2 of the

MTOCIPCSET register to start the handshake. In the mean time, the C28x is continually polling the

MTOCIPCFLG register while waiting for the message. As soon as the Cortex™-M3 writes ‘1’ to bit 2 of the

MTOCIPCSET register, bit 2 of MTOCIPCFLG also turns ‘1’, thus announcing the event to the C28x. As

soon as the C28x CPU reads a ‘1’ from the MTOCIPCFLG register, it should acknowledge by writing a ‘1’

to bit 2 of the MTOCIPCACK register. This, in turn, clears bit 2 of the MTOCIPCFLG register, enabling the

Cortex™-M3 to send another message. Since the first four channels (bits 0, 1, 2, 3) are backed up by

interrupts, both processors in the above example can use IPC interrupt 2 instead of polling to increase

performance.

A similar handshake is also used when sending data (not just event) from the Master Subsystem to the

Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the

Cortex™-M3 should first load the MTOC Message RAM with a block of data that it wants to make

available to the C28x. In the second additional step, the C28x should read the data before setting a bit in

the MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given

block of the message RAM.

The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. This is

typically accomplished using the following three registers: CTOMIPCSET, CTOMIPCFLG and

CTOMIPCACK. The process is exactly the same as that for the MTOC IPC communication above.

Peripheral Information and Timings

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

INTRS

STS(3:0)

CTOMIPCINT (3:0)

NVIC

CPU

M3 SYSTEM BUS

FLG(31:0)

SET(31:0)

WRDATA

(31:0)

RDDATA

(31:0)

ACK(31:0)

STS(31:0)

32 MTOC IPC CHANNELS

ACK

STS

. . .

SET REG

FLG REG

FLG

SET

. . .

STS REG

ACK REG

MTOC IPC

MTOC MSG RAM

SYNC HANDSHAKE

FOR ONE OF 32

MTOC CHANNELS

C28

SYNC HANDSHAKE

FOR ONE OF 32

. . .

ACK REG

STS REG

MTOC CHANNELS

CTOM MSG RAM

CTOM IPC

FLG REG

SET REG

SET

FLG

STS

ACK

C28

RDDATA

(31:0)

WRDATA

(31:0)

32 CTOM IPC CHANNELS

STS(31:0)

ACK(31:0)

SET(31:0)

FLG(31:0)

C28 CPU BUS

STS(3:0)

INTRS

C28x

CPU

MTOCIPCINT(3:0)

PIE

Figure 5-5. Interprocessor Communications (IPC)

Peripheral Information and Timings

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

5.4 Current Consumption

Table 5-1. F28M35Hx Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK⁽¹⁾⁽²⁾

VREG ENABLED

VREG DISABLED

I_DD12I_DDIO

TYP⁽⁵⁾

MODE

TEST CONDITIONS⁽³⁾

I_DDIO

TYP⁽⁵⁾

I_DDA

I_DD18

I_DDA

(4)

MAX

TYP⁽⁵⁾

MAX

TYP⁽⁵⁾

MAX

TYP⁽⁵⁾

MAX

TYP⁽⁵⁾

MAX

The following Cortex™-M3

peripherals are exercised:

•

I2C1

SSI1/2

UART0/1/2

CAN0

USB

µDMA

Timer0/1

µCRC

WDOG0/1

Flash

Internal Oscillators 1 and 2

The following C28x peripherals are

exercised:

Operational

(RAM)

217 mA

–

30 mA

–

20 mA

–

121 mA

–

74 mA

–

30 mA

–

•

ePWM1/2/3/4/7/8

McBSP

eQEP1/2

eCAP1/2/3/4

SCI-A

SPI-A

I2C

DMA

VCU

FPU

Flash

The following Analog peripherals

are exercised:

•

ADC1/2

Comparator1/2/3/4/5/6

•

PLL is on.

Cortex™-M3 CPU is not

executing.

•

M3SSCLK is on.

SLEEP IDLE

TBD

–

TBD

–

TBD

–

TBD

–

TBD

–

TBD

–

C28CLKIN is on.

C28x™ CPU is not executing.

C28CPUCLK is off.

C28SYSCLK is on.

(1) Currently only typical current consumption data is available, maximum numbers will come in another release of this data sheet.

(2) The numbers in Table 5-1 are not assured at this time, and are subject to change.

(3) The following is done in a loop:

•

Code is running out of RAM.

All I/O pins are left unconnected.

All the communication peripherals are exercised in loop-back mode.

USB – Only logic is exercised by loading and unloading FIFO.

µDMA does memory-to-memory transfer.

DMA does memory-to-memory transfer.

VCU – CRC calculated and checked.

FPU – Float operations performed.

ePWM – 6 enabled and generates 20-MHz PWM output on 12 pins, HRPWM clock enabled.

Timers and Watchdog serviced.

eCAP in APWM mode generates 36.6-kHz output on 4 pins.

ADC performs continuous conversion.

FLASH is continuously read and in active state.

XCLKOUT is turned off.

(4) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(5) The TYP numbers are applicable over room temperature and nominal voltage.

Peripheral Information and Timings

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F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

Table 5-1. F28M35Hx Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz

M3SSCLK⁽¹⁾⁽²⁾(continued)

VREG ENABLED

VREG DISABLED

I_DD12I_DDIO

TYP⁽⁵⁾

MODE

TEST CONDITIONS⁽³⁾

I_DDIO

TYP⁽⁵⁾

I_DDA

I_DD18

I_DDA

(4)

MAX

TYP⁽⁵⁾

MAX

TYP⁽⁵⁾

MAX

TYP⁽⁵⁾

MAX

TYP⁽⁵⁾

MAX

•

PLL is on.

Cortex™-M3 CPU is not

executing.

•

M3SSCLK is on.

SLEEP

STANDBY

TBD

–

TBD

–

TBD

–

TBD

–

TBD

–

TBD

–

C28CLKIN is off.

C28x™ CPU is not executing.

C28CPUCLK is off.

C28SYSCLK is off.

•

PLL is off.

Cortex™-M3 CPU is not

executing.

•

M3SSCLK is 32 kHz.

C28CLKIN is off.

DEEP SLEEP

STANDBY

TBD

–

TBD

–

TBD

–

TBD

–

TBD

–

TBD

–

C28x™ CPU is not executing.

C28CPUCLK is off.

C28SYSCLK is off.

NOTE

The peripheral - I/O multiplexing implemented in the device prevents all available peripherals

from being used at the same time. This is because more than one peripheral function may

share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the

same time, although such a configuration is not useful. If this is done, the current drawn by

the device will be more than the numbers specified in the current consumption table.

Peripheral Information and Timings

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

5.5 Power Sequencing

5.5.1 Power Management and Supervisory Circuit Solutions

Table 5-2 lists the power management and supervisory circuit solutions for F28M35x devices. LDO

selection depends on the total power consumed in the end application. Go to www.ti.com and click on

Power Management for a complete list of TI power ICs or select the Power Management Selection Guide

link for specific power reference designs.

Table 5-2. Power Management and Supervisory Circuit Solutions

SUPPLIER

Texas Instruments

TYPE

LDO

PART

DESCRIPTION

TPS767D301 Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)

LDO

TPS70202

TPS766xx

TPS3808

TPS3803

TPS799xx

TPS736xx

TPS62110

TPS6230x

TPS62290

TPS62291

Dual 500/250-mA LDO with SVS

LDO

250-mA LDO with PG

SVS

Open Drain SVS with programmable delay

Low-cost Open-drain SVS with 5 μS delay

200-mA LDO in WCSP package

SVS

LDO

400-mA LDO with 40 mV of V_DO

DC/DC

EVM

High V_in1.2-A dc/dc converter in 4x4 QFN package

500-mA converter in WCSP package

6-V input, 1.8-V output, 1-A evaluation module

1-A step-down dc/dc converter in 2x2 SON package

DC/DC

Peripheral Information and Timings

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

6 Device and Documentation Support

6.1 Device Support

6.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the

processors, generate code, develop algorithm implementations, and fully integrate and debug software

and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of processor applications:

Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):

including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (SYS/BIOS), which provides the basic run-time target software

needed to support any processor application.

Hardware Development Tools: Extended Development System ( XDS™) Emulator

For a complete listing of development-support tools for the processor platform, visit the Texas Instruments

website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office

or authorized distributor.

6.1.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

Concerto™ MCU devices and support tools. Each Concerto™ MCU commercial family member has one

of three prefixes: x, p, or no prefix (e.g., xF28M35H52C1RFPT). Texas Instruments recommends two of

three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent

evolutionary stages of product development from engineering prototypes (with prefix x/TMDX) through

fully qualified production devices/tools (no prefix/TMDS).

xF28M35...

pF28M35...

F28M35...

Experimental device that is not necessarily representative of the final device's

electrical specifications

Final silicon die that conforms to the device's electrical specifications but has

not completed quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

Devices with prefix x or p and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, RFP) and temperature range (for example, T).

Device and Documentation Support

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

www.ti.com

For device part numbers and further ordering information of F28M35x devices in the RFP package type,

see the TI website (www.ti.com) or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the F28M35H20B1,

F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1,

F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU Silicon Errata (literature number

SPRZ357).

F28M3

RFP

PREFIX

TEMPERATURE RANGE

experimental device

prototype device

qualified device

−40°C to 105°C

−40°C to 125°C

(Q refers to Q100 qualification

for automotive applications.)

no prefix

DEVICE FAMILY

F28M3 = Concerto^TM

PACKAGE TYPE

144-Pin RFP PowerPAD^TM

Thermally Enhanced Thin Quad Flatpack (HTQFP)

SERIES NUMBER

PINS

1 = 144 pins

PERFORMANCE

(C28x^TMSpeed / Cortex^TM-M3 Speed)

150 / 75 MHz or 100 / 100 MHz

75 / 75 MHz

60 / 60 MHz

PERIPHERALS

Connectivity

Base

FLASH

2 = 256KB each core

3 = additional 256KB to one core^(A)

5 = 512KB each core

RAM

132KB

additional 64KB of masterable RAM

A. The additional 256KB is added to the Cortex™-M3 core (Connectivity Devices) or to the C28x™ core (Base Devices).

Figure 6-1. Device Nomenclature

6.2 Documentation Support

The following documents describe the MCU. Copies of these documents are available on the Internet at

www.ti.com. Tip: Enter the literature number in the search box.

SPRUH22 Concerto F28M35x Technical Reference Manual

SPRZ357

F28M35H20B1,

F28M35H20C1,

F28M35H22B1,

F28M35H22C1,

F28M35H32B1,

F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto

MCU Silicon Errata

6.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and

help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster

innovation and growth of general knowledge about the hardware and software surrounding

these devices.

Device and Documentation Support

Submit Documentation Feedback

F28M35H20B1, F28M35H20C1

F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1

F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1

www.ti.com

SPRS742B–JUNE 2011–REVISED OCTOBER 2011

7 Mechanical Packaging and Orderable Information

7.1 Packaging Information

The following packaging information and addendum reflect the most current data available for the

designated device(s). This data is subject to change without notice and without revision of this document.

Mechanical Packaging and Orderable Information

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

24-Aug-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

F28M35H20B1RFPQ

F28M35H20B1RFPS

F28M35H20B1RFPT

F28M35H20C1RFPQ

F28M35H20C1RFPS

F28M35H20C1RFPT

F28M35H22B1RFPQ

F28M35H22B1RFPS

F28M35H22B1RFPT

F28M35H22C1RFPQ

F28M35H22C1RFPS

F28M35H22C1RFPT

F28M35H32B1RFPQ

F28M35H32B1RFPS

F28M35H32B1RFPT

F28M35H32C1RFPQ

F28M35H32C1RFPS

F28M35H32C1RFPT

F28M35H50B1RFPQ

F28M35H50B1RFPS

F28M35H50B1RFPT

F28M35H50C1RFPQ

F28M35H50C1RFPS

F28M35H50C1RFPT

F28M35H52B1RFPQ

F28M35H52B1RFPS

F28M35H52B1RFPT

F28M35H52C1RFPQ

F28M35H52C1RFPS

F28M35H52C1RFPT

PREVIEW

HTQFP

RFP

144

1000

TBD

Call TI

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Aug-2011

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

XF28M35H52C1RFPT

ACTIVE

HTQFP

RFP

144

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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Addendum-Page 2

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F28M35H20B1_1110 [TI]

相关型号：

F28M35H20B1_12

F28M35H20C

F28M35H20C1

F28M35H20C1RFPQ

F28M35H20C1RFPS

F28M35H20C1RFPT

F28M35H22B

F28M35H22B1

F28M35H22B1RFPQ

F28M35H22B1RFPS

F28M35H22B1RFPT

F28M35H22C