F28M35M52CRFP [TI]
F28M35x Concerto⢠Microcontrollers;
| 型号： | F28M35M52CRFP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | F28M35x Concerto⢠Microcontrollers 微控制器 |
| 文件： | 总226页 (文件大小：4723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
F28M35x Concerto™ Microcontrollers
– Embedded memory
1 Features
•
•
•
•
Up to 512KB of flash (ECC)
•
Master Subsystem — Arm® Cortex®-M3
Up to 36KB of RAM (ECC or parity)
Up to 64KB of shared RAM
2KB of IPC Message RAM
– Up to 100 MHz
– Embedded memory
•
•
•
•
Up to 512KB of flash (ECC)
– IEEE-754 single-precision Floating-Point Unit
Up to 32KB of RAM (ECC or parity)
Up to 64KB of shared RAM
2KB of IPC Message RAM
(FPU)
– Viterbi, Complex Math, CRC Unit (VCU)
– Serial Communications Interface (SCI)
– Five Universal Asynchronous Receiver/
Transmitters (UARTs)
– SPI
– I2C
– Four Synchronous Serial Interfaces (SSIs) and
a Serial Peripheral Interface (SPI)
– Two Inter-integrated Circuits (I2Cs)
– Universal Serial Bus On-the-Go (USB-OTG) +
PHY
– 10/100 ENET 1588 MII
– Two Controller Area Network, D_CAN, modules
(pin-bootable)
– 32-channel Micro Direct Memory Access
(µDMA)
– Dual security zones (128-bit password per
zone)
– External Peripheral Interface (EPI)
– Micro Cyclic Redundancy Check (µCRC)
module
– Four general-purpose timers
– Two watchdog timer modules
– Three external interrupts
– Endianness: little endian
Clocking
– On-chip crystal oscillator and external clock
input
– Dynamic Phase-Locked Loop (PLL) ratio
changes supported
1.2-V digital, 1.8-V analog, 3.3-V I/O design
Interprocessor Communications (IPC)
– 32 handshaking channels
– Four channels generate IPC interrupts
– Can be used to coordinate transfer of data
through IPC Message RAMs
– 6-channel Direct Memory Access (DMA)
– Nine Enhanced Pulse Width Modulator (ePWM)
modules
•
18 outputs (16 high-resolution)
– Six 32-bit Enhanced Capture (eCAP) modules
– Three 32-bit Enhanced Quadrature Encoder
Pulse (eQEP) modules
– Multichannel Buffered Serial Port (McBSP)
– EPI
– One security zone (128-bit password)
– Three 32-bit timers
– Endianness: little endian
Analog Subsystem
•
– Dual 12-bit Analog-to-Digital Converters
(ADCs)
– Up to 2.88 MSPS
– Up to 20 channels
– Four Sample-and-Hold (S/H) circuits
– Up to six comparators with 10-bit Digital-to-
Analog Converter (DAC)
•
•
•
Package
– 144-Pin RFP PowerPAD™ Thermally Enhanced
Thin Quad Flatpack (HTQFP)
Temperature options:
– T: –40°C to 105°C Junction
– S: –40°C to 125°C Junction
– Q: –40°C to 125°C Free-Air
(AEC Q100 qualification for automotive
applications)
•
•
2 Applications
•
•
Up to 74 individually programmable, multiplexed
General-Purpose Input/Output (GPIO) pins
– Glitch-free I/Os
Control Subsystem — TMS320C28x 32-bit CPU
– Up to 150 MHz
•
•
•
•
•
Automated sorting equipment
CNC control
Central inverter
String inverter
AC drive control module
– C28x core hardware built-in self-test
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
•
•
•
Servo drive control module
AC-input BLDC motor drive
DC-input BLDC motor drive
•
•
Industrial AC-DC
Three phase UPS
3 Description
The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent communication
and real-time control subsystems. The F28M35x family of devices is the first series in the Concerto family.
The communications subsystem is based on the industry-standard 32-bit Arm Cortex-M3 CPU and features a
wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, Controller Area
Network (CAN), UART, SSI, I2C, and an external interface.
The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x floating-point CPU and
features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and
encoders and captures—all as implemented by TI’s TMS320C2000™ Entry performance MCUs and Premium
performance MCUs. In addition, the C28-CPU has been enhanced with the addition of the VCU instruction
accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms.
A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage
regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC),
parity, and code secure memory, as well as documentation to assist with system-level industrial safety
certification.
Device Information
PART NUMBER(1)
F28M35H52CRFP
PACKAGE
HTQFP (144)
HTQFP (144)
HTQFP (144)
HTQFP (144)
BODY SIZE
20.0 mm × 20.0 mm
20.0 mm × 20.0 mm
20.0 mm × 20.0 mm
20.0 mm × 20.0 mm
F28M35H22CRFP
F28M35M52CRFP
F28M35E20BRFP
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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3.1 Functional Block Diagram
SECURE
C1
C3
1.8-V
VREG
1.2-V
VREG
RAM
8KB
RAM
8KB
GPIO_MUX1
SECURE
FLASH
(ECC)
(parity)
BOOT
ROM
SECURE
C0
C2
512KB
(ECC)
RAM
8KB
RAM
8KB
64KB
(ECC)
(parity)
APB BUS
REGS
ONLY
AHB BUS
uDMA BUS
10
ADC
ADC_1
M3
BUS
MPU
NVIC
INPUTS
M3
MODULE
M3 CPU
uDMA
MATRIX
I-CODE BUS
D-CODE BUS
4
COMP
INPUTS
M3 SYSTEM BUS
INTER-
PROC
C28 CPU/DMA
ACCESS TO EPI
COMM
CLOCKS
RESETS
NMI
FREQ
GASKET
6
MTOC
MSG
CTOM
COMPARE
+ DAC
S0
S1
S2
S3
S4
S5
S6
S7
MSG
RAM
6
MEM32
TO AHB
BUS
RAM
IPC
COMP
OUT
UNITS
8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB
(parity)
2KB
(parity)
2KB
PUTS
BRIDGE
DEBUG
SECURITY
S0–S7 SHARED RAM (parity)
INTER-
PROC
COMM
4
C28 DMA BUS
COMP
INPUTS
C28 CPU
C28
C28
C28
FPU
ADC_2
10
DMA
VCU
PIE
MODULE
ADC
INPUTS
C28 CPU BUS
ANALOG
SUBSYSTEM
16-
BIT
PF2
32-
BIT
PF1
32-
BIT
PF3
16/32-
BIT
PF0
BOOT
ROM
SECURE
L3
M1
L1
RAM
8KB
RAM
8KB
RAM
2KB
64KB
SECURE
FLASH
(ECC)
(parity)
(ECC)
M0
SECURE
L0
L2
512KB
(ECC)
GPIO_MUX1
66 PINS
RAM
8KB
RAM
8KB
RAM
2KB
(ECC)
(parity)
(ECC)
Copyright © 2017, Texas Instruments Incorporated
A. Some peripherals are not available on the F28M35Mx and F28M35Ex devices.
Figure 3-1. Functional Block Diagram
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................3
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 8
6 Terminal Configuration and Functions..........................9
6.1 Pin Diagram................................................................ 9
6.2 Signal Descriptions................................................... 11
7 Specifications................................................................ 31
7.1 Absolute Maximum Ratings...................................... 31
7.2 ESD Ratings – Automotive....................................... 31
7.3 ESD Ratings – Commercial...................................... 31
7.4 Recommended Operating Conditions.......................32
7.5 Power Consumption Summary................................. 33
7.6 Electrical Characteristics...........................................38
7.7 Thermal Resistance Characteristics for RFP
PowerPAD Package....................................................39
7.8 Thermal Design Considerations................................39
7.9 Timing and Switching Characteristics....................... 40
7.10 Analog and Shared Peripherals..............................59
7.11 Master Subsystem Peripherals............................... 94
7.12 Control Subsystem Peripherals.............................111
8 Detailed Description....................................................141
8.1 Memory Maps......................................................... 142
8.2 Identification............................................................153
8.3 Master Subsystem.................................................. 154
8.4 Control Subsystem..................................................160
8.5 Analog Subsystem..................................................164
8.6 Master Subsystem NMIs.........................................167
8.7 Control Subsystem NMIs........................................ 167
8.8 Resets.....................................................................168
8.9 Internal Voltage Regulation and Power-On-
Reset Functionality....................................................173
8.10 Input Clocks and PLLs..........................................176
8.11 Master Subsystem Clocking..................................186
8.12 Control Subsystem Clocking.................................190
8.13 Analog Subsystem Clocking................................. 192
8.14 Shared Resources Clocking................................. 192
8.15 Loss of Input Clock (NMI Watchdog Function)......192
8.16 GPIOs and Other Pins.......................................... 193
8.17 Emulation/JTAG....................................................208
8.18 Code Security Module...........................................210
8.19 µCRC Module....................................................... 213
9 Applications, Implementation, and Layout............... 215
9.1 TI Reference Design...............................................215
10 Device and Documentation Support........................216
10.1 Device and Development Support Tool
Nomenclature............................................................216
10.2 Tools and Software............................................... 217
10.3 Documentation Support........................................ 218
10.4 Trademarks...........................................................219
10.5 Support Resources............................................... 219
10.6 Electrostatic Discharge Caution............................220
10.7 Glossary................................................................220
11 Mechanical, Packaging, and Orderable
Information.................................................................. 221
11.1 Packaging Information.......................................... 221
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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4 Revision History
Changes from June 23, 2020 to February 1, 2021 (from Revision K (June 2020) to Revision L
(February 2021))
Page
•
•
•
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1: Added Q1 Part Numbers....................................................................................................................6
Figure 10-1: Added GPN information............................................................................................................. 216
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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5 Device Comparison
Table 5-1 lists the features of the F28M35x devices.
Table 5-1. Device Comparison
H52C
H52C-Q1
FEATURE
TYPE(1)
H22C
M52C
M22C
E20B
Master Subsystem — Arm Cortex-M3
Speed (MHz)(2)
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
–
–
100
512
16
16
2
100
256
16
16
2
75
512
16
16
2
75
256
16
16
2
60
256
16
16
2
Flash (ECC) (KB)
RAM (ECC) (KB)
RAM (Parity) (KB)
IPC Message RAM (Parity) (KB)
Security Zones
10/100 ENET 1588 MII
USB OTG FS
SSI/SPI
2
2
2
2
2
Yes
Yes
4
Yes
Yes
4
Yes
Yes
4
Yes
Yes
4
No
No
4
UART
5
5
5
5
5
I2C
CAN(3)
2
2
2
2
2
2
2
2
2
2
µDMA
EPI(4)
32-ch
1
32-ch
1
32-ch
1
32-ch
1
32-ch
1
µCRC module
General-Purpose Timers
Watchdog Timer modules
1
1
1
1
1
4
4
4
4
4
2
2
2
2
2
Control Subsystem — C28x
Speed (MHz)(2)
150
150
75
75
60
FPU
Yes
VCU
Yes
Flash (ECC) (KB)
512
256
20
16
2
512
256
20
16
2
256
20
16
2
RAM (ECC) (KB)
20
20
16
RAM (Parity) (KB)
16
IPC Message RAM (Parity) (KB)
2
2
Security Zones
1
1
1
1
1
ePWM modules
2
2
0
0
–
9: 18 outputs
16 outputs
6 (32-bit)
3 (32-bit)
High-Resolution PWM (HRPWM) outputs
eCAP modules/PWM outputs
eQEP modules
Fault Trip Zones
McBSP/SPI
SCI
12 on any of 64 GPIO pins
1
0
0
0
0
0
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SPI
1
1
1
I2C
1
1
1
DMA
EPI(4)
6-ch
1
6-ch
1
6-ch
1
6-ch
1
6-ch
1
32-Bit Timers
3
3
3
3
3
Shared
64
Shared RAM (Parity) (KB)
64
64
64
0
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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Table 5-1. Device Comparison (continued)
H52C
H52C-Q1
FEATURE
TYPE(1)
H22C
M52C
M22C
E20B
MSPS(5)
Conversion Time(5)
2.88
347 ns
10
2.88
347 ns
10
2.88
347 ns
10
2.88
347 ns
10
2.31
433 ns
10
12-Bit ADC 1
12-Bit ADC 2
3
Channels
Sample-and-Hold
MSPS(5)
Conversion Time(5)
2
2
2
2
2
2.88
347 ns
10
2.88
347 ns
10
2.88
347 ns
10
2.88
347 ns
10
2.31
433 ns
10
3
0
Channels
Sample-and-Hold
2
2
2
2
2
Comparators with Integrated DACs
Voltage Regulator
6
6
6
6
6
Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125°C)
See Section 8.10
Clocking
Additional Safety
Master Subsystem
Control Subsystem
Shared
2 Watchdogs, NMI Watchdog: CPU, Memory
NMI Watchdog: CPU, Memory
Critical Register and I/O Function Lock Protection; RAM Fetch Protection
Packaging
144-Pin RFP PowerPAD
HTQFP
Package Type
Yes
Yes
Yes
Yes
Yes
T: –40°C to 105°C
S: –40°C to 125°C
Q: –40°C to 150°C(6)
–
–
–
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Junction
Temperature (TJ)
Free-Air
Temperature (TA)
Q: –40°C to 125°C(6)
–
Yes
No
No
No
No
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) The maximum frequency at which the Cortex-M3 core can run is 100 MHz. The clock divider before the Cortex-M3 core can only take
values of /1, /2, or /4. For this reason, when the C28x is configured to run at the maximum frequency of 150 MHz, the fastest allowable
frequency for the Cortex-M3 is 75 MHz. If the Cortex-M3 is configured to run at 100 MHz, the maximum frequency of the C28x is
limited to 100 MHz.
(3) The CAN module uses the popular IP known as D_CAN. This document uses the names “CAN” and “D_CAN” interchangeably to
reference this peripheral.
(4) Single EPI arbitrated between masters in Master and Control Subsystems.
(5) An integer divide ratio must be maintained between the C28x and ADC clock frequencies. All MSPS and Conversion Time values are
based on the maximum C28x clock frequency.
(6) "Q" refers to AEC Q100 qualification for automotive applications.
Table 5-2. Possible Speed Combinations for Cortex-M3 and C28x Cores
Cortex-M3
C28x
75 MHz
100 MHz
75 MHz
60 MHz
60 MHz
150 MHz
100 MHz
75 MHz
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F28M35M52C, F28M35M22C, F28M35E20B
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5.1 Related Products
For information about other devices in this family of products, see the following link:
F28M36x Concerto™ Microcontrollers
The F28M3x series of microcontrollers brings together connectivity and control by combining an Arm Cortex-M3
core with the C28x core on to one device. With F28M3x, applications such as solar inverters and industrial
control can keep the benefits of separating the communication and control portions while maintaining a single-
chip solution. In addition, F28M3x microcontrollers enable safety certifications in your system through enhanced
hardware and safety features.
The F28M36x family of devices is the second series in the Concerto family.
TMS320F2838x Microcontrollers With Connectivity Manager
The TMS320F2838x is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-
loop control applications. The F2838x supports a dual-core C28x architecture along with a new Connectivity
Manager that offloads critical communication tasks, significantly boosting system performance. The integrated
analog and control peripherals with advanced connectivity peripherals like EtherCAT and Ethernet also let
designers consolidate real-time control and real-time communications architectures, reducing requirements for
multicontroller systems.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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6 Terminal Configuration and Functions
6.1 Pin Diagram
Figure 6-1 shows the 144-pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack pin assignments.
GPIO135/COMP5OUT(A)
GPIO134
GPIO133/COMP4OUT
GPIO132/COMP3OUT
VREG18EN
PG5_GPIO45
PG2_GPIO42
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
PG6_GPIO46
PF6_GPIO38
PD7_GPIO23
VDDIO
ADC1INB7
ADC1INB4
ADC1INB3
ADC1INB0
VDD12
PD4_GPIO20
PD5_GPIO21
PJ0_GPIO56
PJ1_GPIO57
VSSA1
VDDA1
ADC1VREFHI
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC2INA7
ADC2INA6
PJ2_GPIO58
PJ3_GPIO59
VDDIO
VDD12
PJ4_GPIO60
PJ5_GPIO61
VDD12
VDDIO
PJ6_GPIO62
PG7_GPIO47
PF5_GPIO37
PG1_GPIO41
PG0_GPIO40
PF4_GPIO36
PH5_GPIO53
PH4_GPIO52
PE1_GPIO25
VDDIO
PE0_GPIO24
PH1_GPIO49
PH0_GPIO48
PC7_GPIO71
PC6_GPIO70
PC5_GPIO69
PC4_GPIO68
ADC2INA4
ADC2INA3
ADC2INA2
ADC2INA0
ADC2VREFHI
VDDA2
VSSA2
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
GPIO128
GPIO129/COMP1OUT
GPIO130/COMP6OUT
GPIO131/COMP2OUT
ARS
A. All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 8.11.
B. See Section 6.2.1, Signal Descriptions, for the complete multiplexed signal names.
Figure 6-1. 144-Pin RFP PowerPAD Thermally Enhanced Thin Quad Flatpack (Top View)
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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Note
The exposed lead frame die pad of the PowerPAD package serves two functions: to remove heat from
the die and to provide ground path for the digital ground (analog ground is provided through dedicated
pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB because this
will provide both the digital ground path and good thermal conduction path. To make optimum use of
the thermal efficiencies designed into the PowerPAD package, the PCB must be designed with this
technology in mind. A thermal land is required on the surface of the PCB directly underneath the body
of the PowerPAD. The thermal land should be soldered to the exposed lead frame die pad of the
PowerPAD package; the thermal land should be as large as needed to dissipate the required heat. An
array of thermal vias should be used to connect the thermal pad to the internal GND plane of the
board. See PowerPAD™ Thermally Enhanced Package for more details on using the PowerPAD
package.
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
6.2 Signal Descriptions
Section 6.2.1 describes the signals.
6.2.1 Signal Descriptions
TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PD(3)
NAME
PIN NO.
ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1
ADC1 External High Reference – used only when
in ADC external reference mode.
ADC1VREFHI
ADC1VREFLO
120
I
I
ADC1 External Low Reference – used only when
in ADC external reference mode.
see VSSA1
121
ADC1INA0
ADC1INA2
COMPA1
AIO2
I
ADC1 Group A, Channel 0 input
ADC1 Group A, Channel 2 input
Comparator Input A1
I
122
123
124
I
4 mA
I/O
Digital AIO2
ADC1INA3
ADC1INA4
COMPA2
AIO4
I
ADC1 Group A, Channel 3 input
ADC1 Group A, Channel 4 input
Comparator Input A2
I
I
4 mA
4 mA
I/O
Digital AIO4
ADC1INA6
COMPA3
AIO6
I
ADC1 Group A, Channel 6 input
Comparator Input A3
125
I
I/O
Digital AIO6
ADC1INA7
ADC1INB0
ADC1INB3
ADC1INB4
COMPB2
AIO12
126
117
116
I
ADC1 Group A, Channel 7 input
ADC1 Group B, Channel 0 input
ADC1 Group B, Channel 3 input
ADC1 Group B, Channel 4 input
Comparator Input B2
I
I
I
I
115
114
4 mA
I/O
I
Digital AIO12
ADC1INB7
ADC1 Group B, Channel 7 input
ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2
ADC2 External High Reference – used only when
in ADC external reference mode.
ADC2VREFHI
ADC2VREFLO
133
I
I
ADC2 External Low Reference – used only when
in ADC external reference mode.
see VSSA2
132
ADC2INA0
ADC2INA2
COMPA4
AIO18
I
ADC2 Group A, Channel 0 input
ADC2 Group A, Channel 2 input
Comparator Input A4
I
131
130
129
I
4 mA
I/O
Digital AIO18
ADC2INA3
ADC2INA4
COMPA5
AIO20
I
ADC2 Group A, Channel 3 input
ADC2 Group A, Channel 4 input
Comparator Input A5
I
I
4 mA
4 mA
I/O
Digital AIO20
ADC2INA6
COMPA6
AIO22
I
ADC2 Group A, Channel 6 input
Comparator Input A6
128
I
I/O
Digital AIO22
ADC2INA7
ADC2INB0
ADC2INB3
127
136
137
I
I
I
ADC2 Group A, Channel 7 input
ADC2 Group B, Channel 0 input
ADC2 Group B, Channel 3 input
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F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
ADC2INB4
I
I
ADC2 Group B, Channel 4 input
Comparator Input B5
COMPB5
AIO28
138
139
4 mA
I/O
I
Digital AIO28
ADC2INB7
ADC2 Group B, Channel 7 input
ADC Modules Analog Power and Ground
3.3-V Analog Module 1 Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VDDA1
VDDA2
VSSA1
VSSA2
119
134
118
135
3.3-V Analog Module 2 Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
Analog ground for ADC1, ADC1VREFLO, COMP1–
3, and DAC1–3
Analog ground for ADC2, ADC2VREFLO, COMP4–
6, and DAC4–6
Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only)
GPIO128
140
I/O
I/O
O
General-purpose input/output 128
PU
PU
4 mA
4 mA
GPIO129
General-purpose input/output 129
141
COMP1OUT
GPIO130
Compare result from Analog Comparator 1
General-purpose input/output 130
I/O
O
142
143
112
PU
PU
PU
4 mA
4 mA
8 mA
COMP6OUT
GPIO131
Compare result from Analog Comparator 6
General-purpose input/output 131
I/O
O
COMP2OUT
GPIO132
Compare result from Analog Comparator 2
General-purpose input/output 132
I/O
O
COMP3OUT
GPIO133
Compare result from Analog Comparator 3
General-purpose input/output 133
I/O
O
111
110
109
PU
PU
PU
4 mA
4 mA
8 mA
COMP4OUT
Compare result from Analog Comparator 4
General-purpose input/output 134
GPIO134
I/O
I/O
O
GPIO135(4)
COMP5OUT
General-purpose input/output 135
Compare result from Analog Comparator 5
GPIO Group 1 and Peripheral Signals
PA0_GPIO0
M_U0RX
I/O/Z
I
General-purpose input/output 0
UART-0 receive data
M_I2C1SCL
M_U1RX
5
I/OD
I
I2C-1 clock open-drain bidirectional port
UART-1 receive data
PU
4 mA
C_EPWM1A
PA1_GPIO1
M_U0TX
O
Enhanced PWM-1 output A
General-purpose input/output 1
UART-0 transmit data
I/O/Z
O
M_I2C1SDA
M_U1TX
I/OD
O
I2C-1 data open-drain bidirectional port
UART-1 data transmit
6
7
PU
PU
4 mA
M_SSI1FSS
C_EPWM1B
C_ECAP6
I/O
O
SSI-1 frame
Enhanced PWM-1 output B
Enhanced Capture-6 input/output
General-purpose input/output 2
SSI-0 clock
I/O
I/O/Z
I/O
O
PA2_GPIO2
M_SSI0CLK
M_MIITXD2
C_EPWM2A
4 mA
EMAC MII transmit data bit 2
Enhanced PWM-2 output A
O
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PA3_GPIO3
M_SSI0FSS
M_MIITXD1
M_SSI1CLK
C_EPWM2B
C_ECAP5
I/O/Z
I/O
O
General-purpose input/output 3
SSI-0 frame
EMAC MII transmit data bit 1
SSI-1 clock
8
9
PU
PU
4 mA
I/O
O
Enhanced PWM-2 output B
Enhanced Capture-5 input/output
General-purpose input/output 4
SSI-0 receive data
I/O
I/O/Z
I
PA4_GPIO4
M_SSI0RX
M_MIITXD0
M_CAN0RX
C_EPWM3A
PA5_GPIO5
M_SSI0TX
M_MIIRXDV
M_CAN0TX
C_EPWM3B
C_MFSRA
O
EMAC MII transmit data bit 0
CAN-0 receive data
4 mA
I
O
Enhanced PWM-3 output A
General-purpose input/output 5
SSI-0 transmit data
I/O/Z
O
I
EMAC MII receive data valid
CAN-0 transmit data
12
O
PU
4 mA
O
Enhanced PWM-3 output B
McBSP-A receive frame sync
Enhanced Capture-1 input/output
General-purpose input/output 6
I2C-1 clock open-drain bidirectional port
I
C_ECAP1
I/O
I/O/Z
I/OD
PA6_GPIO6
M_I2C1SCL
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
I/O
M_MIIRXCK
M_CAN0RX
I
I
EMAC MII receive clock
CAN-0 receive data
13
PU
4 mA
USB-0 external power enable
(optionally used in host mode)
M_USB0EPEN
O
M_MIITXD3
C_EPWM4A
O
O
EMAC MII transmit data bit 3
Enhanced PWM-4 output A
C_EPWMSYNCO
PA7_GPIO7
O
Enhanced PWM-4 external sync pulse
General-purpose input/output 7
I2C-1 data open-drain bidirectional port
I/O/Z
I/OD
M_I2C1SDA
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
I/O
M_MIIRXER
M_CAN0TX
I
EMAC MII receive error
CAN-0 transmit data
O
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
14
I/O
I
PU
4 mA
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
M_MIIRXD1
C_EPWM4B
C_MCLKRA
C_ECAP2
I
O
I
EMAC MII receive data 1
Enhanced PWM-4 output B
McBSP-A receive clock
I/O
Enhanced Capture-1 input/output
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PB0_GPIO8
I/O/Z
I/O
General-purpose input/output 8
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
M_U1RX
I
O
UART-1 data receive data
SSI-2 transmit data
M_SSI2TX
M_CAN1TX
M_U4TX
15
PU
4 mA
O
CAN-1 transmit data
O
UART-4 transmit data
C_EPWM5A
C_ADCSOCAO
PB1_GPIO9
O
Enhanced PWM-5 output A
ADC start-of-conversion A
General-purpose input/output 9
O
I/O/Z
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
M_CCP1
I/O
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
18
PU
4 mA
M_U1TX
O
I
UART-1 transmit data
M_SSI2RX
C_EPWM5B
C_ECAP3
SSI-2 receive data
O
Enhanced PWM-5 output B
Enhanced Capture-3 input/output
General-purpose input/output 10
I2C-0 clock open-drain bidirectional port
I/O
I/O/Z
I/OD
PB2_GPIO10
M_I2C0SCL
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
I/O
O
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
USB-0 external power enable
(optionally used in the host mode)
19
PU
4 mA
M_USB0EPEN
M_SSI2CLK
M_CAN1RX
M_U4RX
I/O
SSI-2 clock
I
I
CAN-1 receive data
UART-4 receive data
C_EPWM6A
C_ADCSOCBO
PB3_GPIO11
M_I2C0SDA
O
Enhanced PWM-6 output A
ADC start-of-conversion B
General-purpose input/output 11
I2C-0 data open-drain bidirectional port
O
I/O/Z
I/OD
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
20
PU
4 mA
M_SSI2FSS
M_U1RX
I/O
SSI-2 frame
I
O
UART-1 receive data
Enhanced PWM-6 output B
Enhanced Capture-4 input/output
General-purpose input/output 12
UART-2 receive data
CAN-0 receive data
C_EPWM6B
C_ECAP4
I/O
I/O/Z
I
PB4_GPIO12
M_U2RX
M_CAN0RX
M_U1RX
I
I
UART-1 receive data
EPI-0 signal 23
30
PU
4 mA
M_EPI0S23
M_CAN1TX
M_SSI1TX
C_EPWM7A
I/O
O
CAN-1 transmit data
O
SSI-1 transmit data
O
Enhanced PWM-7 output A
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PB5_GPIO13
M_CCP5
I/O/Z
I/O
General-purpose input/output 13
Capture/Compare/PWM-5
(General-purpose Timer)
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
O
M_CAN0TX
M_CCP2
CAN-0 transmit data
31
PU
4 mA
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
M_U1TX
O
UART-1 transmit data
EPI-0 signal 22
M_EPI0S22
M_CAN1RX
M_SSI1RX
C_EPWM7B
PB6_GPIO14
I/O
I
I
CAN-1 receive data
SSI-1 receive data
O
Enhanced PWM-7 output B
General-purpose input/output 14
I/O/Z
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
M_CCP7
M_CCP5
I/O
I/O
I/O
Capture/Compare/PWM-7
(General-purpose Timer)
Capture/Compare/PWM-5
(General-purpose Timer)
26
PU
4 mA
M_EPI0S37(5)
M_MIICRS
M_I2C0SDA
M_U1TX
I/O
I
EPI-0 signal 37
EMAC MII carrier sense
I2C-0 data open-drain bidirectional port
UART-1 transmit data
I/OD
O
M_SSI1CLK
C_EPWM8A
PB7_GPIO15
M_EXTNMI
M_MIIRXD1
M_EPI0S36(5)
M_I2C0SCL
M_U1RX
I/O
O
SSI-1 clock
Enhanced PWM-8 output A
General-purpose input/output 15
Cortex-M3 external nonmaskable interrupt
EMAC MII receive data 1
EPI-0 signal 36
I/O/Z
I
I
I/O
I/OD
I
27
PU
4 mA
I2C-0 clock open-drain bidirectional port
UART-1 receive data
M_SSI1FSS
C_EPWM8B
I/O
O
SSI-1 frame
Enhanced PWM-8 output B
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PD0_GPIO16
I/O/Z
General-purpose input/output 16
CAN-0 receive data
M_CAN0RX
M_U2RX
I
I
I
UART-2 receive data
M_U1RX
UART-1 receive data
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
M_MIIRXDV
M_MIIRXD2
M_SSI0TX
M_CAN1TX
102
I
EMAC MII receive data valid
EMAC MII receive data 2
SSI-0 transmit data
PU
4 mA
I
O
O
CAN-1 transmit data
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
C_SPISIMOA
PD1_GPIO17
M_CAN0TX
M_U2TX
I/O
I/O/Z
O
SPI-A slave in, master out
General-purpose input/output 17
CAN-0 transmit data
O
UART-2 transmit data
M_U1TX
O
UART-1 transmit data
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
I/O
O
M_MIITXER
M_CCP2
EMAC MII transmit error
98
PU
4 mA
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
M_MIICOL
M_SSI0RX
M_CAN1RX
I
I
I
EMAC MII collision detect
SSI-0 receive data
CAN-1 receive data
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
C_SPISOMIA
PD2_GPIO18
M_U1RX
I/O
I/O/Z
I
SPI-A master in, slave out
General-purpose input/output 18
UART-1 receive data
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
M_CCP5
I/O
I/O
Capture/Compare/PWM-5
(General-purpose Timer)
28
PU
4 mA
M_EPI0S20
M_SSI0CLK
M_U1TX
I/O
I/O
O
EPI-0 signal 20
SSI-0 clock
UART-1 transmit data
CAN-0 receive data
SPI-A clock
M_CAN0RX
C_SPICLKA
I
I/O
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PD3_GPIO19
M_U1TX
I/O/Z
O
General-purpose input/output 19
UART-1 transmit data
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
M_CCP0
I/O
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
29
PU
4 mA
M_EPI0S21
M_SSI0FSS
M_U1RX
I/O
I/O
I
EPI-0 signal 21
SSI-0 frame
UART-1 receive data
CAN-0 transmit data
SPI-A slave transmit enable
General-purpose input/output 20
M_CAN0TX
C_SPISTEA
PD4_GPIO20
O
I/O
I/O/Z
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
M_CCP3
I/O
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
M_MIITXD3
M_EPI0S19
M_U3TX
O
I/O
O
EMAC MII transmit data 3
EPI-0 signal 19
65
PU
4 mA
UART-3 transmit data
CAN-1 transmit data
M_CAN1TX
C_EQEP1A
C_MDXA
O
I
Enhanced QEP-1 input A
McBSP-A transmit data
General-purpose input/output 21
O
PD5_GPIO21
I/O/Z
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
M_CCP4
I/O
I/O
Capture/Compare/PWM-4
(General-purpose Timer)
M_MIITXD2
M_U2RX
O
EMAC MII transmit data 2
UART-2 receive data
64
PU
6 mA
I
I/O
I
M_EPI0S28
M_U3RX
EPI-0 signal 28
UART-3 receive data
M_CAN1RX
C_EQEP1B
C_MDRA
I
CAN-1 receive data
I
Enhanced QEP-1 input B
McBSP-A receive data
General-purpose input/output 22
EMAC MII transmit data 1
UART-2 transmit data
EPI-0 signal 29
I
PD6_GPIO22
M_MIITXD1
M_U2TX
I/O/Z
O
O
M_EPI0S29
M_I2C1SDA
M_U1TX
I/O
I/OD
O
73
PU
6 mA
I2C-0 data open-drain bidirectional port
UART-1 transmit data
Enhanced QEP-1 strobe
McBSP-A transmit clock
C_EQEP1S
C_MCLKXA
I/O
O
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PD7_GPIO23
I/O/Z
I/O
General-purpose input/output 23
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
M_MIITXD0
M_EPI0S30
M_I2C1SCL
M_U1RX
O
I/O
I/OD
I
EMAC MII transmit data 0
EPI-0 signal 30
68
PU
6 mA
I2C-1 clock open-drain bidirectional port
UART-1 receive data
C_EQEP1I
C_MFSXA
PE0_GPIO24
M_SSI1CLK
I/O
O
Enhanced QEP-1 index
McBSP-A transmit frame sync
General-purpose input/output 24
SSI-1 clock
I/O/Z
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
I/O
I
M_EPI0S8
M_USB0PFLT
EPI-0 signal 8
USB-0 external power error state
(optionally used in the host mode)
43
PU
4 mA
M_SSI3TX
M_CAN0RX
M_SSI1TX
C_ECAP1
O
I
SSI-3 transmit data
CAN-1 receive data
O
SSI-1 transmit data
I/O
I
Enhanced Capture-1 input/output
Enhanced QEP-2 input A
General-purpose input/output 25
SSI-1 frame
C_EQEP2A
PE1_GPIO25
M_SSI1FSS
I/O/Z
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
M_CCP6
I/O
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
45
PU
4 mA
M_EPI0S9
M_SSI3RX
M_CAN0TX
M_SSI1RX
C_ECAP2
I/O
I
EPI-0 signal 9
SSI-3 receive data
O
CAN-1 transmit data
O
SSI-1 receive data
I/O
I
Enhanced Capture-2 input/output
Enhanced QEP-2 input B
General-purpose input/output 26
C_EQEP2B
PE2_GPIO26
I/O/Z
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
M_SSI1RX
M_CCP2
I/O
I
SSI-1 receive data
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
32
PU
4 mA
M_EPI0S24
M_SSI3CLK
M_U2RX
I/O
I/O
I
EPI-0 signal 24
SSI-3 clock
UART-2 receive data
SSI-1 clock
M_SSI1CLK
C_ECAP3
C_EQEP2I
I/O
I/O
I/O
Enhanced Capture-3 input/output
Enhanced QEP-2 index
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PE3_GPIO27
M_CCP1
I/O/Z
I/O
O
General-purpose input/output 27
Capture/Compare/PWM-1
(General-purpose Timer)
M_SSI1TX
M_CCP7
SSI-1 transmit data
Capture/Compare/PWM-7
(General-purpose Timer)
I/O
33
PU
4 mA
M_EPI0S25
M_SSI3FSS
M_U2TX
I/O
I/O
O
EPI-0 signal 25
SSI-3 frame
UART-2 transmit data
SSI-1 frame
M_SSI1FSS
C_ECAP4
I/O
I/O
I/O
I/O/Z
Enhanced Capture-4 input/output
Enhanced QEP-2 strobe
General-purpose input/output 28
C_EQEP2S
PE4_GPIO28
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
M_U2TX
M_CCP2
I/O
O
UART-2 transmit data
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
M_MIIRXD0
M_EPI0S34(5)
M_U0RX
I
EMAC MII receive data 0
EPI-0 signal 34
77
PU
4 mA
I/O
I
UART-0 receive data
EPI-0 signal 38
M_EPI0S38(5)
I/O
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
C_SCIRXDA
PE5_GPIO29
I
SCI-A receive data
I/O/Z
General-purpose input/output 29
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
I/O
M_EPI0S35(5)
M_MIITXER
M_U0TX
I/O
O
EPI-0 signal 35
76
EMAC MII transmit error
UART-0 transmit data
PU
4 mA
O
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
C_SCITXDA
PE6_GPIO30
M_MIIMDIO
M_CAN0RX
C_EPWM9A
PE7_GPIO31
M_MIIRXD3
M_CAN0TX
C_EPWM9B
O
I/O/Z
I/O
I
SCI-A transmit data
General-purpose input/output 30
EMAC management data input/output
CAN-0 receive data
22
23
PU
PU
4 mA
4 mA
O
Enhanced PWM-9 output A
General-purpose input/output 31
EMAC MII receive data 3
CAN-0 transmit data
I/O/Z
I
O
O
Enhanced PWM-9 output B
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PF0_GPIO32
I/O/Z
General-purpose input/output 32
CAN-1 receive data
M_CAN1RX
M_MIIRXCK
M_I2C0SDA
M_TRACED2
C_I2CASDA
C_SCIRXDA
C_ADCSOCAO
PF1_GPIO33
M_CAN1TX
M_MIIRXER
I
I
I/OD
O
EMAC MII receive clock
I2C-0 data open-drain bidirectional port
Trace data 2
104
PU
4 mA
I/OD
I
I2C-A data open-drain bidirectional port
SCI-A receive data
ADC start-of-conversion A(6)
General-purpose input/output 33
CAN-1 transmit data
O
I/O/Z
O
I
EMAC MII receive error
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
I/O
103
PU
4 mA
M_I2C0SCL
M_TRACED3
C_I2CASCL
C_EPWMSYNCO
C_ADCSOCBO
PF2_GPIO34
M_MIIPHYINTR
M_EPI0S32(5)
M_SSI1CLK
M_TRACECLK
M_XCLKOUT
C_ECAP1
I/OD
O
I2C-0 clock open-drain bidirectional port
Trace data 3
I/OD
O
I2C-A clock open-drain bidirectional port
Enhanced PWM sync out
ADC start-of-conversion B(6)
General-purpose input/output 34
EMAC PHY MII interrupt
EPI-0 signal 32
O
I/O/Z
I
I/O
I/O
O
SSI-1 clock
Trace clock
82
PU
4 mA
O
External output clock
Enhanced Capture-1 input/output
SCI-A receive data
I/O
I
C_SCIRXDA
C_XCLKOUT
Bmode_pin4
PF3_GPIO35
M_MIIMDC
M_EPI0S33(5)
M_SSI1FSS
M_U0TX
O
External output clock
Boot mode pin 4
I
I/O/Z
I
General-purpose input/output 35
EMAC management data clock
EPI-0 signal 33
I/O
I/O
O
SSI-1 frame
81
PU
4 mA
UART-0 transmit data
Trace data 0
M_TRACED0
C_SCITXDA
Bmode_pin3
PF4_GPIO36
O
O
SCI-A transmit data
I
Boot mode pin 3
I/O/Z
General-purpose input/output 36
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
M_MIIMDIO
M_EPI0S12
M_SSI1RX
M_U0RX
I/O
EMAC management data input/output
EPI-0 signal 12
48
PU
4 mA
I/O
I
I
I
SSI-1 receive data
UART-0 receive data
SCI-A receive data
C_SCIRXDA
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PF5_GPIO37
M_CCP2
I/O/Z
I/O
General-purpose input/output 37
Capture/Compare/PWM-2
(General-purpose Timer)
M_MIIRXD3
M_EPI0S15
M_SSI1TX
C_ECAP2
I
EMAC MII receive data 3
EPI-0 signal 15
51
PU
4 mA
I/O
O
SSI-1 transmit data
I/O
Enhanced Capture-2 input/output
General-purpose input/output 38. If configured as
an output, place a capacitor with a value of 56 pF
or greater near the pin. If configured as an input,
place a series resistor with a value equal to 1 kΩ
or greater near the pin. See the F28M35x
Concerto™ MCUs Silicon Errata for details.
NOTE: For this pin, only the USB0VBUS function
is available on silicon revision 0 devices (GPIO
and the four other functions listed are not
available).
PF6_GPIO38
I/O/Z
69
PU
4 mA
M_USB0VBUS
M_CCP1
Analog
I/O
USB0 VBUS power (5-V tolerant)
Capture/Compare/PWM-1
(General-purpose Timer)
M_MIIRXD2
M_EPI0S38(5)
PF7_GPIO39
PG0_GPIO40
M_U2RX
I
I/O
EMAC MII receive data 2
EPI-0 signal 38
No Pin
No Pin
I/O/Z
I
General-purpose input/output 39 is not pinned out.
General-purpose input/output 40
UART-2 receive data
M_I2C1SCL
I/OD
I2C-1 clock open-drain bidirectional port
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
49
O
PU
4 mA
M_EPI0S13
M_MIIRXD2
M_U4RX
I/O
EPI-0 signal 13
I
EMAC MII receive data 2
UART-4 receive data
I
PG1_GPIO41
M_U2TX
I/O/Z
General-purpose input/output 41
UART-2 transmit data
O
M_I2C1SDA
M_EPI0S14
M_MIIRXD1
M_U4TX
I/OD
I2C-1 data open-drain bidirectional port
EPI-0 signal 14
50
71
PU
4 mA
I/O
I
EMAC MII receive data 1
UART-4 transmit data
O
PG2_GPIO42
M_USB0DM
M_MIICOL
M_EPI0S39(5)
PG3_GPIO43
M_MIICRS
I/O/Z
General-purpose input/output 42
USB0 data minus
Analog
PU
PU
4 mA
4 mA
I
EMAC MII collision detect
EPI-0 signal 39
I/O
I/O/Z
General-purpose input/output 43
EMAC MII carrier sense
EMAC MII receive data valid
Trace data 1
I
M_MIIRXDV
M_TRACED1
Bmode_pin1
PG4_GPIO44
78
I
O
I
Boot mode pin 1
No Pin
No Pin
General-purpose input/output 44 is not pinned out.
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PG5_GPIO45
I/O/Z
General-purpose input/output 45
USB0 data plus
M_USB0DP
Analog
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
72
I/O
PU
4 mA
M_MIITXEN
M_EPI0S40(5)
O
EMAC MII transmit enable
EPI-0 signal 40
I/O
General-purpose input/output 46. If configured as
an output, place a capacitor with a value of 56 pF
or greater near the pin. If configured as an input,
place a series resistor with a value equal to 1 kΩ
or greater near the pin. See the F28M35x
PG6_GPIO46
I/O/Z
Concerto™ MCUs Silicon Errata for details.
NOTE: For this pin, only the USB0ID function is
available on silicon revision 0 devices (GPIO and
the three other functions listed are not available).
70
PU
4 mA
M_USB0ID
Analog
USB0 ID (5-V tolerant)
EMAC MII transmit clock
EPI-0 signal 41
M_MIITXCK
M_EPI0S41(5)
PG7_GPIO47
M_MIITXER
I
I/O
I/O/Z
O
General-purpose input/output 47
EMAC MII transmit error
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
52
I/O
PU
6 mA
M_EPI0S31
Bmode_pin2
PH0_GPIO48
I/O
I
EPI-0 signal 31
Boot mode pin 2
I/O/Z
General-purpose input/output 48
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
M_MIIPHYRST
M_EPI0S6
O
I/O
O
EMAC PHY MII reset
41
PU
4 mA
EPI-0 signal 6
M_SSI3TX
SSI-3 transmit data
C_ECAP5
I/O
I/O/Z
Enhanced Capture-5 input/output
General-purpose input/output 49
PH1_GPIO49
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP7
I/O
M_EPI0S7
M_MIIRXD0
M_SSI3RX
C_ECAP6
I/O
I
EPI-0 signal 7
42
36
PU
PU
4 mA
EMAC MII receive data 0
SSI-3 receive data
I
I/O
I/O/Z
I/O
O
Enhanced Capture-6 input/output
General-purpose input/output 50
EPI-0 signal 1
PH2_GPIO50
M_EPI0S1
M_MIITXD3
M_SSI3CLK
C_EQEP1A
EMAC MII transmit data 3
SSI-3 clock
4 mA
I/O
I
Enhanced QEP-1 input A
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PH3_GPIO51
M_USB0EPEN
I/O/Z
O
General-purpose input/output 51
USB-0 external power enable
(optionally used in the host mode)
M_EPI0S0
I/O
O
EPI-0 signal 0
35
PU
4 mA
M_MIITXD2
M_SSI3FSS
C_EQEP1B
PH4_GPIO52
EMAC MII transmit data 2
SSI-3 frame
I/O
I
Enhanced QEP-1 input B
General-purpose input/output 52
I/O/Z
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
M_EPI0S10
M_MIITXD1
M_SSI1CLK
M_U3TX
I/O
O
EPI-0 signal 10
46
PU
4 mA
EMAC MII transmit data 1
SSI-1 clock
I/O
O
UART-3 transmit data
Enhanced QEP-1 strobe
General-purpose input/output 53
EPI-0 signal 11
C_EQEP1S
PH5_GPIO53
M_EPI0S11
M_MIITXD0
M_SSI1FSS
M_U3RX
I/O
I/O/Z
I/O
O
EMAC MII transmit data 0
SSI-1 frame
47
PU
4 mA
I/O
I
UART-3 receive data
Enhanced QEP-1 index
General-purpose input/output 54
EPI-0 signal 26
C_EQEP1I
PH6_GPIO54
M_EPI0S26
M_MIIRXDV
M_SSI1RX
M_MIITXEN
M_SSI0TX
I/O
I/O/Z
I/O
I
EMAC MII receive data valid
SSI-1 receive data
I
79
PU
4 mA
O
EMAC MII transmit enable
SSI-0 transmit data
O
C_SPISIMOA
C_EQEP3A
PH7_GPIO55
M_MIIRXCK
M_EPI0S27
M_SSI1TX
I/O
I
SPI-A slave in, master out
Enhanced QEP-1 input A
General-purpose input/output 55
EMAC MII receive clock
EPI-0 signal 27
I/O/Z
I
I/O
O
SSI-1 transmit data
80
PU
4 mA
M_MIITXCK
M_SSI0RX
C_SPISOMIA
C_EQEP3B
PJ0_GPIO56
M_MIIRXER
M_EPI0S16
M_I2C1SCL
M_SSI0CLK
C_SPICLKA
C_EQEP3S
I
EMAC MII transmit clock
SSI-0 receive data
I
I/O
I
SPI-A master in, slave out
Enhanced QEP-3 input B
General-purpose input/output 56
EMAC MII receive error
EPI-0 signal 16
I/O/Z
I
I/O
I/OD
I/O
I/O
I/O
63
I2C-1 clock open-drain bidirectional port
SSI-0 clock
PU
4 mA
SPI-A clock
Enhanced QEP-3 strobe
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PJ1_GPIO57
I/O/Z
I/O
General-purpose input/output 57
EPI-0 signal 17
M_EPI0S17
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
I
M_I2C1SDA
M_MIIRXDV
M_SSI0FSS
C_SPISTEA
C_EQEP3I
I/OD
I
I2C-1 data open-drain bidirectional port
EMAC MII receive data valid
SSI-0 frame
62
61
60
PU
PU
PU
4 mA
4 mA
4 mA
I/O
I/O
I/O
I/O/Z
I/O
SPI-A slave transmit enable
Enhanced QEP-3 index
General-purpose input/output 58
EPI-0 signal 18
PJ2_GPIO58
M_EPI0S18
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
M_MIIRXCK
M_SSI0CLK
M_U0TX
I
I/O
O
EMAC MII receive clock
SSI-0 clock
UART-0 transmit data
McBSP-A receive clock
Enhanced PWM-7 output A
General-purpose input/output 59
EPI-0 signal 19
C_MCLKRA
C_EPWM7A
PJ3_GPIO59
M_EPI0S19
I
O
I/O/Z
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP6
I/O
M_MIIMDC
M_SSI0FSS
M_U0RX
O
I/O
I
EMAC management data clock
SSI-0 frame
UART-0 receive data
C_MFSRA
C_EPWM7B
PJ4_GPIO60
M_EPI0S28
I
McBSP-A receive frame sync
Enhanced PWM-7 output B
General-purpose input/output 60
EPI-0 signal 28
O
I/O/Z
I/O
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
I/O
57
PU
6 mA
M_MIICOL
I
EMAC MII collision detect
SSI-1 clock
M_SSI1CLK
C_EPWM8A
PJ5_GPIO61
M_EPI0S29
I/O
O
Enhanced PWM-8 output A
General-purpose input/output 61
EPI-0 signal 29
I/O/Z
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP2
I/O
56
PU
6 mA
M_MIICRS
M_SSI1FSS
C_EPWM8B
I
EMAC MII carrier sense
SSI-1 frame
I/O
O
Enhanced PWM-8 output B
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
PJ6_GPIO62
M_EPI0S30
I/O/Z
I/O
General-purpose input/output 62
EPI-0 signal 30
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP1
I/O
53
PU
6 mA
M_MIIPHYINTR
M_U2RX
I
I
EMAC PHY MII interrupt
UART-2 receive data
C_EPWM9A
PJ7_GPIO63
O
Enhanced PWM-9 output A
General-purpose input/output 63
I/O/Z
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I/O
97
PU
4 mA
M_MIIPHYRST
M_U2TX
O
EMAC PHY MII reset
O
UART-2 transmit data
C_EPWM9B
PC0_GPIO64
PC1_GPIO65
PC2_GPIO66
PC3_GPIO67
PC4_GPIO68
O
Enhanced PWM-9 output B
No Pin
No Pin
No Pin
No Pin
No Pin
No Pin
No Pin
No Pin
I/O/Z
General-purpose input/output 64 is not pinned out.
General-purpose input/output 65 is not pinned out.
General-purpose input/output 66 is not pinned out.
General-purpose input/output 67 is not pinned out.
General-purpose input/output 68
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP5
I
O
I
M_MIITXD3
M_CCP2
EMAC MII transmit data 3
Capture/Compare/PWM-2
(General-purpose Timer)
37
PU
4 mA
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
I
M_EPI0S2
M_CCP1
I/O
EPI-0 signal 2
Capture/Compare/PWM-1
(General-purpose Timer)
I
I/O/Z
I
PC5_GPIO69
M_CCP1
General-purpose input/output 69
Capture/Compare/PWM-1
(General-purpose Timer)
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
38
I
PU
4 mA
USB-0 external power enable
(optionally used in the host mode)
M_USB0EPEN
O
M_EPI0S3
I/O
EPI-0 signal 3
PC6_GPIO70
I/O/Z
General-purpose input/output 70
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP3
M_U1RX
M_CCP0
I
I
I
UART-1 receive data
39
PU
4 mA
Capture/Compare/PWM-0
(General-purpose Timer)
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
M_EPI0S4
I
I/O
EPI-0 signal 4
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
PC7_GPIO71
I/O/Z
I
General-purpose input/output 71
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP0
I
O
I
40
PU
4 mA
M_U1TX
UART-1 transmit data
USB-0 external power error state
(optionally used in the host mode)
M_USB0PFLT
M_EPI0S5
I/O
EPI-0 signal 5
Resets
Digital Subsystem Reset (in) and Watchdog/
Power-on Reset (out). In most applications, TI
recommends that the XRS pin be tied with the
ARS pin. The Digital Subsystem has a built-in
POR circuit, and during a power-on condition, this
pin is driven low by the Digital Subsystem. This pin
is also driven low by the Digital Subsystem when a
watchdog reset occurs. During watchdog reset, the
XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. If needed, an
external circuitry may also drive this pin to assert
device reset. In this case, this pin should be driven
by an open-drain device. A noise filtering circuit
can be connected to this pin. A resistor with a
value from 2.2 kΩ to 10 kΩ should be placed
between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should
be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRS pin to VOL
within 512 OSCCLK cycles when the watchdog
reset is asserted. Regardless of the source, a
device reset causes the Digital Subsystem to
terminate execution. The Cortex-M3 program
counter points to the address contained at the
location 0x00000004. The C28 program counter
points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution
begins at the location designated by the program
counter. The output buffer of this pin is an open-
drain with an internal pullup.
XRS
4
I/OD
PU
4 mA
Analog Subsystem Reset (in) and Power-on Reset
(out). TI recommends that the ARS pin be tied with
the XRS pin. The Analog Subsystem has a built-in
POR circuit, and during a power-on condition, this
pin is driven low by the Analog Subsystem. If
needed, an external circuitry may also drive this
pin to assert a device reset. In this case, TI
recommends that this pin be driven by an open-
drain device. Regardless of the source, the Analog
Subsystem reset causes the digital logic
ARS
144
I/OD
PU
4 mA
associated with the Analog Subsystem, to enter
reset state. The output buffer of this pin is an
open-drain with an internal pullup.
Clocks
External oscillator input or on-chip crystal-oscillator
input. To use the on-chip oscillator, a quartz crystal
or a ceramic resonator must be connected across
X1 and X2. See Figure 8-7.
X1
93
I
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
On-chip crystal-oscillator output. A quartz crystal
or a ceramic resonator must be connected across
X1 and X2. If X2 is not used, it must be left
unconnected. See Figure 8-7.
X2
95
94
O
Clock Oscillator Ground Pin. Use this pin to
connect the GND of external crystal load
capacitors or the ground pin of 3-terminal ceramic
resonators with built-in capacitors. Do not connect
to board ground. See Figure 8-7.
VSSOSC
External oscillator input. This pin feeds a clock
from an external 3.3-V oscillator to internal USB
PLL module and to the CAN peripherals.
see
PJ7_GPIO63
XCLKIN
I
External oscillator output. This pin outputs a clock
divided-down from the internal PLL System Clock.
The divide ratio is defined in the XPLLCLKCFG
register.
see
PF2_GPIO34
XCLKOUT
O/Z
Boot Pins
One of four boot mode pins. Bmode_pin1 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PG3_GPIO43
Bmode_pin1
Bmode_pin2
Bmode_pin3
Bmode_pin4
I
I
I
I
PU
PU
PU
PU
One of four boot mode pins. Bmode_pin2 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PG7_GPIO47
One of four boot mode pins. Bmode_pin3 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PF3_GPIO35
One of four boot mode pins. Bmode_pin4 selects a
specific configuration source from which the
Concerto device boots on start-up.
see
PF2_GPIO34
JTAG
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system control of
the operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored. NOTE: TRST is an active-low test pin and
must be maintained low during normal device
operation. An external pulldown resistor is required
on this pin. The value of this resistor should be
based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor
generally offers adequate protection. Because the
value of the resistor is application-specific, TI
recommends that each target board be validated
for proper operation of the debugger and the
application.
TRST
85
I
PD
TCK
TMS
89
87
I
I
JTAG test clock
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK.
PU
PU
JTAG test data input (TDI) with internal pullup. TDI
is clocked into the selected register (instruction or
data) on a rising edge of TCK.
TDI
88
84
I
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of
TCK.
TDO
O
4 mA
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
Emulator pin 0. When TRST is driven high, this pin
is used as an interrupt to or from the JTAG debug
probe system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With the
EMU0 pin at a logic-high state and the EMU1 pin
at a logic-low state, a rising edge on the TRST pin
would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is required on
this pin. The value of this resistor should be based
on the drive strength of the debugger pods
applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because the value
of the resistor is application-specific, TI
EMU0
83
I/O/Z
PU
4 mA
recommends that each target board be validated
for proper operation of the debugger and the
application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming
out of reset, the device enters Wait-in-Reset mode.
WIR suspends bootloader execution, allowing the
JTAG debug probe to connect to the device and to
modify FLASH contents.
Emulator pin 1. When TRST is driven high, this pin
is used as an interrupt to or from the JTAG debug
probe system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With the
EMU0 pin at a logic-high state and the EMU1 pin
at a logic-low state, a rising edge on the TRST pin
would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is required on
this pin. The value of this resistor should be based
on the drive strength of the debugger pods
applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because the value
of the resistor is application-specific, TI
EMU1
86
I/O/Z
PU
4 mA
recommends that each target board be validated
for proper operation of the debugger and the
application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming
out of reset, the device enters Wait-in-Reset mode.
WIR suspends bootloader execution, allowing the
JTAG debug probe to connect to the device and to
modify FLASH contents.
ITM Trace (Arm Instrumentation Trace Macrocell)
see
PF3_GPIO35
TRACED0
TRACED1
TRACED2
TRACED3
TRACECLK
O
O
O
O
O
ITM Trace data 0
ITM Trace data 1
ITM Trace data 2
ITM Trace data 3
ITM Trace clock
4 mA
4 mA
4 mA
4 mA
4 mA
see
PG3_GPIO43
see
PF0_GPIO32
see
PF1_GPIO33
see
PF2_GPIO34
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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TERMINAL(1)
NAME
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
Test Pins
FLASH Test Pin 1. Reserved for TI. Must be left
unconnected.
FLT1
FLT2
16
21
I/O
I/O
FLASH Test Pin 2. Reserved for TI. Must be left
unconnected.
Internal Voltage Regulator Control
Internal 1.8-V VREG Enable/Disable for VDD18
.
VREG18EN
VREG12EN
113
101
Pull low to enable the internal 1.8-V voltage
regulator (VREG18), pull high to disable VREG18.
PD
PD
Internal 1.2-V VREG Enable/Disable for VDD12
Pull low to enable the internal 1.2-V voltage
.
regulator (VREG12), pull high to disable VREG12.
Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
107
10
25
34
44
54
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin. When
the 1.2-V VREG is enabled (by pulling the
VREG12EN pin low), these pins also supply power
to the Digital Subsystem. When the 1.8-V VREG is
enabled (by pulling the VREG18EN pin low), these
pins also supply power to the Analog Subsystem.
59
105
3
67
74
92
100
96
17
2
106
Digital Logic Power Pins (Analog Subsystem)
VDD18
1
1.8-V Digital Logic Power Pins (associated with the
Analog Subsystem) - no supply needed when
using internal VREG18. Tie with 1.2-µF (minimum)
ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may
be used but could impact supply-rail ramp-up time.
VDD18
108
Digital Logic Power Pins (Master and Control Subsystems)
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
24
55
66
99
75
58
11
90
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 250-nF
(minimum) to 750-nF (maximum) ceramic
capacitor (10% tolerance) to ground when using
internal VREG. Higher value capacitors may be
used but could impact supply-rail ramp-up time.
Digital Logic Ground (Analog, Master, and Control Subsystems)
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TERMINAL(1)
PU
or
OUTPUT
BUFFER
STRENGTH
I/O/Z(2)
DESCRIPTION
RFP
PIN NO.
PD(3)
NAME
Digital Ground Power Pad (located on the bottom
of the chip)
VSS
NC
PWR PAD
91
No Connect Pins
This pin is a "no connect" (that is, this pin is not
connected to any circuitry internal to the device).
(1) Throughout this table, Master Subsystem signals are denoted by the color blue; Control Subsystem signals are denoted by the color
green; and Analog Subsystem signals are denoted by the color orange.
(2) I = Input, O = Output, Z = High Impedance, OD = Open Drain
(3) PU = Pullup, PD = Pulldown
•
•
•
•
•
GPIO_MUX1 pullups can be enabled or disabled by Cortex-M3 software (disabled on reset).
GPIO_MUX2 pullups can be enabled or disabled by C28x software (disabled on reset).
AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns.
All other pullups are always enabled ( XRS, ARS, TMS, TDI, EMU0, EMU1).
All pulldowns are always enabled ( VREG18EN, VREG12EN, TRST).
(4) All I/Os, except for GPIO135, are glitch-free during power up and power down. See Section 8.11.
(5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
(6) Output from the Concerto ePWM is meant for the external ADC (if present).
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SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
4.6
2.5
1.5
4.6
4.6
4.6
105
20
UNIT
VDDIO (I/O and Flash) with respect to VSS
Supply voltage
VDD18 with respect to VSS
VDD12 with respect to VSS
VDDA with respect to VSSA
VIN (3.3 V)
V
Analog voltage
V
V
Input voltage
Output voltage
VO
V
Supply ramp rate
Input clamp current
Output clamp current
Free-Air temperature
Junction temperature(4)
Storage temperature(4)
VDDIO, VDD18, VDD12, VDDA with respect to VSS
V/s
mA
mA
°C
°C
°C
(3)
IIK (VIN < 0 or VIN > VDDIO
)
–20
–20
–40
–40
–65
IOK (VO < 0 or VO > VDDIO
)
20
TA
125
150
150
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics.
7.2 ESD Ratings – Automotive
VALUE
UNIT
F28M35H52C in 144-pin RFP package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
±500
±750
V(ESD)
Electrostatic discharge
V
Charged device model (CDM),
per AEC Q100-011
Corner pins on 144-pin RFP:
1, 36, 37, 72, 73, 108, 109, 144
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings – Commercial
VALUE
UNIT
F28M35H52C, F28M35H22C, F28M35M52C, F28M35M22C, F28M35E20B in 144-pin RFP package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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7.4 Recommended Operating Conditions
MIN NOM
MAX
UNIT
(1)
Device supply voltage, I/O, VDDIO
2.97
3.3
3.63
V
Device supply voltage, Analog Subsystem, VDD18
(when internal VREG is disabled and 1.8 V is
supplied externally)
1.71
1.8
1.995
1.32
V
V
Device supply voltage, Master and Control
Subsystems, VDD12
(when internal VREG is disabled and 1.2 V is
supplied externally)
1.14
2.97
1.2
Supply ground, VSS
0
3.3
0
V
V
V
(1)
Analog supply voltage, VDDA
3.63
Analog ground, VSSA
H52C, H22C
2
2
100
75
Device clock frequency (system clock)
Master Subsystem
M52C, M22C
E20B
MHz
MHz
2
60
H52C, H22C
M52C, M22C
E20B
2
150
75
Device clock frequency (system clock)
Control Subsystem
2
2
60
T version
S version(2)
–40
–40
105
125
Junction temperature, TJ
Free-Air temperature, TA
°C
°C
Q version
–40
–40
150
125
(AEC Q100 qualification)(2)
Q version
(AEC Q100 qualification)
(1) VDDIO and VDDA should be maintained within approximately 0.3 V of each other.
(2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
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7.5 Power Consumption Summary
7.5.1 Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP
(2)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP
IDDA
IDD18
IDDA
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
MAX
The following Cortex-M3
peripherals are exercised:
•
•
•
•
•
•
•
•
•
•
•
I2C1
SSI1, SSI2
UART0, UART1, UART2
CAN0
USB
µDMA
Timer0, Timer1
µCRC
WDOG0, WDOG1
Flash
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
•
•
•
McBSP
Operational (1)
(RAM)
eQEP1, eQEP2
–
325 mA
–
40 mA
–
25 mA
–
225 mA
–
65 mA
–
40 mA
eCAP1, eCAP2,
eCAP3, eCAP4
•
•
•
•
•
•
•
SCI-A
SPI-A
I2C
DMA
VCU
FPU
Flash
The following Analog peripherals
are exercised:
•
•
ADC1, ADC2
Comparator 1,
Comparator 2,
Comparator 3,
Comparator 4,
Comparator 5,
Comparator 6
•
•
PLL is on.
Cortex-M3 CPU is not
executing.
•
•
•
•
•
M3SSCLK is on.
SLEEP IDLE
–
146 mA
–
2 mA
–
20 mA
–
110 mA
–
11 mA
–
2 mA
C28CLKIN is on.
C28x CPU is not executing.
C28CPUCLK is off.
C28SYSCLK is on.
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VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP
(2)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP
IDDA
IDD18
IDDA
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
MAX
•
•
PLL is on.
Cortex-M3 CPU is not
executing.
•
•
•
•
•
M3SSCLK is on.
SLEEP
STANDBY
–
126 mA
–
2 mA
–
20 mA
–
90 mA
–
11 mA
–
2 mA
C28CLKIN is off.
C28x CPU is not executing.
C28CPUCLK is off.
C28SYSCLK is off.
•
•
PLL is off.
Cortex-M3 CPU is not
executing.
•
•
•
•
•
M3SSCLK is 32 kHz.
C28CLKIN is off.
DEEP SLEEP
STANDBY
–
76 mA
–
2 mA
–
5 mA
–
60 mA
–
7 mA
–
2 mA
C28x CPU is not executing.
C28CPUCLK is off.
C28SYSCLK is off.
(1) The following is done in a loop:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Code is running out of RAM.
All I/O pins are left unconnected.
All the communication peripherals are exercised in loop-back mode.
USB – Only logic is exercised by loading and unloading FIFO.
µDMA does memory-to-memory transfer.
DMA does memory-to-memory transfer.
VCU – CRC calculated and checked.
FPU – Float operations performed.
ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
Timers and Watchdog serviced.
eCAP in APWM mode generates 36.6-kHz output on 4 pins.
ADC performs continuous conversion.
FLASH is continuously read and in active state.
XCLKOUT is turned off.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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7.5.2 Current Consumption at 100-MHz C28x SYSCLKOUT and 100-MHz M3SSCLK
VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP
(2)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP
IDDA
IDD18
IDDA
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
MAX
The following Cortex-M3
peripherals are exercised:
•
•
•
•
•
•
•
•
•
•
•
I2C1
SSI1, SSI2
UART0, UART1, UART2
CAN0
USB
µDMA
Timer0, Timer1
µCRC
WDOG0, WDOG1
Flash
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
•
•
•
McBSP
Operational (1)
(RAM)
eQEP1, eQEP2
–
295 mA
–
40 mA
–
20 mA
–
200 mA
–
65 mA
–
40 mA
eCAP1, eCAP2,
eCAP3, eCAP4
•
•
•
•
•
•
•
SCI-A
SPI-A
I2C
DMA
VCU
FPU
Flash
The following Analog peripherals
are exercised:
•
•
ADC1, ADC2
Comparator 1,
Comparator 2,
Comparator 3,
Comparator 4,
Comparator 5,
Comparator 6
(1) The following is done in a loop:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Code is running out of RAM.
All I/O pins are left unconnected.
All the communication peripherals are exercised in loop-back mode.
USB – Only logic is exercised by loading and unloading FIFO.
µDMA does memory-to-memory transfer.
DMA does memory-to-memory transfer.
VCU – CRC calculated and checked.
FPU – Float operations performed.
ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
Timers and Watchdog serviced.
eCAP in APWM mode generates 36.6-kHz output on 4 pins.
ADC performs continuous conversion.
FLASH is continuously read and in active state.
XCLKOUT is turned off.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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7.5.3 Current Consumption at 75-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP
(2)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP
IDDA
IDD18
IDDA
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
MAX
The following Cortex-M3
peripherals are exercised:
•
•
•
•
•
•
•
•
•
•
•
I2C1
SSI1, SSI2
UART0, UART1, UART2
CAN0
USB
µDMA
Timer0, Timer1
µCRC
WDOG0, WDOG1
Flash
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
•
•
•
McBSP
Operational (1)
(RAM)
eQEP1, eQEP2
–
275 mA
–
40 mA
–
25 mA
–
175 mA
–
65 mA
–
40 mA
eCAP1, eCAP2,
eCAP3, eCAP4
•
•
•
•
•
•
•
SCI-A
SPI-A
I2C
DMA
VCU
FPU
Flash
The following Analog peripherals
are exercised:
•
•
ADC1, ADC2
Comparator 1,
Comparator 2,
Comparator 3,
Comparator 4,
Comparator 5,
Comparator 6
(1) The following is done in a loop:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Code is running out of RAM.
All I/O pins are left unconnected.
All the communication peripherals are exercised in loop-back mode.
USB – Only logic is exercised by loading and unloading FIFO.
µDMA does memory-to-memory transfer.
DMA does memory-to-memory transfer.
VCU – CRC calculated and checked.
FPU – Float operations performed.
ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
Timers and Watchdog serviced.
eCAP in APWM mode generates 36.6-kHz output on 4 pins.
ADC performs continuous conversion.
FLASH is continuously read and in active state.
XCLKOUT is turned off.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
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7.5.4 Current Consumption at 60-MHz C28x SYSCLKOUT and 60-MHz M3SSCLK
VREG ENABLED
VREG DISABLED
IDD12 IDDIO
TYP
(2)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP
IDDA
IDD18
IDDA
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
MAX
The following Cortex-M3
peripherals are exercised:
•
•
•
•
•
•
•
•
•
•
•
I2C1
SSI1, SSI2
UART0, UART1, UART2
CAN0
USB
µDMA
Timer0, Timer1
µCRC
WDOG0, WDOG1
Flash
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
•
•
•
McBSP
Operational (1)
(RAM)
eQEP1, eQEP2
–
250 mA
–
40 mA
–
20 mA
–
155 mA
–
65 mA
–
40 mA
eCAP1, eCAP2,
eCAP3, eCAP4
•
•
•
•
•
•
•
SCI-A
SPI-A
I2C
DMA
VCU
FPU
Flash
The following Analog peripherals
are exercised:
•
•
ADC1, ADC2
Comparator 1,
Comparator 2,
Comparator 3,
Comparator 4,
Comparator 5,
Comparator 6
(1) The following is done in a loop:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Code is running out of RAM.
All I/O pins are left unconnected.
All the communication peripherals are exercised in loop-back mode.
USB – Only logic is exercised by loading and unloading FIFO.
µDMA does memory-to-memory transfer.
DMA does memory-to-memory transfer.
VCU – CRC calculated and checked.
FPU – Float operations performed.
ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
Timers and Watchdog serviced.
eCAP in APWM mode generates 36.6-kHz output on 4 pins.
ADC performs continuous conversion.
FLASH is continuously read and in active state.
XCLKOUT is turned off.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
Note
The peripheral-I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time because more than one peripheral function may share an I/O pin. It is,
however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If the clocks to all the peripherals are turned on at the same time, the
current drawn by the device will be more than the numbers specified in the current consumption tables
(Section 7.5.1, Section 7.5.2, Section 7.5.3, and Section 7.5.4).
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MAX UNIT
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VSS – 0.3
TYP
VIL
Low-level input voltage (3.3 V)
High-level input voltage (3.3 V)
Low-level output voltage
VDDIO * 0.3
V
V
V
VIH
VOL
VDDIO * 0.7
VDDIO + 0.3
VDDIO * 0.2
IOL = IOL MAX
IOH = IOH MAX
IOH = 50 μA
VDDIO * 0.8
VDDIO – 0.2
–50
VOH
High-level output voltage
V
All GPIO pins
–230
–230
–400
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V XRS pin
ARS pin
–50
Input current
(low level)
IIL
μA
–100
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
±2(1)
±2(1)
200
Pin with pullup
enabled
Input current
(high level)
IIH
μA
Pin with pulldown
enabled
50
All GPIO/AIO pins
Group 2(2)
4
8
Low-level output sink current, VOL
= VOL(MAX)
IOL
mA
mA
All GPIO/AIO pins
Group 2(2)
–4
–8
High-level output source current,
VOH = VOH(MIN)
IOH
Output current, pullup or pulldown
disabled
IOZ
CI
VO = VDDIO or 0 V
±2(1) μA
Input capacitance
2
pF
µs
Digital Subsystem POR reset
release delay time
Time after POR event is removed to XRS release
Time after POR event is removed to ARS release
50
Analog Subsystem POR reset
release delay time
400
800 µs
VREG VDD18 output
VREG VDD12 output
Internal VREG18 on
Internal VREG12 on
1.77
1.935
V
V
1.2
(1) For GPIO38 and GPIO46 (USB OTG pins), this parameter is ±8 µA.
(2) Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1,
PD0_GPIO16, AIO7, AIO4.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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7.7 Thermal Resistance Characteristics for RFP PowerPAD Package
°C/W(1)
6.3
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
0
4.4
0
18.8
11.5
10.0
8.6
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
0.3
0.2
150
250
500
0
PsiJT
0.3
0.3
4.8
4.6
150
250
500
PsiJB
Junction-to-board
4.5
4.4
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end-application design and operational profile, the IDD12, IDD18, and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require additional
thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The
critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature.
Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the
operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. For
more details about thermal metrics and definitions, see Semiconductor and IC Package Thermal Metrics.
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7.9 Timing and Switching Characteristics
7.9.1 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to
prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO135, are glitch-free
during power up and power down.) No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to
any digital pin (for analog pins, this value is 0.7 V above VDDA) before powering up the device. Voltages applied
to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable
results.
VDDIO, VDDA
(3.3 V)
VDD12, VDD18
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
t
w(RSL2)
t
w(RSL1)
XRS(D)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
User-code execution phase
User-code dependent
t
d(EX)
(C)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
GPIO pins as input (state depends on internal PU/PD)
I/O Pins
User-code dependent
Figure 7-1. Power-On Reset
A. Upon power up, PLLSYSCLK is OSCCLK/8. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0,
PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32 during this phase.
B. Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at
the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or
without PLL enabled.
D. The XRS pin will be driven low by on-chip POR circuitry until the VDDIO voltage crosses the POR threshold. (The POR threshold is lower
than the operating voltage requirement.) To allow the external clock to stabilize, the XRS pin may also need to be driven low by the
system for additional time.
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7.9.1.1 Reset ( XRS) Timing Requirements
MIN
14000tc(M3C)
32tc(OCK)
MAX
UNIT
cycles
cycles
(1)
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRS low
(1) The minimum hold time for boot mode pins is 23 times longer for silicon revision 0 devices.
7.9.1.2 Reset ( XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
μs
tw(RSL1)
tw(WDRS)
td(EX)
Pulse duration, XRS driven by device
Pulse duration, reset pulse generated by watchdog
Delay time, address/data valid after XRS high
Start-up time, internal zero-pin oscillator
On-chip crystal-oscillator start-up time
600
512tc(OCK)
cycles
cycles
μs
32tc(OCK)
tINTOSCST
3
2
(1)
tOSCST
ms
(1) Dependent on crystal/resonator and board design.
X1/X2
XCLKOUT
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
User-Code Execution
Control
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current M3SSCLK speed. The M3SSCLK will be based on user environment and could be with or
without PLL enabled.
Figure 7-2. Warm Reset
7.9.1.3 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power management
product folder to select a device and to access reference designs, technical documents, support and training.
The Power management guide is also available for download.
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7.9.2 Clock Specifications
This section provides the frequencies and timing requirements of the input clocks; PLL lock times; frequencies of
the internal clocks; and the frequency and switching characteristics of the output clock.
7.9.2.1 Changing the Frequency of the Main PLL
When configuring the PLL, it should be locked twice in a row. The PLL will be ready to use in the system when
the xPLLSTS[xPLLLOCKS] bit is set after the second lock. The SysCtlClockPllConfig () function in sysctl.c,
found in controlSUITE™, may be referenced as an example of a proper PLL initialization sequence. For
additional information, see the "Clock Control" section of the Concerto F28M35x Technical Reference Manual.
7.9.2.2 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.9.2.2.1 shows the frequency requirements for the input clocks to the F28M35x devices. Table 7-1
shows the crystal equivalent series resistance requirements. Section 7.9.2.2.3, Section 7.9.2.2.4, Section
7.9.2.2.5, Section 7.9.2.2.6 and show the timing requirements for the input clocks to the F28M35x devices.
Section 7.9.2.2.7 shows the PLL lock times for the Main PLL and the USB PLL. The Main PLL operates from the
X1 or X1/X2 input clock pins, and the USB PLL operates from the XCLKIN input clock pin.
7.9.2.2.1 Input Clock Frequency
MIN
2
MAX UNIT
20 MHz
30 MHz
100 MHz
60 MHz
f(OSC)
f(OCI)
f(OCI)
f(XCI)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator (PLL enabled)
Frequency, X1, from external oscillator (PLL disabled)
Frequency, XCLKIN, from external oscillator
2
2
2
Table 7-1. Crystal Equivalent Series Resistance (ESR) Requirements
CRYSTAL FREQUENCY (MHz)
MAXIMUM ESR (Ω)
(CL1/2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1/2 = 24 pF)
(1)
2
4
175
100
75
65
55
50
50
45
45
45
375
195
145
120
110
95
6
8
10
12
14
16
18
20
90
75
65
50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
7.9.2.2.2 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 20 MHz; ESR MAX = 50 Ω;
CL1 = CL2 = 24 pF, C0 = 7 pF
Start-up time(1)
2
ms
(1) Start-up time is dependent on the crystal and tank circuit components. It is recommended that the crystal vendor characterize the
application with the chosen crystal.
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7.9.2.2.3 X1 Timing Requirements - PLL Enabled (1)
MIN
MAX UNIT
tf(OCI)
Fall time, X1
6
6
ns
ns
tr(OCI)
Rise time, X1
tw(OCL)
tw(OCH)
Pulse duration, X1 low as a percentage of tc(OCI)
Pulse duration, X1 high as a percentage of tc(OCI)
45%
45%
55%
55%
(1) The possible Main PLL configuration modes are shown in Table 8-19 to Table 8-22.
7.9.2.2.4 X1 Timing Requirements - PLL Disabled
MIN
MAX UNIT
Up to 20 MHz
6
tf(OCI)
Fall time, X1
Rise time, X1
ns
2
20 MHz to 100 MHz
Up to 20 MHz
6
tr(OCI)
ns
2
20 MHz to 100 MHz
tw(OCL)
tw(OCH)
Pulse duration, X1 low as a percentage of tc(OCI)
Pulse duration, X1 high as a percentage of tc(OCI)
45%
45%
55%
55%
7.9.2.2.5 XCLKIN Timing Requirements - PLL Enabled
MIN(1)
MAX UNIT
tf(XCI)
Fall time, XCLKIN
6
6
ns
ns
tr(XCI)
Rise time, XCLKIN
tw(XCL)
tw(XCH)
Pulse duration, XCLKIN low as a percentage of tc(XCI)
Pulse duration, XCLKIN high as a percentage of tc(XCI)
45%
45%
55%
55%
(1) The possible USB PLL configuration modes are shown in Table 8-23 and Table 8-24.
7.9.2.2.6 XCLKIN Timing Requirements - PLL Disabled
MIN
MAX UNIT
Up to 20 MHz
6
tf(XCI)
Fall time, XCLKIN
Rise time, XCLKIN
ns
2
20 MHz to 100 MHz
Up to 20 MHz
6
tr(XCI)
ns
2
20 MHz to 100 MHz
tw(XCL)
tw(XCH)
Pulse duration, XCLKIN low as a percentage of tc(XCI)
Pulse duration, XCLKIN high as a percentage of tc(XCI)
45%
45%
55%
55%
7.9.2.2.7 PLL Lock Times
MIN
NOM
MAX
UNIT
input clock
cycles
t(PLL)
t(USB)
Lock time, Main PLL (X1, from external oscillator)
Lock time, USB PLL (XCLKIN, from external oscillator)
2000(1)
2000(1)
input clock
cycles
(1) For example, if the input clock to the PLL is 10 MHz, then a single PLL lock time is 100 ns × 2000 = 200 µs. This defines the time of a
single write to the PLL configuration registers until the xPLLSTS[xPLLLOCKS] bit is set. The PLL should be locked twice to ensure a
good PLL output frequency is present.
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F28M35M52C, F28M35M22C, F28M35E20B
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7.9.2.3 Output Clock Frequency and Switching Characteristics
Section 7.9.2.3.1 provides the frequency of the output clock from the F28M35x devices. Section 7.9.2.3.2 shows
the switching characteristics of the output clock from the F28M35x devices, XCLKOUT.
7.9.2.3.1 Output Clock Frequency
MIN
MAX UNIT
f(XCO)
Frequency, XCLKOUT
2
37.5 MHz
7.9.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
5
5
tr(XCO)
Rise time, XCLKOUT
ns
tw(XCOL)
tw(XCOH)
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
H – 2
H – 2
H + 2
H + 2
ns
ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
7.9.2.4 Internal Clock Frequencies
Section 7.9.2.4 provides the clock frequencies for the internal clocks of the F28M35x devices.
7.9.2.4.1 Internal Clock Frequencies (150-MHz Devices)
MIN
NOM
MAX
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
f(USB)
f(PLL)
f(OCK)
f(M3C)
f(ADC)
f(SYS)
f(HSP)
f(LSP)
f(10M)
f(32K)
Frequency, USBPLLCLK
Frequency, PLLSYSCLK
Frequency, OSCCLK
60
2
2
2
2
2
2
2
150
100
Frequency, M3SSCLK
Frequency, ASYSCLK
Frequency, C28SYSCLK
Frequency, C28HSPCLK
Frequency, C28LSPCLK(2)
Frequency, 10MHzCLK
Frequency, 32KHzCLK
100(1)
37.5
150(1)
150(1)
150(1)
37.5(3)
10
32
(1) An integer divide ratio must be maintained between the C28x and Cortex-M3 clock frequencies. For example, when the C28x is
configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 will be 75 MHz. See Figure
8-10 and Figure 8-12 to see the internal clocks and clock divider options.
(2) Lower LSPCLK will reduce device power consumption.
(3) This is the default reset value if C28SYSCLK = 150 MHz.
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7.9.3 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
7.9.3.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.9.3.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
DATA SHEET
TESTER PIN ELECTRONICS
TIMING
REFERENCE
(A)
POINT
Z0 = 50 W
TD = 6 ns
25 W
15 W
(B)
TRANSMISSION LINE
DEVICE PIN
20 pF
20 pF
OUTPUT
UNDER
TEST
CONCERTO DEVICE
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-3. 3.3-V Test Load Circuit
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7.9.4 Flash Timing – Master Subsystem
7.9.4.1 Master Subsystem – Flash/OTP Endurance
MIN
TYP
MAX
UNIT
cycles
write
Nf
Flash endurance for the array (write/erase cycles)
OTP endurance for the array (write cycles)
20000
50000
NOTP
1
7.9.4.2 Master Subsystem – Flash Parameters
TEST
CONDITIONS
PARAMETER(1)
MIN
TYP
MAX
UNIT
128 data bits + 16 ECC bits
Program Time(2) 16K sector
64K sector
40
160
640
25
300
320
1280
50
µs
ms
ms
Erase Time(3)
at < 25 cycles
16K sector
ms
ms
64K sector
35
60
Erase Time(3)
at 50k cycles
16K sector
115
130
105
55
4000
4000
64K sector
(4) (5)
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VREG disabled
VREG enabled
mA
mA
(4) (5)
IDDIOP
(4) (5)
IDDIOP
195
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:
•
•
•
Code that uses Flash API to program the Flash
Flash API itself
Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(3) Erase time includes Erase verify by the CPU.
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
(5) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral.
7.9.4.3 Master Subsystem – Flash/OTP Access Timing
PARAMETER(1)
MIN
25
MAX UNIT
ta(f)
Flash access time
OTP access time
ns
ns
ta(OTP)
50
(1) Access time numbers shown in this table are before device characterization. Final numbers will be published in the data sheet for the
fully qualified production device.
7.9.4.4 Master Subsystem – Flash Data Retention Duration
PARAMETER
Data retention duration
TEST CONDITIONS
TJ = 85°C
MIN
MAX UNIT
tretention
20
years
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7.9.4.5 Master Subsystem – Minimum Required Flash/OTP Wait States at Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
WAIT STATE
100
90
80
70
60
50
40
30
20
10
10
11.11
12.5
14.29
16.67
20
2
2
1
1
1
1
0
0
0
0
25
33.33
50
100
The equation to compute the Flash wait state in Section 7.9.4.5 is as follows:
SYSCLK (MHz)
RWAIT
=
1
40 (MHz)
round up to the next integer, or 1, whichever is larger.
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7.9.5 Flash Timing – Control Subsystem
7.9.5.1 Control Subsystem – Flash/OTP Endurance
MIN
TYP
MAX
UNIT
cycles
write
Nf
Flash endurance for the array (write/erase cycles)
OTP endurance for the array (write cycles)
20000
50000
NOTP
1
7.9.5.2 Control Subsystem – Flash Parameters
TEST
CONDITIONS
PARAMETER(1)
MIN
TYP
MAX
UNIT
128 data bits + 16 ECC bits
Program Time(2) 16K sector
64K sector
40
120
480
25
300
240
960
50
µs
ms
ms
Erase Time(3)
at < 25 cycles
16K sector
ms
ms
64K sector
35
60
Erase Time(3)
at 50k cycles
16K sector
105
120
90
4000
4000
64K sector
(4) (5)
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VREG disabled
VREG enabled
mA
mA
(4) (5)
IDDIOP
55
(4) (5)
IDDIOP
150
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:
•
•
•
Code that uses Flash API to program the Flash
Flash API itself
Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(3) Erase time includes Erase verify by the CPU.
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
(5) This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral.
7.9.5.3 Control Subsystem – Flash/OTP Access Timing
PARAMETER(1)
MIN
25
MAX UNIT
ta(f)
Flash access time
OTP access time
ns
ns
ta(OTP)
50
(1) Access time numbers shown in this table are before device characterization. Final numbers will be published in the data sheet for the
fully qualified production device.
7.9.5.4 Control Subsystem – Flash Data Retention Duration
PARAMETER
Data retention duration
TEST CONDITIONS
TJ = 85°C
MIN
MAX UNIT
tretention
20
years
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Table 7-2. Control Subsystem – Minimum Required Flash/OTP Wait States at
Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
WAIT STATE
150
140
130
120
110
100
90
6.7
7.14
7.7
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
8.33
9.1
10
11.11
12.5
14.29
16.67
20
80
70
60
50
40
25
30
33.33
50
20
10
100
The equation to compute the Flash wait state in Table 7-2 is as follows:
SYSCLK (MHz)
RWAIT
=
1
40 (MHz)
round up to the next integer, or 1, whichever is larger.
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7.9.6 GPIO Electrical Data and Timing
7.9.6.1 GPIO - Output Timing
7.9.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPIO pins
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
tr(GPO)
tf(GPO)
Figure 7-4. General-Purpose Output Timing
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7.9.6.2 GPIO - Input Timing
7.9.6.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
QUALPRD ≠ 0
tw(SP)
Sampling period
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-5. Sampling Mode
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7.9.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 7-6. General-Purpose Input Timing
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7.9.6.4 Low-Power Mode Wakeup Timing
Section 7.9.6.4.1 shows the timing requirements, Section 7.9.6.4.2 shows the switching characteristics, and
Figure 7-7 shows the timing diagram for IDLE mode.
7.9.6.4.1 IDLE Mode Timing Requirements
MIN(1)
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
Pulse duration, external wake-up
signal
tw(WAKE-INT)
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.6.4.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program
execution resume (2)
Wake-up from Flash
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
cycles
cycles
cycles
•
Flash module in active state
20tc(SCO) + tw(IQSW)
1050tc(SCO)
td(WAKE-IDLE)
Wake-up from Flash
•
•
Flash module in sleep state
Wake-up from SARAM
1050tc(SCO) + tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
7.9.6.4.3 IDLE Entry and Exit Timing Diagram
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE-INT)
WAKE INT(A)(B)
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-7. IDLE Entry and Exit Timing
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7.9.6.4.4 STANDBY Mode Timing Requirements
MIN
3tc(OSCCLK)
MAX
UNIT
Without input qualification
With input qualification(1)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.6.4.5 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction executed
to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO) cycles
Delay time, external wake signal to
program execution resume(1)
•
Wake up from flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
cycles
–
100tc(SCO) + tw(WAKE-INT)
td(WAKE-STBY)
•
Wake up from flash
Flash module in sleep state
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
cycles
cycles
–
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
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7.9.6.4.6 STANDBY Entry and Exit Timing Diagram
(A)
(C)
(E)
(B)
(D)
(F)
STANDBY
STANDBY
Normal Execution
Device Status
Flushing Pipeline
Wake-up Signal(G)
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
td(IDLE-XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to
XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to
enter STANDBY mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
G. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4
OSCCLK cycles have elapsed.
Figure 7-8. STANDBY Entry and Exit Timing Diagram
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7.9.6.4.7 HALT Mode Timing Requirements
MIN
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Section 7.9.1.2 for an explanation of toscst
.
7.9.6.4.8 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
32tc(SCO)
MAX
45tc(SCO)
UNIT
cycles
cycles
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
131072tc(OSCCLK)
Delay time, PLL lock to program execution resume
•
Wake up from flash
– Flash module in sleep state
1125tc(SCO)
cycles
cycles
td(WAKE-HALT)
•
Wake up from SARAM
35tc(SCO)
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7.9.6.4.9 HALT Entry and Exit Timing Diagram
(G)
(A)
(C)
(E)
(B)
(D)
(F)
Device Status
HALT
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn(H)
td(WAKE-HALT)
tp
tw(WAKE-GPIO)
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off
and the CLKIN to the core is stopped:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its
access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF access in
progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be
taken to maintain a low noise environment before entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
These 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this duration even
when the PLL is disabled).
F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
G. Normal operation resumes.
H. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4
OSCCLK cycles have elapsed.
Figure 7-9. HALT Wake-Up Using GPIOn
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7.9.7 External Interrupt Electrical Data and Timing
7.9.7.1 External Interrupt Timing Requirements
MIN(1)
1tc(SCO)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
(2)
tw(INT)
Pulse duration, INT input low/high
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.9.7.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
MIN
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.7.3 External Interrupt Timing Diagram
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-10. External Interrupt Timing
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7.10 Analog and Shared Peripherals
Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem. The
Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six Comparator + DAC
(10-bit) modules. The ADC Result Registers are accessible by CPUs and DMAs of the Master and Control
Subsystems. All other analog registers, such as the ADC Configuration and Comparator Registers, are
accessible by the C28x CPU only. The Digital Shared Peripherals include the IPC peripheral and the EPI. IPC is
accessible by both CPUs; EPI is accessible by both CPUs and both DMAs.
IPC is used for sending and receiving synchronization events between Master and Control subsystems to
coordinate execution of software running on both processors, or exchanging of data between the two
processors. EPI is used by this device to communicate with external memory and other devices.
For detailed information on the processor peripherals, see the Concerto F28M35x Technical Reference Manual.
7.10.1 Analog-to-Digital Converter
Figure 7-11 shows the internal structure of each of the two ADC peripherals that are present on Concerto. Each
ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion trigger, set the
sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read 16 result registers.
The 16 ADC channels can be used independently or in pairs, based on the assignments inside the
SAMPLEMODE register. Pairing up the channels allows two analog inputs to be sampled simultaneously—
thereby, increasing the overall conversion performance.
7.10.1.1 Sample Mode
Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital
conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For example, if
bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential mode. Both the
SOC4CTL and SOC5CTL registers can then be programmed to configure channels 4 and 5 to independently
perform analog-to-digital conversions with results being stored in the RESULT4 and RESULT5 registers.
"Independently" means that channel 4 may use a different SOC trigger, different analog input, and different
sampling window than the trigger, input, and window assigned to channel 5.
The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when corresponding bits
in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in the SAMPLEMODE
register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. The SOC4CTL register now contains
configuration parameters for both channel 4 and channel 5, and the SOC5CTL register is ignored. While channel
4 and channel 5 are still using dedicated analog inputs (now selected as pairs in the CHSEL field of SOC4CTL),
they both share the same SOC trigger and Sampling Window, with the results being stored in the RESULT4 and
RESULT5 registers.
The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each sample-
and-hold unit has its own mux for selecting analog inputs (see Figure 7-11). By programming the
SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels, 8 channel
pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous pairs).
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ADC_INT(8:1)
TRIGS(8:1)
INTSOCSEL1 REG
INTSOCSEL2 REG
ADCINT1
ADCINT2
SOC0CTL REG
SOC1CTL REG
SOC2CTL REG
SOC3CTL REG
SOC4CTL REG
SOC5CTL REG
SOC6CTL REG
SOC7CTL REG
SOC8CTL REG
SOC9CTL REG
SOC10CTL REG
SOC11CTL REG
SOC12CTL REG
SOC13CTL REG
SOC14CTL REG
SOC15CTL REG
INTSEL1N2 REG
INTSEL3N4 REG
INTSEL5N6 REG
INTSEL7N8 REG
INTFLG REG
INTFLGCLR REG
INTOVF REG
SOCFLG REG
SOCFRC REG
SOCOVF REG
ADC INTERUPT
CONTROL
SOCx TRIGGER
CONTROL
INTOVFCLR REG
SOCOVFCLR REG
SOCPRICTL REG
EOC(15:0)
SOC(15:0)
SAMPLEMODE REG
ADC CONTROL
4
ASEL
SHSEL
SOC
REGSEL
ANALOG BUS
ADC_INA0
0
1
2
3
4
5
6
7
N/C
ADC_INA2
ADC_INA3
ADC_INA4
RESULT0 REG
RESULT1 REG
RESULT2 REG
RESULT3 REG
RESULT4 REG
RESULT5 REG
RESULT6 REG
RESULT7 REG
RESULT8 REG
RESULT9 REG
RESULT10 REG
RESULT11 REG
RESULT12 REG
RESULT13 REG
RESULT14 REG
RESULT15 REG
N/C
ADC_INA6
ADC_INA7
S / H
A
A
STORE
RESULT
12-BIT ADC
CONVERTER
ADCCTL1 REG
VREFLOCONV
BSEL
S / H
B
0
1
2
3
4
5
6
7
B
ADC_INB0
N/C
N/C
ADCCTL1 REG
REFTRIM REG
OFFTRIM REG
REV REG
ADC_INB3
ADC_INB4
VREFLO 1
N/C
ADC_INB7
(1) CURRENTLY DEFAULT IS “NO CONNECT”, CHANGE ADDCCTL1 REGISTER TO CONNECT TO VREFLO
Figure 7-11. ADC
7.10.1.2 Start-of-Conversion Triggers
There are eight external SOC triggers that go to each of the two ADC modules (from the Control Subsystem). In
addition to the eight external SOC triggers, there are also two internal SOC triggers derived from EOC interrupts
inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1 and 2 are used to configure each
of the 16 ADC channels for internal or external SOC sources. If internal SOC is chosen for a given channel, the
INTSOCSEL1 and 2 registers also select whether the internal source is ADCINT1 or ADCINT2. If external SOC
is chosen for a given ADC channel, the TRIGSEL field of the corresponding SOCxCTL register selects which of
the eight external triggers is used for SOC in that channel. One analog-to-digital conversion can be performed at
a time by the 12-bit ADC. The analog-to-digital conversion priority is managed according to the state of the
PRICTL register.
7.10.1.3 Analog Inputs
Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group having a
dedicated mux and sample-and-hold unit (see Figure 7-11). Mux A selects one of six possible analog inputs
through AIO MUX. Mux B selects one of five possible analog inputs—four external inputs through AIO MUX, and
one from the internal VREFLO signal, which is currently tied to the Analog Ground. The Mux A and Mux B inputs
can be simultaneously or sequentially sampled by the two sample-and-hold units according to the sampling
window chosen in the SOCxCTL register for the corresponding channel.
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7.10.1.4 ADC Result Registers and EOC Interrupts
Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for ADC2).
The 16 ADCx channels can be programmed through the INTSELxNy registers to trigger up to eight ADCINT
interrupts per ADC module, when their results are ready to be read. The eight ADCINT interrupts from ADC1 and
the eight ADCINT interrupts from ADC2 are AND-ed together before propagating to both the Master Subsystem
and the Control Subsystem, announcing that the Result Registers are ready to be read by a CPU or DMA (see
Figure 8-3).
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7.10.1.5 ADC Electrical Data and Timing
7.10.1.5.1 ADC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
Bits
ADC clock
2
7
37.5
MHz
Sample Window
64 ADC clocks
ACCURACY
INL (Integral nonlinearity)
DNL (Differential nonlinearity)
–4
–1
4
LSB
LSB
1.5
Executing a single self-
recalibration
–20
–4
0
0
20
4
Offset error
LSB
Executing periodic self-
recalibration
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
VREFLO input current
–60
–40
–4
60
40
4
LSB
LSB
LSB
LSB
µA
–4
4
–100
100
VREFHI input current
µA
ANALOG INPUT
Analog input voltage with internal reference
Analog input voltage with external reference
VREFLO input voltage
0
VREFLO
VSSA
3.3
VREFHI
0.66
V
V
V
VREFHI input voltage
2.64
VDDA
V
Input capacitance
5
pF
μA
Input leakage current
±2
ADDITIONAL
ADC SNR
65
62
dB
dB
ADC SINAD
ADC THD (50 kHz)
–65
10.1
66
dB
ENOB (SNR)
Bits
dB
SFDR
7.10.1.5.2 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
32tc(HCO)
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
cycles
7.10.1.5.3 ADCSOCAO or ADCSOCBO Timing Diagram
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-12. ADCSOCAO or ADCSOCBO Timing
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7.10.2 Comparator + DAC Units
Figure 7-13 shows the internal structure of the six analog Comparator + DAC units present in Concerto devices.
Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of the A input is
greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs and two B inputs
come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10-bit digital-to-analog units
that are present in each comparator DAC. The 10-bit value for each DAC unit is programmed in the respective
DACVAL register. Another comparator register, COMPCTL, can be programmed to select the source of the B
input, to enable or disable the comparator circuit, to invert comparator output, to synchronize comparator output
to C28x SYSCLK, and to select the qualification period (number of clock cycles). All six output signals from the
six comparators can be routed out to the device pins through GPIO_MUX2 pin mux.
AIO_MUX1
GPIO_MUX2
COMPA(1)
COMPOUT(1)
COMP1
DAC1
N/C
4
4
COMP2
COMPCTL REG
COMPSOURCE
COMPDACE
COMPINV
QUALSEL
SYNCSEL
1
0
COMPA(2)
COMPB(2)
+
0
1
COMPOUT(2)
10
COMP2
_
1
0
SYNC / QUAL
VDDA
VSSA
10-BIT
DAC2
V
C28SYSCLK
COMPSTS
COMPSTS REG
V = ( DACVAL * ( VDDA-VSSA ) ) / 1023
DACVAL(8:0)
DACVAL REG
COMP = 0 WHEN VOLTAGE A < VOLTAGE B
COMP = 1 WHEN VOLTAGE A > VOLTAGE B
COMPA(3)
COMPOUT(3)
COMP3
DAC3
N/C
8
AIO_MUX2
COMPA(4)
COMPOUT(4)
COMPOUT(5)
COMPOUT(6)
COMP4
COMP5
COMP6
DAC4
DAC5
DAC6
N/C
4
COMPA(5)
COMPB(5)
10
COMPA(6)
N/C
Figure 7-13. Comparator + DAC Units
7.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
7.10.2.1.1 Electrical Characteristics of the Comparator/DAC
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
Comparator response time to GPIO
Input Offset
VSSA – VDDA
V
30
±5
35
ns
mV
mV
Input Hysteresis(1)
DAC
DAC Output Range
VSSA – VDDA
V
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over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNITS
DAC resolution
DAC settling time
DAC Gain
10
bits
See Figure 7-14
–1.5%
10
DAC Offset
Monotonic
INL
mV
Yes
±3
LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback
resistance between the output of the comparator and the noninverting input of the comparator.
1100
1000
900
800
700
600
500
400
300
200
100
0
0
50
100
150
200
250
300
350
400
450
500
DAC Step Size (Codes)
DAC Accuracy
15 Codes
7 Codes
3 Codes
1 Code
Figure 7-14. DAC Settling Time
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7.10.3 Interprocessor Communications
Figure 7-15 shows the internal structure of the IPC peripheral used to synchronize program execution and
exchange of data between the Cortex-M3 and the C28x CPU. IPC can be used by itself when synchronizing
program execution or it can be used in conjunction with Message RAMs when coordinating data transfers
between processors. In either case, the operation of the IPC is the same. There are two independent sides to
the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master).
The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC IPC
typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET, MTOCIPCFLG/
MTOCIPCSTS 1, and MTOCIPCACK. Each of the 32 bits of these registers represents 32 independent channels
through which the Cortex-M3 CPU can send up to 32 events to the C28x CPU through software handshaking.
Additionally, the first 4 bits of the MTOCIPC registers are supplemented with interrupts. To send an event
through channel 2 from Cortex-M3 to C28x, for example, the Cortex-M3 and C28x CPUs use bit 2 of the
MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers. The handshake starts with the Cortex-
M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is ‘0’. Next, the Cortex-M3 writes a ‘1’ into bit 2
of the MTOCIPCSET register to start the handshake. In the mean time, the C28x is continually polling the
MTOCIPCSTS register while waiting for the message. As soon as the Cortex-M3 writes ‘1’ to bit 2 of the
MTOCIPCSET register, bit 2 of MTOCIPCFLG/MTOCIPCSTS also turns ‘1’, thus announcing the event to the
C28x. As soon as the C28x CPU reads a ‘1’ from the MTOCIPCSTS register, the C28x CPU should
acknowledge by writing a ‘1’ to bit 2 of the MTOCIPCACK register, which in turn, clears bit 2 of the
MTOCIPCFLG/MTOCIPCSTS register, enabling the Cortex-M3 to send another message. Because the first four
channels (bits 0, 1, 2, 3) are backed up by interrupts, both processors in the above example can use IPC
interrupt 2 instead of polling to increase performance.
A similar handshake is also used when sending data (not just event) from the Master Subsystem to the Control
Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the Cortex-M3
should first load the MTOC Message RAM with a block of data that is to be made available to the C28x. In the
second additional step, the C28x should read the data before setting a bit in the MTOCIPCACK register. This
way, no data gets lost during multiple data transfers through a given block of the message RAM.
The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM IPC
typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET,
CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC IPC
communication above.
1
Physically, MTOCIPCFLG/MTOCIPCSTS is one register, but it is referred to as the MTOCIPCFLG register
when the Cortex-M3 CPU reads it, and as the MTOCIPCSTS register when the C28x CPU reads it.
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CTOM
IPC
INTRS
STS(3:0)
M3
NVIC
INT
CPU
(3:0)
WRDATA
(31:0)
RDDATA
(31:0)
SET(31:0)
FLG(31:0)
STS(31:0)
ACK(31:0)
M3 SYSTEM BUS
M3
32 MTOC IPC CHANNELS
3
4
ACK
STS
FLG
SET
MTOCIPCSET REG
MTOC IPC
CTOMIPCSACK REG
SYNC HANDSHAKE
FOR ONE OF 32
. . .
SET REG 31
FLG REG 31
31
0
1
2
C28
MTOC CHANNELS
. . .
. . .
0
0
STS REG
ACK REG
MTOC MSG RAM
PHYSICALLY THIS IS ONE REGISTER
PHYSICALLY THIS IS ONE REGISTER
WITH TWO DIFFERENT NAMES – FLG
FOR THE C28 AND STS FOR THE M3
MTOCIPCFLG REG
MTOCIPCSTS REG
CTOMIPCSTS REG
CTOMIPCSFLG REG
WITH TWO DIFFERENT NAMES – FLG
FOR THE M3 AND STS FOR THE C28
. . .
31
0
0
0
ACK REG
STS REG
CTOM IPC
CTOM MSG RAM
. . .
. . .
FLG REG 31
SET REG 31
SYNC HANDSHAKE
FOR ONE OF 32
MTOC CHANNELS
M3
1
2
MTOCIPCACK REG
CTOMIPCSET REG
SET
FLG
STS
ACK
3
4
C28
32 CTOM IPC CHANNELS
C28 CPU BUS
RDDATA
(31:0)
ACK(31:0)
STS(31:0)
FLG(31:0)
SET(31:0)
WRDATA
(31:0)
MTOC
IPC
STS(3:0)
INTRS
C28x
CPU
PIE
INT
(3:0)
Figure 7-15. IPC
7.10.4 External Peripheral Interface
The EPI provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is accessible
from both the Master Subsystem and the Control Subsystem. EPI has several modes of operation to enable
glueless connectivity to most types of external devices. Some EPI modes of operation conform to standard
microprocessor address/data bus protocols, while others are tailored to support a variety of fast custom
interfaces, such as those communicating with field-programmable gate arrays (FPGAs) and complex
programmable logic devices (CPLDs).
The EPI peripheral can be accessed by the Cortex-M3 CPU, the Cortex-M3 DMA, the C28x CPU, and the C28x
DMA over the high-performance AHB bus. The Cortex-M3 CPU and the µDMA drive AHB bus cycles directly
through the Cortex-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex-M3 Bus Matrix, but not
directly. Before entering the Cortex-M3 Bus Matrix, the native C28x CPU and DMA bus cycles are first converted
to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass through the Frequency Gasket to
reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus Matrix, the Cortex-M3 bus cycles may
have to compete with C28x bus cycles for access to the AHB bus on the way to the EPI peripheral. See Figure
7-16 to see how EPI interfaces to the Concerto Master Subsystem, the Concerto Control Subsystem, Resets,
Clocks, and Interrupts.
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Note
The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration between
the Cortex-M3 and C28x bus cycles is fixed-priority with Cortex-M3 having higher priority than C28x, or the C28x
having the option to own the Bus Matrix for a fixed period of time (window)—effectively stalling all Cortex-M3
accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is the Memory Protection
Register, which enables assignments of chip-select spaces to Cortex-M3 or C28x EPI accesses (or both). The
assignments of chip-select spaces prevent a bus cycle (from any processor) that does not own a given chip-
select space, from getting through to EPI. The Real-time Window registers are the only EPI-related registers that
are configurable by the C28x. The Memory Protection Register is configurable only by the Cortex-M3 CPU, as
are all configuration registers inside the EPI peripheral. Figure 7-16 shows the EPI registers and how they relate
to individual blocks within the EPI.
Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the
General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode chosen
through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO; therefore, in
most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes full. Read cycles can
be handled in two different ways: blocking read cycles and nonblocking read cycles. Blocking read cycles are
implemented when the content of a Read Data Register is 0. Blocking reads stall the CPU or DMA until the bus
transaction completes. Nonblocking read cycles are triggered when a non-zero value is written into a Read Data
Register. A non-zero value being written into a Read Data register triggers EPI to autonomously perform multiple
data reads in the background (without involving CPU or DMA) according to values stored inside the Read
Address Register and the Read Size Register. The incoming data is then temporarily stored in the Non-Blocking
Read (NBR) FIFO until an EPI interrupt is generated to prompt the CPU or DMA to read the FIFO without risk of
stalling. Furthermore, EPI has actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-
pong operation of nonblocking reads. In a ping-pong operation, while the previously fetched data is being read
by the CPU or DMA from one end of the NBR FIFO, the next set of data words is simultaneously being
deposited into the other end of the NBR FIFO.
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EPI
42 PINS
EPI MUX
GENERAL-PURPOSE INTERFACE
SDRAM INTERFACE
SDRAMCFGREG
HOST BUS INTERFACE
GPCONFIGREG
GPCONFIG2REG
HB-8CONFIGREG
HB-16CONFIGREG
HB-16CONFIG2REG
16-BIT MODE
EPI CONFIG REG
EPI STATUS REG
GPIO_MUX1
HB-8CONFIG2REG
8-BIT MODE
EPI RD SIZE0 REG
EPI RD ADDR0 REG
EPI RD DATA0 REG
EPI INTERRUPT
4X32 WR FIFO
8X32 NBR FIFO
READ FIFO ALIAS 1
READ FIFO ALIAS 2
READ FIFO ALIAS 3
READ FIFO ALIAS 4
READ FIFO ALIAS 5
READ FIFO ALIAS 6
READ FIFO ALIAS 7
INT MASK REG
MASK INT STAT REG
RAW INT STAT REG
ERR INT STAT/CLR
WR FIFO CNT REG
READ FIFO CNT REG
READ FIFO REG
EPI NONBLOCKING
ACCESS REGISTERS
FIFO LEVEL SEL REG
EPI RD SIZE0 REG
EPI RD ADDR0 REG
EPI RD DATA1 REG
INTERRUPT
SOURCES
FIFO READ
NON-FIFO READ
(BLOCKING)
EPI CLK
EPI RST
(NONBLOCKING)
WRITE
BAUD RATE CONTROL
AHB BUS INTERFACE
EPI ADDRMAPREG
EPI BAUD REG
M3SSCLK
M3SYSRST
AHB BUS
APB BUS
MEMORY PROTECTION LOGIC ASSIGNS CS
SPACES TO C28 ONLY, M3 ONLY, OR BOTH
EPI REQ
MEMPROT REG
RTWEPIREG REG
RTWEPICNTR REG
RTWEPIWD REG
CEPISTATUS REG
M3
M3 CLOCKS
RESETS
M3
NVIC
EPI
CPU
M3 BUS
MATRIX
uDMA
CHAN 20
CHAN 22
VECT# 69
REAL-TIME WINDOW MODE
ALLOWS UNINTERRUPTED ACCESS
TO EPI FROM C28 CPU/DMA, WHILE
STALLING M3 CPU/DMA CYCLES
FREQ
INT12/INTx.6
EPI
GASKET
MEM32
TO AHB
BUS
MEM32 TO AHB BUS BRIDGE
C28
C28
CPU
THE M3 FREQUENCY GASKET REDUCES AHB
BUS ACCESS FREQUENCY FOR C28 CPU/DMA
CYCLES BY FACTOR OF 2 OR FACTOR OF 4
PIE
CONVERTS C28 CPU/DMA BUS
CYCLES TO M3 AHB BUS CYCLES
DMA
BRIDGE
Figure 7-16. EPI
EPI can directly interrupt the Cortex-M3 CPU, the Cortex-M3 uDMA, and the C28x CPU (but not the C28x DMA)
through the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move data to and from
EPI. There are four EPI Interrupt registers that control various facets of interrupt generation, clearing, and
masking. The EPI Interrupt can trigger µDMA to perform reads and writes through DMA Channels 20 and 22. If a
CPU is the intended recipient, the Cortex-M3 CPU is interrupted by NVIC vector 69, and the C28x CPU is
interrupted through the INT12/INTx6 vector to the PIE.
During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be
remapped to different addresses according to values stored in the EPI Address Map Register in conjunction with
the most significant bit of the incoming address.
The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the Host Bus
Mode (including 8-bit and 16-bit versions).
7.10.4.1 EPI General-Purpose Mode
The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones communicating with
FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower Host Bus interfaces, which
have more relaxed timings that are compatible with established protocols like ones used to communicate with
8051 devices. Support of bus cycle framing and precisely controlled clocking are the additional features of the
General-Purpose Mode that differentiate the General-Purpose Mode from the 8-bit and 16-bit Host Bus Modes.
Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The slave
device responding to the bus cycles may use this signal to recognize related words of data and to speed up their
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transfers. The frame lengths are programmable and may vary from 1 to 30 clocks, depending on the clocking
mode used.
Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus cycles
can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled through the Baud
Rate Control block. This output clock can be gated or free-running. A gated approach uses a setup-time model in
which the EPI clock controls when bus transactions are starting and stopping. A free-running EPI clock requires
another method for determining when data is live, such as the frame pin or RD/WR strobes.
These and numerous other aspects of the General-Purpose Mode are controlled through the General-Purpose
Configuration Register and the General-Purpose Configuration2 Register. The clocking for the General-Purpose
Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block.
See Figure 7-17 for a snapshot of the General-Purpose Mode registers, modes, and features. For more detailed
maps of the General-Purpose Mode, see Table 7-3.
EPI CONFIG REG
GP CONFIG REG
MODE = GEN PURP
ASIZE = 3
ASIZE = 2
ASIZE = 1
ASIZE = 0
DSIZE = 0
DSIZE = 1
DSIZE = 2
DSIZE = 3
ADDRESS
RANGE
DATA
SIZE
FRAME
SIGNAL
READY
SIGNAL
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A18
A0 – A18
8
8
YES
YES
YES
NO
FRMPIN = 0
RDYEN = 1
RDYEN = 0
A0 – A19
A0 – A19
8
8
NO
NO
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A10
A0 – A10
16
16
YES
YES
YES
NO
FRMPIN = 0
RDYEN = 1
RDYEN = 0
A0 – A11
A0 – A11
16
16
NO
NO
YES
NO
FRMPIN = 1
RDYEN = 1
RDYEN = 0
A0 – A2
A0 – A2
24
24
YES
YES
YES
NO
FRMPIN = 0
RDYEN = 1
RDYEN = 0
A0 – A3
A0 – A3
24
24
NO
NO
YES
NO
FRMPIN = X
RDYEN = X
N/A
32
NO
NO
Figure 7-17. EPI General-Purpose Modes
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Table 7-3. EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
GENERAL-
PURPOSE
SIGNAL
GENERAL-
PURPOSE
SIGNAL
GENERAL-
PURPOSE
SIGNAL
GENERAL-
PURPOSE
SIGNAL
ACCESSIBLE BY ACCESSIBLE BY
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
Cortex-M3
C28x
(D8, A20)
(D16, A12)
(D24, A4)
(D30, NO ADDR)
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D0
D1
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
D2
D2
D2
D3
D3
D3
D4
D4
D4
D5
D5
D5
D6
D6
D6
D7
D7
D7
D8
D8
D8
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S28
EPI0S29
EPI0S30
EPI0S31
A8
A9
A0
A1
D16
D17
D18
D19
D29
D21
D22
D23
A0
D16
D17
D18
D19
D29
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A10
A2
A11
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PG7_GPIO47
PJ3_GPIO59
A12
A4
A13
A5
A14
A6
A15
A7
A16
A8
A17
A9
A1
A18
A10
A11/RDY
WR
RD
A2
A19/RDY
WR
A3/RDY
WR
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
RD
RD
FRAME
CLK
FRAME
CLK
FRAME
CLK
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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7.10.4.2 EPI SDRAM Mode
The EPI SDRAM Mode combines high performance, low cost, and low pin use to access up to 512 megabits
(Mb) of external memory. Main features of the EPI SDRAM interface are:
•
•
•
•
•
Supports x16 (single data rate) SDRAM
Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb]
Includes automatic refresh and access to all banks, rows
Includes Sleep/STANDBY Mode to keep contents active with minimal power drain
Multiplexed address/data interface for reduced pin count
See Figure 7-18 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more detailed
maps of the SDRAM Mode, see Table 7-4.
EPI CONFIG REG
MODE = SDRAM
SDRAM CFG REG
SDRAM
SIZE
DATA
SIZE
SIZE = 0
SIZE = 1
SIZE = 2
SIZE = 3
64 MBit
128 MBit
256 MBit
512 MBit
16
16
16
16
Figure 7-18. EPI SDRAM Mode
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Table 7-4. EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
COLUMN/ROW
ADDRESS
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
DATA
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
A0
D0
D1
PH3_GPIO51
A1
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7
A8
D8
A9
D9
A10
A11
A12
BA0
BA1
D10
D11
D12
D13
D14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S28
EPI0S29
EPI0S30
EPI0S31
D15
DQML
DQMH
CAS
RAS
WE
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PG7_GPIO47
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
CS
CKE
CLK
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
x
x
x
x
x
x
x
x
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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7.10.4.3 EPI Host Bus Mode
There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16). Section
7.10.4.3.1 discusses the EPI 8-Bit Host Bus Mode. Section 7.10.4.3.2 discusses the EPI 16-Bit Host Bus Mode.
7.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence, more pins
are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in order to
accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration Register. Within
the HB-8 Mode, two additional registers are used to select address/data muxing, chip selects, and other options.
These registers are the HB-8 Configuration Register and the HB-8 Configuration2 Register. See Figure 7-19 for
a snapshot of HB-8 registers, modes, and features.
EPI CONFIG REG
HP8 CONFIG REG
HB8 CONFIG2 REG
MODE = HB-8
ADDRESS
RANGE
DATA
SIZE
READY
SIGNAL
MODE = MUXED
CSCFG = ALE
CSCFG = 1 CS
A0 – A27
A0 – A27
A0 – A26
A0 – A25
8
8
8
8
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
MODE = NOMUX
CSCFG = ALE
CSCFG = 1 CS
A0 – A19
A0 – A19
A0 – A18
A0 – A17
8
8
8
8
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
MODE = FIFO
CSCFG = 2 CS
N/A
N/A
8
8
NO
NO
CSCFG = ALE + 2 CS
Figure 7-19. EPI 8-Bit Host Bus Mode
7.10.4.3.1.1 HB-8 Muxed Address/Data Mode
The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed
Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed Mode is
selected with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the
HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the
address until the data phase); RD and WR data strobes; and 1–4 CS (Chip Select) signals to enable one of four
external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2
Register. For more detailed maps of the HB-8 Muxed Mode, see Table 7-5.
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Table 7-5. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Muxed (EPIHB16CFG/MODE = 0x0)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
EPI0S8
EPI0S9
A8
A8
A8
A8
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A9
A9
A9
A9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
ALE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
CS0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
CS1
CS0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CS0
CS1
ALE
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
PJ3_GPIO59
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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7.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed
Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode is selected
with the MODE field of the HB-8 Configuration Register. In addition to data and address signals, the HB-8 Non-
Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the
address until the data phase); RD and WR data strobes; and 1–4 CS (Chip Select) signals to enable one of four
external peripherals. The ALE and CS options are chosen with the CSCFG field of the HB-8 Configuration2
Register. For more detailed maps of the HB-8 Non-Muxed Mode, see Table 7-6.
Table 7-6. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
EPI0S8
EPI0S9
A0
A1
A0
A1
A0
A1
A0
A1
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A2
A2
A2
A2
A3
A3
A3
A3
A4
A4
A4
A4
A5
A5
A5
A5
A6
A6
A6
A6
A7
A7
A7
A7
A8
A8
A8
A8
A9
A9
A9
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ALE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CS0
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS1
CS0
A10
A11
A12
A13
A14
A15
A16
A17
CS0
CS1
ALE
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
PJ3_GPIO59
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
EPI0S31
EPI0S32
EPI0S33
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PC0_GPIO64
PC1_GPIO65
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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Table 7-6. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
7.10.4.3.1.3 HB-8 FIFO Mode
The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external FIFO
Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including
USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO Mode presents the data
side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the
FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA
accesses. For more detailed maps of the HB-8 FIFO Mode, see Table 7-7.
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-7. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH ONE
CHIP SELECT
(CSCFG = 0x1)
WITH TWO
CHIP SELECTS
(CSCFG = 0x2)
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
EPI0S25
EPI0S30
x
CS1
CS0
PE3_GPIO27
PD7_GPIO23
CS0
PJ6_GPIO62
EPI0S27
EPI0S26
EPI0S29
EPI0S28
FFULL
FEMPTY
WR
FFULL
FEMPTY
WR
PH7_GPIO55
PH6_GPIO54
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
RD
RD
EPI0S8
EPI0S9
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PF2_GPIO34
PG7_GPIO47
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S32
EPI0S31
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
PJ3_GPIO59
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
7.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence, more
pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order to
accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration Register.
Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte selects, chip
selects, and other options. These registers are the HB-16 Configuration Register and the
HB-16 Configuration2 Register. See Figure 7-20 for a snapshot of HB-16 registers, modes, and features.
EPI CONFIG REG
HP16 CONFIG REG
HB16 CONFIG2 REG
MODE = HB-16
MODE = MUXED
ADDRESS
RANGE
DATA
SIZE
READY
SIGNAL
BSEL = YES
CSCFG = ALE
CSCFG = 1 CS
A0 – A25
A0 – A25
A0 – A24
A0 – A23
16
16
16
16
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
BSEL = NO
CSCFG = ALE
CSCFG = 1 CS
A0 – A27
A0 – A27
A0 – A26
A0 – A25
16
16
16
16
NO
NO
NO
NO
CSCFG = 2 CS
CSCFG = ALE + 2 CS
MODE = NOMUX
BSEL = YES
CSCFG = ALE
CSCFG = 1 CS
A0 – A9
A0 – A9
A0 – A8
A0 – A7
A0 – A16
A0 – A14
16
16
16
16
16
16
NO
YES
YES
YES
YES
YES
CSCFG = 2 CS
CSCFG = ALE + 2 CS
CSCFG = 3 CS
CSCFG = 4 CS
BSEL = NO
CSCFG = ALE
CSCFG = 1 CS
A0 – A11
A0 – A11
A0 – A10
A0 – A9
16
16
16
16
16
16
NO
YES
YES
YES
YES
YES
CSCFG = 2 CS
CSCFG = ALE + 2 CS
CSCFG = 3 CS
A0 – A18
A0 – A16
CSCFG = 4 CS
MODE = FIFO
BSEL = DON’T CARE
CSCFG = 2 CS
N/A
N/A
16
16
NO
NO
CSCFG = ALE + 2 CS
Figure 7-20. EPI 16-Bit Host Bus Mode
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
7.10.4.3.2.1 HB-16 Muxed Address/Data Mode
The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the Muxed
Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed Mode is
selected with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the
HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the
address until the data phase); RD and WR data strobes; 1–4 CS (Chip Select) signals to enable one of four
external peripherals; and two BSEL (Byte Select) signals to accommodate byte accesses to lower or upper half
of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE
and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For more detailed maps
of the HB-16 Muxed Mode without Byte Selects, see Table 7-8. For more detailed maps of the HB-16 Muxed
Mode with Byte Selects, see Table 7-9.
Table 7-8. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
AD0
AD1
AD0
AD1
AD0
AD1
AD0
AD1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
AD2
AD2
AD2
AD2
AD3
AD3
AD3
AD3
AD4
AD4
AD4
AD4
AD5
AD5
AD5
AD5
AD6
AD6
AD6
AD6
AD7
AD7
AD7
AD7
AD8
AD8
AD8
AD8
AD9
AD9
AD9
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
ALE
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
CS0
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
CS1
CS0
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CS0
CS1
ALE
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
PJ3_GPIO59
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
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F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-8. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
Table 7-9. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
AD0
AD1
AD0
AD1
AD0
AD1
AD0
AD1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
AD2
AD2
AD2
AD2
AD3
AD3
AD3
AD3
AD4
AD4
AD4
AD4
AD5
AD5
AD5
AD5
AD6
AD6
AD6
AD6
AD7
AD7
AD7
AD7
AD8
AD8
AD8
AD8
AD9
AD9
AD9
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
AD10
AD11
AD12
AD13
AD14
AD15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
A16
A17
A18
A19
A20
A21
A22
A16
A17
A18
A19
A20
A21
A22
A16
A17
A18
A19
A20
A21
A22
A16
A17
A18
A19
A20
A21
A22
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PJ3_GPIO59
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F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-9. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY ACCESSIBLE BY
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
Cortex-M3
C28x
MUXING CHOICES FOR EPI)
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A23
A24
A23
A24
A23
A24
A23
BSEL0
BSEL1
CS0
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
A25
A25
BSEL0
BSEL1
CS1
BSEL0
BSEL1
ALE
BSEL0
BSEL1
CS0
CS1
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
EPI0S28
WR
RD
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PJ5_GPIO61
PJ4_GPIO60
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF2_GPIO34
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC0_GPIO64
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
7.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-Muxed
Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode is selected
with the MODE field of the HB-16 Configuration Register. In addition to data and address signals, the HB-16
Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture address and hold the
address until the data phase); RD and WR data strobes; 1–4 CS (Chip Select) signals to enable one of four
external peripherals; and two BSEL (Byte Select) signals to accommodate byte accesses to lower or upper half
of 16-bit data. The Byte Selects are chosen with the BSEL field of the HB-16 Configuration Register. The ALE
and CS options are chosen with the CSCFG field of the HB-16 Configuration2 Register. For Non-Muxed bus
cycles, most of the CSCFG modes also support a RDY signal. The RDY input to EPI is used by an external
peripheral to extend bus cycles when the peripheral needs more time to complete reading or writing of data.
While most EPI modes use up to 32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 10
additional pins to extend the address reach and the number of CS signals. For detailed maps of HB-16 Non-
Muxed Modes without Byte Selects, see Table 7-10 and Table 7-11. For detailed maps of HB-16 Non-Muxed
Modes with Byte Selects, see Table 7-12 and Table 7-13.
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F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-10. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS LATCH
ENABLE
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
(CSCFG = 0x0)
EPI0S0
D0
D1
D0
D1
D0
D1
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A0
A1
A0
A1
A0
A1
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A2
A2
A2
A2
A3
A3
A3
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
PJ3_GPIO59
A4
A4
A4
A4
A5
A5
A5
A5
A6
A6
A6
A6
A7
A7
A7
A7
A8
A8
A8
A8
A9
A9
A9
A9
A10
A11
ALE
A10
A11
CS0
A10
CS1
CS0
CS0
CS1
ALE
PJ6_GPIO62
EPI0S29
EPI0S28
EPI0S32
WR
RD
x
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
RDY
EPI0S31
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-11. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)
EPI SIGNAL
FUNCTION
EPI SIGNAL
FUNCTION
EPI PORT NAME
DEVICE PIN
EPI PORT NAME
DEVICE PIN
WITH
THREE
CHIP SELECTS
(CSCFG = 0x7)
WITH
FOUR
CHIP SELECTS
(CSCFG = 0x5)
ACCESSIBLE
BY
Cortex-M3
ACCESSIBLE
BY
ACCESSIBLE
BY
Cortex-M3
ACCESSIBLE
BY
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
C28x
C28x
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D10
D11
D12
D13
D14
D15
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S27
EPI0S35
EPI0S40
EPI0S41
EPI0S30
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
EPI0S30
EPI0S27
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A2
A2
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PH7_GPIO55
PE5_GPIO29
PG5_GPIO45
PG6_GPIO46
PD7_GPIO23
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PD7_GPIO23
PH7_GPIO55
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS0
CS2
CS3
A10
A11
A12
A13
A14
A15
A16
CS0
CS1
CS2
CS3
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PJ6_GPIO62
PC1_GPIO65
PJ6_GPIO62
PC1_GPIO65
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
EPI0S31
EPI0S35
x
x
PG7_GPIO47
PE5_GPIO29
EPI0S31
x
PG7_GPIO47
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-12. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS LATCH
ENABLE
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
(CSCFG = 0x0)
EPI0S0
D0
D1
D0
D1
D0
D1
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S30
A0
A1
A0
A1
A0
A1
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A2
A2
A2
A2
A3
A3
A3
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PE3_GPIO27
PH6_GPIO54
PH7_GPIO55
PD7_GPIO23
PJ3_GPIO59
A4
A4
A4
A4
A5
A5
A5
A5
A6
A6
A6
A6
A7
A7
A7
A7
A8
A8
A8
BSEL0
BSEL1
CS0
CS1
ALE
A9
A9
BSEL0
BSEL1
CS1
CS0
BSEL0
BSEL1
ALE
BSEL0
BSEL1
CS0
PJ6_GPIO62
EPI0S29
EPI0S28
EPI0S32
WR
RD
x
WR
RD
WR
RD
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
RDY
EPI0S31
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF3_GPIO35
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC1_GPIO65
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 7-13. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)
EPI SIGNAL
FUNCTION
EPI SIGNAL
FUNCTION
EPI PORT NAME
DEVICE PIN
EPI PORT NAME
DEVICE PIN
WITH
THREE
CHIP SELECTS
(CSCFG = 0x7)
WITH
FOUR
CHIP SELECTS
(CSCFG = 0x5)
ACCESSIBLE
BY
Cortex-M3
ACCESSIBLE
BY
ACCESSIBLE
BY
Cortex-M3
ACCESSIBLE
BY
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
C28x
C28x
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S0
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
D12
D13
D14
D15
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D10
D11
D12
D13
D14
D15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S40
EPI0S41
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S27
EPI0S35
EPI0S25
EPI0S26
EPI0S30
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S40
EPI0S41
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S25
EPI0S26
EPI0S30
EPI0S27
EPI0S34
EPI0S33
A0
A1
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
A2
A2
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PG5_GPIO45
PG6_GPIO46
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PH7_GPIO55
PE5_GPIO29
PE3_GPIO27
PH6_GPIO54
PD7_GPIO23
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A3
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PG5_GPIO45
PG6_GPIO46
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PE3_GPIO27
PH6_GPIO54
PD7_GPIO23
PH7_GPIO55
PE4_GPIO28
PF3_GPIO35
PJ3_GPIO59
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A11
A12
A13
A14
A15
A16
BSEL0
BSEL1
CS0
CS2
CS3
A10
A11
A12
A13
A14
BSEL0
BSEL1
CS0
CS1
CS2
CS3
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
PJ6_GPIO62
PC1_GPIO65
PJ6_GPIO62
PC1_GPIO65
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
EPI0S29
EPI0S28
EPI0S32
WR
RD
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RDY
RDY
EPI0S31
EPI0S35
x
x
PG7_GPIO47
PE5_GPIO29
EPI0S31
x
PG7_GPIO47
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7.10.4.3.2.3 HB-16 FIFO Mode
The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external FIFO
Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication devices (including
USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO Mode presents the data
side of the normal Host-Bus interface, but is paced by FIFO control signals. It is important to consider that the
FIFO Full/Empty control inputs may stall the EPI interface and can potentially block other CPU or DMA
accesses. For detailed maps of the HB-16 FIFO Mode, see Table 7-14.
Table 7-14. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH ONE
CHIP SELECT
(CSCFG = 0x1)
WITH TWO
CHIP SELECTS
(CSCFG = 0x2)
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0
D0
D1
D0
D1
PH3_GPIO51
PH2_GPIO50
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
PH0_GPIO48
PH1_GPIO49
PE0_GPIO24
PE1_GPIO25
PH4_GPIO52
PH5_GPIO53
PF4_GPIO36
PG0_GPIO40
PG1_GPIO41
PF5_GPIO37
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
EPI0S25
EPI0S30
x
CS1
CS0
PE3_GPIO27
CS0
PD7_GPIO23
PJ6_GPIO62
EPI0S27
EPI0S26
EPI0S29
EPI0S28
EPI0S32
FFULL
FEMPTY
WR
FFULL
FEMPTY
WR
PH7_GPIO55
PH6_GPIO54
PD6_GPIO22
PD5_GPIO21
PF2_GPIO34
PJ5_GPIO61
PJ4_GPIO60
PC0_GPIO64
RD
RD
x
x
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PD4_GPIO20
PD2_GPIO18
PD3_GPIO19
PB5_GPIO13
PB4_GPIO12
PE2_GPIO26
PJ3_GPIO59
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Table 7-14. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH ONE
CHIP SELECT
(CSCFG = 0x1)
WITH TWO
CHIP SELECTS
(CSCFG = 0x2)
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S31
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PG7_GPIO47
PF3_GPIO35
EPI0S33
EPI0S34
EPI0S35
EPI0S36
EPI0S37
EPI0S38
EPI0S39
EPI0S40
EPI0S41
PC1_GPIO65
PE4_GPIO28
PE5_GPIO29
PB7_GPIO15
PB6_GPIO14
PF6_GPIO38
PG2_GPIO42
PG5_GPIO45
PG6_GPIO46
PC3_GPIO67
PC2_GPIO66
PE4_GPIO28
7.10.4.4 EPI Electrical Data and Timing
The signal names in Figure 7-21 through Figure 7-29 are defined in Table 7-15.
Table 7-15. Signals in Figure 7-21 Through Figure
7-29
SIGNAL
DESCRIPTION
AD
Address/Data
Address
ALE
Address output
Address latch enable
Bank Address/Data
Byte select
BAD
BSEL0, BSEL1
CAS
Column address strobe
Clock enable
CKE
CLK, Clock
Command
CS
Clock
Command signal
Chip select
Data
Data signals
DQMH
DQML
Frame
iRDY
Data mask high
Data mask low
Frame signal
Ready input
Muxed Address/Data Multiplexed Address/Data
RAS
Row address strobe
Read enable/Output enable
Write enable
RD/ OE
WE, WR
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7.10.4.4.1 EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted) (see Figure 7-21 , Figure 7-22 , and Figure 7-23 )
NO.
E1
PARAMETER
Cycle time, SDRAM clock
MIN
20
10
10
–5
–5
–5
10
0
MAX UNIT
tc(CK)
ns
ns
ns
E2
tw(CKH)
tw(CKL)
td(CK-OV)
td(CK-OIV)
td(CK-OZ)
tsu(AD-CK)
th(CK-AD)
tPU
Pulse duration, SDRAM clock high
Pulse duration, SDRAM clock low
Delay time, clock to output valid
Delay time, clock to output invalid
Delay time, clock to output high-impedance
Setup time, input before clock
Hold time, input after clock
Power-up time
E3
E4
5
5
5
ns
ns
ns
ns
ns
µs
ns
ns
ns
E5
E6
E7
E8
E9
100
20
66
40
E10
E11
E12
tpc
Precharge time, all banks
Autorefresh
trf
tMRD
Program mode register
7.10.4.4.2 EPI SDRAM Timing Diagrams
CLK
(EPI0S31)
E1
E2
E3
CKE
(EPI0S30)
NOP
NOP
NOP
NOP
NOP
Command
(EPI0S[29:28,19:18])
NOP
PRE
AREF
PRE
AREF
LOAD
NOP
AREF
Active
DQMH, DQML
(EPI0S[17:16])
AD11, AD[9:0]
(EPI0S[11,9:0]
Code
Code
Row
Row
Bank
All Banks
AD10
(EPI0S[10])
Single Bank
BAD[1:0]
(EPI0S[14:13])
AD [15,12]
(EPI0S [15,12])
E9
E10
E11
E12
A. If CS is high at clock high time, all applied commands are NOP.
B. The Mode register may be loaded before the autorefresh cycles if desired.
C. JEDEC and PC100 specify three clocks.
D. Outputs are ensured High-Z after command is issued.
Figure 7-21. SDRAM Initialization and Load Mode Register Timing
CLK
(EPI0S31)
CKE
(EPI0S30)
E4
E5
E6
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
E7
DQMH, DQML
(EPI0S [17:16])
E8
AD [15:0]
(EPI0S [15:0])
Row
Column
Read
Data 0
Data 1
...
Data n
Burst
Term
Activate
NOP
NOP
NOP
AD [15:0] driven in
AD [15:0] driven out
AD [15:0] driven out
Figure 7-22. SDRAM Read Timing
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CLK
(EPI0S31)
CKE
(EPI0S30)
E4
E5
E6
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Column-1
Write
Row
Activate
Data 0
Data 1
...
Data n
Burst
Term
NOP
NOP
AD [15:0] driven out
AD [15:0] driven out
Figure 7-23. SDRAM Write Timing
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7.10.4.4.3 EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended Operating
Conditions (Unless Otherwise Noted)
(see Figure 7-24 , Figure 7-25 , Figure 7-26 , and Figure 7-27 )
NO.
PARAMETER
MIN
TYP
MAX
UNIT
ns
E16 td(WR-WDATAV)
E17 td(WRIV-DATA)
E18 td(CS-OV)
E19 td(CS-OIV)
E20 tw(STL)
Delay time, WR to write data valid
Delay time, WR invalid to data
5
2
–5
–5
2
EPI clocks
ns
Delay time, CS to output valid
5
5
Delay time, CS to output invalid
Pulse duration, WR/ RD strobe low
Pulse duration, ALE high
ns
EPI clocks
EPI clocks
EPI clocks
EPI clocks
EPI clocks
E22 tw(ALEH)
E23 tw(CSL)
1
Pulse duration, CS low
4
2
1
E24 td(ALE-ST)
E25 td(ALE-ADHZ)
Delay time, ALE rising to WR/ RD strobe falling
Delay time, ALE falling to Address/Data high-impedance
7.10.4.4.4 EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1)
(see Figure 7-24 and Figure 7-26 )
NO.
MIN
MAX UNIT
E14
E15
tsu(RDATA)
th(RDATA)
Setup time, read data
Hold time, read data
10
0
ns
ns
(1) Setup time for FEMPTY and FFULL signals from clock edge is 2 system clocks (MIN).
7.10.4.4.5 EPI Host-Bus 8/16 Mode Timing Diagrams
E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
WR
(EPI0S29)
E18
E24
E19
E20
RD/OE
(EPI0S28)
BSEL0/BSEL1(A)
Address
E15
E14
Data
Data
A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 7-24. Host-Bus 8/16 Mode Read Timing
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E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
E18
E19
E20
WR
(EPI0S29)
E24
RD/OE
(EPI0S28)
BSEL0/BSEL1(A)
Address
E16
E17
Data
Data
A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 7-25. Host-Bus 8/16 Mode Write Timing
E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
WR
(EPI0S29)
E19
E18
E24
E20
RD/OE
(EPI0S28)
E25
BSEL0/BSEL1(A)
E14
E15
Muxed
Address/Data
Address
Data
A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 7-26. Host-Bus 8/16 Mode Muxed Read Timing
E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
E18
E19
E20
WR
(EPI0S29)
E24
RD/OE
(EPI0S28)
BSEL0/BSEL1(A)
E16
Muxed
Address/Data
Address
Data
A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 7-27. Host-Bus 8/16 Mode Muxed Write Timing
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7.10.4.4.6 EPI General-Purpose Interface Switching Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) (see Figure 7-28 )
NO.
E26
E27
E30
E31
E33
PARAMETER
MIN
10
MAX UNIT
tw(CKH)
tw(CKL)
td(CK-OV)
td(CK-OIV)
tc(CK)
Pulse duration, general-purpose clock high
Pulse duration, general-purpose clock low
Delay time, falling clock edge to output valid
Delay time, falling clock edge to output invalid
Cycle time, general-purpose clock
ns
ns
10
–5
5
5
ns
ns
ns
–5
20
7.10.4.4.7 EPI General-Purpose Interface Timing Requirements (see Figure 7-28 and Figure 7-29 )
NO.
E28
E29
E32
MIN
MAX UNIT
tsu(IN-CK)
th(CK-IN)
Setup time, input signal before rising clock edge
10
0
ns
ns
ns
Hold time, input signal after rising clock edge
tsu(IRDY-CK)
Setup time, iRDY assertion or deassertion before falling clock edge
10
7.10.4.4.8 EPI General-Purpose Interface Timing Diagrams
E33
E27
Clock
(EPI0S31)
E26
E30
Frame
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
Data
E30
E31
E28
Data
Data
E29
Read
Write
A. This figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the RD2CYC bit is clear, and the WR2CYC bit is
clear.
Figure 7-28. General-Purpose Mode Read and Write Timing
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Clock
(EPI0S31)
Frame
(EPI0S30)
E32
E32
RD
(EPI0S29)
iRDY
(EPI0S27)
Address
Data
Figure 7-29. General-Purpose Mode iRDY Timing
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7.11 Master Subsystem Peripherals
Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the Cortex-
M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB peripherals include
EMAC, two I2Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG, and a µCRC module
(Cyclic Redundancy Check). The Cortex-M3 CPU/µDMA also have access to Analog (Result Registers only) and
Shared peripherals (see Section 7.10).
For detailed information on the processor peripherals, see the Concerto F28M35x Technical Reference Manual.
7.11.1 Synchronous Serial Interface
This device has four SSI modules. Each SSI has a Master or Slave interface for synchronous serial
communication with peripheral devices that have Texas Instruments™ SSIs, SPI, or Freescale™ serial format.
The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO
memories, allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. The
SSI also supports µDMA transfers. The transmit and receive FIFOs can be programmed as destination/source
addresses in the µDMA module. An µDMA operation is enabled by setting the appropriate bit or bits in the
SSIDMACTL register.
Figure 7-30 shows the SSI peripheral.
7.11.1.1 Bit Rate Generation
The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock. Bit
rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The
serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided by an even prescale
value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register. The clock
is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI
Control 0 (SSICR0) register. The frequency of the output clock SSIClk is defined by:
SSIClk = SysClk / [CPSDVSR * (1 + SCR)]
Note
For master mode, the system clock must be at least four times faster than SSIClk, with the restriction
that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must be at least 12 times
faster than SSIClk.
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SSIxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
SSI
DMA
CLOCK
CONTROL
PRESCALER
DMAxREQ
M3
uDMA
SSICPSR REG
SSIDMACTL REG
TX/RX FIFO
ACCESS
SSIxCLK
SSITX
SSIRX
SSICLK
SSIFSS
TX FIFO
CONTROL
(8 ´ 16)
PIN
PIN
PIN
PIN
/ STATUS
SSICR0 REG
SSICR1 REG
SSISR REG
TX
RX
TRANSMIT/
RECEIVE
LOGIC
FIFO
STAT
FIFO
STAT
SSIDR REG
RX FIFO
(8 ´ 16)
SSIIM REG
SSIPCELLID0 REG
SSIPCELLID1 REG
SSIPCELLID2 REG
SSIPCELLID3 REG
SSIPERIPHLD0 REG
SSIPERIPHLD1REG
SSIPERIPHLD2 REG
SSIPERIPHLD3 REG
SSIPERIPHLD4 REG
SSIPERIPHLD5 REG
SSIPERIPHLD6 REG
SSIPERIPHLD7 REG
SSIMIS REG
SSIRIS REG
SSIICR REG
INTxREQ
INTR CONTROL
IDENTIFICATION REGISTERS
Figure 7-30. SSI
7.11.1.2 Transmit FIFO
The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data to the
FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read out by the
transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO before
serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is empty
and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit FIFO. If less
than eight values have been written to the transmit FIFO since the SSI module clock was enabled using the SSI
bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure that valid data is in the FIFO
as needed. The SSI can be configured to generate an interrupt or an µDMA request when the FIFO is empty.
7.11.1.3 Receive FIFO
The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the serial
interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR
register. When configured as a master or slave, serial data received through the SSIRx pin is registered before
parallel loading into the attached slave or master receive FIFO, respectively.
7.11.1.4 Interrupts
The SSI can generate interrupts when the following conditions are observed:
•
•
•
•
Transmit FIFO service (when the transmit FIFO is half full or less)
Receive FIFO service (when the receive FIFO is half full or more)
Receive FIFO time-out
Receive FIFO overrun
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•
End of transmission
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI generates a
single interrupt request to the controller regardless of the number of active interrupts. Each of the four individual
maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt Mask (SSIIM) register.
Setting the appropriate mask bit enables the interrupt.
The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt service
routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow interrupts
have been separated from the status interrupts so that data can be read or written in response to the FIFO
trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status
(SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers.
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is
currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is emptied
before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the Receive FIFO
Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the SSI Interrupt Clear
(SSIICR) register. The interrupt should not be cleared so late that the ISR returns before the interrupt is actually
cleared, or the ISR may be reactivated unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This interrupt
can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In addition, because
transmitted data and received data complete at exactly the same time, the interrupt can also indicate that read
data is ready immediately, without waiting for the receive FIFO time-out period to complete.
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7.11.1.5 Frame Formats
Each data frame is between 4 bits and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. The following basic frame types can be selected:
•
•
Texas Instruments Synchronous Serial
Freescale SPI
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the
programmed frequency only during active transmission or reception of data. The idle state of SSIClk is used to
provide a receive time-out indication that occurs when the receive FIFO still contains data after a time-out period.
7.11.2 Universal Asynchronous Receiver/Transmitter
This device has five UART modules. The CPU accesses data, control, and status information. The UART also
supports µDMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel conversions.
Each of the five UART modules is similar in functionality to a 16C550 UART, but is not register-compatible.
The UART is configured for transmit and receive through the TXE bit and the RXE bit, respectively, of the UART
Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control registers are
programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled
during a TX or RX operation, the current transaction is completed before the UART stops.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared
transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL
register.
Figure 7-31 shows the UART peripheral.
7.11.2.1 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number
formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional
baud-rate divider allows the UART to generate all the standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6-bit
fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud rate
divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD, and
BRDF is the fractional part, separated by a decimal place).
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in UARTCTL is
clear) or 8 (if HSE is set).
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be
calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64, and adding
0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as Baud8 and
Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is divided by 8 or 16
to generate the transmit clock, and is used for error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD registers
form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is
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performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for
the changes to take effect.
UARTxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
UARTCLKENBx
REGISTER
ACCESS
UART
UARTxCLK
DMA
BAUDE RATE
GENERATOR
CONTROL
DMAxREQ
M3
uDMA
UARTIBRD REG
UARTFBRD REG
UARTDMACTL REG
TX/RX FIFO
ACCESS
XCLK
TRANSMITTER
UxTX
TX FIFO
CONTROL/
STATUS
(WITH SIR TRANSMIT
ENCODER)
(8 ´ 16)
PIN
UARTCR0 REG
UARTCR1 REG
UARTSR REG
TX
RX
FIFO
STAT
FIFO
STAT
UARTDR REG
RECEIVER
UxRX
RX FIFO
(WITH SIR RECEIVE
DECODER)
(8 ´ 16)
PIN
UARTIFLS REG
UARTPCELLID0
UARTPCELLID1
UARTPCELLID2
UARTPCELLID3
UARTPERIPHLD0
UARTPERIPHLD1
UARTPERIPHLD2
UARTPERIPHLD3
UARTPERIPHLD4
UARTPERIPHLD5
UARTPERIPHLD6
UARTPERIPHLD7
UARTIM REG
UARTMIS REG
UARTRIS REG
UARTICR REG
INTxREQ
IDENTIFICATION REGISTERS
INTR CONTROL
Figure 7-31. UART
7.11.2.2 Transmit and Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control
logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit,
and the stop bits according to the programmed configuration in the control registers.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has
been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their
status accompanies the data that is written to the receive FIFO.
7.11.2.3 Data Transmission and Reception
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra 4 bits per
character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled,
a data frame starts transmitting with the parameters indicated in the UARTLCRH register. Data continues to be
transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register is
asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is nonempty) and remains asserted
while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last
character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is
busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit has been
received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or the fourth
cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL).
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The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE clear) or
the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is detected,
successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, 1 bit period later),
according to the programmed length of the data characters and value of the HSE bit in UARTCTL. The parity bit
is then checked if parity mode is enabled. Data length and parity are defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred. When a
full word is received, the data is stored in the receive FIFO along with any error bits associated with that word.
7.11.2.4 Interrupts
The UART can generate interrupts when the following conditions are observed:
•
•
•
•
•
•
Overrun Error
Break Error
Parity Error
Framing Error
Receive Time-out
Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT bit in
UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
•
All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only
generate a single interrupt request to the controller at any given time. Software can service multiple interrupt
events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register.
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM)
register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status is always visible
through the UART Raw Interrupt Status (UARTRIS) register.
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the
corresponding bit in the UART Interrupt Clear (UARTICR) register.
The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is received
over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty through
reading all the data (or by reading the holding register), or when a "1" is written to the corresponding bit in the
UARTICR register.
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7.11.3 Cortex-M3 Inter-Integrated Circuit
This device has two Cortex-M3 I2C peripherals. The Cortex-M3 I2C bus provides bidirectional data transfer
through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C
devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The
I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture.
The microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with
other I2C devices on the bus.
The two Cortex-M3 I2C modules include the following features:
•
Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
Four I2C modes
•
– Master transmit
– Master receive
– Slave transmit
– Slave receive
•
•
Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when a START or
STOP condition is detected
•
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
Figure 7-32 shows the Cortex-M3 I2C peripheral.
7.11.3.1 Functional Overview
Each I2C module comprises both master and slave functions. For proper operation, the SDA and SCL pins must
be configured as open-drain signals.
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional serial
data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is 9 bits long, consisting of eight data bits and a single acknowledge bit. The
number of bytes per transfer (defined as the time between a valid START and STOP condition) is unrestricted,
but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a
receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
7.11.3.2 Available Speed Modes
The I2C bus can run in either standard mode (100 Kbps) or fast mode (400 Kbps). The selected mode should
match the speed of the other I2C devices on the bus.
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I2CxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
I2CxCLK
2
I C (M3)
2
I C
I2CSCL_M
I2CSDA_M
I2CMSA REG
I2CxSCL
2
I C MASTER CORE
CONTROL
I2CMCS REG
I2CMTPR REG
I2CMCR REG
PIN
I2CSOAR REG
I2CSCSR REG
2
I C I/O
SELECT
I2CMDR REG
I2CMIMR REG
I2CMRISREG
I2CMMIS REG
I2CMICR REG
I2CSDR REG
I2CSIMR REG
I2CSRISREG
I2CSMIS REG
I2CSICR REG
I2CSCL_S
I2CSDA_S
I2CxSDA
2
I C SLAVE CORE
PIN
Figure 7-32. I2C (Cortex-M3)
7.11.3.3 I2C Electrical Data and Timing
7.11.3.3.1 I2C Timing
TEST CONDITIONS
MIN
MAX
400
UNIT
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
fSCL
SCL clock frequency
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
Low level output voltage
3 mA sink current
0.4
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tLOW Low period of SCL clock
tHIGH High period of SCL clock
1.3
μs
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
lI
–10
10
μA
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7.11.4 Cortex-M3 Controller Area Network
Note
The CAN module uses the popular IP known as D_CAN. This document uses the names “CAN” and
“D_CAN” interchangeably to reference this peripheral.
This device has two Cortex-M3 CAN peripherals. CAN is a serial communications protocol that efficiently
supports distributed real-time control with a high level of security. The CAN module supports bit rates up to
1 Mbit/s and is compliant with the ISO11898-1 (CAN 2.0B) protocol specification.
CAN implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
CAN protocol version 2.0 part A, B
Bit rates up to 1 Mbit/s
Multiple clock sources
32 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM parity check mechanism
Two interrupt lines
Global power down and wakeup support
Figure 7-33 shows the Cortex-M3 CAN peripheral.
7.11.4.1 Functional Overview
CAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN protocol
specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbit/s. Additional transceiver hardware
is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message objects and
identifier masks are stored in the Message RAM. All functions concerning the handling of messages are
implemented in the message handler. Those functions are: acceptance filtering, the transfer of messages
between the CAN Core and the Message RAM, and the handling of transmission requests.
The register set of the CAN is accessible directly by the CPU through the module interface. These registers are
used to control/configure the CAN Core and the message handler, and to access the message RAM.
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CANxIRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
CANxCLK
CAN (M3)
CANxTX
MODULE INTERFACE
PIN
MESSAGE
RAM
REGISTERS AND MESSAGE
OBJECT ACCESS (IFX)
CAN
CORE
32 MESSAGE
OBJECTS
CANxRX
MESSAGE RAM
INTERFACE
MESSAGE HANDLER
PIN
Figure 7-33. CAN (Cortex-M3)
7.11.5 Cortex-M3 Universal Serial Bus Controller
This device has one Cortex-M3 USB controller. The USB controller operates as a full-speed or low-speed
function controller during point-to-point communications with the USB Host, Device, or OTG functions. The
controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirty-two
endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and one endpoint
for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support multiple packet
queuing. DMA access to the FIFO allows minimal interference from system software. Software-controlled
connect and disconnect allow flexibility during USB device start-up. The controller complies with the Session
Request Protocol (SRP) and Host Negotiation Protocol (HNP) of the OTG standard.
The USB controller includes the following features:
•
•
•
•
•
Complies with USB-IF certification standards
USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation
Integrated PHY
Four transfer types: Control, Interrupt, Bulk, and Isochronous
32 endpoints:
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte isochronous
packet size
•
•
•
VBUS droop and valid ID detection and interrupt
Efficient transfers using DMA:
– Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints
– Channel requests asserted when FIFO contains required amount of data
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•
Electrical specifications are compliant with the USB Specification Rev. 2.0 (full-speed and low-speed support)
and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of the USB system
are integrated within the Concerto microcontroller and are specific to its design.
Figure 7-34 shows the USB peripheral.
7.11.5.1 Functional Description
The USB controller provides full OTG negotiation by supporting both the SRP and the HNP. The SRP allows
devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used after the initial
session request protocol has powered the bus and provides a method to determine which end of the cable will
act as the Host controller. When the device is connected to non-OTG peripherals or devices, the controller can
detect which cable end was used and provides a register to indicate if the controller should act as the Host
controller or the Device controller. This indication and the mode of operation are handled automatically by the
USB controller. This autodetection allows the system to use a single A/B connector instead of having both A and
B connectors in the system, and supports full OTG negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers. The
USB controller can be configured to act as either a dedicated Host or Device, in which case, the USB0VBUS and
USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a self-powered Device, a
GPIO input must be connected to VBUS and configured to generate an interrupt when the VBUS level drops.
This interrupt is used to disable the pullup resistor on the USB0DP signal.
Note
When the USB is used, the system clock frequency (SYSCLK) must be at least 20 MHz.
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
USBCLKENB
USBPLLCLK
REGISTER
ACCESS
USBMAC_IRQ
USB
CPU
ENDPOINT CONTROL
INTERFACE
EP REGISTER
DECODER
TRANSMIT
EP 0-31
CONTROL
USB0EPEN
USB0PFLT
RECEIVE
COMMON
REGS
PIN
PIN
CYCLE
HOST TRANSACTION
SCHEDULER
COMBINE
CONTROL
ENDPOINTS
PHY
FIFO DECODER
USB0VBUS
FIFO RAM CONTROLLER
PACKET
UTM
(5V TOLERANT)
INTERRUPT
CONTROL
ENCODE / DECODE
SYNCHRONIZATION
PIN
PIN
PIN
PIN
TX
TX
BUFF
BUFF
USB0ID
PACKET ENCODE
PACKET DECODE
CRC GEN/CHECK
DATA SYNC
(5V TOLERANT)
RX
RX
DMAxREQ
USB0DM
USB0DP
HNP / SRP
TIMERS
BUFF
BUFF
M3
uDMA
TX/RX FIFO
ACCESS
CYCLE CONTROL
USBMAC REQ
Figure 7-34. USB
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7.11.6 Cortex-M3 Ethernet Media Access Controller
The Cortex-M3 EMAC conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX
standards. This device has one Ethernet Media Access Controller.
The EMAC module has the following features:
•
Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant
Multiple operational modes
•
– Full- and half-duplex 100-Mbps
– Full- and half-duplex 10-Mbps
– Power-saving and power-down modes
Highly configurable:
•
– Programmable MAC address
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
•
•
IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
Efficient transfers using the Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO
Figure 7-35 shows the EMAC peripheral.
7.11.6.1 Functional Overview
The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the
Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the device. These
layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the Ethernet Controller
through the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC
layer also provides the interface to the external PHY layer through an internal Media Independent Interface (MII).
The PHY layer communicates with the Ethernet bus.
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EMAC_IRQ
INTR
M3
M3 CLOCKS
M3 NVIC
CPU
M3SSCLK
EMACCLKENB
REGISTER
ACCESS
EMAC
MIITXCLK
DMAxREQ
M3
RECEIVE
INTR CONTROL
PIN
uDMA
CONTROL
MIITXEN
TX/RX FIFO
ACCESS
MACRIS REG
MACIACK REG
MACIM REG
PIN
MACRCTL REG
MACNP REG
MIITXD(3:0)
TRANSMIT
FIFO
PIN
EMACRX_REQ
EMACTX_REQ
MIICRS
DATA ACCESS
PIN
MIICOL
MACDDATA REG
PIN
TIMER SUPPORT
MACTS REG
MIIRXCLK
TRANSMIT
CONTROL
PIN
RECEIVE
FIFO
MIIRXDV
MACTCTL REG
MACTHR REG
MACTR REG
PIN
MIIRXER
PIN
MIIRXD(3:0)
MII CONTROL
PIN
INDIVIDUAL
ADDRESS
MACMCTL REG
MACMDV REG
MACMTXD REG
MACMRXD REG
MADIX REG
MDIO_CK
MACIA0 REG
MACIA1 REG
PIN
MDIO
MDIO_D
MACMAR REG
PIN
Figure 7-35. EMAC
7.11.6.2 MII Signals
The individual EMAC and Management Data Input/Output (MDIO) signals for the MII interface are summarized
in Table 7-16.
Table 7-16. EMAC and MDIO Signals for MII Interface
SIGNAL
TYPE(1)
DESCRIPTION
Transmit clock. The transmit clock is a continuous clock that provides the timing reference
for transmit operations. The MIITXD and MIITXEN signals are tied to this clock. The clock is
generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps
operation.
MIITXCK
MIITXER
I
O
O
This pin is always driven low from the MAC controller on the device.
Transmit data. The transmit data pins are a collection of four data signals comprising 4 bits
of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MIITXCLK
and are valid only when MIITXEN is asserted.
MIITXD[3-0]
MIITXEN
Transmit enable. The transmit enable signal indicates that the MIITXD pins are generating
nibble data for use by the PHY. MIITXEN is driven synchronously to MIITXCLK.
O
I
Collision detected. In half-duplex operation, the MIICOL pin is asserted by the PHY when
the PHY detects a collision on the network. The MIICOL pin remains asserted while the
collision condition persists. This signal is not necessarily synchronous to MIITXCLK or
MIIRXCLK. In full-duplex operation, the MIICOL pin is used for hardware transmit flow
control. Asserting the MIICOL pin will stop packet transmissions; packets in the process of
being transmitted when MIICOL is asserted will complete transmission. The MIICOL pin
should be held low if hardware transmit flow control is not used.
MIICOL
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Table 7-16. EMAC and MDIO Signals for MII Interface (continued)
SIGNAL
TYPE(1)
DESCRIPTION
Carrier sense. In half-duplex operation, the MIICRS pin is asserted by the PHY when the
network is not idle in either transmit or receive. The pin is deasserted when both transmit
and receive are idle. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK.
In full-duplex operation, the MIICRS pin should be held low.
MIICRS
I
Receive clock. The receive clock is a continuous clock that provides the timing reference for
receive operations. The MIIRXD, MIIRXDV, and MIIRXER signals are tied to this clock. The
clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-
Mbps operation.
MIIRXCK
I
Receive data. The receive data pins are a collection of four data signals comprising 4 bits of
data. MRDX0 is the least-significant bit. The signals are synchronized by MIIRXCLK and are
valid only when MIIRXDV is asserted.
MIIRXD[3-0]
MIIRXDV
I
I
I
Receive data valid. The receive data valid signal indicates that the MIIRXD pins are
generating nibble data for use by the EMAC. MIIRXDV is driven synchronously to
MIIRXCLK.
Receive error. The receive error signal is asserted for one or more MIIRXCLK periods to
indicate that an error was detected in the received frame. The MIIRXER signal being
asserted is meaningful only during data reception when MIIRXDV is active.
MIIRXER
Management data clock. The MDIO data clock is sourced by the MDIO module on the
system. MDIO_CK is used to synchronize MDIO data access operations done on the MDIO
pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO Control
Register (CONTROL).
MDIO_CK
MDIO_D
O
Management data input output. The MDIO data pin drives PHY management data into and
out of the PHY by way of an access frame that consists of start-of-frame, read/write
indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an
output for all but the data bit cycles, at which time the pin is an input for read operations.
I/O
(1) I = Input, O = Output, I/O = Input/Output
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7.11.6.3 EMAC Electrical Data and Timing
7.11.6.3.1 Timing Requirements for MIITXCK (see Figure 7-36 )
100 Mbps
MIN
10 Mbps
MIN
NO.
UNIT
MAX
MAX
Cycle time, MIITXCK (25 MHz)
40
40
1
tc(TXCK)
ns
Cycle time, MIITXCK (2.5 MHz)
Pulse duration, MIITXCK high
Pulse duration, MIITXCK low
400
196
196
400
204
204
2
3
tw(TXCKH)
tw(TXCKL)
16
16
24
24
ns
ns
7.11.6.3.2 MIITXCK Timing Diagrams
1
2
3
MIITXCK
Figure 7-36. 100/10Mb/s MII Transmit Clock Timing
7.11.6.3.3 Timing Requirements for MIIRXCK (see Figure 7-37 )
100 Mbps
MIN
10 Mbps
MIN
NO.
UNIT
MAX
MAX
Cycle time, MIIRXCK (25 MHz)
Cycle time, MIIRXCK (2.5 MHz)
Pulse duration, MIIRXCK high
Pulse duration, MIIRXCK low
40
40
1
tc(RXCK)
ns
400
196
196
400
204
204
2
3
tw(RXCKH)
tw(RXCKL)
16
16
24
24
ns
ns
7.11.6.3.4 MIIRXCK Timing Diagram
1
2
3
MIIRXCK
Figure 7-37. 100/10Mb/s MII Receive Clock Timing
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7.11.6.3.5 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for EMAC
MII Transmit (see Figure 7-38 )
NO.
PARAMETER
MIN
MAX UNIT
25 ns
1
td(TXCKH-MTXDV)
Delay time, MIITXCK high to transmit selected signals valid
5
7.11.6.3.6 EMAC MII Transmit Timing Diagram
1
MIITXCK
MIITXD[3:0],
MIITXEN
Figure 7-38. 100/10Mb/s MII Transmit Timing
7.11.6.3.7 Timing Requirements for EMAC MII Receive (see Figure 7-39 )
NO.
MIN
NOM
MAX UNIT
1
2
tsu(MRXDV-RXCKH) Setup time, receive selected signals valid before MIIRXCK high
th(RXCKH-MRXDV) Hold time, receive selected signals valid after MIIRXCK high
8
7
ns
ns
7.11.6.3.8 EMAC MII Receive Timing Diagram
1
2
MIIRXCK
MIIRXD[3:0],
MIIRXDV,
MIIRXER (Inputs)
Figure 7-39. 100/10Mb/s MII Receive Timing
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7.11.6.4 MDIO Electrical Data and Timing
7.11.6.4.1 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for
MDIO_CK (see Figure 7-40 )
NO.
1
PARAMETER
MIN
400
196
196
MAX
400
204
204
UNIT
ns
tc(MCK)
Cycle time, MDIO_CK (2.5 MHz)
Pulse duration, MDIO_CK high
Pulse duration, MDIO_CK low
2
tw(MCKH)
tw(MCKL)
ns
3
ns
7.11.6.4.2 MDIO_CK Timing Diagram
1
2
3
MDIO_CK
Figure 7-40. MII Serial Management Timing
7.11.6.4.3 Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) for MDIO
as Output (see Figure 7-41 )
NO.
PARAMETER
MIN
MAX
UNIT
1
td(MCKH-MDV)
Delay time, MDIO_CK high to MDIO_D valid
5
25
ns
7.11.6.4.4 MDIO as Output Timing Diagram
1
MDIO_CK
MDIO_D
Figure 7-41. MII Serial Management Timing – MDIO as Output
7.11.6.4.5 Timing Requirements for MDIO as Input (see Figure 7-42 )
NO.
4
MIN
NOM
20
MAX UNIT
tsu(MDV-MCKH)
th(MCKH-MDV)
Setup time, MDIO_D valid before MDIO_CK high
Hold time, MDIO_D valid after MDIO_CK high
ns
ns
5
7
7.11.6.4.6 MDIO as Input Timing Diagram
MDIO_CK
4
5
MDIO_D
(Input)
Figure 7-42. MII Serial Management Timing – MDIO as Input
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7.12 Control Subsystem Peripherals
Control Subsystem peripherals are accessible from the C28x CPU through the C28x Memory Bus, and from the
C28x DMA through the C28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port
Peripherals (SCI, SPI, McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP, eCAP). Additionally,
the C28x CPU/DMA also have access to the EPI, and to Analog and Shared peripherals (see Section 7.10).
For detailed information on the processor peripherals, see the Concerto F28M35x Technical Reference Manual.
7.12.1 High-Resolution PWM and Enhanced PWM Modules
There are nine PWM modules in the Concerto device. Eight of these are of the HRPWM type with high-
resolution control on both A and B signal outputs, and one is of the ePWM type. The HRPWM modules have all
the features of the ePWM plus they offer significantly higher PWM resolution (time granularity on the order of
150 ps). Figure 7-43 shows the eight HRPWM modules (PWM 1–8) and one ePWM module (PWM 9).
The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of
GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output SYNCO1
comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering GPIO_MUX1. There are
two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from GPTRIP1–12 (from
GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR signal from the C28x
CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1), EQEPERR (from the eQEP
peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x CPU).
There are 9 SOCA PWM outputs and 9 SOCB PWM outputs—a pair from each PWM module. The 9 SOCA
outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1 as a single
SOCAO signal. The 9 SOCB outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering
GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from PWM1–PWM9 also go to the Analog
Subsystem, where they can be selected to become conversion triggers to ADC modules.
The nine PWM modules also drive two other sets of outputs which can interrupt the C28x CPU through the C28x
PIE block. These are nine EPWMINT interrupts and nine EPWMTZINT trip-zone interrupts. See Figure 7-44 for
the internal structure of the HRPWM and ePWM modules. The green-colored blocks are common to both ePWM
and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution blocks.
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SOCA (9:1)
SOCB(9:1)
PULSE STRETCH
SOCAO
32 HSPCLK CYCLES
PULSE STRETCH
SOCBO
32 HSPCLK CYCLES
GPTRIP6
EPWM (9:1) A
SYNCI
GPTRIP1
GPTRIP2
GPTRIP3
GPTRIP4
GPTRIP5
GPTRIP6
GPTRIP7
GPTRIP8
GPTRIP9
GPTRIP10
GPTRIP11
GPTRIP12
‘0’
TRIPIN1
TRIPIN2
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
TRIPIN13
TRIPIN14
TRIPIN15
PWM
1
PWM
2
PWM
3
SYNCO
GPTRIP1
GPTRIP2
GPTRIP3
EQEPERR
CLOCKFAIL
EMUSTOP
TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
PWM
4
PWM
5
PWM
6
PWM
7
PWM
8
PWM
9
ECCDBLERR
PIEERR
EPWM (9:1) B
EPWM
TBCLKSYNC
EPWM (9:1) TZINT
EPWM (9:1) INT
SYNCO
SYNCO1
PULSE STRETCH
8 HSPCLK CYCLES
CPCLKCR0 REG
EQEP(3:1)INT
ECAP(6:1)INT
EQEP1A
EQEP1S
EQEP1I
SYNCI
EQEP1B
EQEP 1
ECAP
1
ECAP
ECAP
GPTRIP7
GPTRIP8
GPTRIP9
GPTRIP10
GPTRIP11
GPTRIP12
ECAP1INP
SYNCO
2
3
ECAP2INP
ECAP3INP
ECAP4INP
ECAP5INP
ECAP6INP
EQEP2A
EQEP2B
EQEP2S
EQEP2I
EQEP 2
ECAP
ECAP
ECAP
EQEP3A
EQEP3B
EQEP3S
EQEP3I
4
5
6
ECAP
EQEP
EQEP3
ECAP(6:1)
LEGEND:
PWM
1-8
EPWM +
GPTRIP(1-12)
GPIO_MUX1
ECCDBLERR
PIEERR
EMUSTOP
EQEPERR
CLOCKFAIL
HiRES PWM
PWM
9
EPWM
ONLY
C28x
CPU
C28x
C28x LOCAL RAM
SHARED RAM
CLOCKS
Copyright © 2017, Texas Instruments Incorporated
Figure 7-43. PWM, eCAP, eQEP
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C28SYSCLK
TBCLKSYNC
TRIPIN(15:1)
(1)
SYNCO
DCAEVT1.SYNC
DCAEVT1.SOC
DCBEVT1.SOC
SYNCI
DCBEVT1.SYNC
TIME BASE
(TB)
PHS
PRD
DIGITAL
TBCLK
CTR=ZER
CTR=PRD
COMPARE
CTR=
(DC)
CMPB
TBCTR
(15:0)
CTR=ZER
TBCTR
(15:0)
HiRES
TBCLK
CTR=PRD
CTR_DIR
CONTROL
CMPA
CMPB
CAL
CNTRL
DCAEVT1.FORCE DCBEVT1.FORCE
DCAEVT2.FORCE DCBEVT2.FORCE
DCAEVT1.SYNC
DCBEVT1.SYNC
COUNTER
COMPARE
RED
FED
DCAEVT1.INTER DCBEVT1.INTER
DCAEVT2.INTER DCBEVT2.INTER
(CC)
CTR=ZER
CTR=PRD
CTR_DIR
EPWM_A
EPWM_B
ACTION
DEAD
BAND
PWM
TRIP
HiRES
PWM
QUALIFIER
CHOPPER
ZONE
CTR=CMPA
CTR=CMPB
(AQ)
(DB)
(PC)
(TZ)
(HRPWM)
SWFSYNC
SYNCI
CTR=ZER
CTR=PRD
C28SYSCLK
CTR=CMPA
CTR=CMPB
CTR=CMPC
CTR=CMPD
DCAEVT1.SOC
DCBEVT1.SOC
EVENT
SYNCI
TRIGGER
(ET)
EPWM_TZINT
EPWM_INT
EPWM_INT
SOCA
SOCB
TZ (6:1)
(1) SYNCO OUTPUTS FROM PWM MODULES 3,6 AND 9 ARE NOT CONNECTED, THUS THEY ARE NOT USEABLE.
Copyright © 2017, Texas Instruments Incorporated
Figure 7-44. Internal Structure of PWM
7.12.1.1 HRPWM Electrical Data and Timing
Section 7.12.1.1.1 shows the high-resolution PWM switching characteristics.
7.12.1.1.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
7.12.1.2 ePWM Electrical Data and Timing
Section 7.12.1.2.1 shows the PWM timing requirements and Section 7.12.1.2.2 shows the PWM switching
characteristics.
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7.12.1.2.1 ePWM Timing Requirements
MIN(1)
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
Asynchronous
Synchronous
tw(SYCIN)
Sync input pulse width
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.12.1.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SCO)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(PWM)tza
no pin load
25
20
ns
ns
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
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7.12.1.2.3 Trip-Zone Input Timing
7.12.1.2.3.1 Trip-Zone Input Timing Requirements
MIN(1)
1tc(SCO)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
SYSCLK
tw(TZ)
TZ(A)
td(TZ-PWM)HZ
PWM(B)
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-45. PWM Hi-Z Characteristics
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7.12.2 Enhanced Capture Module
There are six identical eCAP modules in Concerto devices: eCAP1, 2, 3, 4, 5, and 6. Each eCAP module
represents one complete capture channel. Its main function is to accurately capture the timings of external
events. One can also use eCAP modules for PWM, when they are not being used for input captures. This
secondary function is selected by flipping the CAP/APWM bit of the ECCTL2 Register. For PWM function, the
counter operates in count-up mode, providing a time base for asymmetrical pulse width (PWM) waveforms. The
CAP1 and CAP2 registers become the period and compare registers, respectively; while the CAP3 and CAP4
registers become the shadow registers of the main period and capture registers, respectively.
The left side of Figure 7-46 shows internal components associated with the capture block, and the right side
depicts the PWM block. The two blocks share a set of four registers that are used in both Capture and PWM
modes. Other components include the Counter block that uses the SYNCIN and SYNCOUT ports to synchronize
with other modules; and the Interrupt Trigger and Flag Control block that sends Capture, PWM, and Counter
events to the C28x PIE block through the ECAPxINT output. There are six ECAPxINT interrupts—one for each
eCAP module.
The eCAP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This
peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers.
7.12.2.1 eCAP Electrical Data and Timing
Section 7.12.2.1.1 shows the eCAP timing requirement and Section 7.12.2.1.2 shows the eCAP switching
characteristics.
7.12.2.1.1 eCAP Timing Requirement
MIN(1)
2tc(SCO)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.12.2.1.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
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EPWM1 OR
OTHER ECAP
PERIPHERALS
SYNCIN
SYNC IN
ECAPx
CTR_OVF
COUNTER
CTRPHS REG
TSCTR REG
SYNCOUT
SYNC OUT
RST
OTHER ECAP
PERIPHERALS
DELTA
MODE
CTR(31:0)
CAPTURE
MODE
PWM
MODE
LD1
LD2
LD3
LD4
POLARITY
CAP1/PERIOD REG
MASTER
SELECT
SUBSYSTEM
PRD(31:0)
C28CLKIN
POLARITY
SELECT
CAP2/COMP REG
CMP(31:0)
CAPTURE
EVENT
C28SYSCLK
QUALIFIER
POLARITY
SELECT
ECAPxENCLK
CAP3/PER SHDW
PWM
COMPARE
LOGIC
SYSTEM
CONTROL
REGISTERS
POLARITY
SELECT
CAP4/CMP SHDW
REGISTER
ACCESS
C28x
CPU
4
4
CTR=PER
EVENT
PRESCALE
CAPTURE
CONTROL
CEVT (4:1)
CTR=CMP
CTR_OVF
INTERRUPT TRIGGER
AND FLAG CONTROL
(CAPTURE EVENTS)
MODE
SELECT
ECAPx
PIN
ECCTL2 REG
ECAPxINT
C28x PIE
Copyright © 2017, Texas Instruments Incorporated
Figure 7-46. eCAP
7.12.3 Enhanced Quadrature Encoder Pulse Module
The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and
speed information from rotating machines used in high-performance motion and position-control systems. There
are three Type 0 eQEP modules in each Concerto device.
Each eQEP peripheral comprises five major functional blocks: Quadrature Capture Unit (QCAP), Position
Counter/Control Unit (PCCU), Quadrature Decoder (QDU), Unit Time Base for speed and frequency
measurement (UTIME), and Watchdog timer for detecting stalls (QWDOG). The C28x CPU controls and
communicates with these modules through a set of associated registers (see Figure 7-47). The eQEP
peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This peripheral clock
can be enabled or disabled by flipping a bit in one of the system control registers.
Each eQEP peripheral connects through the GPIO_MUX1 block to four device pins. Two of the four pins are
always inputs, while the other two can be inputs or outputs, depending on the operating mode. The PCCU block
of each eQEP also drives one interrupt to the C28x PIE. There is a total of three EQEPxINT interrupts—one from
each of the three eQEP modules.
7.12.3.1 eQEP Electrical Data and Timing
Section 7.12.3.1.1 shows the eQEP timing requirement and Section 7.12.3.1.2 shows the eQEP switching
characteristics.
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7.12.3.1.1 eQEP Timing Requirements
MIN(1)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
tw(QEPP)
QEP input period
2[1tc(SCO) + tw(IQSW)
]
Asynchronous(2)/synchronous
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous(2)/synchronous
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) Refer to the F28M35x Concerto™ MCUs Silicon Errata for limitations in the asynchronous mode.
7.12.3.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO)
cycles
Delay time, QEP input edge to position compare sync
output
td(PCS-OUT)QEP
6tc(SCO)
cycles
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MASTER
SUBSYSTEM
EQEPx
QCPRD REG
QCTMR REG
QCAPCTL REG
16
C28CLKIN
16
C28SYSCLK
QUADRATURE CAPTURE UNIT
( QCAP )
OCTMRLAT REG
QCPRDLAT REG
EQEPxENCLK
16
SYSTEM
CONTROL
REGISTERS
REGISTER
ACCESS
C28x
QUTMR REG
QUPRD REG
QWDTMR REG
QWDPRD REG
CPU
REGISTERS USED
32
16
BY MULTIPLE UNITS
QEPCTL REG
QEPSTS REG
QFLG REG
QDECCTL REG
16
UTOUT
UTIME
QWDOG
WDTOUT
EQEPxAIN
EQEPxA
/XCLK
PIN
QCLK
QDIR
EQEPxINT
EQEPxB
/XDIR
QI
QS
EQEPxBIN
POSITION COUNTER/CONTROL UNIT
( PCCU )
QUADRATURE
DECODER
PIN
PIN
PIN
QPOSLAT REG
QPOSSLAT REG
QPOSILAT REG
PHE
PCSOUT
( QDU )
EQEPxIIN
EQEPxIOUT
EQEPxIOE
16
EQEPxI
EQEPxS
32
32
16
QPOSCNT REG
QPOSINIT REG
QPOSMAX REG
QPOSCMP REG
QEINT REG
QFRC REG
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QCLR REG
QPOSCTL REG
Copyright © 2017, Texas Instruments Incorporated
Figure 7-47. eQEP
7.12.4 C28x Inter-Integrated Circuit Module
This device has one C28x I2C peripheral. The I2C provides an interface between a Concerto device and devices
compliant with the NXP® I2C-bus specification and user manual (UM10204) and connected by way of an I2C
bus. External components attached to this 2-wire serial bus can transmit 1-bit to 8-bit data to and receive 1-bit to
8-bit data from the device through the I2C module.
Note
A unit of data transmitted or received by the I2C module can have fewer than 8 bits; however, for
convenience, a unit of data is called a data byte in this section. The number of bits in a data byte is
selectable through the BC bits of the mode register, I2CMDR.
The I2C module has the following features:
•
Compliance with the NXP I2C-bus specification and user manual (UM10204):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit-and-receive and receive-and-transmit mode
– Data transfer rate of from 10 Kbps up to 400 Kbps (I2C Fast-mode rate)
One 4-word receive FIFO and one 4-word transmit FIFO
•
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•
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable or disable capability
Free data format mode
The I2C module does not support:
•
•
High-speed mode (Hs-mode)
CBUS-compatibility mode
Figure 7-48 shows the C28x I2C peripheral.
MASTER
2
I C (C28)
SUBSYSTEM
REGISTER
C28CLKIN
ACCESS CLK
C28SYSCLK
MASTER CLOCK
DIVIDER
I2CCLK
I2CCLK
I2CPSC REG
I2CA_ENCLK
I2CCLKH REG
I2CCLKL REG
CLOCK
PRESCALER
SYSTEM
CONTROL
REGISTERS
SLAVE CLOCK
I2CASCL
SYNCHRONIZER
MODE AND STATUS
REGISTERS
PIN
C28x
CPU
I2CFFTX REG
I2CMDR REG
I2CSTR REG
REGISTER
ACCESS
TX FIFO
I2CDXR REG
INTR
I2CXSR REG
I2CINT2A
I2CINT1A
I2COAR REG
I2CSAR REG
I2CCNT REG
C28x PIE
I2CASDA
PIN
I2CIER REG
I2CISRC REG
I2CRXR REG
INTERRUPT
CONTROL AND
ARBITRATION
RX FIFO
I2CDRR REG
TX/RX
LOGIC
I2CFFRX REG
Figure 7-48. I2C (C28x)
7.12.4.1 Functional Overview
Each device connected to an I2C Bus is recognized by a unique address. Each device can operate as either a
transmitter or a receiver, depending on the function of the device. A device connected to the I2C Bus can also be
considered as the master or the slave when performing data transfers. A master device is the device that
initiates a data transfer on the bus and generates the clock signals to permit that transfer. During this transfer,
any device addressed by this master is considered a slave. The I2C module supports the multi-master mode, in
which one or more devices capable of controlling an I2C Bus can be connected to the same I2C Bus.
For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL). These two
pins carry information between the C28x device and other devices connected to the I2C Bus. The SDA and SCL
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pins both are bidirectional. They each must be connected to a positive supply voltage using a pullup resistor.
When the bus is free, both pins are high. The driver of these two pins has an open-drain configuration to perform
the required wired-AND function. There are two major transfer techniques:
1. Standard Mode: Send exactly n data values, where n is a value you program in an I2C module register.
2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new START
condition.
The I2C module consists of the following primary blocks:
•
•
A serial interface: one data pin (SDA) and one clock pin (SCL)
Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the SDA pin
and the CPU
•
•
Control and status registers
A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.
7.12.4.2 Clock Generation
The device clock generator receives a signal from an external clock source and produces an I2C input clock with
a programmed frequency. The I2C input clock is equivalent to the CPU clock and is then divided twice more
inside the I2C module to produce the module clock and the master clock.
7.12.4.3 I2C Electrical Data and Timing
7.12.4.3.1 I2C Timing
TEST CONDITIONS
MIN
MAX
400
UNIT
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
fSCL
SCL clock frequency
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
Low level output voltage
3 mA sink current
0.4
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tLOW Low period of SCL clock
tHIGH High period of SCL clock
1.3
μs
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
lI
–10
10
μA
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7.12.5 C28x Serial Communications Interface
This device has one SCI peripheral. SCI is a two-wire asynchronous serial port, commonly known as a UART.
The SCI module supports digital communications between the CPU and other asynchronous peripherals that
use the standard non-return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
Data-word format
•
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
•
•
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is
read as zeros. Writing to the upper byte has no effect.
•
•
Auto baud-detect hardware logic
16-level transmit and receive FIFO
Figure 7-49 shows the C28x SCI peripheral.
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MASTER
SCI (C28)
SUBSYSTEM
SCICTL2 REG
SCICTL1A REG
TX INTERRUPT LOGIC
SCIFFTXA REG
AUTO-BAUD DETECT LOGIC
SCEFFCT REG
C28CLKIN
C28SYSCLK
REGISTER
ACCESS
TX FIFO
SCITXBUF REG
TX DELAY
SCIA_ENCLK
/1
/2
SYSTEM
CONTROL
REGISTERS
/4
…
C28LSPCLK
SCITXDA
BAUD-RATE GEN
TXSHF REG
/14
SCIHBAUD REG
SCILBAUD REG
PIN
C28x
CPU
SCIRXDA
SCICCRA REG
RXSHF REG
REGISTER ACCESS
PIN
SCIRXEMUA REG
SCIRXBUF REG
TX/RX
LOGIC
RX FIFO
INTR
SCIFFRXA REG
SCIPRI REG
SCIRXINA
SCITXINA
RX INTERRUPT LOGIC
C28x PIE
SCRXST REG
Figure 7-49. SCI (C28x)
7.12.5.1 Architecture
The major elements used in full-duplex operation include:
•
A transmitter (TX) and its major registers:
– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto
the SCITXD pin, 1 bit at a time
•
A receiver (RX) and its major registers:
– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU
registers
•
•
A programmable baud generator
Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and
FIFOs.
The SCI receiver and transmitter can operate either independently or simultaneously.
7.12.5.2 Multiprocessor and Asynchronous Communication Modes
The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit multiprocessor
mode. These protocols allow efficient data transfer between multiple processors.
The SCI offers the UART communications mode for interfacing with many popular peripherals. The
asynchronous mode requires two lines to interface with many standard devices such as terminals and printers
that use RS-232-C formats.
Data transmission characteristics include:
•
One start bit
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•
•
•
One to eight data bits
An even/odd parity bit or no parity bit
One or two stop bits with a programmed frequency
7.12.6 C28x Serial Peripheral Interface
This device has one C28x SPI. The SPI is a high-speed synchronous serial input/output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-
transfer rate. The SPI is normally used for communications between the DSP controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. The port supports a 16-level, receive-and-transmit FIFO for reducing CPU servicing
overhead.
The SPI module features include:
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO, if the SPI module is not used.
•
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Twelve SPI module control registers: Located in control register frame beginning at address 7040h.
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (bits 7−0), and the upper byte (bits 15−8) is
read as zeros. Writing to the upper byte has no effect.
•
•
16-level transmit and receive FIFO
Delayed transmit control
Figure 7-50 shows the C28x SPI peripheral.
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MASTER
SPI (C28)
SUBSYSTEM
TX INTERRUPT LOGIC
SPIFFTX REG
C28CLKIN
SPICTL REG
SPISIMOA
SPIFFCT REG
PIN
C28SYSCLK
REGISTER
ACCESS
(1)
TX FIFO
SPITXBUF REG
TX DELAY
SPISOMIA
SPIA_ENCLK
/1
/2
PIN
SYSTEM
CONTROL
REGISTERS
SPI BIT RATE
SPIBRR REG
C28LSPCLK
/4
…
SPIDAT REG
/14
SPISTEA
SPICCR REG
PIN
C28x
CPU
REGISTER ACCESS
(1)
TX/RX
RX FIFO
SPICLKA
SPIRXBUF REG
SPIRXEMU REG
LOGIC
PIN
INTR
SPIFFRX REG
SPIPRI REG
SPITXINA
SPIRXINA
SPIST REG
RX INTERRUPT LOGIC
C28x PIE
(1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIFFENA OF THE SPIFFTX REGISTER
Figure 7-50. SPI (C28x)
7.12.6.1 Functional Overview
The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For
both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched
into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is
transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive
data simultaneously. The application software determines whether the data is meaningful or dummy data. There
are three possible methods for data transmission:
•
•
•
Master sends data; slave sends dummy data
Master sends data; slave sends data
Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
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7.12.6.2 SPI Electrical Data and Timing
This section contains both Master Mode and Slave Mode timing data.
7.12.6.2.1 Master Mode Timing
Section 7.12.6.2.1.1 lists the master mode timing (clock phase = 0) and Section 7.12.6.2.1.2 lists the master
mode timing (clock phase = 1). Figure 7-51 and Figure 7-52 show the timing waveforms.
7.12.6.2.1.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
+
2
3
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
–
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
4
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
5
0.5tc(SPC)M – 10
Setup time, SPISOMI before
SPICLK
8
35
0
35
0
Hold time, SPISOMI valid after
SPICLK
9
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M –
3tc(SYSCLK) – 10
23
24
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 7-51. SPI Master Mode External Timing (Clock Phase = 0)
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UNIT
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7.12.6.2.1.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
(5)
MAX
MAX
127tc(LSPCLK)
0.5tc(SPC)M –
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
ns
ns
Pulse duration, SPICLK first
pulse
–
2
3
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
0.5tc(LSPCLK) + 10
+
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
6
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
35
0
35
Hold time, SPISOMI valid after
SPICLK
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
0.5tc(SPC) – 10
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 7-52. SPI Master Mode External Timing (Clock Phase = 1)
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7.12.6.2.2 Slave Mode Timing
Section 7.12.6.2.2.1 lists the slave mode timing (clock phase = 0) and Section 7.12.6.2.2.2 lists the slave mode
timing (clock phase = 1). Figure 7-53 and Figure 7-54 show the timing waveforms.
7.12.6.2.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(4) (3)
(5)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-53. SPI Slave Mode External Timing (Clock Phase = 0)
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7.12.6.2.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(3) (4)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-54. SPI Slave Mode External Timing (Clock Phase = 1)
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7.12.7 C28x Multichannel Buffered Serial Port
This device provides one high-speed McBSP that allows direct interface to codecs and other devices. The CPU
accesses data, control, and status information. The MCBSP also supports µDMA transfers.
The McBSP consists of a data-flow path and a control path connected to external devices by six pins. Data is
communicated to devices interfaced with the McBSP through the data transmit (DX) pin for transmission and
through the data receive (DR) pin for reception. Control information in the form of clocking and frame
synchronization is communicated through the following pins: CLKX (transmit clock), CLKR (receive clock), FSX
(transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible through
the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the data transmit
registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX through the transmit shift registers (XSR1,
XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers (RSR1, RSR2) and copied
into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is then copied to the DRRs, which can
be read by the CPU or the DMA controller. This method allows simultaneous movement of internal and external
data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is 8 bits,
12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and FSR. If
the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads instead of the
CLKR and FSR pins.
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McBSP features include:
•
•
•
•
•
•
•
Full-duplex communication
Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
Independent clocking and framing for reception and transmission
The capability to send interrupts to the CPU and to send DMA events to the DMA controller
128 channels for transmission and reception
Multichannel selection modes that enable or disable block transfers in each of the channels
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D
and D/A devices
•
•
Support for external generation of clock signals and frame-synchronization signals
A programmable sample rate generator for internal generation and control of clock signals and frame
synchronization signals
•
•
Programmable polarity for frame-synchronization pulses and clock signals
Direct interface to:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multi-phase frame capability is provided)
– I2S compliant devices
– SPI devices
•
A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
Note
A value of the chosen data size is referred to as a serial word or word in this section. Elsewhere,
word is used to describe a 16-bit value.
•
•
•
•
µ-law and A-law companding
The option of transmitting/receiving 8-bit data with the LSB first
Status bits for flagging exception/error conditions
ABIS mode is not supported
Figure 7-55 shows the C28x McBSP peripheral.
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MASTER
MCBSP
SUBSYSTEM
MCR2 REG
MCR1 REG
XCERA REG
XCERB REG
XCERC REG
XCERD REG
XCERE REG
XCERF REG
XCERG REG
XCERH REG
RCERA REG
RCERB REG
RCERC REG
RCERD REG
RCERE REG
RCERF REG
RCERG REG
RCERH REG
C28CLKIN
MULTI -
CHANNEL
SELECTION
(128 CHAN)
C28SYSCLK
REG
ACCESS
MCBSPA_ENCLK
/1
/2
SYSTEM
CONTROL
REGISTERS
/4
…
C28LSPCLK
PERIPH
LOGIC
/14
MCLKXA
MFSXA
MDXA
SPCR2 REG
XCR2 REG
SPCR2 REG
SRGR2 REG
SPCR1 REG
XCR1 REG
SPCR1 REG
SRGR1 REG
PIN
PIN
PIN
C28x
CPU
ALL REG
ACCESS
GENERATION AND CONTROL
OF CLOCK AND FRAME SYNC
INTR
PCR REG
C28x PIE
MCLKRA
MFSRA
MDRA
MXINTA
MRINTA
RX/TX
INTERRUPT
LOGIC
MFFINT REG
PIN
PIN
PIN
COMPRESS
EXPAND
DXR2 REG
DRR1 REG
DXR1 REG
DRR2 REG
XSR REG
RSR REG
C28
DMA
DRR / DXR
RBR REG
REG ACCESS
Figure 7-55. McBSP (C28x)
7.12.7.1 McBSP Electrical Data and Timing
7.12.7.1.1 McBSP Transmit and Receive Timing
7.12.7.1.1.1 McBSP Timing Requirements
NO.(1)
MIN
MAX UNIT
(2)
1
kHz
McBSP module clock (CLKG, CLKX, CLKR) range
25 (3)
MHz
ns
40
McBSP module cycle time (CLKG, CLKX, CLKR) range
1
ms
ns
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
P – 7
ns
7
7
ns
Fall time, CLKR/X
ns
18
2
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
0
6
18
5
0
Hold time, DR valid after CLKR low
3
18
2
Setup time, external FSX high before CLKX low
CLKX ext
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MAX UNIT
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NO.(1)
MIN
(2)
CLKX int
CLKX ext
0
6
M20 th(CKXL-FXH)
Hold time, external FSX high after CLKX low
ns
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (30 MHz).
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7.12.7.1.1.2 McBSP Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1) (2)
NO.
M1
M2
M3
PARAMETER
MIN
MAX UNIT
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P
ns
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 5 (3)
D + 5 (3)
ns
ns
C – 5 (3)
C + 5 (3)
0
3
0
3
4
27
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
4
27
8
Disable time, CLKX high to DX high impedance
following last data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
28
8
Delay time, CLKX high to DX valid.
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes.
M7
td(CKXH-DXV)
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
ns
14
P + 8
P + 14
0
6
Enable time, CLKX high to DX driven.
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes.
M8
M9
ten(CKXH-DX)
ns
ns
ns
P
P + 6
8
14
Delay time, FSX high to DX valid.
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
FSX ext
td(FXH-DXV)
FSX int
P + 8
P + 14
FSX ext
FSX int
0
6
Enable time, FSX high to DX driven.
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
FSX ext
M10 ten(FXH-DX)
FSX int
P
FSX ext
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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7.12.7.1.1.3 McBSP Timing Diagrams
M1, M11
M2, M12
M3, M12
M13
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−3)
(n−2)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
Figure 7-56. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
(XDATDLY=01b)
Bit (n−1)
M8
Bit 0
M6
M7
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 7-57. McBSP Transmit Timing
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7.12.7.1.2 McBSP as SPI Master or Slave Timing
7.12.7.1.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.(1)
UNIT
MIN
30
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(BFXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.12.7.1.2.2 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M24
M25
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
2P(1)
ns
ns
P
Disable time, DX high impedance following
last data bit from FSX high
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
7.12.7.1.2.3 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Timing Diagram
M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
M31
(n-2)
(n-3)
(n-4)
M30
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 7-58. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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UNIT
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
7.12.7.1.2.4 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.(1)
MIN
30
1
MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
M41 tsu(FXL-CKXH)
M42 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.12.7.1.2.5 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M34 th(CKXL-FXL)
M35 td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
P
ns
ns
2P(1)
Disable time, DX high impedance following last data bit
from CLKX low
M37 tdis(CKXL-DXHZ)
M38 td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
7.12.7.1.2.6 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Timing Diagram
M42
MSB
LSB
M41
CLKX
FSX
DX
M35
M34
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M40
(n-2)
(n-3)
(n-4)
M39
DR
Bit 0
(n-3)
(n-4)
Figure 7-59. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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7.12.7.1.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.(1)
UNIT
MIN
30
1
MAX
M49 tsu(DRV-CKXH)
M50 th(CKXH-DRV)
M51 tsu(FXL-CKXL)
M52 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.12.7.1.2.8 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
M43 th(CKXH-FXL)
M44 td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
M47 tdis(FXH-DXHZ)
M48 td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
7.12.7.1.2.9 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Timing Diagram
M52
M51
MSB
LSB
CLKX
FSX
M43
M44
M48
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M50
(n-3)
(n-4)
M49
Bit 0
(n-2)
(n-3)
(n-4)
Figure 7-60. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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UNIT
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
7.12.7.1.2.10 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.(1)
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.12.7.1.2.11 McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
MASTER(2)
SLAVE
MIN
NO.(1)
PARAMETER
UNIT
MIN
MAX
MAX
M53 th(CKXH-FXL)
M54 td(FXL-CKXL)
M55 td(CLKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
P
ns
ns
ns
2P(1)
–2
0
3P + 6
5P + 20
Disable time, DX high impedance following last data
bit from CLKX high
M56 tdis(CKXH-DXHZ)
M57 td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
7.12.7.1.2.12 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 Timing Diagram
M61
M60
MSB
M54
LSB
CLKX
FSX
DX
M53
M56
M55
M57
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
M58
M59
(n-2)
DR
Bit 0
Bit(n-1)
(n-3)
Figure 7-61. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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8 Detailed Description
The Concerto MCU comprises three subsystems: the Master Subsystem, the Control Subsystem, and the
Analog Subsystem. While the Master and Control Subsystem each have dedicated local memories and
peripherals, they can also share data and events through shared memories and peripherals. The Analog
Subsystem has two ADC converters and six Analog Comparators. Both the Master and Control Subsystems
access the Analog Subsystem through the Analog Common Interface Bus (ACIB). The NMI Blocks force
communication of critical events to the Master and Control Subsystem processors and their Watchdog Timers.
The Reset Block responds to Watchdog Timer NMI Reset, External Reset, and other events to initialize
subsystem processors and the rest of the chip to a known state. The Clocking Blocks support multiple low-power
modes where clocks to the processors and peripherals can be slowed down or stopped in order to manage
power consumption.
Note
Throughout this document, the Master Subsystem is denoted by the color blue; the Control
Subsystem is denoted by the color green; and the Analog Subsystem is denoted by the color orange.
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8.1 Memory Maps
Section 8.1.1 shows the Control Subsystem Memory Map. Section 8.1.2 shows the Master Subsystem Memory
Map.
8.1.1 Control Subsystem Memory Map
Table 8-1. Control Subsystem M0, M1 RAM
C ADDRESS
SIZE
(BYTES)
C DMA ACCESS(1)
CONTROL SUBSYSTEM M0, M1 RAM
(x16 ALIGNED)(1)
no
no
0000 0000 – 0000 03FF
0000 0400 – 0000 07FF
M0 RAM (ECC)
M1 RAM (ECC)
2K
2K
(1) The letter "C" refers to the Control Subsystem.
Table 8-2. Control Subsystem Peripheral Frame 0
C ADDRESS
CONTROL SUBSYSTEM PERIPHERAL FRAME 0
(INCLUDES ANALOG)
SIZE
(BYTES)
C DMA ACCESS(1)
(x16 ALIGNED)(1)
0000 0800 – 0000 087F
0000 0880 – 0000 0890
Reserved
Control Subsystem Device Configuration Registers (Read
Only)
no
34
0000 0891 – 0000 0ADF
0000 0AE0 – 0000 0AEF
0000 0AF0 – 0000 0AFF
0000 0B00 – 0000 0B0F
0000 0B10 – 0000 0B3F
0000 0B40 – 0000 0B4F
0000 0B50 – 0000 0BFF
0000 0C00 – 0000 0C07
0000 0C08 – 0000 0C0F
0000 0C10 – 0000 0C17
0000 0C18 – 0000 0CDF
0000 0CE0 – 0000 0CFF
0000 0D00 – 0000 0DFF
0000 0E00 – 0000 0EFF
0000 0F00 – 0000 0FFF
0000 1000 – 0000 11FF
0000 1200 – 0000 16FF
0000 1700 – 0000 177F
0000 1780 – 0000 17FF
0000 1800 – 0000 3FFF
Reserved
no
C28x CSM Registers
Reserved
32
32
32
yes
yes
ADC1 Result Registers
Reserved
ADC2 Result Registers
Reserved
no
no
no
CPU Timer 0
16
16
16
CPU Timer 1
CPU Timer 2
Reserved
no
no
no
PIE Registers
64
PIE Vector Table
PIE Vector Table Copy (Read Only)
Reserved
512
512
no
C28x DMA Registers
Reserved
1K
no
no
Analog Subsystem Control Registers
Hardware BIST Registers
Reserved
256
256
(1) The letter "C" refers to the Control Subsystem.
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Table 8-3. Control Subsystem Peripheral Frame 3
C ADDRESS
CONTROL SUBSYSTEM
PERIPHERAL FRAME 3
SIZE
(BYTES)
M ADDRESS
µDMA
ACCESS
C DMA ACCESS(1)
(x16 ALIGNED)(1)
(BYTE-ALIGNED)(2)
no
0000 4000 – 0000 4181
0000 4182 – 0000 42FF
C28x Flash Control Registers
Reserved
772
72
C28x Flash ECC Error Log
Registers
no
0000 4300 – 0000 4323
0000 4324 – 0000 43FF
0000 4400 – 0000 443F
0000 4440 – 0000 48FF
0000 4900 – 0000 497F
0000 4980 – 0000 49FF
Reserved
no
no
M Clock Control Registers(2)
128
256
400F B800 – 400F B87F
400F B200 – 400F B2FF
no
no
Reserved
RAM Configuration Registers
Reserved
RAM ECC/Parity/Access Error
Log Registers
no
0000 4A00 – 0000 4A7F
256
400F B300 – 400F B3FF
400F B700 – 400F B77F
no
no
0000 4A80 – 0000 4DFF
0000 4E00 – 0000 4E3F
0000 4E40 – 0000 4FFF
0000 5000 – 0000 503F
0000 5040 – 0000 50FF
0000 5100 – 0000 517F
0000 5180 – 0000 51FF
0000 5200 – 0000 527F
0000 5280 – 0000 52FF
0000 5300 – 0000 537F
0000 5380 – 0000 53FF
0000 5400 – 0000 547F
0000 5480 – 0000 54FF
0000 5500 – 0000 557F
0000 5580 – 0000 57FF
Reserved
no
CtoM and MtoC IPC Registers
Reserved
128
128
yes
McBSP-A
Reserved
yes
yes
yes
yes
yes
yes
yes
yes
yes
EPWM1 (Hi-Resolution)
EPWM2 (Hi-Resolution)
EPWM3 (Hi-Resolution)
EPWM4 (Hi-Resolution)
EPWM5 (Hi-Resolution)
EPWM6 (Hi-Resolution)
EPWM7 (Hi-Resolution)
EPWM8 (Hi-Resolution)
EPWM9
256
256
256
256
256
256
256
256
256
Reserved
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
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Table 8-4. Control Subsystem Peripheral Frame 1
C ADDRESS
SIZE
(BYTES)
C DMA ACCESS(1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 1
Reserved
(x16 ALIGNED)(1)
0000 5800 – 0000 59FF
0000 5A00 – 0000 5A1F
0000 5A20 – 0000 5A3F
0000 5A40 – 0000 5A5F
0000 5A60 – 0000 5A7F
0000 5A80 – 0000 5A9F
0000 5AA0 – 0000 5ABF
0000 5AC0 – 0000 5AFF
0000 5B00 – 0000 5B3F
0000 5B40 – 0000 5B7F
0000 5B80 – 0000 5BBF
0000 5BC0 – 0000 5F7F
0000 5F80 – 0000 5FFF
0000 6000 – 0000 63FF
0000 6400 – 0000 641F
0000 6420 – 0000 643F
0000 6440 – 0000 645F
0000 6460 – 0000 647F
0000 6480 – 0000 649F
0000 64A0 – 0000 64BF
0000 64C0 – 0000 6F7F
0000 6F80 – 0000 6FFF
no
no
no
no
no
no
ECAP1
64
64
64
64
64
64
ECAP2
ECAP3
ECAP4
ECAP5
ECAP6
Reserved
no
no
no
EQEP1
128
128
128
EQEP2
EQEP3
Reserved
no
C GPIO Group 1 Registers(1)
256
Reserved
no
no
no
no
no
no
COMP1 Registers
COMP2 Registers
COMP3 Registers
COMP4 Registers
COMP5 Registers
COMP6 Registers
Reserved
64
64
64
64
64
64
no
C GPIO Group 2 Registers and AIO Mux Registers(1)
256
(1) The letter "C" refers to the Control Subsystem.
Table 8-5. Control Subsystem Peripheral Frame 2
C ADDRESS
SIZE
(BYTES)
C DMA ACCESS(1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 2
(x16 ALIGNED)(1)
0000 7000 – 0000 70FF
0000 7010 – 0000 702F
0000 7030 – 0000 703F
0000 7040 – 0000 704F
0000 7050 – 0000 705F
0000 7060 – 0000 706F
0000 7070 – 0000 707F
0000 7080 – 0000 70FF
Reserved
no
C28x System Control Registers
64
Reserved
no
no
no
no
SPI-A
32
32
32
32
SCI-A
NMI Watchdog Interrupt Registers
External Interrupt Registers
Reserved
ADC1 Configuration Registers
(Only 16-bit read/write access supported)
no
no
0000 7100 – 0000 717F
0000 7180 – 0000 71FF
256
256
ADC2 Configuration Registers
(Only 16-bit read/write access supported)
0000 7200 – 0000 78FF
0000 7900 – 0000 793F
0000 7940 – 0000 7FFF
Reserved
I2C-A
no
128
Reserved
(1) The letter "C" refers to the Control Subsystem.
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Table 8-6. Control Subsystem RAMs
C ADDRESS
CONTROL SUBSYSTEM
RAMS
SIZE
(BYTES)
M ADDRESS
µDMA
ACCESS
C DMA ACCESS(1)
(x16 ALIGNED)(1)
(BYTE-ALIGNED)(2)
no
0000 8000 – 0000 8FFF
0000 9000 – 0000 9FFF
0000 A000 – 0000 AFFF
0000 B000 – 0000 BFFF
0000 C000 – 0000 CFFF
0000 D000 – 0000 DFFF
0000 E000 – 0000 EFFF
0000 F000 – 0000 FFFF
0001 0000 – 0001 0FFF
0001 1000 – 0001 1FFF
0001 2000 – 0001 2FFF
0001 3000 – 0001 3FFF
0001 4000 – 0003 F7FF
L0 RAM (ECC, Secure)
L1 RAM (ECC, Secure)
L2 RAM (Parity, Interleaving)
L3 RAM (Parity, Interleaving)
S0 RAM (Parity, Shared)
S1 RAM (Parity, Shared)
S2 RAM (Parity, Shared)
S3 RAM (Parity, Shared)
S4 RAM (Parity, Shared)
S5 RAM (Parity, Shared)
S6 RAM (Parity, Shared)
S7 RAM (Parity, Shared)
Reserved
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
2000 8000 – 2000 9FFF
2000 A000 – 2000 BFFF
2000 C000 – 2000 DFFF
2000 E000 – 2000 FFFF
2001 0000 – 2001 1FFF
2001 2000 – 2001 3FFF
2001 4000 – 2001 5FFF
2001 6000 – 2001 7FFF
yes
yes
yes
yes
yes
yes
yes
yes
yes
read only
yes
0003 F800 – 0003 FBFF
0003 FC00 – 0003 FFFF
CtoM MSG RAM (Parity)
MtoC MSG RAM (Parity)
2K
2K
2007 F000 – 2007 F7FF
2007 F800 – 2007 FFFF
yes
read only
yes
0004 0000 – 0004 7FFF
0004 8000 – 0004 8FFF
0004 9000 – 0004 9FFF
0004 A000 – 0004 AFFF
0004 B000 – 0004 BFFF
0004 C000 – 0004 CFFF
0004 D000 – 0004 DFFF
0004 E000 – 0004 EFFF
0004 F000 – 0004 FFFF
0005 0000 – 0005 0FFF
0005 1000 – 0005 1FFF
0005 2000 – 0005 2FFF
0005 3000 – 0005 3FFF
0005 4000 – 0007 EFFF
0007 F000 – 0007 F3FF
0007 F400 – 0007 F7FF
0007 F800 – 0007 FBFF
0007 FC00 – 0007 FFFF
0008 0000 – 0009 FFFF
Reserved
no
no
no
no
no
no
no
no
no
no
no
no
L0 RAM - ECC Bits
L1 RAM - ECC Bits
L2 RAM - Parity Bits
L3 RAM - Parity Bits
S0 RAM - Parity Bits
S1 RAM - Parity Bits
S2 RAM - Parity Bits
S3 RAM - Parity Bits
S4 RAM - Parity Bits
S5 RAM - Parity Bits
S6 RAM - Parity Bits
S7 RAM - Parity Bits
Reserved
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
2008 8000 – 2008 9FFF
2008 A000 – 2008 BFFF
2008 C000 – 2008 DFFF
2008 E000 – 2008 FFFF
2009 0000 – 2009 1FFF
2009 2000 – 2009 3FFF
2009 4000 – 2009 5FFF
2009 6000 – 2009 7FFF
no
no
no
no
no
no
no
no
no
no
no
no
M0 RAM - ECC Bits
M1 RAM - ECC Bits
CtoM MSG RAM - Parity Bits
MtoC MSG RAM - Parity Bits
Reserved
2K
2K
2K
2K
200F F000 – 200F F7FF
200F F800 – 200F FFFF
no
no
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
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Table 8-7. Control Subsystem Flash, ECC, OTP, Boot ROM
CONTROL SUBSYSTEM
FLASH, ECC, OTP,
BOOT ROM
C ADDRESS
SIZE
(BYTES)
M ADDRESS
µDMA
ACCESS
C DMA ACCESS(1)
(x16 ALIGNED)(1)
(BYTE-ALIGNED)(2)
Sector N (not available for
256KB Flash configuration)
no
no
no
no
no
no
no
0010 0000 – 0010 1FFF
0010 2000 – 0010 3FFF
0010 4000 – 0010 5FFF
0010 6000 – 0010 7FFF
0010 8000 – 0010 FFFF
0011 0000 – 0011 7FFF
0011 8000 – 0011 FFFF
16K
16K
16K
16K
64K
64K
64K
Sector M (not available for
256KB Flash configuration)
Sector L (not available for
256KB Flash configuration)
Sector K (not available for
256KB Flash configuration)
Sector J (not available for
256KB Flash configuration)
Sector I (not available for 256KB
Flash configuration)
Sector H (not available for
256KB Flash configuration)
no
no
no
no
no
no
0012 0000 – 0012 7FFF
0012 8000 – 0012 FFFF
0013 0000 – 0013 7FFF
0013 8000 – 0013 9FFF
0013 A000 – 0013 BFFF
0013 C000 – 0013 DFFF
Sector G
Sector F
Sector E
Sector D
Sector C
Sector B
64K
64K
64K
16K
16K
16K
Sector A
no
0013 E000 – 0013 FFFF
(CSM password in the high
address)
16K
0014 0000 – 001F FFFF
0020 0000 – 0020 7FFF
0020 8000 – 0024 01FF
0024 0200 – 0024 03FF
0024 0400 – 002F FFFF
Reserved
Flash - ECC Bits
(1/8 of Flash used = 64KB)
no
no
64K
1K
Reserved
TI one-time programmable
(OTP) memory
Reserved
EPI0
yes
no
0030 0000 – 003F 7FFF
003F 8000 – 003F FFFF
(External Peripheral/Memory
2M(4)
64K
6000 0000 – DFFF FFFF
yes
Interface)(3)
C28x Boot ROM (64KB)
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
(3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
(4) The Control Subsystem has less address reach to EPI memory than the Master Subsystem.
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8.1.2 Master Subsystem Memory Map
Table 8-8. Master Subsystem Flash, ECC, OTP, Boot ROM
M ADDRESS
SIZE
(BYTES)
µDMA ACCESS
MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM
(BYTE-ALIGNED)(1)
Boot ROM - Dual-mapped to 0x0100 0000
(Both maps access same physical location.)
no
no
0000 0000 – 0000 FFFF
0001 0000 – 001F FFFF
0020 0000 – 0020 3FFF
64K
Reserved
Sector N
16K
(Zone 1 CSM password in the low address.)
no
no
no
no
no
no
no
no
no
no
no
no
0020 4000 – 0020 7FFF
0020 8000 – 0020 BFFF
0020 C000 – 0020 FFFF
0021 0000 – 0021 FFFF
0022 0000 – 0022 FFFF
0023 0000 – 0023 FFFF
0024 0000 – 0024 FFFF
0025 0000 – 0025 FFFF
0026 0000 – 0026 FFFF
0027 0000 – 0027 3FFF
0027 4000 – 0027 7FFF
0027 8000 – 0027 BFFF
Sector M
16K
16K
16K
64K
64K
64K
64K
64K
64K
16K
16K
16K
Sector L
Sector K
Sector J
Sector I (not available for 256KB Flash configuration)
Sector H (not available for 256KB Flash configuration)
Sector G (not available for 256KB Flash configuration)
Sector F (not available for 256KB Flash configuration)
Sector E
Sector D
Sector C
Sector B
Sector A
no
0027 C000 – 0027 FFFF
0028 0000 – 005F FFFF
0060 0000 – 0060 FFFF
16K
(Zone 2 CSM password in the high address.)
Reserved
Flash - ECC Bits
(1/8 of Flash used = 64KB)
no
64K
0061 0000 – 0068 047F
0068 0480 – 0068 07FF
0068 0800
Reserved
no
no
TI OTP
896
4
OTP – Security Lock
0068 0804
Reserved
0068 0808
Reserved
no
no
no
0068 080C
OTP – Zone 2 Flash Start Address
OTP – Ethernet Media Access Controller (EMAC) Address 0
OTP – EMAC Address 1
Reserved
4
4
4
0068 0810
0068 0814
0068 0818
no
no
no
0068 081C
Main Oscillator Clock Frequency
Reserved
4
4
4
0068 0820
0068 0824
Alternate Boot mode Pin Configuration
Reserved
0068 0828
0068 082C
OTP ENTRY POINT
0068 0830 – 0070 00FF
Reserved
OTP – ECC Bits – Application Use
(1/8 of OTP used = 3 Bytes)
no
no
0070 0100 – 0070 0102
0070 0103 – 00FF FFFF
0100 0000 – 0100 FFFF
0101 0000 – 03FF FFFF
3
Reserved
Boot ROM – Dual-mapped to 0x0000 0000
(Both maps access same physical location.)
64K
Reserved
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Table 8-8. Master Subsystem Flash, ECC, OTP, Boot ROM (continued)
M ADDRESS
SIZE
(BYTES)
µDMA ACCESS
MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM
(BYTE-ALIGNED)(1)
ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC.
Accessing this area of memory by the µCRC peripheral will cause an
access in 0000 0000 – 03FF FFFF memory space.
Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dual-mapped
ROM address)
Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF
Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF
(Read cycles from this space cause the µCRC peripheral to
continuously update data checksum inside a register, when reading a
block of data.)
no
0400 0000 – 07FF FFFF
0800 0000 – 1FFF FFFF
64M
Reserved
(1) The letter "M" refers to the Master Subsystem.
Table 8-9. Master Subsystem RAMs
µDMA
ACCESS
M ADDRESS
SIZE
MASTER SUBSYSTEM RAMS
(BYTES)
C ADDRESS
C DMA ACCESS(2)
(BYTE-ALIGNED)(1)
(x16 ALIGNED)(2)
no
2000 0000 – 2000 1FFF
2000 2000 – 2000 3FFF
2000 4000 – 2000 5FFF
2000 6000 – 2000 7FFF
2000 8000 – 2000 9FFF
2000 A000 – 2000 BFFF
2000 C000 – 2000 DFFF
2000 E000 – 2000 FFFF
2001 0000 – 2001 1FFF
2001 2000 – 2001 3FFF
2001 4000 – 2001 5FFF
2001 6000 – 2001 7FFF
2001 8000 – 2007 EFFF
C0 RAM (ECC, Secure)
C1 RAM (ECC, Secure)
C2 RAM (Parity)
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
C3 RAM (Parity)
S0 RAM (Parity, Shared)
S1 RAM (Parity, Shared)
S2 RAM (Parity, Shared)
S3 RAM (Parity, Shared)
S4 RAM (Parity, Shared)
S5 RAM (Parity, Shared)
S6 RAM (Parity, Shared)
S7 RAM (Parity, Shared)
Reserved
0000 C000 – 0000 CFFF
0000 D000 – 0000 DFFF
0000 E000 – 0000 EFFF
0000 F000 – 0000 FFFF
0001 0000 – 0001 0FFF
0001 1000 – 0001 1FFF
0001 2000 – 0001 2FFF
0001 3000 – 0001 3FFF
yes
yes
yes
yes
yes
yes
yes
yes
yes
read only
2007 F000 – 2007 F7FF
2007 F800 – 2007 FFFF
CtoM MSG RAM (Parity)
MtoC MSG RAM (Parity)
2K
2K
0003 F800 – 0003 FBFF
0003 FC00 – 0003 FFFF
yes
yes
read only
yes
no
no
no
no
no
no
no
no
no
no
no
no
2008 0000 – 2008 1FFF
2008 2000 – 2008 3FFF
2008 4000 – 2008 5FFF
2008 6000 – 2008 7FFF
2008 8000 – 2008 9FFF
2008 A000 – 2008 BFFF
2008 C000 – 2008 DFFF
2008 E000 – 2008 FFFF
2009 0000 – 2009 1FFF
2009 2000 – 2009 3FFF
2009 4000 – 2009 5FFF
2009 6000 – 2009 7FFF
2009 8000 – 200F EFFF
200F F000 – 200F F7FF
200F F800 – 200F FFFF
2010 0000 – 21FF FFFF
C0 RAM - ECC Bits
C1 RAM - ECC Bits
C2 RAM - Parity Bits
C3 RAM - Parity Bits
S0 RAM - Parity Bits
S1 RAM - Parity Bits
S2 RAM - Parity Bits
S3 RAM - Parity Bits
S4 RAM - Parity Bits
S5 RAM - Parity Bits
S6 RAM - Parity Bits
S7 RAM - Parity Bits
Reserved
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
0004 C000 – 0004 CFFF
0004 D000 – 0004 DFFF
0004 E000 – 0004 EFFF
0004 F000 – 0004 FFFF
0005 0000 – 0005 0FFF
0005 1000 – 0005 1FFF
0005 2000 – 0005 2FFF
0005 3000 – 0005 3FFF
no
no
no
no
no
no
no
no
no
no
CtoM MSG RAM - Parity Bits
MtoC MSG RAM - Parity Bits
Reserved
2K
2K
0007 F800 – 0007 FBFF
0007 FC00 – 0007 FFFF
no
no
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SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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Table 8-9. Master Subsystem RAMs (continued)
µDMA
ACCESS
M ADDRESS
SIZE
(BYTES)
C ADDRESS
MASTER SUBSYSTEM RAMS
C DMA ACCESS(2)
(BYTE-ALIGNED)(1)
(x16 ALIGNED)(2)
Bit Banded RAM Zone
(Dedicated address for each
RAM bit of Cortex-M3 RAM
blocks above)
yes
2200 0000 – 23FF FFFF
32M
All RAM Spaces – Mirror-
Mapped for µCRC.
Accessing this memory by the
µCRC peripheral will cause an
access to
2000 0000 – 23FF FFFF
memory space.
yes
2400 0000 – 27FF FFFF
2800 0000 – 3FFF FFFF
64M
(Read cycles from this space
cause the µCRC peripheral to
continuously update data
checksum inside a register
when reading a block of data.)
Reserved
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
Table 8-10. Master Subsystem Peripherals
µDMA
ACCESS
M ADDRESS
MASTER SUBSYSTEM
PERIPHERALS
SIZE
(BYTES)
C ADDRESS
C DMA ACCESS(2)
(BYTE-ALIGNED)(1)
(x16 ALIGNED)(2)
yes
yes
4000 0000 – 4000 0FFF
4000 1000 – 4000 1FFF
4000 2000 – 4000 3FFF
4000 4000 – 4000 4FFF
4000 5000 – 4000 5FFF
4000 6000 – 4000 6FFF
4000 7000 – 4000 7FFF
4000 8000 – 4000 8FFF
4000 9000 – 4000 9FFF
4000 A000 – 4000 AFFF
4000 B000 – 4000 BFFF
4000 C000 – 4000 CFFF
4000 D000 – 4000 DFFF
4000 E000 – 4000 EFFF
4000 F000 – 4000 FFFF
4001 0000 – 4001 0FFF
4001 1000 – 4001 FFFF
4002 0000 – 4002 07FF
4002 0800 – 4002 0FFF
4002 1000 – 4002 17FF
4002 1800 – 4002 1FFF
4002 2000 – 4002 3FFF
4002 4000 – 4002 4FFF
4002 5000 – 4002 5FFF
4002 6000 – 4002 6FFF
4002 7000 – 4002 7FFF
4002 8000 – 4002 FFFF
Watchdog Timer 0 Registers
Watchdog Timer 1 Registers
Reserved
4K
4K
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
M GPIO Port A (APB Bus)(1)
M GPIO Port B (APB Bus)(1)
M GPIO Port C (APB Bus)(1)
M GPIO Port D (APB Bus)(1)
SSI0
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
SSI1
SSI2
SSI3
UART0
UART1
UART2
UART3
UART4
Reserved
no
no
no
no
I2C0 Master
2K
2K
2K
2K
I2C0 Slave
I2C1 Master
I2C1 Slave
Reserved
yes
yes
yes
yes
M GPIO Port E (APB Bus)(1)
M GPIO Port F (APB Bus)(1)
M GPIO Port G (APB Bus)(1)
M GPIO Port H (APB Bus)(1)
Reserved
4K
4K
4K
4K
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Table 8-10. Master Subsystem Peripherals (continued)
µDMA
ACCESS
M ADDRESS
MASTER SUBSYSTEM
PERIPHERALS
SIZE
(BYTES)
C ADDRESS
C DMA ACCESS(2)
(BYTE-ALIGNED)(1)
(x16 ALIGNED)(2)
yes
yes
yes
yes
4003 0000 – 4003 0FFF
4003 1000 – 4003 1FFF
4003 2000 – 4003 2FFF
4003 3000 – 4003 3FFF
4003 4000 – 4003 CFFF
4003 D000 – 4003 DFFF
4003 E000 – 4003 FFFF
4004 8000 – 4004 8FFF
4004 9000 – 4004 FFFF
4005 0000 – 4005 0FFF
4005 1000 – 4005 7FFF
4005 8000 – 4005 8FFF
4005 9000 – 4005 9FFF
4005 A000 – 4005 AFFF
4005 B000 – 4005 BFFF
4005 C000 – 4005 CFFF
4005 D000 – 4005 DFFF
4005 E000 – 4005 EFFF
4005 F000 – 4005 FFFF
4006 0000 – 4006 0FFF
4006 1000 – 4006 FFFF
4007 0000 – 4007 3FFF
4007 4000 – 4007 7FFF
4007 8000 – 400C FFFF
400D 0000 – 400D 0FFF
400D 1000 – 400F 9FFF
400F A000 – 400F A303
400F A304 – 400F A5FF
GP Timer 0
4K
4K
4K
4K
GP Timer 1
GP Timer 2
GP Timer 3
Reserved
yes
yes
yes
M GPIO Port J (APB Bus)(1)
4K
4K
4K
Reserved
ENET MAC0
Reserved
USB MAC0
Reserved
yes
yes
yes
yes
yes
yes
yes
yes
yes
M GPIO Port A (AHB Bus)(1)
M GPIO Port B (AHB Bus)(1)
M GPIO Port C (AHB Bus)(1)
M GPIO Port D (AHB Bus)(1)
M GPIO Port E (AHB Bus)(1)
M GPIO Port F (AHB Bus)(1)
M GPIO Port G (AHB Bus)(1)
M GPIO Port H (AHB Bus)(1)
M GPIO Port J (AHB Bus)(1)
Reserved
4K
4K
4K
4K
4K
4K
4K
4K
4K
no
no
CAN0
16K
16K
CAN1
Reserved
no
no
EPI0 (Registers only)
Reserved
4K
M Flash Control Registers(1)
772
Reserved
M Flash ECC Error Log
Registers(1)
no
400F A600 – 400F A647
72
400F A648 – 400F AFFF
400F B000 – 400F B1FF
400F B200 – 400F B2FF
Reserved
no
no
Reserved
RAM Configuration Registers
256
256
0000 4900 – 0000 497F
0000 4A00 – 0000 4A7F
no
no
RAM ECC/Parity/Access Error
Log Registers
no
400F B300 – 400F B3FF
no
no
400F B400 – 400F B5FF
400F B600 – 400F B67F
400F B680 – 400F B6FF
400F B700 – 400F B77F
400F B780 – 400F B7FF
400F B800 – 400F B87F
400F B880 – 400F B8BF
400F B8C0 – 400F B8FF
M CSM Registers(1)
512
128
µCRC
Reserved
no
CtoM and MtoC IPC Registers
Reserved
128
0000 4E00 – 0000 4E3F
0000 4400 – 0000 443F
no
no
no
no
no
M Clock Control Registers(1)
M LPM Control Registers(1)
M Reset Control Registers(1)
128
64
64
0000 0880 – 0000 0890
(Read Only)
no
400F B900 – 400F B93F
400F B940 – 400F B97F
Device Configuration Registers
Reserved
64
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Table 8-10. Master Subsystem Peripherals (continued)
µDMA
ACCESS
M ADDRESS
MASTER SUBSYSTEM
PERIPHERALS
SIZE
(BYTES)
C ADDRESS
C DMA ACCESS(2)
(BYTE-ALIGNED)(1)
(x16 ALIGNED)(2)
no
no
400F B980 – 400F B9FF
400F BA00 – 400F BA7F
400F BA80 – 400F BAFF
400F BB00 – 400F BBFF
400F BC00 – 400F EFFF
400F F000 – 400F FFFF
4010 0000 – 41FF FFFF
M Write Protect Registers(1)
M NMI Registers(1)
Reserved
128
128
no
no
Reserved
Reserved
µDMA Registers
Reserved
4K
Bit Banded Peripheral Zone
(Dedicated address for each
register bit of Cortex-M3
peripherals above.)
yes
4200 0000 – 43FF FFFF
4400 0000 – 4FFF FFFF
32M
Reserved
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
Table 8-11. Master Subsystem Analog and EPI
µDMA
ACCESS
M ADDRESS
MASTER SUBSYSTEM
ANALOG AND EPI
SIZE
(BYTES)
C ADDRESS
C DMA ACCESS(2)
(BYTE-ALIGNED)(1)
(x16 ALIGNED)(2)
5000 0000 – 5000 15FF
5000 1600 – 5000 161F
5000 1620 – 5000 167F
5000 1680 – 5000 169F
5000 16A0 – 5FFF FFFF
Reserved
yes
yes
ADC1 Result Registers
Reserved
32
32
ADC2 Result Registers
Reserved
EPI0
yes
6000 0000 – DFFF FFFF
(External Peripheral/Memory
Interface)
2G
0030 0000 – 003F 7FFF(3) (4)
yes
(1) The letter "M" refers to the Master Subsystem.
(2) The letter "C" refers to the Control Subsystem.
(3) The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
(4) The Control Subsystem has less address reach to EPI memory than the Master Subsystem.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 8-12. Cortex-M3 Private Bus
µDMA
ACCESS
Cortex-M3 ADDRESS
(BYTE-ALIGNED)
SIZE
(BYTES)
Cortex-M3 PRIVATE BUS
no
no
no
E000 0000 – E000 0FFF
E000 1000 – E000 1FFF
E000 2000 – E000 2FFF
E000 3000 – E000 E007
E000 E008 – E000 E00F
E000 E010 – E000 E01F
E000 E020 – E000 E0FF
E000 E100 – E000 E4EF
E000 E4F0 – E000 ECFF
E000 ED00 – E000 ED3F
E000 ED40 – E000 ED8F
E000 ED90 – E000 EDB8
E000 EDB9 – E000 EEFF
E000 EF00 – E000 EF03
E000 EF04 – FFFF FFFF
ITM (Instrumentation Trace Macrocell)
DWT (Data Watchpoint and Trace)
FPB (Flash Patch and Breakpoint)
Reserved
4K
4K
4K
no
no
System Control Block
System Timer
8
16
Reserved
no
no
no
no
Nested Vectored Interrupt Controller (NVIC)
Reserved
1008
64
System Control Block
Reserved
Memory Protection Unit
Reserved
41
Nested Vectored Interrupt Controller
Reserved
4
Note
MPU is not available on silicon revision 0 devices.
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8.2 Identification
Table 8-13. Device Identification Registers
C ADDRESS
M ADDRESS
NAME
DESCRIPTION
(x16 ALIGNED)(1)
(BYTE ALIGNED)(2)
DID0.REVID
REVID
400F E000 – 400F E001
Device Identification 0 Register - Revision_ID
REVID - Current Revision ID of device
0x0000 0883
Silicon Revision Number
REVID
0
A
B
E
0
1
1
5
DID1.PARTNO
400F E006
Device Identification 1 Register - Part_Number
PARTID.PARTNO
0x0000 0882
C28x Device PARTID Register - Device Part Number
Device
PARTNO (M3/C28x)
F28M35E20B1
F28M35M52C1
F28M35M22C1
F28M35H52C1
F28M35H22C1
0x49
0x4A
0x50
0x54
0x5A
(1) The letter "C" refers to the Control Subsystem.
(2) The letter "M" refers to the Master Subsystem.
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8.3 Master Subsystem
The Master Subsystem includes the Cortex-M3 CPU, µDMA, Nested Vectored Interrupt Controller (NVIC),
Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and µDMA can access the Control
Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and read ADC
Result Registers through the Analog Common Interface Bus. The Master Subsystem can also receive events
from the NMI block and send events to the Resets block.
Figure 8-1 shows the Master Subsystem.
8.3.1 Cortex-M3 CPU
The 32-bit Cortex-M3 processor offers high performance, fast interrupt handling, and access to a variety of
communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection Unit
(MPU) to provide a privileged mode for protected operating system functionality. A bus bridge adjacent to the
MPU can route program instructions and data on the I-CODE and D-CODE buses that connect to the Boot ROM
and Flash. Other data is typically routed through the Cortex-M3 System Bus connected to the local RAMs. The
System Bus also goes to the Shared Resources block (also accessible by the Control Subsystem) and to the
Analog Subsystem through the ACIB. Another bus bridge allows bus cycles from both the Cortex-M3 System
Bus and those of the µDMA bus to access the Master Subsystem peripherals (through the APB bus or the AHP
bus).
Most of the interrupts to the Cortex-M3 CPU come from the NVIC, which manages the interrupt requests from
peripherals and assigns handling priorities. There are also several exceptions generated by Cortex-M3 CPU that
can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the NVIC. In addition to
programmable priority interrupts, there are also three levels of fixed-priority interrupts of which the highest
priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets block. The next highest priority,
level-2, is assigned to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault)
interrupt is assigned to level-1 priority, and this interrupt is caused by one of the error condition exceptions
(Memory Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not
properly serviced.
The Cortex-M3 CPU has two low-power modes: Sleep and Deep Sleep.
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M3PORRST
3
M3 NMI
RESETS
M3SYSRST
FIXED
M3NMIINT
M3NMI
M3NMIINT
M3NMIINT
M3HRDFLT
PRIORITY
2
1
INTERRUPTS
M3NMIRST
M3WDRST
(1:0)
NVIC
M3 PERIPHERALS
PERIPHERAL
I/O s
M3SWRST
M3DBGRST
APB BUS
AHB BUS
M3
GPTA/B
CPU
USB
EMACRX
EMACTX
REQ
UART
(5:1)
REQ
(3:0)
(3:0)
REQ
SSI
EPI
MAC
REQ
(3:0)
REQ
REQ
BUS
uDMA
MATRIX
DMA INTRS
CAN0/1
(1:0)
USAGE FAULT
SVCALL
ADC
INT
GPIO
(S:A)
IRQ
USB
MAC
IRQ
I2C
UART
(1:5)
IRQ
SSI
GPTA/B DMA
DMA
SW
WDT
(1:0)
IRQ
(0:3)
IRQ
(3:0)
(3:0)
IRQ
ERR
IRQ
(1:0)
IRQ
EPI
EMAC
IRQ
EXCEPTIONS
(1:0)
DBG MONITOR
PENDING SV
SYS TICK
(8:1)
IRQ
IRQ
FROM M3 CORE
IRQ
NVIC
INTERRUPTS
PROGRAM-
MABLE
(NESTED VECTORED INTERRUPT CONTROLLER)
PRIORITY
INTERRUPTS
RAMSINGERR
FLSINGER
FLFSM
CTOM IPC (4:1)
APB BUS (REG ACCESS ONLY)
uDMA BUS
M3 SYSTEM BUS
LOCAL MEMORY
FREQ
GASKET
SECURE
C2 - C3
SECURE
FLASH
(ECC)
S0-S7
MTOC
MSG
CTOM
DATA
MPU /
BOOT
IPC
C0/C1
RAM
RAM
SHARED
RAM
MSG
RAM
BRIDGE
ROM
REGS
INSTRUCTIONS
(parity)
RAM
BUS
(ECC)
(parity)
(parity)
(parity)
BRIDGE
SHARED RESOURCES
I-CODE BUS
D-CODE BUS
RAMACCVIOL
RAMUNCERR
FLASHUNCERR
RAMUNCERR
CONTROL SUBSYSTEM
BUSFAULT
BUS CNTRL/FAULT LOGIC
Figure 8-1. Master Subsystem
8.3.2 Cortex-M3 DMA and NVIC
The Cortex-M3 direct memory access (µDMA) module provides a hardware method of transferring data between
peripherals, between memory, and between peripherals and memory without intervention from the Cortex-M3
CPU. The NVIC manages and prioritizes interrupt handling for the Cortex-M3 CPU.
The Cortex-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the µDMA. If
a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the data transfer,
following which an IRQ request may be sent from the µDMA to the NVIC to announce to the Cortex-M3 that the
transfer has completed. If a DMA channel is not enabled for a given peripheral, REQ/DONE will directly drive
IRQ to the NVIC so that the Cortex-M3 CPU can transfer the data. For those peripherals that are not supported
by the µDMA, IRQs are supplied directly to the NVIC, bypassing the DMA. This case is true for both Watchdogs,
CANs, I2Cs, and the Analog-to-Digital Converters sending ADCINT[8:1] interrupts from the Analog Subsystem.
The NMI Watchdog does not send any events to the µDMA or the NVIC (only to the Resets block).
8.3.3 Cortex-M3 Interrupts
Table 8-14 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are associated
with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor exceptions
generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 8-15.
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Table 8-14. Interrupts from NVIC to Cortex-M3
INTERRUPT NUMBER
(BIT IN INTERRUPT
REGISTERS)
VECTOR ADDRESS OR
OFFSET
VECTOR NUMBER
DESCRIPTION
–
0
0–15
16
0x0000.0000–0x0000.003C
0x0000.0040
0x0000.0044
0x0000.0048
0x0000.004C
0x0000.0050
0x0000.0054
0x0000.0058
0x0000.005C
0x0000.0060
–
Processor exceptions
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
UART0
1
17
2
18
3
19
4
20
5
21
6
22
UART1
7
23
SSI0
8
24
I2C0
9–17
18
25–33
34
Reserved
Watchdog Timers 0 and 1
Timer 0A
0x0000.0088
0x0000.008C
0x0000.0090
0x0000.0094
0x0000.0098
0x0000.009C
0x0000.00A0
–
19
35
20
36
Timer 0B
21
37
Timer 1A
22
38
Timer 1B
23
39
Timer 2A
24
40
Timer 2B
25–27
28
41–43
44
Reserved
System Control
Reserved
GPIO Port F
GPIO Port G
GPIO Port H
UART2
0x0000.00B0
0x0000.00B4
0x0000.00B8
0x0000.00BC
0x0000.00C0
0x0000.00C4
0x0000.00C8
0x0000.00CC
0x0000.00D0
0x0000.00D4
–
29
45
30
46
31
47
32
48
33
49
34
50
SSI1
35
51
Timer 3A
36
52
Timer 3B
37
53
I2C1
38–41
42
54–57
58
Reserved
Ethernet Controller
USB
0x0000.00E8
0x0000.00F0
–
44
60
45
61
Reserved
µDMA Software
µDMA Error
Reserved
EPI
46
62
0x0000.00F8
0x0000.00FC
–
47
63
48–52
53
64–68
69
0x0000.0114
0x0000.0118
–
54
70
GPIO Port J
Reserved
SSI 2
55–56
57
71–72
73
0x0000.0124
0x0000.0128
0x0000.012C
0x0000.0130
–
58
74
SSI 3
59
75
UART3
60
76
UART4
61–63
77–79
Reserved
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Table 8-14. Interrupts from NVIC to Cortex-M3 (continued)
INTERRUPT NUMBER
(BIT IN INTERRUPT
REGISTERS)
VECTOR ADDRESS OR
OFFSET
VECTOR NUMBER
DESCRIPTION
64
65
80
81
0x0000.0140
0x0000.0144
0x0000.0148
0x0000.014C
–
CAN0 INT0
CAN0 INT1
CAN1 INT0
CAN1 INT1
Reserved
66
82
67
83
68–71
72
84–87
88
0x0000.0160
0x0000.0164
0x0000.0168
0x0000.016C
0x0000.0170
0x0000.0174
0x0000.0178
0x0000.017C
0x0000.0180
0x0000.0184
0x0000.0188
0x0000.018C
–
ADCINT1
73
89
ADCINT2
74
90
ADCINT3
75
91
ADCINT4
76
92
ADCINT5
77
93
ADCINT6
78
94
ADCINT7
79
95
ADCINT8
80
96
CTOMIPC1
CTOMIPC2
CTOMIPC3
CTOMIPC4
Reserved
81
97
82
98
83
99
84–87
88
100–103
104
105
106
107
108–149
0x0000.01A0
0x0000.01A4
0x0000.01A8
0x0000.01AC
–
RAM Single Error
System / USB PLL Out of Lock
M3 Flash Single Error
Reserved
89
90
91
92–133
Reserved
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Table 8-15. Exceptions from Cortex-M3 Core to NVIC
VECTOR ADDRESS OR
OFFSET (2)
EXCEPTION TYPE
PRIORITY (1)
VECTOR NUMBER
ACTIVATION
Stack top is loaded from
the first entry of the vector
table on reset.
–
–
0
1
0x0000.0000
0x0000.0004
Reset
–3 (highest)
Asynchronous
Asynchronous
On Concerto devices
activated by clock fail
condition, C28 PIE error,
external M3GPIO NMI
input signal, and C28 NMI
WD time-out reset.
Nonmaskable Interrupt
(NMI)
–2
2
0x0000.0008
Hard Fault
–1
3
4
0x0000.000C
0x0000.0010
–
Memory Management
programmable(3)
Synchronous
Synchronous when
precise and asynchronous
when imprecise.
On Concerto devices
activated by memory
access errors and RAM
and flash uncorrectable
data errors.
Bus Fault
programmable(3)
5
0x0000.0014
Usage Fault
–
programmable(3)
–
6
0x0000.0018
–
Synchronous
Reserved
7–10
SVCall
programmable(3)
programmable(3)
–
11
0x0000.002C
0x0000.0030
–
Synchronous
Synchronous
Reserved
Debug Monitor
–
12
13
PendSV
SysTick
Interrupts
programmable(3)
programmable(3)
programmable (4)
14
15
0x0000.0038
0x0000.003C
Asynchronous
Asynchronous
16 and above
0x0000.0040 and above Asynchronous
(1) 0 is the default priority for all the programmable priorities
(2) See the "Vector Table" subsection of the "Exception Model" section in the Cortex-M3 Processor chapter of the Concerto F28M35x
Technical Reference Manual.
(3) See SYSPRI1 in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual.
(4) See PRIn registers in the Cortex-M3 Peripherals chapter of the Concerto F28M35x Technical Reference Manual.
8.3.4 Cortex-M3 Vector Table
Each peripheral interrupt of Table 8-14 is assigned an address offset containing the location of the peripheral
interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers 16–107).
Similarly, each exception interrupt of Table 8-15 (including Reset) is also assigned an address offset containing
the location of the exception interrupt handler (relative to the vector table base) for that particular interrupt
(vector numbers 1–15).
In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table location 0.
Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory
location, in the range 0x0000 0200 to 0x3FFF FE00. When configuring the VTABLE register, the offset must be
aligned on a 512-byte boundary.
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8.3.5 Cortex-M3 Local Peripherals
The Cortex-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose Timers, four
SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB + PHY, EPI, and µCRC
(Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus (Advanced High-
Performance Bus). The EPI peripheral is also accessible from the Control Subsystem. The remaining peripherals
are accessible through the APB Bus (Advanced Peripheral Bus). The APB and AHB bus cycles originate from
the CPU System Bus or the µDMA Bus through a bus bridge.
While the Cortex-M3 CPU has access to all the peripherals, the µDMA has access to most, with the exception of
the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The Cortex-M3 peripherals
connect to the Concerto device pins through GPIO_MUX1. Most of the peripherals also generate event signals
for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the NVIC (triggered by software) and send
M3WDRST[1:0] reset requests to the Reset block. The NMI Watchdog receives the M3NMI event from the NMI
block and sends the M3NMIRST request to the Resets block.
See Section 7.11 for more information on the Cortex-M3 peripherals.
8.3.6 Cortex-M3 Local Memory
The Local Memory includes Boot ROM; Secure Flash with ECC; Secure C0/C1 RAM with ECC; and C2/C3 RAM
with Parity Error Checking. The Boot ROM and Flash are both accessible through the I-CODE and D-CODE
Buses. Flash registers can also be accessed by the Cortex-M3 CPU through the APB Bus. All Local Memory is
accessible from the Cortex-M3 CPU; the C2/C3 RAM is also accessible by the µDMA.
Two types of error correction events can be generated during access of the Local Memory: uncorrectable errors
and single errors. The uncorrectable errors (including one from the Shared Memories) generate a Bus Fault
Exception to the Cortex-M3 CPU. The less critical single errors go to the NVIC where they can result in
maskable interrupts to the Cortex-M3 CPU.
8.3.7 Cortex-M3 Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem.
The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight
individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity Error
Checking.
The Message RAMs and the Shared RAMs can be accessed by the Cortex-M3 CPU and µDMA. The MTOC
Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem, having R/W
access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM Message RAM is intended
for sending data from the Control Subsystem to the Master Subsystem, having R/W access for the C28x/DMA
and read-only access for the Cortex-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control
Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated
with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however,
the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or
from Control to Master Subsystem.
The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed through
the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the Master
and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only. The
Cortex-M3 CPU accesses the ACIB through the System Bus, and the µDMA through the µDMA Bus. The ACIB
arbitrates for access to the ADC and Analog Comparator registers between CPU/DMA bus cycles of the Master
Subsystem with those of the Control Subsystem. In addition to managing bus cycles, the ACIB also transfers
End-of-Conversion ADC interrupts to the Master Subsystem (as well as to the Control Subsystem). The eight
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EOC sources from ADC1 and the eight EOC sources from ADC2 are AND-ed together by the ACIB, with the
resulting eight ADC interrupts going to destinations in both the Master Subsystem and the Control Subsystem.
See Section 7.10 for more information on shared resources and analog peripherals.
8.4 Control Subsystem
The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block, DMA,
C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared Resources:
IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals through the Analog Common
Interface Bus.
Figure 8-2 shows the Control Subsystem.
8.4.1 C28x CPU/FPU/VCU
The F28M35x Concerto MCU family is a member of the TMS320C2000 MCU platform. The Concerto C28x
CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Entry performance MCUs, combined with
a single-precision (32-bit) IEEE 754 FPU of TI’s existing Premium performance MCUs. Each F28M35x device is
a very efficient C/C++ engine, enabling users to develop their system control software in a high-level language.
Each F28M35x device also enables math algorithms to be developed using C/C++. The device is equally
efficient at DSP math tasks and at system control tasks. The 32 × 32-bit MAC 64-bit processing capabilities
enable the controller to handle higher numerical resolution problems efficiently. With the addition of the fast
interrupt response with automatic context save of critical registers, the device is capable of servicing many
asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined
memory accesses. This pipelining enables the device to execute at high speeds without resorting to expensive
high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities.
Special conditional store operations further improve performance. The VCU extends the capabilities of the C28x
CPU and C28x+FPU processors by adding additional instructions to accelerate Viterbi, Complex Arithmetic, 16-
bit FFTs, and CRC algorithms. No changes have been made to existing instructions, pipeline, or memory bus
architecture. Therefore, programs written for the C28x are completely compatible with the C28x+VCU.
There are two events generated by the FPU block that go to the C28x PIE: LVF and LUV. Inside PIE, these and
other events from C28x peripherals and memories result in 12 PIE interrupts PIEINTS[12:1] into the C28x CPU.
The C28x CPU also receives three additional interrupts directly (instead of through PIE) from Timer 1 (TINT1),
from Timer 2 (TINT2), and from the NMI block (C28uNMIINT).
The C28x has two low-power modes: IDLE and STANDBY.
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RAMUNCERR
RAMUNCERR
GPIO_MUX1
EPI
MASTER SUBSYSTEM
C28x NMI
GPI (63:0) MINUS
GPI 39 AND GPI 44
(NOT PINNED OUT)
ECCDBLERR
FLASHUNCERR
SHARED RESOURCES
C28x LOCAL MEMORY
M0/M1
L2/L3
FREQ
S0-S7
MTOC
MSG
CTOM
MSG
SECURE
L0/L1
RAM
LPM WAKEUP
LPMWAKE
GASKET
SHARED
RAM
SECURE
FLASH
(ECC)
BOOT
IPC
RAM
RAM
RAM
RAM
ROM
REGS
(ECC)
BUS
(parity)
(parity)
(parity)
(ECC)
(parity)
BRIDGE
MTOCIPC (4:1)
LVF
LUF
RAMACCVIOL
FLSINGERR
FLFSM
RAMSINGERR
C28x
FPU
ANALOG
SUBSYSTEM
PIE (PERIPHERAL INTERRUPT EXPANSION)
PIEINTRS (12:1)
DINTCH (6:1)
ADCINT (8:1)
ADCINT (4:1)
MXINTA, MRINTA
TINT 0,1,2
I2CINT1A, I2CINT2A
SCIRXINTA, SCITXINTA
SPIRXINTA, SPITXINTA
EQEP(3:1)INT
C28x
CPU
C28x
TINT 0,1,2
XINT 2
DMA
XINT 1,2,3
EPWM(9:1)INT
EPWM(9:1)TZINT
ECAP(6:1)INT
SOCA (9:1), SOCB(9:1)
SOCA (9:1), SOCB(9:1)
C28 DMA BUS
C28 CPU BUS
TINT1
TINT2
C28x
VCU
C28x PERIPHERALS
PERIPHERAL
I/O s
EQEP
ERR
C28NMI
C28NMIINT
ECCDBLERR
EMUSTOP
PIENMIERR
GPTRIP
(12:1)
GPTRIP
(12:7)
GPTRIP
(6:4)
CLOCKFAIL
C28NMIRST
SOCAO
SOCBO
SYNCO
GPIO_MUX1
GPIO_MUX1
M3 CLOCKS
RESETS
M3 NMI
C28x NMI
Figure 8-2. Control Subsystem
8.4.2 C28x Core Hardware Built-In Self-Test
The Concerto microcontroller C28x CPU core includes a HWBIST feature for testing the CPU core logic for
errors. Tests using HWBIST can be initiated through a software library provided by TI.
8.4.3 C28x Peripheral Interrupt Expansion
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the F28M35x, 66 of the possible 96 interrupts are used. The 96
interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12).
Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the 96 interrupts has its own
vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched
by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save critical
CPU registers. Hence, the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled or disabled within the PIE block. See Table
8-16 for PIE interrupt assignments.
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Table 8-16. PIE Peripheral Interrupts
PIE INTERRUPTS
CPU
INTERRUPTS(1)
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
C28.LPMWAKE
(C28LPM)
TINT0
(TIMER 0)
0x0D4C
Reserved
–
0x0D4A
XINT2
–
0x0D48
XINT1
–
0x0D46
Reserved
–
0x0D44
ADCINT2
(ADC)
0x0D42
ADCINT1
(ADC)
0x0D40
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
0x0D4E
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
0x0D5E
0x0D5C
0x0D5A
0x0D58
0x0D56
0x0D54
0x0D52
0x0D50
EPWM8_INT
(ePWM8)
0x0D6E
EPWM7_INT
(ePWM7)
0x0D6C
EPWM6_INT
(ePWM6)
0x0D6A
EPWM5_INT
(ePWM5)
0x0D68
EPWM4_INT
(ePWM4)
0x0D66
EPWM3_INT
(ePWM3)
0x0D64
EPWM2_INT
(ePWM2)
0x0D62
EPWM1_INT
(ePWM1)
0x0D60
EPWM9_TZINT
(ePWM9)
Reserved
–
0x0D7C
ECAP6_INT
(eCAP6)
0x0D7A
ECAP5_INT
(eCAP5)
0x0D78
ECAP4_INT
(eCAP4)
0x0D76
ECAP3_INT
(eCAP3)
0x0D74
ECAP2_INT
(eCAP2)
0x0D72
ECAP1_INT
(eCAP1)
0x0D70
0x0D7E
EPWM9_INT
(ePWM9)
0x0D8E
Reserved
–
0x0D8C
Reserved
–
0x0D8A
Reserved
–
0x0D88
Reserved
–
0x0D86
EQEP3_INT
(eQEP3)
0x0D84
EQEP2_INT
(eQEP2)
0x0D82
EQEP1_INT
(eQEP1)
0x0D80
Reserved
–
0x0D9E
Reserved
–
0x0D9C
MXINTA
(McBSPA)
0x0D9A
MRINTA
(McBSPA)
0x0D98
Reserved
–
0x0D96
Reserved
–
0x0D94
SPITXINTA
(SPIA)
0x0D92
SPIRXINTA
(SPIA)
0x0D90
Reserved
–
0x0DAE
Reserved
–
0x0DAC
DINTCH6
(C28 DMA)
0x0DAA
DINTCH5
(C28 DMA)
0x0DA8
DINTCH4
(C28 DMA)
0x0DA6
DINTCH3
(C28 DMA)
0x0DA4
DINTCH2
(C28 DMA)
0x0DA2
DINTCH1
(C28 DMA)
0x0DA0
Reserved
–
0x0DBE
Reserved
–
0x0DBC
Reserved
–
0x0DBA
Reserved
–
0x0DB8
Reserved
–
0x0DB6
Reserved
–
0x0DB4
I2CINT2A
(I2CA)
0x0DB2
I2CINT1A
(I2CA)
0x0DB0
Reserved
–
0x0DCE
Reserved
–
0x0DCC
Reserved
–
0x0DCA
Reserved
–
0x0DC8
Reserved
–
0x0DC6
Reserved
–
0x0DC4
SCITXINTA
(SCIA)
0x0DC2
SCIRXINTA
(SCIA)
0x0DC0
ADCINT8
(ADC)
0x0DDE
ADCINT7
(ADC)
0x0DDC
ADCINT6
(ADC)
0x0DDA
ADCINT5
(ADC)
0x0DD8
ADCINT4
(ADC)
0x0DD6
ADCINT3
(ADC)
0x0DD4
ADCINT2
(ADC)
0x0DD2
ADCINT1
(ADC)
0x0DD0
Reserved
–
Reserved
–
Reserved
–
Reserved
–
MTOCIPCINT4
(IPC)
MTOCIPCINT3
(IPC)
MTOCIPCINT2
(IPC)
MTOCIPCINT1
(IPC)
0x0DEE
0x0DEC
0x0DEA
0x0DE8
0x0DE6
0x0DE4
0x0DE2
0x0DE0
C28RAMSINGER
R
LUF
(C28FPU)
0x0DFE
LVF
(C28FPU)
0x0DFC
EPI_INT
(EPI)
0x0DFA
C28RAMACCVIOL
(Memory)
Reserved
–
0x0DF4
C28FLSINGERR
(Memory)
XINT3
(Ext. Int. 3)
0x0DF0
INT12
(Memory)
0x0DF6
0x0DF8
0x0DF2
(1) Out of the 96 possible interrupts, 66 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
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8.4.4 C28x Direct Memory Access
The C28x DMA module provides a hardware method of transferring data between peripherals, between memory,
and between peripherals and memory without intervention from the CPU, thereby freeing up bandwidth for other
system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as the data is
transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into
blocks for optimal CPU processing. The interrupt trigger source for each of the six DMA channels can be
configured separately and each channel contains its own independent PIE interrupt to notify the CPU when a
DMA transfer has either started or completed. Five of the six channels are exactly the same, while Channel 1
has one additional feature: the ability to be configured at a higher priority than the others.
8.4.5 C28x Local Peripherals
The C28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI, SPI,
McBSP, I2C), an EPI, and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals are
accessible by the C28x CPU through the C28x Memory Bus. Additionally, the McBSP and ePWM are accessible
by the C28x DMA Bus. The EPI peripheral is also accessible from the Master Subsystem. The Serial Port
Peripherals and the Control Peripherals connect to the pins in Concerto through the GPIO_MUX1 block.
Internally, the C28x peripherals generate events to the PIE block, C28x DMA, and the Analog Subsystem. The
C28x NMI Watchdog receives a C28NMI event from the NMI block and sends a counter time-out event to the
Cortex-M3 NMI block and the Resets block to flag a potentially critical condition.
The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and EPWMxB.
These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and EMUSTOP events
from the C28x CPU, and up to 12 trips from GPIO_MUX1.
See Section 7.12 for more information on C28x peripherals.
8.4.6 C28x Local Memory
The C28x Local Memory includes Boot ROM; Secure Flash with ECC; Secure L0/L1 RAM with ECC; L2/L3 RAM
with Parity Error Checking; and M0/M1 with ECC. All local memories are accessible from the C28x CPU; the
L2/L3 RAM is also accessible by the C28x DMA. Two types of error correction events can be generated during
access of the C28x Local Memory: uncorrectable errors and single errors. The uncorrectable errors propagate to
the NMI block where they can become the C28NMI to the C28x NMI Watchdog and the C28NMIINT
nonmaskable interrupt to the C28x CPU. The less critical single errors go to the PIE block where they can
become maskable interrupts to the C28x CPU.
8.4.7 C28x Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into the Shared Resources and the Analog Subsystem.
The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and eight
individually configurable Shared RAM blocks.
The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have Parity-Error
Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the Control
Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM
Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having R/W
access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the Message
RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the Control Subsystem
side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way; however,
the direction of the data flow can be individually set for each block to be from Master to Control Subsystem or
from Control to Master Subsystem.
See Section 7.10 for more information on shared resources and analog peripherals.
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8.5 Analog Subsystem
The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed
through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of the
Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x CPU only.
The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through the C28x DMA
Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between CPU/DMA bus cycles of
the C28x Subsystem with those of the Cortex-M3 Subsystem. In addition to managing bus cycles, the ACIB also
transfers Start-Of-Conversion triggers to the Analog Subsystem and returns End-Of-Conversion ADC interrupts
to both the Master Subsystem and the Control Subsystem.
There are 22 possible Start-Of-Conversion (SOC) sources from the C28x Subsystem that are mapped to a total
of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).
Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from ADC2
are AND-ed together to form eight interrupts going to destinations in both the Master and Control Subsystems.
Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same eight go to the
C28x DMA.
The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2); six
Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with the two digital
subsystems of Concerto (Cortex-M3 and C28x).
Figure 8-3 shows the Analog Subsystem.
8.5.1 ADC1
The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are
currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H) units A and
B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in ADC1 result
registers. The two S/H units enable simultaneous sampling of two analog signals at a time. Additional channels
or channel pairs are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital
conversions. EOC interrupts from ADCs notify the Master and Control Subsystems that the conversion results
are ready to be read from ADC1 result registers. See Section 7.10.1 for more information on ADC peripherals.
8.5.2 ADC2
The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which 10 are
currently pinned out. The analog channels are internally preassigned to two S/H units A and B, both feeding an
Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2 result registers. The two
S/H units enable simultaneous sampling of two analog signals at a time. Additional channels or channel pairs
are converted sequentially. SOC triggers from the Control Subsystem initiate analog-to-digital conversions. EOC
interrupts from ADCs notify the Master and Control Subsystems that the conversion results are ready to be read
from ADC2 result registers. See Section 7.10.1 for more information on ADC peripherals.
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10
AIO_MUX1
GPIO
MUX
4
ANALOG
COMMON
INTERFACE
BUS
ADC1INA0
ADC1INB0
ADC1INB3
ADC1INB4
ADC1INB7
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ANALOG BUS
M3
M3
MCIBSTATUS REG
CPU
uDMA
TRIGS (8:1)
ADC
1
M3
SYSTEM
BUS
M3
uDMA
BUS
COMPA1
COMPA2
COMPA3
COMPB2
EOC
INTER-
RUPTS
(8:1)
ADC1INT (8:1)
ADC2INT (8:1)
VDDA
ADCINT(8:1)
(3.3V)
6
COMPARATOR
+ DAC UNITS
8
COMPOUT (6:1)
VSSA
(0V)
C28
CPU
BUS
C28
DMA
BUS
8
COMPA4
COMPB5
COMPA5
COMPA6
C28x
CPU
C28x
DMA
CCIBSTATUS REG
ADCINT
(4:1)
TRIGS (8:1)
ADC
2
SOC
TRIG-
GERS
(8:1)
TINT (2:0)
ADC2INA0
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
ADCEXTTRIG
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
SOC (9:1) A
SOC (9:1) B
TRIG8SEL REG
TRIG7SEL REG
. . .
GPIO
MUX
TRIG2SEL REG
TRIG1SEL REG
TIMER
(3)
EPWM
(9)
GPIO
4
AIO_MUX2
10
Figure 8-3. Analog Subsystem
8.5.3 Analog Comparator + DAC
There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs, resulting
in six digital comparison outputs. The external analog inputs that are being compared in the comparators come
from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared against each other or the
outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual Comparator modules. The six comparator
outputs go to the GPIO_MUX2 block where they can be mapped to six out of eight available pins.
To use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first routed externally from
pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before they can be assigned to
selected 12 ePWM Trip Inputs.
See Section 7.10.2 for more information on the analog comparator + DAC.
8.5.4 Analog Common Interface Bus
The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the Cortex-
M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers to the
Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3 uses its System
Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory Bus and the DMA bus to
access ADC Result registers and other registers of the Analog Subsystem. The ACIB arbitrates between up to
four possibly simultaneously occurring bus cycles on the Master/Control Subsystem side of ACIB to access the
ADC and Analog Comparator registers on the Analog Subsystem side.
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Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger destinations
inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC interrupt sources from
the Analog Subsystem to 8 destinations inside the Master and Control Subsystems. The eight ADC interrupts
are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC interrupts from ADC2. The total of 16
possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines because it is unlikely that any application
would need all 16 interrupts at the same time.
Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22 possible
trigger sources to each SOC trigger.
There are two registers that provide status of ACIB to the Master Subsystem and to the Control Subsystem.
The Cortex-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly powered up;
the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly
propagating between the Master, Control, and Analog subsystems.
The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered up; the
Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are correctly
propagating between the Master, Control, and Analog subsystems.
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8.6 Master Subsystem NMIs
The Cortex-M3 NMI Block generates an M3NMIINT nonmaskable interrupt to the Cortex-M3 CPU and an M3NMI
event to the NMI Watchdog in response to potentially critical conditions existing inside or outside the Concerto
MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address the NMI condition and
disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an M3NMIRST reset signal is sent to
the Resets block.
The inputs to the Cortex-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR,
EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI Watchdog;
C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter from counting out.
PIENMIERR indicates that an error condition was generated during the NMI vector fetch from the C28x PIE
block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a missing clock source to the
Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog Common Interface Bus. EXTGPIO
comes from the GPIO_MUX1 to announce an external emergency. MLBISTERR is generated by the Cortex-M3
core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR is generated by
the C28x core to signal that a BIST time-out or signature mismatch error has been detected.
The Cortex-M3 NMI block can be accessed through the Cortex-M3 NMI configuration registers—including the
MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the
flags, and force the flags to active state, respectively.
Figure 8-4 shows the Cortex-M3 NMI and C28x NMI.
8.7 Control Subsystem NMIs
The C28x NMI Block generates a C28NMIINT nonmaskable interrupt to the C28x CPU and a C28NMI event to
the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto MCU. When
able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition and disable the C28x
NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the C28NMIRST reset signal is sent to the
Resets block and the Cortex-M3 NMI Block, where the Cortex-M3 NMI Block can generate an NMI to the Cortex-
M3 processor.
The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR,
PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks Block,
announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the
Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the occurrence of
uncorrectable error conditions during access to the Flash or RAM (local or shared). PIENMIERR indicates that
an error condition was generated during NMI vector fetch from the C28x PIE block. MLBISTERR is generated by
the Cortex-M3 core to signal that a BIST time-out or signature mismatch error has been detected. CLBISTERR
is generated by the C28x core to signal that a BIST time-out or signature mismatch error has been detected.
The C28x NMI block can be accessed through the C28x NMI configuration registers—including the CNMIFLG,
CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags, and force
the flags to active state, respectively.
Figure 8-4 shows the Cortex-M3 NMI and C28x NMI.
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M3
1.2V
M3 NMI
WDOG
M3 WDOG
(2)
BIST
VREG
M3BISTERR
VREGWARN
M3NMI
M3NMIRST
M3WDRST (1:0)
NMI
M3BISTERR
M3NMI
M3EXTNMI
GPIO_MUX
C28BISTERR
M3NMIINT
C28NMIRST
M3 NMI
M3 CPU
ACIBERR
ANALOG
M3WDRST (1:0)
M3NMIRST
SUBSYSTEM
RESETS
C28NMIRST
CLOCKFAIL
CLOCKS
PIENMIERR
M3BISTERR
C28NMIINT
C28NMI
C28x CPU
RAMUNCERR
C28x NMI
SHARED RAM
C28BISTERR
C28x LOCAL
RAM
C28BISTERR
FLASHUNCERR
C28NMI
C28NMIRST
C28x NMI
WDOG
C28x
BIST
C28x
FLASH
Figure 8-4. Cortex-M3 NMI and C28x NMI
8.8 Resets
The Concerto MCU has two external reset pins: XRS for the Master and Control Subsystems and ARS for the
Analog Subsystem. TI recommends that these two pins be externally tied together with a board signal trace.
The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal
out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control Subsystems. A
reset pulse can also be driven out of the XRS pin by the Power-On Reset (POR) block of the Master and Control
Subsystems (see Section 8.9). A reset pulse can be driven out of the XRS pin when the two Cortex-M3
Watchdogs or the Cortex-M3 NMI Watchdog time-out.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is stable. This
requirement is to enable the entire device to start from a known condition.
2. TI recommends that no voltage larger than 0.7 V be applied to any pin before powering up the device.
Voltages applied to pins on an unpowered device can lead to unpredictable results.
The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset signal
out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A reset pulse
can be driven out of the ARS pin by the POR block of the Analog Subsystem.
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Figure 8-5 shows the resets.
8.8.1 Cortex-M3 Resets
The Cortex-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR or the
M3SYSRST reset signal. In both cases, the Cortex-M3 CPU restarts program execution from the address
provided by the reset entry in the vector table. A register can later be referenced to determine the source of the
reset. The M3SYSRST signal also propagates to the Cortex-M3 peripherals and the rest of the Cortex-M3
Subsystem.
The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The M3WDOGS
is set in response to time-out conditions of the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog. The
M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset
that is also output by the NVIC. In addition to driving M3SYSRST, these two resets also propagate to the C28x
Subsystem and the Analog Subsystem.
The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from the
Cortex-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface Bus. In
addition to driving reset signals to other parts of the chip, the Cortex-M3 can also detect a C28SYSRST reset
being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS register.
Cortex-M3 software can also set bits in the SRCR register to selectively reset individual Cortex-M3 peripherals,
provided they are enabled inside the DC (Device Configuration) register. The Reset Cause register (MRESC)
can be read to find out if the latest reset was caused by External Reset, POR, Watchdog Timer 0, Watchdog
Timer 1, or Software Reset from NVIC.
M3 WDOG (1)
M3WDOGS
M3 WDOG (0)
JTAG
CRESSTS REG
CONTROLLER
M3 BIST
MLBISTRST
( SETS DEFAULT VALUES ) XRS
SOFTWARE
CRESCNF REG
M3PORRST
POR
VOLTAGE
REGULATION
AND
M3
M3
M3
NMI
POWER-ON-RESET
XRS
NVIC
CPU
WDOG
M3SYSRST
XRS
FLASH PUMP
M3SYSRST
M3SWRST
M3DBGRST
PERIPHERAL SOFTWARE RESETS
SRCR REG
M3
SUBSYSTEM
MRESC REG
DC REG
CONTAINS RESET CAUSES
GLOBAL PERIPHERAL ENABLES
ARS
PIN
ACIBRST
SRXRST
ANALOG
SUBSYSTEM
XRS
GPIO_MUX
SHARED
RESOURCES
M3WDOGS
POR
C28x BIST
CLBISTRST
C28x
SUBSYSTEM
‘0’
XRS
PIN
C28RSTIN
C28SYSRST
XRS
C28x
CPU
SYNC
DEGLITCH
M3SSCLK
C28x
NMI
XRS
WDOG
RESET INPUT SIGNAL STATUS
C28NMIWD
DEVICECNF REG
Figure 8-5. Resets
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8.8.2 C28x Resets
The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x
Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the address
provided at the top of the Boot ROM Vector Table.
The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the M3RSNIN. The
C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The M3SWRST is a software-
generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the
NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the C28x
Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to selectively reset the C28x Subsystem
from Cortex-M3 software.
The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin by
reading the DEVICECNF register.
8.8.3 Analog Subsystem and Shared Resources Resets
Both the Analog Subsystem and the resources shared between the C28x and Cortex-M3 subsystems (IPC, MSG
RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog Subsystem is also reset by
the internal ACIBRST signal from the Cortex-M3 Subsystem and the external ARS pin, (should be externally tied
to the XRS pin), which can be reset by the POR circuitry.
The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a software-
generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also output by the
NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to propagate to the Analog
Subsystem and the Shared Resources.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is
reset by M3SYSRST.
8.8.4 Device Boot Sequence
The boot sequence of Concerto is used to configure the Master Subsystem and the Control Subsystem for
execution of application code. The boot sequence involves both internal resources, and resources external to
the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factory-programmed
inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code (C-Bootloader)
factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four GPIO_MUX pins for Master
boot mode selection; internal Flash and RAM memories; and selected Cortex-M3 and C28x peripherals for
loading the application code into the Master and Control Subsystems.
The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by device
power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3 NMI
watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and then both
bootloaders work in tandem to configure the device, load application code for both processors (if not already in
the Flash), and branch the execution of each processor to a selected location in the application code.
Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive state. At
that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until the Master
Subsystem takes them out of reset. The M-Bootloader first initializes some device-level functions, then the M-
Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the Control Subsystem and the
Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out of reset, its own C-Bootloader
starts executing in parallel with the M-Bootloader. After initializing the Control Subsystem, the C-Bootloader
enters the C28x processor into the IDLE mode (to wait for the M-Bootloader to wake up the C28x processor later
through the MTOCIPC1 interrupt). Next, the M-Bootloader reads four GPIO pins (see Table 8-17) to determine
the boot mode for the rest of the M-Bootloader operation.
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Table 8-17. Master Subsystem Boot Mode Selection
BOOT
PF2_GPIO34
PF3_GPIO35
PG7_GPIO47
PG3_GPIO43
MASTER SUBSYSTEM BOOT MODES
(3)
MODE NO.(1)
(Bmode_pin4)(2)
(Bmode_pin3)(2)
(Bmode_pin2)(2)
(Bmode_pin1)(2)
0
1
Boot from Parallel GPIO
0
0
0
0
0
0
0
1
Boot to Master Subsystem RAM
Boot from Master Subsystem serial peripherals
(UART0/SSI0/I2C0)
2
0
0
1
0
3
4
Boot from Master Subsystem CAN interface
Boot from Master Subsystem Ethernet interface
Not supported (Defaults to Boot-to-Flash)
Boot-to-OTP
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
5
6(5)
7
8(4)
Boot to Master Subsystem Flash memory
Not supported (Defaults to Boot-to-Flash)
Boot from Master Subsystem serial peripheral –
SSI0 Master
9(4)
1
1
0
0
0
1
1
0
Boot from Master Subsystem serial peripheral –
I2C0 Master
10(4)
11(4)
12(4)
13(4)
14(4)
15(4)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
Not supported (Defaults to Boot-to-Flash)
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
(1) Silicon revision A allows the user to change the GPIO pins used to determine the boot mode. Silicon revision 0 does not have this
option. See the Concerto F28M35x Technical Reference Manual for additional information.
(2) By default, GPIO terminals are not pulled up (they are floating).
(3) On silicon revision 0, PF2_GPIO34 is a "don't care". So, the state of PF2_GPIO34 should not affect boot mode selection.
(4) Boot Modes 8–15 are not supported on silicon revision 0.
(5) Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash.
Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the Master
Flash memory. This branching requires that the Master Flash be already programmed with valid code; otherwise,
a hard fault exception is generated and the Cortex-M3 goes back to the above reset sequence. (Therefore, for a
factory-fresh device, the M-Bootloader will be in a continuous reset loop until the JTAG debug probe is
connected and a debug session started.) If the Master Subsystem Flash has already been programmed, the
application code will start execution. Typically, the Master Subsystem application code will then establish data
communication with the C28x [through the IPC (Interprocessor Communications peripheral)] to coordinate the
rest of the boot process with the Control Subsystem. Following reset, the internal pullup resistors on GPIOs are
disabled. Therefore, Boot Mode 15, for example, will typically require four external pullups.
Boot Mode 1 causes the Master boot program to branch to Cortex-M3 RAM, where the Cortex-M3 processor
starts executing code that has been preloaded earlier. Typically, this mode is used during development of
application code meant for Flash, but which has to be first tested running out of RAM. In this case, the user
would typically load the application code into RAM using the debugger, and then issue a debugger reset, while
setting the four boot pins to 0001b. From that point on, the rest of the boot process on the Master Subsystem
side is controlled by the application code.
Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external peripheral
before branching to the application code. This process is different from the process in Boot Modes 1, 7, and 15,
where the application code was either already programmed in Flash or loaded into RAM by the JTAG debug
probe. If the boot mode selection pins are set to 0000b, the M-Bootloader (running out of M-Boot ROM) will start
uploading the Master application code from preselected Parallel GPIO_MUX pins. If the boot pins are set to
0010b, the application code will be loaded from the Master Subsystem UART0, SSI0, or I2C0 peripheral. (SSI0
and I2C0 are configured to work in Slave mode in this Boot Mode.) If the boot pins are set to 0011b, the
application code will be loaded from the Master Subsystem CAN interface. Furthermore, if the boot pins are set
to 0100b, the application code will be loaded through the Master Subsystem Ethernet interface; the IOs used in
this Boot Mode are compatible with the F28M35x device. If the boot pins are set to 1001b or 1010b, then the
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application code will be loaded through the SSI0 or I2C0 interface, respectively. SSI0 and I2C0 loaders work in
Master Mode in this boot mode.
Regardless of the type of boot mode selected, once the Master application code is resident in Master Flash or
RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the application code
takes over control from the M-Bootloader, and the boot process continues as prescribed by the application code.
At this stage, the Master application program typically establishes communication with the C-Bootloader, which
by now, would have already initialized the Control Subsystem and forced the C28x to go into IDLE mode. To
wake the Control Subsystem out of IDLE mode, the Master application issues the Master-to-Control-IPC-
interrupt 1 (MTOCIPCINT1). Once the data communication has been established through the IPC, the boot
process can now also continue on the Control Subsystem side.
The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing IPC
instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and acting on them
to continue the boot process. At this stage, a boot mode for the Control Subsystem can be established. The
Control Subsystem boot modes are similar to the Master Subsystem boot modes, except for the mechanism by
which they are selected. The Control Subsystem boot modes are chosen through the IPC commands from the
Master application code to the C-Bootloader, which interprets them and acts accordingly. The choices are, as
above, to branch to already existing Control application code in Flash, to branch to preloaded code in RAM
(development mode), or to upload the Control application code from one of several available peripherals (see
Table 8-18). As before, once the Control application code is in place (in Flash or RAM), the C-Bootloader
branches to Flash or RAM, and from that point on, the application code takes over.
Table 8-18. Control Subsystem Boot Mode Selection
CONTROL SUBSYSTEM
BOOT MODES
MTOCIPCBOOTMODE
REGISTER VALUE
DESCRIPTION
Upon receiving this command from the Master Subsystem, C-Boot
ROM will branch to the Control Subsystem RAM entry point location
and start executing code from there.
BOOT_FROM_RAM
0x0000 0001
0x0000 0002
Upon receiving this command, C-Boot ROM will branch to the
Control Subsystem FLASH entry point and start executing code from
there.
BOOT_FROM_FLASH
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SCI peripheral.
BOOT_FROM_SCI
BOOT_FROM_SPI
BOOT_FROM_I2C
0x0000 0003
0x0000 0004
0x0000 0005
0x0000 0006
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SPI interface.
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem I2C interface.
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem GPIO.
BOOT_FROM_PARALLEL
The boot process can be considered completed once the Cortex-M3 and C28x are both running out of their
respective application programs. Following the boot sequence, the C-Bootloader is still available to interpret and
act upon an assortment of IPC commands that can be issued from the Master Subsystem to perform a variety of
configuration, housekeeping, and other functions. See the Concerto F28M35x Technical Reference Manual for
additional information on Concerto boot modes, IPC commands, and the underlying boot philosophy.
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8.9 Internal Voltage Regulation and Power-On-Reset Functionality
While the analog functions of Concerto draw power from a single dedicated external power source—VDDA, its
digital circuits are powered by three separate rails: 3.3-V VDDIO, 1.8-V VDD18, and 1.2-V VDD12. This section
describes the sourcing, regulation, and POR functionality for these three digital power rails.
Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the
Cortex-M3-based Master Subsystem and the C28x-based Control Subsystem). The Digital Subsystem uses
VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses VDD18 to
power the digital logic associated with the analog functions. Both Digital and Analog Subsystems share a
common VDDIO rail to power their 3.3-V I/O buffers through which the Concerto digital signals communicate with
the outside world.
The Analog and Digital Subsystems each have their own POR circuits that operate independently. With the ARS
and XRS reset pins externally tied together, both systems can come out of reset together, and can also be put in
reset together by driving both reset pins low. See Figure 8-6 for a snapshot of the voltage regulation and POR
functions provided within the Analog and Digital Subsystems of Concerto.
8.9.1 Analog Subsystem: Internal 1.8-V VREG
The internal 1.8-V Voltage Regulator (VREG) generates VDD18 power from VDDIO. The 1.8-V VREG is enabled
by pulling the VREG18EN pin to a low state. When enabled, the 1.8V VREG provides 1.8 V to digital logic
associated with the analog functions of the Analog Subsystem.
When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided externally;
however, a 1.2-µF (10% tolerance) capacitor is required for each VDD18 pin to stabilize the internally generated
voltages. These load capacitors are not required if the internal 1.8-V VREG is disabled, and the 1.8 V is provided
from an external supply.
While removing the need for an external power supply, enabling the internal VREG might affect the VDDIO power
consumption.
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CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE
ARS
PIN
XRS
PIN
CONCERTO
DEVICE
M3WDOGS
POR
ARS
XRS
DEGLITCH
DEGLITCH
‘0’
‘0’
POWER-ON-RESET
POWER-ON-RESET
(ANALOG SUBSYSTEM)
(DIGITAL SUBSYSTEM)
3.3 V
POR
1.8-V
POR
3.3-V
POR
3.3-V
POR
1.2-V
POR
1.8 V
1.2 V
DIGITAL LOGIC
M3 CPU
M3 NMI
(DIGITAL SUBSYSTEM)
M3
M3 WDOGS
(0,1)
M3 NMI
WDOG
NVIC
DIGITAL LOGIC
RESETS
(ANALOG SUBSYSTEM)
ACIBRST M3RSNIN
CONTROL
SUB-
I/O
I/O
SYSTEM
RST
1.8 V
1.2 V
CRESCNF REG
1.8 V
3.3 V
1.2 V
3.3 V
1.8-V VREG
1.2-V VREG
(ANALOG SUBSYSTEM)
(DIGITAL SUBSYSTEM)
1.8-V
SUPPLY SUPPLY SUPPLY
PINS PINS PINS
3.3-V
1.2-V
VREG18EN
PIN
VREG12EN
PIN
Figure 8-6. Voltage Regulation and Monitoring
8.9.2 Digital Subsystem: Internal 1.2-V VREG
The internal 1.2-V VREG generates VDD12 power from VDDIO. The 1.2-V VREG is enabled by pulling the
VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic
associated with the processors, memory, and peripherals of the Digital Subsystem.
When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided externally;
however, the minimum and maximum capacitance required for each VDD12 pin to stabilize the internally
generated voltages are 250 nF and 750 nF, respectively. These load capacitors are not required if the internal
1.2-V VREG is disabled and the 1.2 V is provided from an external supply.
While removing the need for an external power supply, enabling the internal VREG might affect the VDDIO power
consumption.
8.9.3 Analog and Digital Subsystems: Power-On-Reset Functionality
The Analog and Digital Subsystems' each have a POR circuit that creates a clean reset throughout the device
enabling glitchless GPIOs during the power-on procedure. The POR function keeps both ARS and XRS driven
low during device power up. This functionality is always enabled, even when VREG is disabled.
While in most applications, the POR generated reset has a long enough duration to also reset other system ICs,
some applications may require a longer lasting pulse. In these cases, the ARS and XRS reset pins (which are
open-drain) can also be driven low to match the time the device is held in reset state with the rest of the system.
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When POR drives the the ARS and XRS pins low, the POR also resets the digital logic associated with both
subsystems and puts the GPIO pins in a high impendance state.
In addition to the POR reset, the Resets block of the Digital Subsystem also receives reset inputs from the NVIC,
the Cortex-M3 Watchdogs (0, 1), and from the Cortex-M3 NMI Watchdog. The resulting reset output signal is
then fed back to the XRS pin after being AND-ed with the POR reset (see Figure 8-6).
On a related note, only the Master Subsystem comes out of reset state immediately following a device power up.
The Control and Analog Subsystems continue to be held in reset until the Master Processor (Cortex-M3) brings
them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the CRESCNF Register (see Figure
8-6).
8.9.4 Connecting ARS and XRS Pins
In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external means
such as through a signal trace on a PCB board. Tying the ARS and XRS pins together ensures that all reset
sources will cause both the Analog and Digital Subsystems to enter the reset state together, regardless of where
the reset condition occurs.
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8.10 Input Clocks and PLLs
Concerto devices have multiple input clock pins from which all internal clocks and the output clock are derived.
Figure 8-7 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2
and XCLKIN.
CONCERTO DEVICE
CONCERTO DEVICE
X1
X2
X1
X2
v
v
ssosc
ssosc
RESONATOR
CRYSTAL
R
C
C
D
L2
L1
CONCERTO DEVICE
CONCERTO DEVICE
X1
X2
XCLKIN
v
ssosc
NC
3.3V
CLK
3.3V
CLK
VDD
OUT
GND
VDD
OUT
GND
3.3V OSCILLATOR
3.3V OSCILLATOR
Figure 8-7. Connecting Input Clocks to a Concerto™ Device
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8.10.1 Internal Oscillator (Zero-Pin)
Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency clocks:
10MHZCLK and 32KHZCLK. These clocks are not configurable by the user and should not be used to clock the
device during normal operation. They are used inside the Master Subsystem to implement low-power modes.
The 10MHZCLK is also used by the Missing Clock Detect circuit.
8.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC
)
The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used (version
of a crystal with built-in load capacitors), its ground terminal should be connected to the pin VSSOSC (not board
ground). The VSSOSC pin should also be used to ground the external load capacitors connected to the two crystal
terminals as shown in Figure 8-7.
8.10.3 External Oscillators (Pins X1 and XCLKIN)
Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external oscillators
or other clock sources. When connecting an external clock source through the X1 terminal, the X2 terminal
should be left unconnected. Most internal clocks of this device are derived from the X1 clock input (or X1/X2
crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 8-7 shows how to
connect external oscillators to the X1 and XCLKIN terminals.
Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be an
isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer. Spacing
should be kept minimal, with any other nearby traces double-spaced away, so that the electromagnetic fields
created by the two opposite currents cancel each other out as much as possible, thus reducing parasitic
inductances that radiate EMI.
8.10.4 Main PLL
The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external crystal/resonator).
The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the SPLLIMULT
and SPLLFMULT fields of the SYSPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer
multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the Main PLL must be
between 150 MHz and 300 MHz. The PLL output clock is then divided by 2 before entering a mux that selects
between this clock and the PLL input clock – OSCCLK (used in PLL bypass mode). The PLL bypass mode is
selected by setting the SPLLIMULT field of the SYSPLLMULT register to 0. The output clock from the mux next
enters a divider controlled by the SYSDIVSEL register, after which the output clock becomes the PLLSYSCLK.
Figure 8-8 shows the Main PLL function and configuration examples. Table 8-19 to Table 8-22 list the integer
multiplier configuration values.
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SYSPLLMULT REG
SYSPLLCTL REG
SYSDIVSEL REG
(2)
SPLLIMULT
SPLLFMULT
SPLLEN
SPLLCLKEN
SYSDIVSEL (1:0)
= 00 ( /1 )
OSCCLK
0
7
2
/1
/2
/4
/8
MAIN PLL
PLLSYSCLK
PIN
X1
INTEGER
FRACTIONAL
MULTIPLIER
MULTIPLIER
MAIN
OSC
/2
1
OSCCLK
0000000 : ´ 1
0000001 : ´ 1
OUPUT OF
MAIN PLL
0000010 : ´ 2
00: NOT USED
0000011 : ´ 3
01:
10:
11:
´ 0.25
´ 0.50
´ 0.75
IS ALWAYS
DIVIDED BY 2
.
.
.
1111101: ´ 125
1111110: ´ 126
1111111: ´ 127
(1) OUTPUT OF THE MAIN PLL MUST RANGE BETWEEN 150–300 MHz.
(2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF.
EXAMPLE 1:
EXAMPLE 2:
EXAMPLE 3:
X1 = 100 MHZ
X1 = 10 MHz
X1 = 10 MHz
SPLLIMULT = 0000000 ( BYPASS PLL)
N/A
PLLSYSCLK = 100 MHz
PLLSYSCLK = [ ( 10 ´ 20)
PLLSYSCLK = [ ( 10 ´ 20.5)
SPLLIMULT = 0010100 ( ´ 20 )
SPLLIMULT = 0010100 ( ´ 20 )
SPLLFMULT = 00 ( NOT USED)
/ 2 ] / 1 = 100 MHz
/ 2 ] / 1 = 102.5 MHz
SPLLFMULT = 10 ( ´ 0.50)
Figure 8-8. Main PLL
Table 8-19. Main PLL Integer Multiplier
Configuration
(Bypass PLL to × 31)
SPLLIMULT(6:0)
0000000 b
0000001 b
0000010 b
0000011 b
0000100 b
0000101 b
0000110 b
0000111 b
MULT VALUE
Bypass PLL
× 1
× 2
× 3
× 4
× 5
× 6
× 7
0001000 b
0001001 b
0001010 b
0001011 b
0001100 b
0001101 b
0001110 b
0001111 b
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
0010000 b
0010001 b
0010010 b
0010011 b
0010100 b
× 16
× 17
× 18
× 19
× 20
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Table 8-19. Main PLL Integer Multiplier
Configuration
(Bypass PLL to × 31) (continued)
SPLLIMULT(6:0)
MULT VALUE
0010101 b
× 21
0010110 b
× 22
0010111 b
× 23
0011000 b
0011001 b
0011010 b
0011011 b
0011100 b
0011101 b
0011110 b
0011111 b
× 24
× 25
× 26
× 27
× 28
× 29
× 30
× 31
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Table 8-20. Main PLL Integer Multiplier
Configuration
(× 32 to × 63)
SPLLIMULT(6:0)
0100000 b
0100001 b
0100010 b
0100011 b
0100100 b
0100101 b
0100110 b
0100111 b
MULT VALUE
× 32
× 33
× 34
× 35
× 36
× 37
× 38
× 39
0101000 b
0101001 b
0101010 b
0101011 b
0101100 b
0101101 b
0101110 b
0101111 b
× 40
× 41
× 42
× 43
× 44
× 45
× 46
× 47
0110000 b
0110001 b
0110010 b
0110011 b
0110100 b
0110101 b
0110110 b
0110111 b
× 48
× 49
× 50
× 51
× 52
× 53
× 54
× 55
0111000 b
0111001 b
0111010 b
0111011 b
0111100 b
0111101 b
0111110 b
0111111 b
× 56
× 57
× 58
× 59
× 60
× 61
× 62
× 63
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Table 8-21. Main PLL Integer Multiplier
Configuration
(× 64 to × 95)
SPLLIMULT(6:0)
1000000 b
1000001 b
1000010 b
1000011 b
1000100 b
1000101 b
1000110 b
1000111 b
MULT VALUE
× 64
× 65
× 66
× 67
× 68
× 69
× 70
× 71
1001000 b
1001001 b
1001010 b
1001011 b
1001100 b
1001101 b
1001110 b
1001111 b
× 72
× 73
× 74
× 75
× 76
× 77
× 78
× 79
1010000 b
1010001 b
1010010 b
1010011 b
1010100 b
1010101 b
1010110 b
1010111 b
× 80
× 81
× 82
× 83
× 84
× 85
× 86
× 87
1011000 b
1011001 b
1011010 b
1011011 b
1011100 b
1011101 b
1011110 b
1011111 b
× 88
× 89
× 90
× 91
× 92
× 93
× 94
× 95
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Table 8-22. Main PLL Integer Multiplier
Configuration
(× 96 to × 127)
SPLLIMULT(6:0)
1100000 b
1100001 b
1100010 b
1100011 b
1100100 b
1100101 b
1100110 b
1100111 b
MULT VALUE
× 96
× 97
× 98
× 99
× 100
× 101
× 102
× 103
1101000 b
1101001 b
1101010 b
1101011 b
1101100 b
1101101 b
1101110 b
1101111 b
× 104
× 105
× 106
× 107
× 108
× 109
× 110
× 111
1110000 b
1110001 b
1110010 b
1110011 b
1110100 b
1110101 b
1110110 b
1110111 b
× 112
× 113
× 114
× 115
× 116
× 117
× 118
× 119
1111000 b
1111001 b
1111010 b
1111011 b
1111100 b
1111101 b
1111110 b
1111111 b
× 120
× 121
× 122
× 123
× 124
× 125
× 126
× 127
8.10.5 USB PLL
The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or the
internal OSCCLK (originating from the external crystal or oscillator through the X1/X2 pins). An input mux selects
the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL Register (see Figure 8-9).
The input clock is multiplied by an integer multiplier and a fractional multiplier as selected by the UPLLIMULT
and UPLLFMULT fields of the UPLLMULT register. For example, to achieve PLL multiply of 28.5, the integer
multiplier should be set to 28, and the fractional multiplier to 0.5. The output clock from the USB PLL must
always be 240 MHz. The PLL output clock is then divided by 4—resulting in 60 MHz that the USB needs—before
entering a mux that selects between this clock and the PLL input clock (used in the PLL bypass mode). The PLL
bypass mode is selected by setting the UPLLIMULT field of the UPLLMULT register to 0. The output clock from
the mux becomes the USBPLLCLK (there is not another clock divider). Figure 8-9 shows the USB PLL function
and configuration examples. Table 8-23 and Table 8-24 list the integer multiplier configuration values.
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UPLLMULT REG
UPLLCTL REG
(2)
UPLLCLKSRC
UPLLIMULT
UPLLFMULT
UPLLEN
UPLLCLKEN
0
6
2
PIN
X1
USB PLL
USBPLLCLK
OSCCLK
XCLKIN
MAIN
OSC
0
INTEGER
FRACTIONAL
MULTIPLIER
MULTIPLIER
/4
1
PLLINP
000000 : ´ 1
000001 : ´ 1
OUPUT OF
1
000010 : ´ 2
00: NOT USED
THE USB PLL
IS ALWAYS
000011 : ´ 3
01:
10:
11:
´ 0.25
´ 0.50
´ 0.75
PIN
.
.
.
DIVIDED BY 4
XCLKIN
111101: ´ 61
111110: ´ 62
111111: ´ 63
(1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLCLK IS 60MHZ )
(2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF
EXAMPLE 1:
EXAMPLE 2:
EXAMPLE 3:
X1 OR XCLKIN = 60 MHZ
X1 OR XCLKIN = 10 MHz
X1 OR XCLKIN = 64 MHz
UPLLIMULT = 000000 ( BYPASS PLL)
UPLLIMULT = 011000 ( ´ 24 )
UPLLIMULT = 000011 ( ´ 3)
N/A
PLLSYSCLK = 60 MHz
PLLSYSCLK ( 10 ´ 24)
PLLSYSCLK = ( 64 ´ 3.75 )
UPLLFMULT = 00 ( NOT USED)
=
/ 4 = 60 MHz
/ 4 = 60 MHz
UPLLFMULT = 11 ( ´ 0.75)
Figure 8-9. USB PLL
Table 8-23. USB PLL Integer Multiplier Configuration
(Bypass PLL to × 31)
SPLLIMULT(5:0)
000000 b
000001 b
000010 b
000011 b
MULT VALUE
Bypass PLL
× 1
× 2
× 3
× 4
× 5
× 6
× 7
000100 b
000101 b
000110 b
000111 b
001000 b
001001 b
001010 b
001011 b
001100 b
001101 b
001110 b
001111 b
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
010000 b
010001 b
010010 b
× 16
× 17
× 18
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Table 8-23. USB PLL Integer Multiplier Configuration
(Bypass PLL to × 31) (continued)
SPLLIMULT(5:0)
MULT VALUE
010011 b
× 19
010100 b
× 20
010101 b
× 21
010110 b
× 22
010111 b
× 23
011000 b
011001 b
011010 b
011011 b
011100 b
011101 b
011110 b
011111 b
× 24
× 25
× 26
× 27
× 28
× 29
× 30
× 31
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Table 8-24. USB PLL Integer Multiplier Configuration
(× 32 to × 63)
SPLLIMULT(5:0)
100000 b
100001 b
100010 b
100011 b
MULT VALUE
× 32
× 33
× 34
× 35
100100 b
100101 b
100110 b
× 36
× 37
× 38
100111 b
× 39
101000 b
101001 b
101010 b
101011 b
101100 b
101101 b
101110 b
101111 b
× 40
× 41
× 42
× 43
× 44
× 45
× 46
× 47
110000 b
110001 b
110010 b
110011 b
110100 b
110101 b
110110 b
110111 b
× 48
× 49
× 50
× 51
× 52
× 53
× 54
× 55
111000 b
111001 b
111010 b
111011 b
111100 b
111101 b
111110 b
111111 b
× 56
× 57
× 58
× 59
× 60
× 61
× 62
× 63
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8.11 Master Subsystem Clocking
The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divided-down
output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the SYSPLLCTL register.
There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The
10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source to the
Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the 10MHZCLK
for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control Subsystem where this
signal can trip the ePWM peripherals.
The 32KHZCLK and 10MHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources for the
Deep Sleep Clock.
There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and
SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has read
access. The C28x can request write access to the above registers through the CLKREQEST register. Cortex-M3
can regain write ownership of these registers through the MCLKREQUEST register.
The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode. Table
8-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and peripherals.
Figure 8-10 shows the Cortex-M3 clocks and the Master Subsystem low-power modes.
Table 8-25. Master Subsystem Low-Power Modes
REGISTER USED
TO GATE CLOCKS MAIN
TO Cortex-M3
PERIPHERALS
Cortex-M3
LOW-POWER
MODE
CLOCK TO
Cortex-M3
PERIPHERALS
CLOCK TO
SHARED
RESOURCES
CLOCK TO
ANALOG
SUBSYSTEM
STATE OF
Cortex-M3 CPU
USB
PLL
CLOCK TO C28x
PLL
Run
Sleep
Active
M3SSCLK(1)
M3SSCLK(1)
RCGC
On
On
Off
On
On
Off
PLLSYSCLK(2)
PLLSYSCLK(2)
Off
PLLSYSCLK(2)
PLLSYSCLK(2)
Off
ASYSCLK(3)
ASYSCLK(3)
Off
Stopped
Stopped
RCGC or SCGC(4)
RCGC or DCGC(4)
Deep Sleep
M3DSDIVCLK(5)
(1) PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes
10MHZCLK divided-down per the M3SSDIVSEL register.
(2) PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed,
the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK
is substituted for the PLLSYSCLK.
(3) PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes
10MHZCLK.
(4) Depends on the ACG bit of the RCC register.
(5) 32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL
register (source determined inside the DSLPCLKCFG register).
Figure 8-11 shows the system clock/PLL.
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M3 CPU
INTR
ASSERT ANY INTERRUPT
NVIC
TO EXIT SLEEP OR DEEP SLEEP
execution of WFI or WFE instr
activates low power modes
REGISTER
ACCESS
REGISTER
ACCESS
SELECTS TYPE
OF WAKEUP
SLEEPEXIT
FCLK
HCLK
M3CLKENBx
M3SSCLK
M3SSCLK
M3SSCLK
PERIPH
LOGIC
SYSCTRL REG
OSCCLK
M3SSCLK
WDOG 1
SELECTS BETWEEN SLEEP
AND DEEP SLEEP MODES
SLEEPDEEP
WDOG 0
uCRC
ENTER A LOW POWER MODE
M3SSCLK
RCC REG
ENABLE
CLOCK MODE
PERIPH
LOGIC
OSCCLK
XCLKIN
CAN
1,2
ACG (Auto Clock Gate)
CLOCKS
NMI WDOG
GP TIMER (4)
SSI (4)
M3RUN
PERIPHERAL
CLOCK
M3SLEEP
M3CLKENBx
USB + PHY
(OTG)
M3DEEPSLEEP
ENABLES
USBPLLCLK
( CLOCK GATING – RUN )
( CLOCK GATING – SLEEP )
RCGC REG
SCGS REG
M3DEEPSLEEP
USB PLL
( CLOCK GATING – DEEP SLEEP )
DCGC REG
DC REG
UART (5)
DSLPCLKCFG REG
DSOSCSRC
M3SSDIVSEL REG
OSCCLK
XCLKIN
( GLOBAL PERIPHERAL ENABLES )
DSDIVOVRIDE
M3SSDIVSEL
2
I C (2)
32KHZCLK
10MHZCLK
OSCCLK
/1
/2
…
/1
/2
/4
M3DSDIVCLK
1
0
M3SSCLK
OSCCLK
EMAC
EPI
/16
XCLKIN
GPIO_MUX1
MCLKREQUEST REG
SYSDIVSEL REG
uDMA
SYSDIVSEL
SYSPLLSTAT REG
SYSPLLMULT REG
SYSPLLCTL REG
32KHZCLK
10MHZCLK
OSCCLK
IPC
X2
X1
M3SSCLK
MAIN OSC
OFF
OSCCLK
/2
SHARED
RAMS
1
0
PLLSYSCLK
0
1
/1
/2
/4
/8
INTERNAL
OSC
MISSING
MAIN PLL
CLK DETECT
MSG
RAMS
10MHZCLK
CLOCKFAIL
CLOCKFAIL
CLPMSTAT REG
M3 NMI
SHARED
10MHZCLK
CLOCKFAIL
OSCCLK
RESOURCES
CONTROL SUBSYSTEM
Figure 8-10. Cortex-M3 Clocks and Low-Power Modes
PLLSYSCLK
150 MHz Max
/1
/1
/2
XPLLCLKOUT Pin
100 MHz Max
OSCCLK
/2
/4*
0*
1
/4
System
PLL
/1
/8*
Master (M3)
Subsystem
/2
/4*
M3 Read/Write
C28 Read Only**
150 MHz Max
/1
on*
off
Control (C28)
Subsystem
0
M3 Read/Write
XCLKIN
0*
0
1
off
/1
37.5 MHz Max
Analog
X1
/2
/4
X2
/8*
* Default at reset
** Semaphore request write
X1/X2 Ext. XTAL 4 – 20 MHz
X1 Ext. CLK source up to 30 MHz
C28 Read/Write
Figure 8-11. System Clock/PLL
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8.11.1 Cortex-M3 Run Mode
In Run Mode, the Cortex-M3 processor, memory, and most of the peripherals are clocked by the M3SSCLK,
which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from a dedicated USB
PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of two watchdogs
(WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is accomplished through
corresponding peripheral configuration registers. Clock gating for individual peripherals is defined inside the
RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to peripherals that are enabled in a
corresponding DC (Device Configuration) register.
Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex-M3 CPU and forces the
Cortex-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of the SLEEPDEEP
bit of the Cortex-M3 SYSCTRL register. To come out of a low-power mode, any properly configured interrupt
event terminates the Sleep or Deep Sleep Mode and returns the Cortex-M3 processor/subsystem to Run Mode.
8.11.2 Cortex-M3 Sleep Mode
In Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking, and thus the code is no
longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC register.
When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in Run Mode);
and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clock-gating settings only
apply to peripherals that are enabled in a corresponding DC register. Peripheral clock frequency for the enabled
peripherals in Sleep Mode is the same as during the Run Mode.
Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode depends on
the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will temporarily wake
up only for the duration of the ISR of the interrupt causing the wake-up. After that, the processor goes back to
Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently (for the ISR and thereafter).
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8.11.3 Cortex-M3 Deep Sleep Mode
In Deep Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking and thus the code is no
longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input clock to the C28x
CPU and Shared Resources are turned off. The gating for the peripheral clocks may change based on the ACG
bit of the RCC register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers
(same as in Run Mode); and when ASC = 1, the clock gating comes from the DCGS register. RCGS and DCGS
clock gating settings only apply to peripherals that are enabled in a corresponding DC register.
Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run Mode. One
of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected with the
DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to DSDIVOVRIDE bits of
the DSLPCLKCFG register. The output of this Deep Sleep Divider is further divided-down per the M3SSDIVSEL
bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If 32KHXCLK or 10MHZCLK is selected in
Deep Sleep mode, the internal oscillator circuit (that generates OSCCLK) is turned off.
The Cortex-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is already
in the STANDBY mode. Typically, just before entering the STANDBY mode, the C28x will record in the
CLPMSTAT that it is about to do so. The Cortex-M3 processor can read the CLPMSTAT register to check if the
C28x is in STANDBY mode, and only then should the Cortex-M3 processor go into Deep Sleep. The reason for
the Cortex-M3 processor to confirm that the C28x is in STANDBY mode before the Cortex-M3 processor enters
the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to C28x and its peripherals, and if this
clock shutdown is not expected by the C28x, unintended consequences could result for some of the C28x
control peripherals.
Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep Mode
depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor will
temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that, the
processor goes back to Deep Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up permanently
(for the ISR and thereafter).
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8.12 Control Subsystem Clocking
The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1 external
clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT
and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has
read access. The C28x can request write access to the above registers through the CLKREQEST register. The
Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.
Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is done
through the CPCLKCR0,2,3 registers.
The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by C28x
peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by OSCCLK or
10MHZCLK (see Figure 8-12). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and PIE.
The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode. Table
8-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and peripherals.
Figure 8-12 shows the Control Subsystem clocks and low-power modes.
Table 8-26. Control Subsystem Low-Power Modes
REGISTERS USED TO
GATE CLOCKS TO
C28x PERIPHERALS
C28x
STATE OF C28x CPU
C28CPUCLK(2)
C28SYSCLK(3)
LOW-POWER MODE(1)
Normal
IDLE
Active
On
Off
Off
On
On
Off
CPCLKCR0,1,3
CPCLKCR0,1,3
N/A
Stopped
Stopped
STANDBY
(1) The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem
enters the Deep Sleep mode.
(2) C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE.
(3) C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals.
8.12.1 C28x Normal Mode
In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the C28SYSCLK,
which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and PIE are clocked by
the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be clocked by the TMR2CLK,
which is a divided-down version of one of three source clocks—C28SYSCLK, OSCCLK, and 10MHZCLK—as
selected by the CLKCTL register. Additionally, the LOSPCP register can be programmed to provide a dedicated
clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals.
Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the IDLE
instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES signal is gated
with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into IDLE mode or STANDBY Mode.
8.12.2 C28x IDLE Mode
In IDLE Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The
C28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the C28NMIINT
(C28x nonmaskable interrupt).
Upon exit from IDLE Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the LPMWAKE ISR
is executed. Next, the C28x processor starts fetching instructions from a location immediately following the IDLE
instruction that originally triggered the IDLE Mode.
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GPIO_MUX1
C28x NMI
MASTER SUBSYSTEM
ACIBRST
ASYSRST
SRXRST
CCLKCTL REG
CLKDIV
CLOCKFAIL
SYSDIVSEL REG
SYSPLLSTAT REG
SYSPLLMULT REG
SYSPLLCTL REG
CLPMSTAT REG
10MHZCLK
OSCCLK
OFF
/1
ASYSCLK
/2
/4
/8
CCLKREQUEST REG
PLLSYSCLK
M3SSCLK
CXCLK REG
XCLKOUTDIV
XPLLCLKCFG REG
XPLLCLKOUTDIV
PULSE
/32
STRETCH
C28SYSCLK
OFF
/4
/2
0
C28SYSCLK
XCLKOUT
1
2
3
GPIO_MUX1
/4
/1
OFF
LOSPCP REG
LSPCLK
CLKOFF REG
EPWM (9)
(NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4)
‘0’
TINT2
/1
/2
TIMER 2
C28LSPCLK
STANDBY
MODE
/4
…
C28CLKIN
McBSP
SCI
TINT 1
/14
TIMER 1
C28x CPU
EXIT
STANDBY
MODE
EXIT
IDLE
TIMER 0
execution of IDLE instruction
activates the IDLES signal
SPI
MODE
PIEINTRS (1)
C28 XINT(3)
2
I C
PIEINTRS (12:1)
C28NMIINT
ENTER
STANDBY
MODE
ENTER
IDLE
IDLES
C28x
PIE
MTOCIPC(1)
MODE
C28 DMA
EQEP (3)
ECAP (6)
C28 FPU/VCU
C28x
PIE
LPM(1)
LPM(0)
CLPMCR0 REG
C28CPUCLK
C28SYSCLK
C28SYSCLK
CLKCTL REG
LPMWAKE
SELECT QUALIFICATION
SELECT ONE OF 62 GPIs
CPCLKCR3 REG
CPCLKCR1 REG
CPCLKCR0 REG
LPM WAKEUP
CTMR2CLK
PRESCALE
TMR2CLKSRCSEL
GPI (63:0) MINUS
GPI 39 AND GPI 44
(NOT PINNED OUT)
LPMSEL1 REG
LPMSEL2 REG
/1
C28SYSCLK
OSCCLK
/2
/4
C28CLKENBx
/8
GPIO_MUX1
IPC
C28x NMI
/16
10MHZCLK
Figure 8-12. C28x Clocks and Low-Power Modes
8.12.3 C28x STANDBY Mode
In STANDBY Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK, and
C28SYSCLK are turned off. Exit from STANDBY Mode is accomplished by 1 of 62 GPIOs from the GPIO_MUX1
block, or MTOCIPCINT2 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected inside the
GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the Qualification Block, the
LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the CPCLKCR0 register) before
propagating into the wake request logic.
Cortex-M3 should use CLPMSTAT register bits to tell the C28x to go into STANDBY mode before going into
Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control software is not
expecting this clock to shut off. When the device is in Deep Sleep/STANDBY mode, wake-up should happen
only from the Master Subsystem, because all C28x clocks are off (C28CLKIN, C28CPUCLK, C28SYSCLK), thus
preventing the C28x from waking up first.
Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the LPMWAKE
interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a
location immediately following the IDLE instruction that originally triggered the STANDBY Mode.
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Note
For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is
available on silicon revision 0 devices (GPIO and other functions listed in Section 6.2.1 are not
available).
8.13 Analog Subsystem Clocking
The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as defined
by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the C28x
processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog Subsystem resets—
ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of ASYSCLK, it is possible
for the Cortex-M3 software to restore the ASYSCLK to its default value by resetting the Analog Subsystem.
The ASYSCLK is shut down when the Cortex-M3 processor enters the Deep Sleep mode.
8.14 Shared Resources Clocking
The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK. The
PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case
the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In
case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore, EPI is
clocked by M3SSCLK.
8.15 Loss of Input Clock (NMI Watchdog Function)
The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of the
Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external crystal or
just pin X1 when using an external oscillator. The second clock enters the chip through the XCLKIN pin and this
second clock can be used to clock the USB PLL and CAN peripherals. Only the main clock has a built-in Missing
Clock Detection circuit to recognize when the clock source vanishes and to enable other chip components to
take corrective or recovery action from such event (see Figure 8-13).
The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator) so
that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing source clock,
the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex-M3 NMI circuit, the C28x NMI,
ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses an active CLOCKFAIL
signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK. Simultaneously, the ePWM
peripherals can use the CLOCKFAIL signal to stop down driving motor control outputs. The NMI blocks respond
to the CLOCKFAIL signal by sending an NMI interrupt to a corresponding CPU, while starting the associated
NMI watchdog counter.
If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in the
device reset. If the software does react to the NMI, the software can prevent the impending reset by disabling the
watchdog timers, and then the software can initiate necessary corrective action such as switching over to an
alternative clock source (if available) or the software can initiate a shut-down procedure for the system.
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X2
1
PIN
MAIN
OSC
OSCCLK
X1
PIN
MAIN
PLL
4
ADDITIONAL CLOCK CONTROL LOGIC
PLLSYSCLK
10MHZCLK
MISSING
M3SSCLK
C28CLKIN
CLK DETECT
3
M3
2
INTERNAL
OSC
CPU
7
5
3
CLOCKFAIL
M3 NMI
M3 NMI WDOG
M3NMI
CLOCKFAIL
OTHER NMI
SOURCES
RESETS
TYPICAL ACTIVITY FOLLOWING
A MISSING CLOCK DETECTION :
3
3
C28NMI
C28x NMI
C28x NMI WDOG
THE INPUT CLOCK IS DISRUPTED
1
2
3
4
5
6
7
CLOCKFAIL
5
CLOCKFAIL SIGNAL BECOMES ACTIVE
7
CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI
BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX
C28x
CPU
EPWM
6
PLLSYSCLK SWITCHES TO THE 10MHZCLK
EPWM_A
EPWM_B
C28CLKIN
CPUS RESPOND TO NMIS AND THE
WATCHDOGS START COUNTING
GPIO_MUX1
SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION
IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE
WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT
PIN
PIN
Figure 8-13. Missing Clock Detection
8.16 GPIOs and Other Pins
Most Concerto external pins are shared among many internal peripherals. This sharing of pins is accomplished
through several I/O muxes where a specific physical pin can be assigned to selected signals of internal
peripherals.
Most of the I/O pins of the Concerto MCU can also be configured as programmable GPIOs. Exceptions include
the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and VREG18EN
internal voltage regulator enables; and five JTAG pins. The 74 primary GPIOs are grouped in 2 programmable
blocks: GPIO_MUX1 block (66 pins) and GPIO_MUX2 block (8 pins). Additionally, eight secondary GPIOs are
available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four pins). Figure 8-14 shows the
GPIOs and other pins.
8.16.1 GPIO_MUX1
Sixty-six pins of the GPIO_MUX1 block can be selectively mapped through corresponding sets of registers to all
Cortex-M3 peripherals, to all C28x peripherals, to 66General-Purpose Inputs, to 66 General-Purpose Outputs, or
a mixture of all of the above. Sixty-two pins of GPIO_MUX1 (GPIO0–GPIO63 minus GPIO39 and GPIO44) can
also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External Interrupts to the C28x PIE, and the C28x
STANDBY Mode Wakeup signal (LMPWAKE). Additionally, each GPIO_MUX1 pin can have a pullup enabled or
disabled. By default, all pullups and outputs are disabled on reset, and all pins of the GPIO_MUX1 block are
mapped to Cortex-M3 peripherals (and not to C28x peripherals).
Figure 8-15 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master Subsystem side
of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in the center, Pin-Level
Mux, is where the GPIO_MUX1 pins are individually assigned between the two subsystems, based on how the
configuration registers are programmed in the blue and green blocks (see Figure 8-16 for the configuration
registers).
Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or GPIOs to
the 66 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to pins, the Pin-Level
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Mux also provides other signals to the subsystems: XCLKIN and GPIO[A:J] IRQ signals to the Master
Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem. XCLKIN carries a clock from an
external pin to USB PLL and CAN modules. The nine GPIO[A:J] IRQ signals are interrupt requests from selected
external pins to the NVIC interrupt controller. The 12 GPTRIP[12:1] signals carry trip events from selected
external pins to C28x control peripherals—ePWM, eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM
GPIO Select block where one of them can be selected to wake up the C28x CPU from Low-Power Mode. Sixty-
six (66) GPI signals go to the C28x QUAL block where they can be configured with a qualification sampling
period (see Figure 8-16).
The configuration registers for the muxing of Master Subsystem peripherals are organized in nine sets (A–J),
with each set being responsible for eight pins. These nine sets of registers are programmable by the Cortex-M3
CPU through the AHB bus or the APB bus. The configuration register for the muxing of Control Subsystem
peripherals are organized in three sets (A–C), with each set being responsible for up to 32 pins. These registers
are programmable by the C28x CPU through the C28x CPU bus. Figure 8-16 shows set A of the Master
Subsystem GPIO configuration registers, set A of the Control Subsystem registers, and the muxing logic for one
GPIO pin as driven by these registers.
10
AIO_MUX1
GPIO
MUX
4
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ADC1INB0
ADC1INB3
ADC1INB4
ADC1INB7
USB
PLL
EPI
USB
EMAC
2
I C
UART
(5)
CAN
SSI
(4)
M3
NVIC
(2)
NMI
(2)
COMPA1
COMPA2
COMPA3
COMPB2
ADC
1
VDDA
(3.3V)
GPIO_MUX1
GPIO
MUX
6
66
66
COMPARATOR
+ DAC UNITS
8
GPI (63:0) MINUS
GPI 39 AND GPI 44
COMPOUT (6:1)
(NOT PINNED OUT)
VSSA
(0V)
8
LPM WAKEUP
LPMWAKE
EPWM
(9)
XINT
(3)
ECAP
(6)
EQEP
(3)
C28X
CPU
2
I C
SPI
COMPA4
COMPB5
ADC
2
COMPA5
COMPA6
McBSP
SCI
ADC2INA0
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
ADC2INB0
ADC2INB3
ADC2INB4
ADC2INB7
VREGS
DEBUG
RESETS
CLOCKS
NMI
GPIO
MUX
4
AIO_MUX2
10
Figure 8-14. GPIOs and Other Pins
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M3 AHB BUS
M3 APB BUS
BUS BRIDGE
XCLKIN
XCLKIN
2
I C
UART
(5)
CAN
(2)
SSI
(4)
USB
PLL
USB
EPI
EMAC
(2)
M3
M3
CPU
uDMA
M3
NMI
M3
EXT
NMI
INTERRUPTS
M3 PERIPHERAL SIGNAL ROUTING
NVIC
M3 MUX A
8
M3 MUX B
M3 MUX D
8
M3 MUX E
8
M3 MUX F
7
M3 MUX G
7
M3 MUX H
8
M3 MUX J
8
M3 MUX C
XCLKIN
GPIO
8
4
(H:A)
IRQ
PIN - LEVEL MUX
66
(TERMINALS GPIO 39 AND GPIO 44 ARE
NOT PINNED OUT ON THIS DEVICE)
GPTRIP
(12:1)
32
30
4
C28 MUX A
C28 MUX B
C28 MUX C
GPI (63:0) MINUS
GPI 39 AND GPI 44
(NOT PINNED OUT)
LPM
WAKEUP
C28 PERIPHERAL SIGNAL ROUTING
LPM
WAKE
C28x
DMA
C28x
CPU
EQEP
(3)
ECAP
(6)
EPWM
(9)
XINT
(3)
2
I C
McBSP
SCI
SPI
GPTRIP (12:7)
GPTRIP (12:1)
GPTRIP (6:4)
C28 CPU BUS
C28 DMA BUS
Figure 8-15. GPIO_MUX1 Block
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PERIPHERALS 1-15 REPRESENT A SET OF UP TO
BLUE REGISTER SET A
15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN
TO/FROM M3 PERIPH 1-11
TO/FROM M3 PERIPH 12-15
M3 CLOCKS
A-H INTR REQUESTS TO M3
REPRESENTS 8 OF 66 GPIOs.
REMAINING 58 GPIOs ARE
CONTROLLED BY SIMILAR
REGISTER SETS B, C, D, E, F,
I, J, H
GPIO63 XCLKIN
ONLY
GPIO (A)
IRQ
GPIOPCTL REG
PRIMARY
ALT
M3 REG SET A
M3 REG SET A
GPIOAMSEL REG
GPIOIS REG
GPIOIBE REG
GPIOIEV REG
GPIOIM REG
GPIORIS REG
GPIOMIS REG
GPIOICR REG
GREY LOGIC IS SPECIFIC TO
ONE DEVICE I/O PIN
M3 REG SET A
PRIMARY
AT RESET
GPIOAPSEL REG
(USB ANALOG SIGNALS)
M3 REG SET A
ENB
GPIODATA REG
GPIODIR REG
GPIOPUR REG
M3 REG SET A
GPIOODR REG
GPIOCSEL REG
GPIODEN REG
GPIOAFSEL REG
GPIOLOCK REG
GPIOCR REG
PULLUP
DISABLED
ON RESET
M3 REG SET A
NORMAL
AT RESET
SELECT M3
AT RESET
I/O DISABLED
AT RESET
GPIO MODE
AT RESET
‘1’
PULLUP
INPUT
(4 PINS ONLY)
ANALOG USB
SIGNALS
‘0’
(M3 GPIO)
ONE OF 66
OUTPUT
GPIO_MUX1 PINS
OUTPUT
DISABLED
OPEN
DRAIN
LOGIC
GPIOAMSEL REG
OE
OE
AFTER RESET
OE
‘1’
ASYNC INPUT
ORANGE LOGIC SHOWS
USB ANALOG FUNCTIONS
(APPLIES TO 4 PINS ONLY)
OE
XRS
SYNC INPUT
SYNC
C28 REG SET A
GPACTRL REG
QUAL
GREEN REGISTER SET A
SHOWN REPRESENTS 32
OF 66 GPIOs. THE
(C28 GPIO)
C28SYSCLK
C28 REG SET A
6 SAMPLES
3 SAMPLES
REMAINING 34 GPIOs ARE
CONTROLLED BY SIMILAR
REGISTER SETS B AND C
GPASET REG
GPACLEAR REG
GPATOGGLE REG
GPADIR REG
GPASEL1 REG
GPASEL2 REG
OUTPUTS
SYNC INPUT
AT RESET
GPIO
SEL(1:0)
C28 REG SET A
AT RESET
EACH I/O PIN HAS A
DEDICATED PAIR OF
BITS FOR MUX SELECT
GPADAT REG
GPAMUX1 REG
GPAMUX2 REG
EACH I/O PIN HAS A
DEDICATED PAIR OF
BITS FOR MUX SELECT
SEL(1:0)
SEL(1:0)
INPUTS
N/C AT RESET
TO C28x CPU WAKE-UP FROM
A LOW POWER MODE
C28 REG SET A
N/C
GPTRIP1SEL REG
…
GPTRIP12SEL REG
PERIPHERALS 1-3 REPRESENT A SET OF UP TO
THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN
GPI (63:0) MINUS
GPI 39 AND GPI 64
GPTRIP (12:1)
TO XINT, ECAP, EPWM
FROM C28 PERIPH 1-3
TO C28 PERIPH 1-3
Figure 8-16. GPIO_MUX1 Pin Mapping Through Register Set A
For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of 11
possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register
GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The input
takes the reverse path. See Table 8-27 and Table 8-28 for the mapping of Cortex-M3 peripheral signals to
GPIO_MUX1 pins.
Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral signals
for each of 32 pins of set A. The selected C28x peripheral output then propagates further along the muxing chain
towards a given pin. The input takes the reverse path. See Table 8-29 for the mapping of C28x peripheral
signals to GPIO_MUX1 pins.
In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog signals. The
GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB signals.
PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes USB0DP, and
PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not available for digital
GPIO_MUX1 options as described above.
Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin
PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is always
available at these modules where it can be selected through local registers.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Note
For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function is
available on silicon revision 0 devices (GPIO and other functions listed in Section 6.2.1 are not
available).
Table 8-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)
ANALOG
MODE
DEVICE
PIN
NAME
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY
(USB
MODE 1
U0RX
U0TX
SSI0CLK
SSI0FSS
SSI0RX
SSI0TX
I2C1SCL
I2C1SDA
CCP0
CCP2
I2C0SCL
I2C0SDA
–
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
MODE 8
MODE 9 MODE 10 MODE 11
PINS)(1)
PA0_GPI
O0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2C1SCL
U1RX
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PA1_GPI
O1
–
–
–
–
–
–
I2C1SDA
U1TX
–
PA2_GPI
O2
–
MIITXD2
–
–
–
–
–
–
–
–
–
–
–
PA3_GPI
O3
–
MIITXD1
–
–
–
–
–
PA4_GPI
O4
–
MIITXD0
–
CAN0RX
–
–
–
–
PA5_GPI
O5
–
CCP1
CCP4
–
MIIRXDV
–
CAN0TX
–
–
–
–
PA6_GPI
O6
USB0EPE
N
MIIRXCK
–
–
CAN0RX
–
–
–
PA7_GPI
O7
USB0PFL
T
MIIRXER
–
–
CAN0TX
CCP3
–
–
PB0_GPI
O8
–
–
U1RX
–
–
–
–
–
–
PB1_GPI
O9
–
–
CCP1
CCP3
–
U1TX
–
–
–
–
PB2_GPI
O10
USB0EPE
N
–
–
CCP0
–
–
–
–
PB3_GPI
O11
USB0PFL
T
–
–
–
–
–
–
–
PB4_GPI
O12
–
–
U2RX
CCP0
–
CAN0RX
–
U1RX
EPI0S23
EPI0S22
–
–
PB5_GPI
O13
–
CCP5
CCP7
–
CCP6
CAN0TX
CCP2
U1TX
–
–
PB6_GPI
O14
EPI0S37
CCP1
–
–
–
CCP5
–
–
–
(2)
PB7_GPI
O15
EPI0S36
–
EXTNMI
U2RX
U2TX
CCP5
CCP0
MIITXD3
MIITXD2
MIITXD1
MIITXD0
–
–
–
MIIRXD1
–
–
(2)
PD0_GPI
O16
–
CAN0RX
CAN0TX
CCP6
CCP7
CCP3
CCP4
–
–
U1RX
CCP6
MIIRXDV
–
–
–
PD1_GPI
O17
–
–
U1TX
CCP7
MIITXER
–
–
CCP2
–
PD2_GPI
O18
U1RX
U1TX
CCP0
CCP2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
EPI0S20
–
PD3_GPI
O19
–
EPI0S21
–
–
–
PD4_GPI
O20
–
–
–
EPI0S19
EPI0S28
EPI0S29
EPI0S30
–
PD5_GPI
O21
–
U2RX
U2TX
–
PD6_GPI
O22
–
–
–
PD7_GPI
O23
–
–
CCP1
CCP3
PE0_GPI
O24
USB0PFL
T
–
SSI1CLK
EPI0S8
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F28M35M52C, F28M35M22C, F28M35E20B
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M3
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
Table 8-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) (continued)
ANALOG
MODE
DEVICE
PIN
NAME
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY
MODE 1
(USB
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
MODE 8
MODE 9 MODE 10 MODE 11
PINS)(1)
PE1_GPI
O25
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SSI1FSS
–
–
–
–
–
–
–
–
–
CCP2
CCP6
–
–
EPI0S9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PE2_GPI
O26
CCP4
CCP1
CCP3
CCP5
–
SSI1RX
–
CCP2
–
–
EPI0S24
EPI0S25
–
–
PE3_GPI
O27
SSI1TX
–
CCP7
–
–
–
–
PE4_GPI
O28
EPI0S34
–
–
–
–
–
–
–
–
–
–
–
–
U2TX
CCP2
MIIRXD0
–
–
(2)
PE5_GPI
O29
EPI0S35
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(2)
PE6_GPI
O30
–
–
–
–
–
–
–
PE7_GPI
O31
–
–
–
–
–
PF0_GPI
O32
CAN1RX
CAN1TX
–
MIIRXCK
–
PF1_GPI
O33
MIIRXER
–
CCP3
PF2_GPI
O34
MIIPHYIN
TR
EPI0S32(2
–
–
–
–
–
SSI1CLK
SSI1FSS
SSI1RX
SSI1TX
–
–
–
–
–
–
)
PF3_GPI
O35
EPI0S33(2
–
MIIMDC
MIIMDIO
MIIRXD3
MIIRXD2
)
PF4_GPI
O36
CCP0
CCP2
CCP1
EPI0S12
EPI0S15
PF5_GPI
O37
USB0VBU PF6_GPI
EPI0S38(2
)
S
O38
PF7_GPI
O39
–
–
–
–
–
–
–
–
–
–
–
–
(no pin)
PG0_GPI
O40
USB0EPE
N
–
U2RX
U2TX
–
–
–
–
–
I2C1SCL
I2C1SDA
MIICOL
–
–
–
–
–
–
–
–
–
–
–
–
EPI0S13
EPI0S14
–
–
–
–
–
–
–
–
–
–
–
–
PG1_GPI
O41
–
USB0DM
–
–
–
–
PG2_GPI
O42
EPI0S39(2
)
PG3_GPI
O43
–
MIICRS
–
–
PG4_GPI
O44
–
–
–
–
–
–
–
–
–
–
–
(no pin)
PG5_GPI
O45
EPI0S40(2
USB0DP
USB0ID
–
CCP5
–
–
–
MIITXEN
MIITXCK
MIITXER
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
)
PG6_GPI
O46
EPI0S41(2
–
–
)
PG7_GPI
O47
CCP5
EPI0S31
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 8-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) (continued)
ANALOG
MODE
DEVICE
PIN
NAME
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
M3
PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY PRIMARY
MODE 1
(USB
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
MODE 8
EPI0S6
EPI0S7
EPI0S1
EPI0S0
EPI0S10
EPI0S11
MODE 9 MODE 10 MODE 11
PINS)(1)
PH0_GPI
O48
MIIPHYRS
T
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CCP6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PH1_GPI
O49
CCP7
–
–
–
–
PH2_GPI
O50
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MIITXD3
MIITXD2
MIITXD1
MIITXD0
–
–
PH3_GPI
O51
USB0EPE
N
–
–
–
PH4_GPI
O52
USB0PFL
T
–
–
SSI1CLK
PH5_GPI
O53
–
–
–
–
–
–
–
–
–
–
–
–
SSI1FSS
PH6_GPI
O54
–
EPI0S26 MIIRXDV
–
–
SSI1RX
PH7_GPI
O55
MIIRXCK
EPI0S27
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S28
EPI0S29
EPI0S30
–
–
SSI1TX
PJ0_GPIO
56
MIIRXER
–
I2C1SCL
PJ1_GPIO
57
USB0PFL
T
–
–
–
–
–
–
–
I2C1SDA
PJ2_GPIO
58
CCP0
–
–
–
–
–
–
PJ3_GPIO
59
–
–
–
–
CCP6
CCP4
CCP2
CCP1
PJ4_GPIO
60
PJ5_GPIO
61
PJ6_GPIO
62
PJ7_GPIO
63
XCLKIN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CCP0
–
–
–
–
–
PC0_GPI
O64
(no pin)
–
–
–
–
PC1_GPI
O65
(no pin)
PC2_GPI
O66
(no pin)
PC3_GPI
O67
–
(no pin)
PC4_GPI
O68
–
–
–
–
CCP5
CCP1
CCP3
CCP4
–
–
–
–
MIITXD3
–
–
CCP2
CCP3
U1RX
U1TX
CCP4
–
–
EPI0S2
EPI0S3
EPI0S4
EPI0S5
CCP1
–
–
–
–
–
–
–
–
PC5_GPI
O69
USB0EPE
N
–
–
–
–
–
–
PC6_GPI
O70
USB0PFL
T
–
CCP0
PC7_GPI
O71
USB0PFL
T
CCP0
–
(1) Blank fields represent Reserved functions.
(2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 8-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)
M3
M3
M3
M3
ANALOG MODE
DEVICE PIN NAME
ALTERNATE
MODE 12
ALTERNATE
MODE 13
ALTERNATE
MODE 14
ALTERNATE
MODE 15
(USB PINS)(1)
–
PA0_GPIO0
PA1_GPIO1
PA2_GPIO2
PA3_GPIO3
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7
PB0_GPIO8
PB1_GPIO9
PB2_GPIO10
PB3_GPIO11
PB4_GPIO12
PB5_GPIO13
PB6_GPIO14
PB7_GPIO15
PD0_GPIO16
PD1_GPIO17
PD2_GPIO18
PD3_GPIO19
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PE0_GPIO24
PE1_GPIO25
PE2_GPIO26
PE3_GPIO27
PE4_GPIO28
PE5_GPIO29
PE6_GPIO30
PE7_GPIO31
PF0_GPIO32
PF1_GPIO33
PF2_GPIO34
PF3_GPIO35
PF4_GPIO36
PF5_GPIO37
PF6_GPIO38
–
–
–
–
–
–
–
–
SSI1FSS
–
–
–
–
–
–
–
–
–
SSI1CLK
–
–
–
–
–
–
–
–
–
–
–
–
MIITXD3
–
–
–
MIIRXD1
–
–
–
–
–
SSI2TX
SSI2RX
SSI2CLK
SSI2FSS
–
CAN1TX
–
U4TX
–
–
–
–
–
CAN1RX
U1RX
CAN1TX
CAN1RX
U1TX
U1RX
CAN1TX
CAN1RX
U1TX
U1RX
U3TX
U3RX
I2C1SDA
I2C1SCL
CAN0RX
CAN0TX
U2RX
U2TX
EPI0S38(2)
–
U4RX
–
–
–
–
–
SSI1TX
SSI1RX
SSI1CLK
SSI1FSS
USB0EPEN
USB0PFLT
CAN0RX
CAN0TX
CAN1TX
CAN1RX
U1TX
U1RX
SSI1TX
SSI1RX
SSI1CLK
SSI1FSS
USB0EPEN
USB0PFLT
–
–
–
–
–
MIICRS
I2C0SDA
I2C0SCL
SSI0TX
SSI0RX
SSI0CLK
SSI0FSS
–
–
–
–
MIIRXD2
–
MIICOL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SSI3TX
SSI3RX
SSI3CLK
SSI3FSS
U0RX
U0TX
CAN0RX
CAN0TX
I2C0SDA
I2C0SCL
–
–
–
–
–
–
–
–
–
–
MIITXER
–
MIIMDIO
–
–
MIIRXD3
–
–
–
–
–
–
–
–
–
–
TRACED2
TRACED3
TRACECLK
TRACED0
–
–
–
–
–
XCLKOUT
–
–
U0TX
U0RX
–
–
–
–
–
–
USB0VBUS
–
–
–
PF7_GPIO39
(no pin)
–
–
–
–
–
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Product Folder Links: F28M35H52C F28M35H52C-Q1 F28M35H22C F28M35M52C F28M35M22C
F28M35E20B
F28M35H52C, F28M35H52C-Q1, F28M35H22C
F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
www.ti.com
Table 8-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes) (continued)
M3
M3
M3
M3
ANALOG MODE
DEVICE PIN NAME
ALTERNATE
MODE 12
ALTERNATE
MODE 13
ALTERNATE
MODE 14
ALTERNATE
MODE 15
(USB PINS)(1)
–
PG0_GPIO40
PG1_GPIO41
PG2_GPIO42
PG3_GPIO43
MIIRXD2
MIIRXD1
–
U4RX
U4TX
–
–
–
–
–
–
–
USB0DM
–
–
–
MIIRXDV
–
TRACED1
PG4_GPIO44
(no pin)
–
–
–
–
–
USB0DP
PG5_GPIO45
PG6_GPIO46
PG7_GPIO47
PH0_GPIO48
PH1_GPIO49
PH2_GPIO50
PH3_GPIO51
PH4_GPIO52
PH5_GPIO53
PH6_GPIO54
PH7_GPIO55
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0ID
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SSI3TX
SSI3RX
SSI3CLK
SSI3FSS
U3TX
–
MIIRXD0
–
–
–
–
–
–
–
–
U3RX
–
MIITXEN
MIITXCK
–
SSI0TX
SSI0RX
SSI0CLK
SSI0FSS
SSI0CLK
SSI0FSS
SSI1CLK
SSI1FSS
U2RX
–
–
–
MIIRXDV
MIIRXCK
MIIMDC
MIICOL
MIICRS
MIIPHYINTR
–
U0TX
U0RX
–
–
–
PJ7_GPIO63/
XCLKIN
–
–
–
–
–
MIIPHYRST
U2TX
–
–
–
–
–
–
–
–
–
–
PC0_GPIO64
(no pin)
–
–
–
–
–
–
–
–
PC1_GPIO65
(no pin)
PC2_GPIO66
(no pin)
PC3_GPIO67
(no pin)
–
–
–
–
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(1) Blank fields represent Reserved functions.
(2) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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Table 8-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
ANALOG MODE
DEVICE PIN NAME
(USB PINS)(1)
–
PA0_GPIO0
PA1_GPIO1
PA2_GPIO2
PA3_GPIO3
PA4_GPIO4
PA5_GPIO5
PA6_GPIO6
PA7_GPIO7
PB0_GPIO8
PB1_GPIO9
PB2_GPIO10
PB3_GPIO11
PB4_GPIO12
PB5_GPIO13
PB6_GPIO14
PB7_GPIO15
PD0_GPIO16
PD1_GPIO17
PD2_GPIO18
PD3_GPIO19
PD4_GPIO20
PD5_GPIO21
PD6_GPIO22
PD7_GPIO23
PE0_GPIO24
PE1_GPIO25
PE2_GPIO26
PE3_GPIO27
PE4_GPIO28
PE5_GPIO29
PE6_GPIO30
PE7_GPIO31
PF0_GPIO32
PF1_GPIO33
PF2_GPIO34
PF3_GPIO35
PF4_GPIO36
PF5_GPIO37
PF6_GPIO38
GPIO0
GPIO1
EPWM1A
EPWM1B
EPWM2A
EPWM2B
EPWM3A
EPWM3B
EPWM4A
EPWM4B
EPWM5A
EPWM5B
EPWM6A
EPWM6B
EPWM7A
EPWM7B
EPWM8A
EPWM8B
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
EQEP1A
EQEP1B
EQEP1S
EQEP1I
ECAP1
–
–
–
ECAP6
–
–
GPIO2
–
–
–
GPIO3
ECAP5
–
–
GPIO4
–
–
–
GPIO5
MFSRA
ECAP1
–
GPIO6
–
EPWMSYNCO
–
GPIO7
MCLKRA
ECAP2
–
GPIO8
–
ADCSOCAO
–
GPIO9
–
ECAP3
–
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
–
ADCSOCBO
–
–
ECAP4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MDXA
–
–
MDRA
–
–
MCLKXA
–
–
MFSXA
–
–
EQEP2A
–
–
ECAP2
EQEP2B
–
–
ECAP3
EQEP2I
–
–
ECAP4
EQEP2S
–
–
SCIRXDA
SCITXDA
–
–
–
–
–
–
–
–
EPWM9A
–
–
–
EPWM9B
–
I2CASDA
I2CASCL
ECAP1
SCIRXDA
ADCSOCAO
–
EPWMSYNCO
ADCSOCBO
–
SCIRXDA
XCLKOUT
–
SCITXDA
SCIRXDA
ECAP2
–
–
–
–
–
–
–
–
–
–
USB0VBUS
–
PF7_GPIO39
(no pin)
–
–
–
–
–
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Table 8-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes) (continued)
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
ANALOG MODE
DEVICE PIN NAME
(USB PINS)(1)
–
PG0_GPIO40
PG1_GPIO41
PG2_GPIO42
PG3_GPIO43
GPIO40
GPIO41
GPIO42
GPIO43
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0DM
–
PG4_GPIO44
(no pin)
–
–
–
–
–
USB0DP
PG5_GPIO45
PG6_GPIO46
PG7_GPIO47
PH0_GPIO48
PH1_GPIO49
PH2_GPIO50
PH3_GPIO51
PH4_GPIO52
PH5_GPIO53
PH6_GPIO54
PH7_GPIO55
PJ0_GPIO56
PJ1_GPIO57
PJ2_GPIO58
PJ3_GPIO59
PJ4_GPIO60
PJ5_GPIO61
PJ6_GPIO62
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB0ID
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ECAP5
ECAP6
EQEP1A
EQEP1B
EQEP1S
EQEP1I
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
MCLKRA
MFSRA
–
–
–
–
–
–
–
EQEP3A
EQEP3B
EQEP3S
EQEP3I
EPWM7A
EPWM7B
EPWM8A
EPWM8B
EPWM9A
–
–
PJ7_GPIO63/
XCLKIN
–
–
–
–
–
GPIO63
–
–
–
–
–
–
–
–
–
–
EPWM9B
PC0_GPIO64
(no pin)
–
–
–
–
–
–
–
–
PC1_GPIO65
(no pin)
PC2_GPIO66
(no pin)
PC3_GPIO67
(no pin)
–
–
–
–
PC4_GPIO68
PC5_GPIO69
PC6_GPIO70
PC7_GPIO71
GPIO68
GPIO69
GPIO70
GPIO71
–
–
–
–
–
–
–
–
–
–
–
–
(1) Blank fields represent Reserved functions.
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F28M35M52C, F28M35M22C, F28M35E20B
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8.16.2 GPIO_MUX2
The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight
General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each GPIO_MUX2
pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are configured as analog
inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed through a separate set of
registers from those used to program GPIO_MUX1.
The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set E. They are
accessible by the C28x CPU only. The middle portion of Figure 8-17 shows set G of Control Subsystem
registers, plus muxing logic for the associated eight GPIO pins. The GPEMUX1 register selects one of six
possible digital output signals from analog comparators, or one of eight general-purpose GPIO digital outputs.
The GPEPUD register disables pullups for the GPIO_MUX2 pins when a corresponding bit of that register is set
to “1”. Other registers of set G allow reading and writing of the eight GPIO bits, as well as setting the direction for
each of the bits (read or write). See Table 8-30 for the mapping of comparator outputs and GPIO to the eight pins
of GPIO_MUX2.
Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPEMUX1 register to “00”, “01”, “10”,
and “11”, respectively. For example, setting bits 5–4 of the GPEMUX1 register to “00” (Peripheral Mode 0)
assigns pin GPIO130 to internal signal GPIO130 (digital GPIO). Setting bits 5–4 of the GPEMUX1 register to
“11” (Peripheral Mode 3) assigns pin GPIO130 to internal signal COMP6OUT coming from Analog Comparator
6. Peripheral Modes 1 and 2 are reserved and are not currently available.
Table 8-30. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
DEVICE PIN NAME(1)
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
COMP1OUT
COMP6OUT
COMP2OUT
COMP3OUT
COMP4OUT
–
COMP5OUT
(1) Blank fields represent Reserved functions.
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F28M35M52C, F28M35M22C, F28M35E20B
SPRS742L – JUNE 2011 – REVISED FEBRUARY 2021
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ADC1INA0 ADC1INB0
ADC1INA2 ADC1INB3
ADC1INA3 ADC1INB4
ADC1INA4 ADC1INB7
ADC1INA6
ADC
1
ADC1INA7
ONE OF 10
AIO_MUX1
PINS
AIO2
AIO4
AIO6
AIO12
AIO_MUX1
AIOMUX1 REG
AIODIR REG
AIOSET REG
AIOCLEAR REG
AIOTOGGLE REG
AIODIR REG
COMPA1
COMPA2
COMPA3
AIODAT REG
COMPB2
COMPOUT1
COMPOUT2
COMPOUT3
COMPOUT4
COMPOUT5
COMPOUT6
6
COMPARATOR
+ DAC UNITS
DIS
GPGPUDREG
‘1’
PULLUP
DISABLED
ON RESET
COMPA4
C28
COMPA5
CPU
BUS
ANALOG
COMMON
INTERFACE
BUS
COMPA6
ANALOG BUS
C28x
CPU
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO_MUX2
COMPB5
PULLUP
GPEMUX1 REG
GPESET REG
GPECLEAR REG
GPETOGGLE REG
GPEDIR REG
GPEDIR REG
ONE OF 8
GPIO_MUX2
PINS
GPEDAT REG
ADC2INA0 ADC2INB0
ADC2INA2 ADC2INB3
ADC2INA3 ADC2INB4
ADC2INA4 ADC2INB7
ADC2INA6
ADC
2
ADC2INA7
ONE OF 10
AIO_MUX2
PINS
AIO18
AIO20
AIO22
AIO28
AIO_MUX2
AIOSET REG
AIOCLEAR REG
AIOTOGGLE REG
AIODIR REG
AIOMUX2 REG
AIODIR REG
AIODAT REG
Figure 8-17. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2
8.16.3 AIO_MUX1
The ten pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog inputs
for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-
Purpose Outputs. While AIO_MUX1 has been named after the analog signals passing through it, the GPIOs
(here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2
blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX1 block are configured as
analog inputs and the GPIO function is disabled. The AIO_MUX1 block is programmed through a separate set of
registers from those used to program AIO_MUX2.
The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU only. The
top portion of Figure 8-17 shows Control Subsystem registers and muxing logic for the associated ten AIO pins.
The AIOMUX1 register selects one of ten possible analog input signals or one of four general-purpose AIO
inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of
the bits (read or write). See Table 8-31 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX1.
AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen by
setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1 register to ‘0’
assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1 register to ‘1’ assigns
pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be enabled at a time in the respective
analog module). Currently, all even bits of the AIOMUX1 register are “don’t cares”.
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F28M35M52C, F28M35M22C, F28M35E20B
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Table 8-31. AIO_MUX1 Pin Assignments (C28x AIO Modes)
DEVICE PIN NAME(1) (2)
C28x AIO MODE 0(3)
C28x AIO MODE 1(4)
ADC1INA0
–
AIO2
–
ADC1INA0
ADC1INA2
ADC1INA2, COMPA1
ADC1INA3
ADC1INA3
ADC1INA4
AIO4
AIO6
–
ADC1INA4, COMPA2
ADC1INA6, COMPA3
ADC1INA7
ADC1INA6
ADC1INA7
ADC1INB0
–
ADC1INB0
ADC1INB3
–
ADC1INB3
ADC1INB4
AIO12
–
ADC1INB4, COMPB2
ADC1INB7
ADC1INB7
(1) Blank fields represent Reserved functions.
(2) For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be
disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
(3) AIO Mode 0 represents digital general-purpose inputs or outputs.
(4) AIO Mode 1 represents analog inputs for ADC1 or the Comparator module.
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8.16.4 AIO_MUX2
The ten pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog inputs
for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or four General-
Purpose Outputs. While AIO_MUX2 has been named after the analog signals passing through it, the GPIOs
(here called AIOs) are still digital, although with fewer features than those in the GPIO_MUX1 and GPIO_MUX2
blocks—for example, they do not offer pullups. On reset, all pins of the AIO_MUX2 block are configured as
analog inputs and the GPIO function is disabled. The AIO_MUX2 block is programmed through a separate set of
registers from those used to program AIO_MUX1.
The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU only. The
bottom portion of Figure 8-17 shows Control Subsystem registers and muxing logic for the associated ten AIO
pins. The AIOMUX2 register selects one of ten possible analog input signals or one of four general-purpose AIO
inputs. Other registers allow reading and writing of the four AIO bits, as well as setting the direction for each of
the bits (read or write). See Table 8-32 for the mapping of analog inputs and AIOs to the ten pins of AIO_MUX2.
Peripheral Modes 1 and 2 are currently not available.
AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen by
setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2 register to ‘0’
assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2 register to ‘1’
assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be enabled at a time in the
respective analog module). Currently, all even bits of the AIOMUX2 register are “don’t cares”.
Table 8-32. AIO_MUX2 Pin Assignments (C28x AIO Modes)
DEVICE PIN NAME(1) (2)
C28x AIO MODE 0(3)
C28x AIO MODE 1(4)
ADC2INA0
–
ADC2INA0
ADC2INA2
AIO18
ADC2INA2, COMPA4
ADC2INA3
ADC2INA3
–
ADC2INA4
AIO20
ADC2INA4, COMPA5
ADC2INA6, COMPA6
ADC2INA7
ADC2INA6
AIO22
ADC2INA7
–
ADC2INB0
–
ADC2INB0
ADC2INB3
–
AIO28
–
ADC2INB3
ADC2INB4
ADC2INB4, COMPB5
ADC2INB7
ADC2INB7
(1) Blank fields represent Reserved functions.
(2) For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be
disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
(3) AIO Mode 0 represents digital general-purpose inputs or outputs.
(4) AIO Mode 1 represents analog inputs for ADC2 or the Comparator module.
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8.17 Emulation/JTAG
Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port and the
5-pin Cortex-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be used to connect to
debug tools through the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin Cortex-M3 ITM port can
only be accessed through the TI 20-pin JTAG header.
The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST signal
should always be pulled down through a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1 signals should
be pulled up through a pair of pullups ranging from 2.2 kΩ to 4.7 kΩ (depending on the drive strength of the
debugger ports). The JTAG port is TI’s standard debug port.
The ITM port uses five GPIO pins that can be mapped to internal Cortex-M3 ITM trace signals: TRACE0,
TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced software debug.
TI JTAG debug probes, and those from other manufacturers, can connect to Concerto devices through TI’s 14-
pin JTAG header or 20-pin JTAG header. See Figure 8-18 to see how the 14-pin JTAG header connects to the
JTAG port signals in Concerto. The 14-pin header does not support the ITM debug mode.
Figure 8-19 shows two possible ways to connect the 20-pin header to the emulation pins in Concerto. The left
side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way the 14-pin
header was connected. The JTAG EMU0 and EMU1 signals are mapped to the corresponding terminals on the
20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4 are left unconnected and the ITM trace
mode is not available.
The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of seven
JTAG signals. The EMU0 and EMU1 signals in Concerto are left unconnected in this mode; thus, the emulation
functions associated with these two signals are not available when debugging with ITM trace.
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CONCERTO F28M35x
85
TRST
2.2K
3.3V
1
3
5
7
9
87
88
2
nTRST
TDIS
KEY
TMS
TMS
TDI
4
6
TDI
PD
84
8
GND
GND
TDO
TDO
10
12
14
4.7K
4.7K
RTCK
TCK
11
13
89
83
86
GND
TCK
EMU1
EMU0
EMU0
EMU1
TI 14-PIN
JTAG HEADER
JTAG
PINS
(A)
GPIO PINS
81
78
TRACED0
TRACED1
TRACECLK
TRACED2
TRACED3
PF3_GPIO35
PG3_GPIO43
PF2_GPIO34
PF0_GPIO32
PF1_GPIO33
82
104
103
ITM trace
from M3
PROCESSOR
A. The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used.
Figure 8-18. Connecting to TI 14-Pin JTAG Debug Probe Header
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F28M35M52C, F28M35M22C, F28M35E20B
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CONCERTO F28M35x
CONCERTO F28M35x
85
85
TRST
TRST
2.2K
3.3V
2.2K
3.3V
1
3
5
7
9
1
3
5
7
9
87
88
2
4
87
88
2
nTRST
TDIS
KEY
nTRST
TMS
TMS
TMS
TDI
TMS
TDI
4
TDIS
KEY
TDI
PD
TDI
PD
6
6
84
8
84
8
GND
GND
GND
EMU1
GND
GND
GND
GND
EMU1
GND
TDO
TDO
TDO
TDO
10
12
14
16
18
20
10
12
14
16
18
20
4.7K
4.7K
RTCK
TCK
4.7K
4.7K
RTCK
TCK
11
11
89
83
86
89
83
86
TCK
TCK
13
15
17
19
13
15
17
19
EMU0
RESETn
EMU2
EMU4
EMU0
RESETn
EMU2
EMU4
NC
NC
EMU0
EMU1
EMU0
EMU1
EMU3
GND
EMU3
GND
NC
NC
NC
JTAG
PINS
JTAG
PINS
TI 20-PIN
JTAG HEADER
TI 20-PIN
JTAG HEADER
(A)
GPIO PINS
GPIO PINS
81
78
81
78
TRACED0
TRACED1
TRACECLK
TRACED2
TRACED3
PF3_GPIO35
PG3_GPIO43
PF2_GPIO34
PF0_GPIO32
PF1_GPIO33
TRACED0
TRACED1
TRACECLK
TRACED2
TRACED3
PF3_GPIO35
PG3_GPIO43
PF2_GPIO34
PF0_GPIO32
PF1_GPIO33
82
82
104
103
104
103
OPEN
OPEN
DRAIN
DRAIN
ITM trace
from M3
ITM trace
from M3
PROCESSOR
PROCESSOR
A LOW PULSE FROM THE JTAG DEBUG PROBE CAN BE TIED
WITH OTHER RESET SOURCES TO RESET THE BOARD
A LOW PULSE FROM THE JTAG DEBUG PROBE CAN BE TIED
WITH OTHER RESET SOURCES TO RESET THE BOARD
A. The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used.
Figure 8-19. Connecting to TI 20-Pin JTAG Debug Probe Header
8.18 Code Security Module
The Code Security Module (CSM) is a security feature incorporated in Concerto devices. The CSM prevents
access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM prevents
duplication and reverse-engineering of proprietary code. The word "secure" means that access to on-chip secure
memories is protected. The word "unsecure" means that access to on-chip secure memory is not protected—
that is, the contents of the memory could be read by any means [for example, by using a debugging tool such as
Code Composer Studio™ Integrated Development Environment (IDE)].
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Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
8.18.1 Functional Description
The security module restricts the CPU access to on-chip secure memory without interrupting or stalling CPU
execution. When a read occurs to a protected memory location, the read returns a zero value and CPU
execution continues with the next instruction. This process, in effect, blocks read and write access to various
memories through the JTAG port or external peripherals. Security is defined with respect to the access of on-
chip secure memories and prevents unauthorized copying of proprietary code or data.
The zone is secure when CPU access to the on-chip secure memories associated with that zone is restricted.
When secure, two levels of protection are possible, depending on where the program counter is currently
pointing. If code is currently running from inside secure memory, only an access through JTAG is blocked (that
is, through the JTAG debug probe). This process allows secure code to access secure data. Conversely, if code
is running from unsecure memory, all accesses to secure memories are blocked. User code can dynamically
jump in and out of secure memory, thereby allowing secure function calls from unsecure memory. Similarly,
interrupt service routines can be placed in secure memory, even if the main program loop is run from unsecure
memory.
The code security mechanism present in this device offers dual-zone security for the Cortex-M3 code and single-
zone security for the C28x code. In case of dual-zone security on the master subsystem, the different secure
memories (RAMs and flash sectors) can be assigned to different security zones by configuring the GRABRAM
and GRABSECT registers associated with each zone. Flash Sector N and Flash Sector A are dedicated to
Zone1 and Zone2, respectively, and cannot be allocated to any other zone by configuration. Similarly, flash
sectors get assigned to different zones based on the setting in the GRABSECT registers.
Security is provided by a CSM password of 128 bits of data (four 32-bit words) that is used to secure or
unsecure the zones. Each zone has its own 128-bit CSM password. The zone can be unsecured by executing
the password match flow (PMF).
The CSM password for each zone is stored in its dedicated flash sector. The password storage locations in the
flash sector store the CSM password. The password is selected by the system designer. If the password
locations of a zone have all 128 bits as ones, the zone is considered "unsecure". Because new flash devices
have erased flash (all ones), only a read of the password locations is required to bring any zone into unsecure
mode. If the password locations of a zone have all 128 bits as zeros, the zone is considered "secure", regardless
of the contents of the CSMKEY registers. The user should not use all zeros as a password or reset the device
during an erase of the flash. Resetting the device during an erase routine can result in either an all-zero or
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unknown password. If a device is reset when the password locations are all zeros, the device cannot be
unlocked by the password match flow. Using a password of all zeros will seriously limit the user’s ability to debug
secure code or reprogram the flash.
Note
If a device is reset while the password locations of a zone contain all zeros or an unknown value, that
zone will be permanently locked unless a method to run the flash erase routine from secure SARAM is
embedded into the flash or OTP. Care must be taken when implementing this procedure to avoid
introducing a security hole.
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8.19 µCRC Module
The µCRC module is part of the master subsystem. This module can be used by Cortex-M3 software to compute
CRC on data and program, which are stored at memory locations that are addressable by Cortex-M3. On this
device, the Cortex-M3 Flash Bank and ROM are mapped to the code space that is only accessed by the ICODE/
DCODE bus of Cortex-M3; and RAMs are mapped on the SRAM space that is accessible by the SYSTEM bus.
Hence, the µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and
program.
8.19.1 Functional Description
The µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and
program. To allow interrupts execution in between CRC calculations for a block of data and to discard the
Cortex-M3 literal pool accesses in between executions of the program (which reads data for CRC calculation),
the Cortex-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The µCRC module grabs
data from the bus to calculate CRC only if the address of the read data belongs to mirrored memory space. After
grabbing, the µCRC module performs the CRC calculation on the grabbed data and updates the µCRC Result
Register (µCRCRES). This register can be read at any time to get the calculated CRC for all the previous read
data. The µCRC module only supports CRC calculation for byte accesses. So, in order to calculate the CRC on
a block of data, software must perform byte accesses to all the data. For half-word and word accesses, the
µCRC module discards the data and does not update the µCRCRES register.
Note
If a read to a mirrored address space is thrown from the debugger (Code Composer Studio or any
other debug platform), the µCRC module ignores the read data and does not update the CRC result
for that particular read.
8.19.2 CRC Polynomials
The following are the CRC polynomials that are supported by the µCRC module:
•
•
•
•
CRC8 Polynomial = 0x07
CRC16 Polynomial-1 = 0x8005
CRC16 Polynomial-2 = 0x1021
CRC32 Polynomial = 0x04C11DB7
8.19.3 CRC Calculation Procedure
The software procedure for calculating CRC for a set of data that is stored in Cortex-M3 addressable memory
space is as follows:
1. Save the current value of the µCRC Result Register (µCRCRES) into the stack to allow calculation of CRC in
nested interrupt
2. Clear the µCRC Result Register (µCRCRES) by setting the CLEAR field of the µCRC Control Register
(µCRCCONTROL) to "1"
3. Configure the µCRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the µCRC Configuration
Register (µCRCCONFIG)
4. Read the data from memory locations for which CRC needs to be calculated using mirrored address
5. Read the µCRCRES register to get the calculated CRC value. Pop the last saved value of the CRC from the
stack and store this value into the µCRC Result Register (uCRCRES)
8.19.4 CRC Calculation for Data Stored In Secure Memory
This device has dual-zone security for the Cortex-M3 subsystem. Because ZoneX (X → 1/2) software does not
have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate CRC on data
stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though software is running from
same secure zone, the software cannot read the data stored in Exe-Only sectors. However, hardware does allow
CRC computation on data stored in Exe-Only flash sectors as long as the read access for this data is initiated by
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code running from same secure zone. These reads are just dummy reads and, in this case, read data only goes
to the µCRC module, not to the CPU.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Single-Phase Energy Meter Solution for Advanced Applications
This design features a dual-core microcontroller implementing an integrated electricity metering solution. The
meter has been tested to prove 0.5% accuracy across a current dynamic range of 2000:1 by using a precision,
low-noise op-amp and a programmable gain amplifier (PGA) to provide four gain stages. The metrology
calculations are performed independently of the MCU integrated cores, leaving both MCUs available for other
applications, including Power Line Communications (PLC). Developers will benefit from this design by taking
advantage of both the Arm® Cortex®-M3 and C28x MCUs to provide the e-meter host applications and PLC
communications.
Power Line Communications (PLC) System-on-Module for ARIB Frequency Band
The SOMPLC-F28M35 is a single-board System-on-Module (SOM) for PLC in the ARIB frequency band. This
single hardware design supports several popular PLC industry standards, including G3 and IEEE-1901.2. TI's
certified PLC software is available along with the SOMPLC-F28M35. Engineers can take the SOM design and
integrate it into their overall system board or keep the design as an add-on board to their application. The only
additional hardware required is the AC mains line coupling circuitry. The included hardware schematics and
Gerber files simplify the task for engineers to add PLC to their end system. OEMs will benefit from having the
ability to rapidly evaluate and prototype PLC technology in their application.
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F28M35M52C, F28M35M22C, F28M35E20B
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10 Device and Documentation Support
10.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
Concerto MCU devices and support tools. Each Concerto MCU commercial family member has one of three
prefixes: x, p, or no prefix (for example, xF28M35H52C1RFPT). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (with prefix x for devices and TMDX for tools) through fully
qualified production devices/tools (with no prefix for devices and TMDS, instead of TMDX, for tools).
xF28M35...
pF28M35...
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
F28M35...
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
Devices with prefix x or p and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RFP) and temperature range (for example, T).
For device part numbers and further ordering information of F28M35x devices in the RFP package type, see the
TI website (www.ti.com) or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the F28M35x Concerto™ MCUs
Silicon Errata.
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Figure 10-1. Device Nomenclature
10.2 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page.
Development Tools
H52C1 Concerto Experimenter Kit
The C2000 Experimenter Kits from Texas Instruments are ideal products for initial device exploration and testing.
The Concerto H52C1 Experimenter Kit has a docking station that features access to all controlCARD signals,
breadboard areas and RS-232 and JTAG connectors. Each kit contains a H52C1 controlCARD. The
controlCARD is a complete board level module that utilizes and industry-standard DIMM form factor to provide a
low-profiles single-board controller solution. Kit is complete with Code Composer StudioTM IDE v4 and USB
cable.
H52C1 Concerto controlCARD
The C2000 controlCARDs from Texas Instruments are ideal products for initial software development and short
run builds for system prototypes, test stands, and many other projects that require easy access to high-
performance controllers. The controlCARDs are complete board-level modules that utilize an industry-standard
DIMM form factor to provide a low-profile single-board controller solution. All of the C2000 controlCARDs use the
same 100-pin connector footprint to provide the analog and digital I/Os on-board controller and are completely
interchangeable. The host system needs to provide only a single 5V power rail to the controlCARD for it to be
fully functional.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
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Software Tools
controlSUITE™ Software Suite: Essential Software and Development Tools for C2000™ Microcontrollers
controlSUITE™ for C2000™ microcontrollers is a cohesive set of software infrastructure and software tools
designed to minimize software development time.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
F021 Flash API
The F021 Flash Application Programming Interface (API) provides a software library of functions to program,
erase, and verify F021 on-chip Flash memory.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific F28M35x hands-on training resources can be found at C2000™ MCU Device Workshops.
10.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
F28M35x Concerto™ MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
Concerto F28M35x Technical Reference Manual details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the F28M35x Microcontroller
Processors.
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CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
10.4 Trademarks
Concerto™, PowerPAD™, TMS320C2000™, controlSUITE™, Texas Instruments™, Code Composer Studio™,
C2000™, TI E2E™ are trademarks of Texas Instruments.
Freescale™ is a trademark of Freescale Semiconductor, Inc.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
NXP® is a registered trademark of NXP Semiconductors.
All trademarks are the property of their respective owners.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
For packages with a thermal pad, the MECHANICAL DATA figure shows a generic thermal pad without
dimensions. For the actual thermal pad dimensions that are applicable to this device, see the THERMAL PAD
MECHANICAL DATA figure.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F28M35E20B1RFPS
F28M35E20B1RFPT
F28M35H22C1RFPS
F28M35H22C1RFPT
F28M35H52C1RFPQ
F28M35H52C1RFPS
F28M35H52C1RFPT
F28M35M22C1RFPS
F28M35M22C1RFPT
F28M35M52C1RFPS
F28M35M52C1RFPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
RFP
144
144
144
144
144
144
144
144
144
144
144
60
60
60
60
60
60
60
60
60
60
60
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
F28M35E20B1RFPS
F28M35E20B1RFPT
F28M35H22C1RFPS
F28M35H22C1RFPT
F28M35H52C1RFPQ
F28M35H52C1RFPS
F28M35H52C1RFPT
F28M35M22C1RFPS
F28M35M22C1RFPT
F28M35M52C1RFPS
F28M35M52C1RFPT
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jan-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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