FDC1004DSCT [TI]
具有源屏蔽驱动器的 4 通道、16 位、电感数字转换器 | DSC | 10 | -40 to 125;
| 型号： | FDC1004DSCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有源屏蔽驱动器的 4 通道、16 位、电感数字转换器 | DSC | 10 | -40 to 125 PC 驱动 光电二极管 驱动器 转换器 |
| 文件： | 总31页 (文件大小：1605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FDC1004
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
FDC1004 用于电容式传感解决方案的 4 通道电容数字转换器
1 特性
3 说明
1
•
输入范围：±15pF
测量分辨率：0.5fF
采用接地电容传感器的电容传感是一种兼具超低功耗、
低成本和高分辨率的无接触传感技术，适用于接近检
测、手势传感、材料分析以及远程液位传感等各类应
用。 电容式传感系统中的传感器可以是任意金属或导
体，从而可实现低成本、高灵活性的系统设计。
•
•
•
•
•
•
•
最大偏置电容：100pF
可编程输出速率：100/200/400S/s
最大屏蔽负载：400pF
电源电压：3.3V
FDC1004 是一款用于实现电容式传感解决方案的高分
辨率、4 通道电容数字转换器。 每个通道的满量程范
围均为 ±15pF，可处理高达 100pF 的传感器偏置电
容，该偏置电容既可以在内部编程，也可以是一个外部
电容，用于跟踪环境随时间和温度的变化。 凭借较高
的偏置电容能力，可以使用远程传感器。
温度范围：–40 到 85°C
电流消耗:
–
–
工作时：750µA
待机时：29µA
•
•
接口：I2C
通道数：4
FDC1004 还包含用于实现传感器屏蔽的屏蔽驱动器，
该驱动器可降低 EMI 干扰并有助于聚焦电容式传感器
的传感方向。 FDC1004 封装尺寸较小，适合在空间受
限的应用中使用。 FDC1004 采用 10 引脚超薄小外形
尺寸无引线 (WSON) 封装，并且具有一个用于连接
MCU 的 I2C 接口。
2 应用
•
•
•
•
•
•
•
•
•
接近唤醒
手势传感
汽车车门/脚踢传感器
汽车雨滴传感器
远程和直接液位传感
高分辨率金属仿形
雨/雾/冰/雪检测
材料尺寸检测
器件信息(1)
器件型号
FDC1004
封装
封装尺寸（标称值）
WSON
3.0mm x 3.0mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
材料堆叠高度
4 典型应用
3.3 V
VDD
SHLD1
SHLD2
LEVEL
SENSOR
EXCITATION
CHA
ENVIRONMENTAL
SENSOR
3.3 V
3.3 V
CIN1
CIN2
CIN3
CIN4
FDC1004
3.3 V
VDD
CHA
MUX
OFFSET
& GAIN
CALIBRATION
CAPACITANCE
TO DIGITAL
CONVERTER
LIQUID
SENSOR
MCU
CHB
MUX
SCL
SDA
CHB
I2C
Peripheral
I2C
CONFIGURATION & DATA
REGISTERS
GND
CAPDAC
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNOSCY5
FDC1004
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
www.ti.com.cn
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
8.5 Programming........................................................... 12
8.6 Register Maps ........................................................ 15
Applications and Implementation ...................... 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
9.3 Do's and Don'ts ...................................................... 21
9.4 Initialization Set Up ................................................ 21
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
典型应用................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information ................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 I2C Interface Voltage Level ...................................... 5
7.7 I2C Interface Timing ................................................. 6
7.8 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 商标....................................................................... 22
12.2 静电放电警告......................................................... 22
12.3 术语表 ................................................................... 22
13 机械封装和可订购信息 .......................................... 22
8
5 修订历史记录
Changes from Original (August 2014) to Revision A
Page
•
•
•
Added Parameter not tested in production ............................................................................................................................ 5
Changed CINx to CINn throughout ....................................................................................................................................... 9
Added note for Applications and Implementation section. ................................................................................................... 19
2
Copyright © 2014, Texas Instruments Incorporated
FDC1004
www.ti.com.cn
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
6 Pin Configuration and Functions
WSON (DSC)
10 Pins
Top View
1
2
3
4
10
9
SHLD1
CIN1
CIN2
CIN3
CIN4
SDA
SCL
DAP
(GND)
8
VDD
7
GND
SHLD2
5
6
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
SHLD1
1
A
A
Capacitive Input Active AC Shielding.
Capacitive Input. The measured capacitance is connected between the CIN1 pin and GND. If
not used, this pin should be left as an open circuit.
CIN1
CIN2
CIN3
CIN4
2
3
4
5
Capacitive Input. The measured capacitance is connected between the CIN2 pin and GND. If
not used, this pin should be left as an open circuit.
A
A
A
Capacitive Input. The measured capacitance is connected between the CIN3 pin and GND. If
not used, this pin should be left as an open circuit.
Capacitive Input. The measured capacitance is connected between the CIN4 pin and GND. If
not used, this pin should be left as an open circuit.
SHLD2
GND
6
7
A
Capacitive Input Active AC Shielding.
Ground
G
Power Supply Voltage. This pin should be decoupled to GND, using a low impedance
capacitor, for example in combination with a 1-μF tantalum and a 0.1-μF multilayer ceramic.
VDD
SCL
8
9
P
I
Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not
already provided elsewhere in the system.
Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up
resistor if not provided elsewhere in the system.
SDA
10
-
I/O
DAP(2)
N/A
Connect to GND
(1) P=Power, G=Ground, I=Input, O=Output, A=Analog
(2) There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the GND pin of the device. Although the DAP
can be left floating, for best performance the DAP should be connected to the same potential as the device's GND pin. Do not use the
DAP as the primary ground for the device. The device GND pin must always be connected to ground.
Copyright © 2014, Texas Instruments Incorporated
3
FDC1004
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
Input voltage
VDD
6
SCL, SDA
at any other pin
at any pin
6
VDD+0.3
3
V
V
Input current
Junction temperature(2)
mA
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC
board.
7.2 Handling Ratings
MIN
MAX
UNIT
TSTG
Storage Temperature
–65
150
°C
V(ESD)
Human body model (HBM), per
–1000
–250
1000
250
V
V
ANSI/ESDA/JEDEC JS-001, all pins(2)
Electrostatic discharge(1)
Charged device model (CDM), per JEDEC
specification -500 500 JESD22-C101, all pins(3)
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.6
UNIT
V
Supply voltage (VDD-GND)
Temperature
3.3
–40
85
°C
7.4 Thermal Information
FDC1004
THERMAL METRIC(1)
WSON
10 PINS
46.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
FDC1004
www.ti.com.cn
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
7.5 Electrical Characteristics
Over recommended operating temperature range, VDD = 3.3 V, for TA = 25°C (unless otherwise noted).
PARAMETER
POWER SUPPLY
IDD Supply current
TEST CONDITION
MIN
TYP
MAX
UNIT
Conversion mode; Digital input to
VDD or GND
750
29
950
70
µA
µA
Standby; Digital input to VDD or
GND
CAPACITIVE INPUT
ICR
Input conversion range
±15
100
pF
pF
COMAX
Max input offset capacitance
per channel, Series resistance at
CINn n=1.4 = 0 Ω
(1)
(2)
RES
Effective resolution
Sample rate = 100S/s
16
33.2
±6
bit
aF/√Hz
fF
(2)
EON
ERR
TcCOFF
GERR
tcG
Output noise
Sample rate = 100S/s
Absolute error
after offset calibration
-40°C < T < 85°C
Offset deviation over temperature
Gain rrror
30
fF
0.07
2.1
% of FS
Gain drift vs. temperature
-40°C < T < 85°C
3 V < VDD < 3.6 V
ppm of
FSR/°C
PSRR
DC power supply rejection
11
fF/V
CAPDAC
FRCAPDAC
Full-scale range
96.875
pF
bit
RESCAPDAC Resolution
5
1
TcCOFFCAP Offset drift vs. temperature
DAC
-40°C < T < 85°C
ppm of
FS/°C
EXCITATION
ƒ
Frequency
25
2.4
1.2
kHz
Vpp
V
VAC
VDC
AC voltage across capacitance
Average DC voltage across
capacitance
SHIELD
DRV
Driver capability
ƒ = 25 kHz, SHLDn to GND, n = 1,2
400
pF
(1) Effective resolution is the ratio of converter full scale range to RMS measurement noise.
(2) No external capacitance connected.
7.6 I2C Interface Voltage Level
Over recommended operating free-air temperature range, VDD = 3.3 V, for TA = TJ = 25°C (unless otherwise noted).
PARAMETER
Input high voltage
Input low voltage
Output low voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
0.7*VDD
V
V
V
V
VIL
0.3*VDD
0.4
VOL
HYS
Sink current 3 mA
(1)
Hysteresis
0.1*VDD
(1) This parameter is specified by design and/or characterization and is not tested in production.
Copyright © 2014, Texas Instruments Incorporated
5
FDC1004
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
www.ti.com.cn
7.7 I2C Interface Timing
Over recommended operating free-air temperature range, VDD = 3.3 V, for TA = TJ = 25°C (unless otherwise noted).
PARAMETER
Clock frequency(1)
Clock low time(1)
Clock high time(1)
TEST CONDITIONS
MIN
10
TYP
MAX
UNIT
kHz
µs
fSCL
400
tLOW
1.3
0.6
0.6
tHIGH
tHD;STA
µs
Hold time (repeated) START
condition(1)
After this period, the first clock pulse
is generated
µs
tSU;STA
Set-up time for a repeated START
condition(1)
0.6
µs
tHD;DAT
tSU;DAT
tf
Data hold time(1)(2)
Data setup time(1)
SDA fall time(1)
Set-up time for STOP condition(1)
0
ns
ns
ns
µs
µs
100
IL ≤ 3mA; CL ≤ 400pF
300
tSU;STO
tBUF
0.6
1.3
Bus free time between a STOP and
START condition(1)
tVD;DAT
tVD;ACK
tSP
Data valid time(1)
Data valid acknowledge time(1)
0.9
0.9
50
ns
ns
ns
Pulse width of spikes that must be
suppressed by the input filter(1)
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) The FDC1004 provides an internal 300 ns minimum hold time to bridge the undefined region of the falling edge of SCL.
SDA
t
BUF
t
t
f
LOW
t
HD;STA
t
r
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 1. I2C Timing
6
Copyright © 2014, Texas Instruments Incorporated
FDC1004
www.ti.com.cn
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
7.8 Typical Characteristics
900
40
35
30
25
20
VDD=3.0V
VDD=3.3V
VDD=3.6V
VDD=3.0V
VDD=3.3V
VDD=3.6V
850
800
750
700
650
600
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 2. Active Conversion Mode Supply Current vs.
Figure 3. Stand-by Mode Supply Current vs. Temperature
Temperature
0.02
0.015
0.01
1000
800
600
400
200
0
0.005
0
-0.005
-0.01
-0.015
-200
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (*C)
Temperature (°C)
CINn = 10 pF
n = 1...4
CINn = open
n = 1...4
Figure 4. Gain Drift vs. Temperature
Figure 5. Offset Drift vs. Temperature
10
0
10
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-100
-110
-120
-130
-140
-150
10-1
100
101
102
103
104
105
10-1
100
101
102
103
104
105
Frequency (Hz)
Frequency (Hz)
Figure 6. Frequency Response 100S/s
Figure 7. Frequency Response 200S/s
Copyright © 2014, Texas Instruments Incorporated
7
FDC1004
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
www.ti.com.cn
Typical Characteristics (continued)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
10-1
100
101
102
103
104
105
Frequency (Hz)
Figure 8. Frequency Response 400S/s
8
Copyright © 2014, Texas Instruments Incorporated
FDC1004
www.ti.com.cn
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
8 Detailed Description
8.1 Overview
The FDC1004 is a high-resolution, 4-channel capacitance-to-digital converter for implementing capacitive
sensing solutions. Each channel has a full scale range of ±15 pF and can handle a sensor offset capacitance of
up to 100 pF, which can be either programmed internally or can be an external capacitor for tracking
environmental changes over time and temperature. The large offset capacitance capability allows for the use of
remote sensors. The FDC1004 also includes shield drivers for sensor shields, which can reduce EMI interference
and help focus the sensing direction of a capacitive sensor. The small footprint of the FDC1004 allows for use in
space-constrained applications.
8.2 Functional Block Diagram
CIN1
VDD
FDC1004
CIN2
M
CHA
U
X
OFFSET
&
GAIN
SHLD1
SHLD2
CAPACITANCE
TO DIGITAL
CONVERTER
EXCITATION
SDA
SCL
I2C
CALIBRATION
CONFIGURATION REGISTERS
&
M
U
X
DATA REGISTERS
CHB
CIN3
CIN4
CAPDAC
GND
8.3 Feature Description
8.3.1 The Shield
The FDC1004 measures capacitance between CINn and ground. That means any capacitance to ground on
signal path between the FDC1004 CINn pins and sensor is included in the FDC1004 conversion result.
In some applications, the parasitic capacitance of the sensor connections can be larger than the capacitance of
the sensor. If that parasitic capacitance is stable, it can be treated as a constant capacitive offset. However, the
parasitic capacitance of the sensor connections can have significant variation due to environmental changes
(such as mechanical movement, temperature shifts, humidity changes). These changes are seen as drift in the
conversion result and may significantly compromise the system accuracy.
To eliminate the CINn parasitic capacitance to ground, the FDC1004 SHLDx signals can be used for shielding
the connection between the sensor and CINn. The SHLDx output is the same signal waveform as the excitation
of the CINn pin; the SHLDx is driven to the same voltage potential as the CINn pin. Therefore, there is no current
between CINn and SHLDx pins, and any capacitance between these pins does not affect the CINn charge
transfer. Ideally, the CINn to SHLD capacitance does not have any contribution to the FDC1004 result.
In differential measurements, SHLD1 is assigned to CHn and SHLD2 is assigned to CHm, where n < m. For
instance in the measurement CIN2 – CIN1, where CHA = CIN2 and CHB = CIN1 (see Table 4), SHDL1 is
assigned to CIN1 and SHDL2 is assigned to CIN2.
Copyright © 2014, Texas Instruments Incorporated
9
FDC1004
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
www.ti.com.cn
Feature Description (continued)
In a single ended configuration, such as CINn vs. GND, SHLD1 is internally shorted to SHLD2. In a single ended
configuration, such as CINn vs. GND with CAPDAC enabled, SHLD1 is assigned to the selected channel,
SHLD2 is floating.
For best results, locate the FDC1004 as close as possible to the capacitive sensor. Minimize the connection
length between the sensor and FDC1004 CINn pins and between the sensor ground and the FDC1004 GND pin.
Shield the PCB traces to the CINn pins and connect the shielding to the FDC1004 SHLDx pins. In addition, if a
shielded cable is used to connect the FDC1004 to the sensor, the shield should be connected to the appropriate
SHLDx pin.
In applications where only one SHLDx pin is used, the unused SHLDx pin can be left unconnected.
8.3.2 The CAPDAC
The FDC1004 full-scale input range is ±15 pF. The part can accept a higher capacitance on the input and the
common-mode or offset (constant component) capacitance can be balanced by the programmable on-chip
CAPDACs. The CAPDAC can be viewed as a negative capacitance connected internally to the CINn pin. The
relation between the input capacitance and output data can be expressed as DATA = (CINn – CAPDAC), n =
1...4. The CAPDACs have a 5-bit resolution, monotonic transfer function, are well matched to each other, and
have a defined temperature coefficient.
8.3.3 Capacitive System Offset Calibration
The capacitive offset can be due to many factors including the initial capacitance of the sensor, parasitic
capacitances of board traces, and the capacitance of any other connections between the sensor and the FDC.
The parasitic capacitances of the FDC1004 are calibrated out at production. If there are other sources of offset in
the system, it may be necessary to calibrate the system capacitance offset in the application. Any offset in the
capacitance input larger than ½ LSB of the CAPDAC should first be removed using the on-chip CAPDACs. Any
residual offset of approximately 1 pF can then be removed by using the capacitance offset calibration register.
The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset
calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the
host controller and reloaded as part of the FDC1004 setup.
8.3.4 Capacitive Gain Calibration
The gain is factory calibrated up to ±15 pF in the production for each part individually. The factory gain coefficient
is stored in a one-time programmable (OTP) memory.
The gain can be temporarily changed by setting the Gain Calibration Register (registers 0x11 to 0x14) for the
appropriate CINn pin, although the factory gain coefficient will be restored after power-up or reset.
The part is tested and specified for use only with the default factory calibration coefficient. Adjusting the Gain
calibration can be used to normalize the capacitance measurement of the CINn input channels.
8.4 Device Functional Modes
8.4.1 Single Ended Measurement
The FDC1004 can be used for interfacing to a single-ended capacitive sensor. In this configuration the sensor
should be connected to the input CINn (n = 1..4) pins of the FDC1004 and GND. The capacitance-to-digital
convertor (without using the CAPDAC, CAPDAC= 0pF) measures the positive (or the negative) input capacitance
in the range of 0 pF to 15 pF. The CAPDAC can be used for programmable shifting of the input range. In this
case it is possible to measure input capacitance in the range of 0 pF to ±15 pF which are on top of an offset
capacitance up to 100 pF. In single ended measurements with CAPDAC disabled SHLD1 is internally shorted to
SHLD2 (see Figure 9); if CAPDAC is enabled SHLD2 is floating (see Figure 10). The single ended mode is
enabled when the CHB register of the Measurements configuration registers (see Table 4) are set to b100 or
b111.
10
Copyright © 2014, Texas Instruments Incorporated
FDC1004
www.ti.com.cn
ZHCSCQ6A –AUGUST 2014–REVISED OCTOBER 2014
Device Functional Modes (continued)
CIN1
CIN2
VDD
FDC1004
M
U
X
CHA
OFFSET
&
GAIN
SHLD1
SHLD2
CAPACITANCE
TO DIGITAL
CONVERTER
EXCITATION
SDA
I2C
CALIBRATION
SCL
CONFIGURATION REGISTERS
&
M
U
X
DATA REGISTERS
CHB
CIN3
CIN4
S1
S2
S3
S4
CAPDAC
GND
Figure 9. Single-Ended Configuration with CAPDAC Disabled
CIN1
VDD
FDC1004
CIN2
M
CHA
U
X
OFFSET
&
GAIN
SHLD1
SHLD2
CAPACITANCE
TO DIGITAL
CONVERTER
EXCITATION
SDA
SCL
I2C
CALIBRATION
CONFIGURATION REGISTERS
&
M
U
X
DATA REGISTERS
CHB
CIN3
CIN4
S1
S2
S3
S4
CAPDAC
GND
Figure 10. Single-Ended Configuration with CAPDAC Enabled
8.4.2 Differential Measurement
When the FDC1004 is used for interfacing to a differential capacitive sensor, each of the two input capacitances
must be less than 115 pF. In this configuration the CAPDAC is disabled. The absolute value of the difference
between the two input capacitances should be kept below 15 pF to avoid introducing errors in the measurement.
In differential measurements, SHLD1 is assigned to CHn and SHLD2 is assigned to CHm, where n < m. For
instance in the measurement CIN2 – CIN1, where CHA = CIN2 and CHB = CIN1 (see Table 4), SHDL1 is
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Device Functional Modes (continued)
assigned to CIN1 and SHDL2 is to CIN2. In the picture below a couple of differential sensors made with S1
versus S3 and S2 versus S4 is shown. S1 and S2 are alternatively connected to CHA and the S3 and S4 are
alternatively connected to CHB, the shield signals are connected as explained in previous paragraph. The
FDC1004 will perform a differential measurement when CHB field of the Measurements Configuration Registers
(refer to Table 4) is less than to b100.
This configuration is very useful in applications where environment conditions need to be tracked. The differential
measurement between the main electrode and the environment electrode makes the measurement independent
of the environment conditions.
CIN1
VDD
FDC1004
CIN2
M
CHA
U
X
OFFSET
&
GAIN
SHLD1
SHLD2
CAPACITANCE
TO DIGITAL
CONVERTER
EXCITATION
SDA
SCL
I2C
CALIBRATION
CONFIGURATION REGISTERS
&
M
U
X
DATA REGISTERS
CHB
CIN3
CIN4
S1
S2
S3
S4
CAPDAC
GND
Figure 11. Differential Configuration
8.5 Programming
The FDC1004 operates only as a slave device on the two-wire bus interface. Every device on the bus must have
a unique address. Connection to the bus is made via the open-drain I/O lines, SDA, and SCL. The SDA and SCL
pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and
bus noise. The FDC1004 supports fast mode frequencies 10 kHz to 400 kHz. All data bytes are transmitted MSB
first.
8.5.1 Serial Bus Address
To communicate with the FDC1004, the master must first address slave devices via a slave address byte. The
slave address byte consists of seven address bits and a direction bit that indicates the intent to execute a read or
write operation. The seven bit address for the FDC1004 is (MSB first): b101 0000.
8.5.2 Read/Write Operations
Access a particular register on the FDC1004 by writing the appropriate value to the Pointer Register. The pointer
value is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the
FDC1004 requires a value for the pointer register. When reading from the FDC1004, the last value stored in the
pointer by a write operation is used to determine which register is read by a read operation. To change the
pointer register for a read operation, a new value must be written to the pointer. This transaction is accomplished
by issuing the slave address byte with the R/W bit low, followed by the pointer byte. No additional data is
12
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Programming (continued)
required. The master can then generate a START condition and send the slave address byte with the R/W bit
high to initiate the read command. Note that register bytes are sent MSB first, followed by the LSB. A write
operation in a read only registers such as MANUFACTURER ID or SERIAL ID returns a NACK after each data
byte; read/write operation to unused address returns a NACK after the pointer; a read/write operation with
incorrect I2C address returns a NACK after the I2C address.
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
R/W
Start by
Master
Ack by
Slave
Ack by
Slave
Frame 1
7-bit Serial Bus Address Byte
Frame 2
Pointer Register Byte
1
9
1
9
SCL
SDA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ack by
Slave
Ack by
Slave
Stop by
Master
Frame 3
Data MSB from
SLAVE
Frame 4
Data LSB from
SLAVE
Figure 12. Write Frame
1
9
1
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
P7 P6 P5 P4 P3 P2 P1 P0
Start by
Master
Ack by
Slave
Ack by
Slave
Frame 1
Frame 2
7-bit Serial Bus Address Byte
Pointer Register Byte
1
9
1
9
1
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start by
Master
Ack by
Slave
Ack by
Master
Nack by Stop by
Master Master
Frame 4
Data MSB from
Slave
Frame 5
Data LSB from
Slave
Frame 3
7-bit Serial Bus Address Byte
Figure 13. Read Frame
8.5.3 Device Usage
The basic usage model of the FDC1004 is to simply follow these steps:
1. Configure measurements (for details, refer to Measurement Configuration).
2. Trigger a measurement set (for details, refer to Triggering Measurements).
3. Wait for measurement completion (for details, refer to Wait for Measurement Completion).
4. Read measurement data (for details, refer to Read of Measurement Result).
8.5.3.1 Measurement Configuration
Configuring a measurement involves setting the input channels and the type of measurement (single-ended or
differential).
The FDC1004 can be configured with up to 4 separate measurements, where each measurement can be any
valid configuration (that is, a specific channel can be used in multiple measurements). There is a dedicated
configuration register for each of the 4 possible measurements (e.g MEAS_CONF1 in register 0x08 configures
measurement 1, MEAS_CONF2 in register 0x09 configures measurement 2, ...). Configuring only one
measurement is fine, and it can be any one of the 4 possible measurement configuration.
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Programming (continued)
1. Setup the input channels for each measurement. Determine which of the 4 measurement configuration
registers to use (registers 0x08 to 0x0A) and set the following:
(a) For single-ended measurement:
(a) Select the positive input pin for the measurement by setting the CHA field (bits[15:13]).
(b) Set CAPDAC (bits[9:5]) if the channel offset capacitance is more than 15pF.
(b) For a differential measurement:
(a) Select the positive input pin for the measurement by setting the CHA field (bits[15:13]).
(b) Select the negative input pin for the measurement by setting the CHB field (bits[12:10]). Note that the
CAPDAC setting has no effect for a differential measurement.
2. Determine the appropriate sample rate. The sample rate sets the resolution of the measurement. Lower the
sample rate higher is the resolution of the measurement.
8.5.3.2 Triggering Measurements
For a single measurement, trigger the desired measurement (i.e. which one of the configured measurements)
when needed by:
1. Setting REPEAT (Register 0x0C:bit[8]) to 0.
2. Setting the corresponding MEAS_x field (Register 0x0C:bit[7:4]) to 1.
–
For example, to trigger a single measurement of Measurement 2 at a rate of 100S/s, set Address 0x0C to
0x0540.
Note that, at a given time, only one measurement of the configured measurements can be triggered in this
manner (i.e. MEAS_1 and MEAS_2 cannot both be triggered in a single operation).
The FDC1004 can also trigger a new measurement on the completion of the previous measurement (repeated
measurements). This is setup by:
1. Setting REPEAT (Register 0x0C:bit[8]) to 1.
2. Setting the corresponding MEAS_x field (Register 0x0C:bit[7:4]) to 1.
When the FDC1004 is setup for repeated measurements, multiple configured measurements (up to a maximum
of 4) can be performed in this manner, but Register 0x0C must be written in a single transaction.
8.5.3.3 Wait for Measurement Completion
Wait for the triggered measurements to complete. When the measurements are complete, the corresponding
DONE_x field (Register 0x0C:bits[3:0]) will be set to 1.
8.5.3.4 Read of Measurement Result
Read the result of the measurement from the corresponding registers:
•
•
•
•
0x00/0x01 for Measurement 1
0x02/0x03 for Measurement 2
0x04/0x05 for Measurement 3
0x06/0x07 for Measurement 4
The measurement results span 2 register addresses; both registers must be read to have a complete conversion
result. The lower address (e.g. 0x00 for Measurement 1) must be read first, then the upper address read
afterwards (for example, 0x01 for Measurement 1).
Once the measurement read is complete, the corresponding DONE_x field (Register 0x0C:bits[3:0]) will return to
0.
If an additional single triggered measurement is desired, simply perform the Trigger, Wait, Read steps again.
If the FDC1004 is setup for repeated measurements (Register 0x0C:bit[8]) = 1), the FDC1004 will continuously
measure until the REPEAT field (Register 0x0C:bit[8]) is set to 0, even if the results are not read back.
14
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8.6 Register Maps
Table 1. Register Map
Pointer
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0xFE
0xFF
Register Name
Reset Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x1C00
0x1C00
0x1C00
0x1C00
0x0000
0x0000
0x0000
0x0000
0x0000
0x4000
0x4000
0x4000
0x4000
0x5449
0x1004
Description
MEAS1_MSB
MEAS1_LSB
MSB portion of Measurement 1
LSB portion of Measurement 1
MSB portion of Measurement 2
LSB portion of Measurement 2
MSB portion of Measurement 3
LSB portion of Measurement 3
MSB portion of Measurement 4
LSB portion of Measurement 4
Measurement 1 Configuration
Measurement 2 Configuration
Measurement 3 Configuration
Measurement 4 Configuration
Capacitance to Digital Configuration
CIN1 Offset Calibration
MEAS2_MSB
MEAS2_LSB
MEAS3_MSB
MEAS3_LSB
MEAS4_MSB
MEAS4_LSB
CONF_MEAS1
CONF_MEAS2
CONF_MEAS3
CONF_MEAS4
FDC_CONF
OFFSET_CAL_CIN1
OFFSET_CAL_CIN2
OFFSET_CAL_CIN3
OFFSET_CAL_CIN4
GAIN_CAL_CIN1
GAIN_CAL_CIN2
GAIN_CAL_CIN3
GAIN_CAL_CIN4
Manufacturer ID
Device ID
CIN2 Offset Calibration
CIN3 Offset Calibration
CIN4 Offset Calibration
CIN1 Gain Calibration
CIN2 Gain Calibration
CIN3 Gain Calibration
CIN4 Gain Calibration
ID of Texas Instruments
ID of FDC1004 device
Registers from 0x15 to 0xFD are reserved and should not be written to.
8.6.1 Registers
The FDC1004 has an 8-bit pointer used to address a given data register. The pointer identifies which of the data
registers should respond to a read or write command on the two-wire bus. This register is set with every write
command. A write command must be issued to set the proper value in the pointer before executing a read
command. The power-on reset (POR) value of the pointer is 0x00.
8.6.1.1 Capacitive Measurement Registers
The capacitance measurement registers are 24-bit result registers in binary format (the 8 LSBs D[7:0] are always
0x00). The result of the acquisition is always a 24 bit value, while the accuracy is related to the selected
conversion time (refer to Electrical Characteristics). The data is encoded in a Two’s complement format. The
result of the measurement can be calculated by the following formula:
Capacitance (pf) = Two's Complement (measurement [23:0])/219) + Coffset
where
•
Coffset is based on the CAPDAC setting.
(1)
Table 2. Measurement Registers Description (0x00, 0x02, 0x04, 0x06)
Field Name
MSB_MEASn(1)
Bits
[15:0]
Description
Most significant 16 bits of Measurement n (read only)
(1) MSB_MEAS1 = register 0x00, MSB_MEAS2 = register 0x02, MSB_MEAS3 = register 0x04, MSB_MEAS4 = register 0x06
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Table 3. Measurement Registers Description (0x01, 0x03, 0x05, 0x07)
Field Name
LSB_MEASn(1)
Bits
[15:8]
[7:0]
Description
Least significant 8 bits of Measurement n (read only)
Reserved, always 0 (read only)
Reserved
(1) LSB_MEAS1 = register 0x01, LSB_MEAS2 = register 0x03, LSB_MEAS3 = register 0x05, LSB_MEAS4 = register 0x07
8.6.2 Measurement Configuration Registers
These registers configure the input channels and CAPDAC setting for a measurement.
Table 4. Measurement Configuration Registers Description (0x08, 0x09, 0x0A, 0x0B)
Field Name
Bits
Description
CHA(1)(2)
[15:13]
Positive input b000
CIN1
channel
capacitive to
digital
converter
b001
CIN2
b010
b011
b000
b001
b010
b011
b100
b111
b00000
- - - - -
CIN3
CIN4
CHB(1)(2)
[12:10]
Negative
CIN1
input channel
capacitive to
digital
CIN2
CIN3
converter
CIN4
CAPDAC
DISABLED
CAPDAC
[9:5]
Offset
Capacitance
0pF (minimum programmable offset)
Configure the single-ended measurement capacitive offset:
Coffset = CAPDAC x 3.125pF
b11111
96.875pF (maximum programmable offset)
Reserved, always 0 (read only)
RESERVED
[04:00]
Reserved
(1) It is not permitted to configure a measurement where the CHA field and CHB field hold the same value (for example, if
CHA=b010, CHB cannot also be set to b010).
(2) It is not permitted to configure a differential measurement between CHA and CHB where CHA > CHB (for example, if CHA=
b010, CHB cannot be b001 or b000).
8.6.3 FDC Configuration Register
This register configures measurement triggering and reports measurement completion.
Table 5. FDC Register Description (0x0C)
Field Name
Bits
[15]
Description
RST
Reset
0
1
Normal operation
Software reset: write a 1 to initiate a device reset; after completion of reset this
field will return to 0
RESERVED
RATE
[14:12]
[11:10]
Reserved
Reserved, always 0 (read only)
Measurement b00 Reserved
Rate
b01 100S/s
b10 200S/s
b11 400S/s
RESERVED
REPEAT
[9]
[8]
Reserved
Reserved, always 0 (read only)
Repeat
Measurements
0
1
0
1
0
1
Repeat disabled
Repeat enabled, all the enabled measurement are repeated
Measurement 1 disabled
MEAS_1
MEAS_2
[7]
[6]
Initiate
Measurements
Measurement 1 enabled
Initiate
Measurements
Measurement 2 disabled
Measurement 2 enabled
16
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Table 5. FDC Register Description (0x0C) (continued)
Field Name
Bits
Description
Measurement 3 disabled
MEAS_3
[5]
[4]
[3]
[2]
[1]
[0]
Initiate
Measurements
0
1
0
1
0
1
0
1
0
1
0
1
Measurement 3 enabled
MEAS_4
DONE_1
DONE_2
DONE_3
DONE_4
Initiate
Measurements
Measurement 4 disabled
Measurement 4 enabled
Measurement
Done
Measurement 1 not completed
Measurement 1 completed
Measurement 2 not completed
Measurement 2 completed
Measurement 3 not completed
Measurement 3 completed
Measurement 4 not completed
Measurement 4 completed
Measurement
Done
Measurement
Done
Measurement
Done
8.6.4 Offset Calibration Registers
These registers configure a digitized capacitance value in the range of -16 pF to 16 pF (max residual offset 250
aF) that can be added to each channel in order to remove parasitic capacitance due to external circuitry. In
addition to the offset calibration capacitance which is a fine-tune offset capacitance, it is possible to support a
larger offset by using the CAPDAC (for up to 100 pF). These 16-bit registers are formatted as a fixed point
number, where the first 5 bits represents the integer portion of the capacitance in Two’s complement format, and
the remaining 11 bits represent the fractional portion of the capacitance.
Table 6. Offset Calibration Registers Description (0x0D, 0x0E, 0x0F, 0x10)
Field Name
Bits
Description
OFFSET_CALn(1) [15:11]
Integer part
Decimal part
Integer portion of the Offset Calibration of Channel CINn
Decimal portion of the Offset Calibration of Channel CINn
[10:0]
(1) OFFSET_CAL1 = register 0x0D, OFFSET_CAL2 = register 0x0E, OFFSET_CAL3 = register 0x0F, OFFSET_CAL4 = register 0x10
8.6.5 Gain Calibration Registers
These registers contain a gain factor correction in the range of 0 to 4 that can be applied to each channel in
order to remove gain mismatch due to the external circuitry. This 16-bit register is formatted as a fixed point
number, where the 2 MSBs of the GAIN_CALn register correspond to an integer portion of the gain correction,
and the remaining 14 bits represent the fractional portion of the gain correction. The result of the conversion
represents a number without dimensions.
The Gain can be set according to the following formula:
Gain = GAIN_CAL[15:0]/214
Table 7. Gain Calibration Registers Description (0x11, 0x12, 0x13, 0x14)
Field Name
GAIN_CALn(1)
Bits
[15:14]
[13:0]
Description
Integer part
Decimal part
Integer portion of the Gain Calibration of Channel CINn
Decimal portion of the Gain Calibration of Channel CINn
(1) GAIN_CAL1 = register 0x11, GAIN_CAL2 = register 0x12, GAIN_CAL3 = register 0x13, GAIN_CAL4 = register 0x14
8.6.6 Manufacturer ID Register
This register contains a factory-programmable identification value that identifies this device as being
manufactured by Texas Instruments. This register distinguishes this device from other devices that are on the
same I2C bus. The manufacturer ID reads 0x5449.
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Table 8. Manufacturer ID Register Description (0xFE)
Field Name
Bits
Description
MANUFACTURER [15:0]
ID
Manufacturer 0x5449h
ID
Texas instruments ID (read only)
8.6.7 Device ID Register
This register contains a factory-programmable identification value that identifies this device as a FDC1004. This
register distinguishes this device from other devices that are on the same I2C bus. The Device ID for the
FDC1004 is 0x1004.
Table 9. Device ID Register Description (0xFF)
Field Name
Bits
[15:0]
Description
DEVICE ID
Device ID
0x1004
FDC1004 Device ID (read only)
18
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Liquid Level Measurement
The FDC1004 can be used to measure liquid level in non-conductive containers. Capacitive sensors can be
attached to the outside of the container or be located remotely from the container, allowing for contactless
measurements. The working principle is based on a ratiometric measurement; Figure 14 shows a possible
system implementation which uses three electrodes. The Level electrode provides a capacitance value
proportional to the liquid level. The Reference Environmental electrode and the Reference Liquid electrode are
used as references. The Reference Liquid electrode accounts for the liquid dielectric constant and its variation,
while the Reference Environmental electrode is used to compensate for any other environmental variations that
are not due to the liquid itself. Note that the Reference Environmental electrode and the Reference Liquid
electrode are the same physical size (hREF).
For this application, single-ended measurements on the appropriate channels are appropriate, as the tank is
grounded.
Use the following formula to determine the liquid level from the measured capacitances:
CLev ꢀ CLev (0)
CRL ꢀ CRE
Level href
where
•
•
•
•
•
CRE is the capacitance of the Reference Environmental electrode,
CRL is the capacitance of the Reference Liquid electrode,
CLev is the current value of the capacitance measured at the Level electrode sensor,
CLev(0) is the capacitance of the Level electrode when the container is empty, and
hREF is the height in the desired units of the Container or Liquid Reference electrodes.
The ratio between the capacitance of the level and the reference electrodes allows simple calculation of the liquid
level inside the container itself. Very high sensitivity values (that is, many LSB/mm) can be obtained due to the
high resolution of the FDC1004, even when the sensors are located remotely from the container.
9.2 Typical Application
3.3 V
VDD
SHLD1
SHLD2
LEVEL
SENSOR
EXCITATION
CHA
ENVIRONMENTAL
SENSOR
3.3 V
3.3 V
CIN1
CIN2
CIN3
CIN4
FDC1004
3.3 V
VDD
CHA
MUX
OFFSET
& GAIN
CALIBRATION
CAPACITANCE
TO DIGITAL
CONVERTER
LIQUID
SENSOR
MCU
CHB
MUX
SCL
SDA
CHB
I2C
Peripheral
I2C
CONFIGURATION & DATA
REGISTERS
GND
CAPDAC
GND
Figure 14. FDC1004 (Liquid Level Measurement)
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Typical Application (continued)
9.2.1 Design Requirements
The liquid level measurement should be independent of the liquid, which can be achieved using the 3-electrode
design described above. Moreover, the sensor should be immune to environmental interferers such as a human
body, other objects, or EMI. This can be achieved by shielding the side of the sensor which does not face the
container.
9.2.2 Detailed Design Procedure
In capacitive sensing systems, the design of the sensor plays an important role in determining system
performance and capabilities. In most cases the sensor is simply a metal plate that can be designed on the PCB.
The sensor used in this example is implemented with a two-layer PCB. On the top layer, which faces the tank,
there are the 3 electrodes (Reference Environmental, Reference Liquid, and Level) with a ground plane
surrounding the electrodes. The bottom layer is covered with a shield plane in order to isolate the electrodes
from any external interference sources.
Depending on the shape of the container, the FDC1004 can be located on the sensor PCB to minimize the
length of the traces between the input channels and the sensors and increase the immunity from EMI sources. In
case the shape of the container or other mechanical constraints do not allow having the sensors and the
FDC1004 on the same PCB, the traces which connect the channels to the sensor need to be shielded with the
appropriate shield. In this design example all of the channels are shielded with SHLD1. For this configuration, the
FDC1004 measures the capacitance of the 3 channels versus ground; and so the SHLD1 and SHLD2 pins are
internally shorted in the FDC1004 (see The Shield).
9.2.3 Application Performance Plot
The data shown below has been collected with the FDC1004EVM. A liquid level sensor with 3 electrodes like the
one shown in the schematic was connected to the EVM. The plot shows the capacitance measured by the 3
electrodes at different levels of liquid in the tank. The capacitance of the Reference Liquid (the RF trace in the
graph below) and Reference Environmental (the RE trace) sensors have a steady value when the liquid is above
their height while the capacitance of the level sensor (Level) increases linearly with the height of the liquid in the
tank.
4.5
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
RF
RE
Level
4
3.5
3
2.5
2
1.5
1
0
5
10
15
20
25
30
35
40
45
50
Level (mm)
Figure 15. Electrodes' Capacitance vs. Liquid Level
20
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9.3 Do's and Don'ts
Avoid long traces to connect the sensor to the FDC1004. Short traces reduce parasitic capacitances between
shield versus input channel and parasitic resistance between input channel versus GND and shield versus GND.
Since the sensor in many cases is simply a metal surface on a PCB, it needs to be protected with solder resist to
avoid short circuits and limit any corrosion. Any change in the sensor may result in a change in system
performance.
9.4 Initialization Set Up
At power on the device is in stand-by. It stays in this mode until a measurement is triggered.
10 Power Supply Recommendations
The FDC1004 requires a voltage supply within 3 V and 3.6 V. Two multilayer ceramic bypass X7R capacitors of
0.1 μF and 1 μF, respectively between VDD and GND pin are recommended. The 0.1-μF capacitor should be
closer to the VDD pin than the 1-μF capacitor.
11 Layout
11.1 Layout Guidelines
The FDC1004 measures the capacitances connected between the CINn (n=1..4) pins and GND. To get the best
result, locate the FDC1004 as close as possible to the capacitive sensor. Minimize the connection length
between the sensor and FDC1004 CINn pins and between the sensor ground and the FDC1004 GND pin. If a
shielded cable is used for remote sensor connection, the shield should be connected to the SHLDm (m=1...2) pin
according to the configured measurement.
11.2 Layout Example
Figure 16 below is optimized for applications where the sensor is not too far from the FDC1004. Each channel
trace runs between 2 shield traces. This layout allows the measurements of 4 single ended capacitance or 2
differential capacitance. The ground plane needs to be far from the channel traces, it is mandatory around or
below the I2C pin.
TOP LAYER
BOTTOM LAYER
Figure 16. Layout
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12 器件和文档支持
12.1 商标
All trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
FDC1004DGSR
FDC1004DGST
FDC1004DSCJ
FDC1004DSCR
FDC1004DSCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
WSON
WSON
WSON
DGS
DGS
DSC
DSC
DSC
10
10
10
10
10
3500 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ZBNX
ZBNX
SN
SN
SN
SN
4500 RoHS & Green
1000 RoHS & Green
F1004
F1004
F1004
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
FDC1004DGSR
FDC1004DGST
FDC1004DSCJ
FDC1004DSCR
FDC1004DSCT
VSSOP
VSSOP
WSON
WSON
WSON
DGS
DGS
DSC
DSC
DSC
10
10
10
10
10
3500
250
330.0
178.0
330.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
5.3
5.3
3.3
3.3
3.3
3.4
3.4
3.3
3.3
3.3
1.4
1.4
1.0
1.0
1.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
4500
1000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
FDC1004DGSR
FDC1004DGST
FDC1004DSCJ
FDC1004DSCR
FDC1004DSCT
VSSOP
VSSOP
WSON
WSON
WSON
DGS
DGS
DSC
DSC
DSC
10
10
10
10
10
3500
250
367.0
210.0
367.0
210.0
210.0
367.0
185.0
367.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
4500
1000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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