概述
规格参数
数据手册FPD87346BXAVS 概述
SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64, TQFP-64 其他 uPs/uCs/外围集成电路
FPD87346BXAVS 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | QFP |
| 包装说明： | TFQFP, TQFP64,.47SQ | 针数： | 64 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.31.00.01 |
| 风险等级： | 5.69 | JESD-30 代码： | S-PQFP-G64 |
| JESD-609代码： | e0 | 长度： | 10 mm |
| 湿度敏感等级： | 2 | 端子数量： | 64 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TFQFP |
| 封装等效代码： | TQFP64,.47SQ | 封装形状： | SQUARE |
| 封装形式： | FLATPACK, THIN PROFILE, FINE PITCH | 峰值回流温度（摄氏度）： | 235 |
| 电源： | 3.3 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.2 mm | 子类别： | Display Controllers |
| 最大压摆率： | 150 mA | 最大供电电压： | 3.6 V |
| 最小供电电压： | 3 V | 标称供电电压： | 3.3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子面层： | Tin/Lead (Sn85Pb15) |
| 端子形式： | GULL WING | 端子节距： | 0.5 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 10 mm | uPs/uCs/外围集成电路类型： | MICROPROCESSOR CIRCUIT |
| Base Number Matches： | 1 |
FPD87346BXAVS 数据手册
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PDF下载FPD87346BXA
FPD87346BXA Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing
Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs
Literature Number: SNOSAC6A
OBSOLETE
September 22, 2011
FPD87346BXA
Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-
LCD Timing Controller with Reduced Swing Differential
Signaling (RSDS™) Outputs
General Description
Features
The FPD87346BXA is a timing controller that combines an
LVDS single pixel input interface with National's Reduced
Swing Differential Signaling (RSDS™) output driver interface
for (SVGA) XGA and Wide XGA resolutions. It resides on the
TFT-LCD panel and provides the data buffering and control
signal generation for (SVGA) XGA, and Wide XGA graphic
modes. The RSDS™ path to the column driver contributes
toward lowering radiated EMI and reducing system dynamic
power consumption.
Reduced Swing Differential Signalling (RSDS™) digital
■
bus reduces dynamic power, EMI and bus width from the
timing controller
LVDS single pixel input interface system
■
■
■
Input clock range om 40 MHz to 85 MHz
Drives RSDS™ oluDrivers at 170 Mb/s with an
85 MHz clock (
Virtual 8 bolor deRC/Dithering mode
■
■
Single w 9-bit diffeential Source Driver bus
minims of Source PCB
This single RSDS™ bus conveys the 8-bit color data for (SV-
GA) XGA, and Wide XGA panels at 170 Mb/s when using
VESA 60 Hz standard timing.
Abity to drive (A) XGA and Wide XGA TFT-LCD
Sems
■
luretect function in DE mode (Bonding Option)
■
■
Ccircy operates from a 3.0V–3.6V supply
System Diagram
20101601
FIGURE 1. Block Diagram of the LCD Module
RSDS™ is a trademark of National Semiconductor Corporation
© 2011 National Semiconductor Corporation
201016
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201016 Version 2 Revision 4 Print Date/Time: 2011/09/22 09:36:00
Block Diagram
20101620
FIGURE 2. Block Diaam
Functional Description
FPD-LINK RECEIVER
DATAPATH BLOCK AND RSDS™ TRANSMITTER
The FPD87346BXA is TFT-LCD Timing Controller (TCON)
that is based on National Semiconductor’s Embedded Logic
Array family of TCON devices. The logic architecture
plemented using standard and default timing controlle
tionality based on an Embedded Gate Array. In it’s st
configuration the Gate Driver Control, Column Driver C
signals, and Logic Functions of the device are eset. Cu
tomization of control signal timing and other lofuncts of
the device are reconfigurable through customeed r-
ilog/RTL Code or User-defined specifications. The coma-
tion of Embedded Logic Array and Natiemicondor’s
world class Mixed-signal Analog funs such as
LVDS and RSDS™ provides a fleximeet the
needs of TFT-LCD Manufacturers.
(8)-bideo data (RGB) is input to the Datapath Block sup-
p to an 85 MHz pixel rate. The data is delayed to align
the Column Driver Start Pulse with the Column Driver data.
The data bus (RSR[2:0]P/N, RSG[2:0]P/N, RSB[2:0]P/N) out-
puts at a 170 MHz rate on 9 differential output channels. The
clock is output on the RSCKP/N differential pair. The RSDS
Column Drivers latch data on both positive and negative
edges of the clock. The RSDS™ output setup/hold timings
are also adjustable through the RSDS[2:0] input pins.
TIMING CONTROL FUNCTION
The Timing Controller Functional Block generates all the nec-
essary control signals to the Column Driver (TP, STH, and
REV) and Gate Drivers (STV, CPV, and OE) to interface with
a TFT-LCD panel.
SPREAD SPECTRUM SUPP
RSDS OUTPUT VOLTAGE CONTROL
The FPD-Link receiver sus controllers with
Spread Spectrum interfaceEMI. The Spread
Spectrum methods supported and down spread. A
maximum of deviation of ±2% center spread or -4% down
spread is supported at a frequency modulation of 100 kHz
maximum.
The RSDS™ output voltage swing is controlled through an
external load resistor connected to the RPI pin. The RSDS™
output signal levels can be adjusted to suit the particular ap-
plication. This is dependent on overall LCD module design
characteristics such as trace impedance, termination, etc.
The RSDS™ output voltage is inversely related to the RPI
value. Lower RPI values will increase the RSDS™ output volt-
age swing and consequently overall power consumption will
also increase.
8-6 BIT TRANSLATOR
8-bit data is reduced to a 6-bit data path via a time multiplexed
dithering technique or simple truncation of the LSBs. This
function is enabled via the input control pins.
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Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Min
Max Units
Supply Voltage (VDD
Operating Temp Range (TA)
Supply Noise Voltage (VDD
)
3.0
0
3.6
70
V
°C
Supply Voltage (VDD
)
−0.3V to +4.0V
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
+150°C
)
200 mVPP
DC TTL Input Voltage (VIN)
Spread Spectrum Support, LVDS
Spreading Range
Modulation Rate
Operating Frequency (f)
DC Output Voltage (VOUT
)
± 2.0
100
85
%
kHz
MHz
Junction Temperature
Storage Temperature Range
(TSTG
40
)
−65°C to +150°C
260°C
Lead Temperature (TL)
(Soldering 10 sec.)
ESD Rating:
(CZAP = 120 pF, RZAP = 1500Ω)
MM = 200V,
HBM = 2000V
DC Electrical Characteristics TA = 0°C to 70°C, VDD = 3.3V ± 0.3100 (Unless otherwise specified).
TTL DC ELECTRICAL CHARACTERISTICS
Symbol
VOH
Parameter
Conditions
STV, CPV, OE
Min
Typ
Max
Units
Minimum High Level Output Voltage
IOH = -6
IOH = -8 mA
I= -24 mA
= mA
IOL +8 mA
L = +24 mA
TP, REV
STH
2.4
V
VOL
Maximum Low Level Output Voltage
STV, CPV, OE
TP, REV
STH
0.4
V
VIH
VIL
IIN
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
Input Current
2.0
V
V
0.8
V
f =
–10
+10
µA
IDD
Average Supply Current
VDD = 3.6V, CL(TTL) = 15 pF,
I 0 µA (Typically PI pin
concted to 13 kΩ to ground)
RRSDS) = 100Ω and
85
150
mA
CL(RSDS) = 5 pF
(jig & test fixture capacitance),
See Figure 3 for input conditions
Note 1: “Absolute Maximum Ratins beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. trical Characteristics” specifies conditions of device operation.
3
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FPD-Link Receiver Input Pattern Used to Measure IDD
20101602
FIGURE 3. FPD-Link Receiver IDD Pern
FPD-Link (LVDS) RECEIVER INPUT (RxCLK+/-, RxIN[y]+/-; y = 0, 1, 2, 3)
Symbol Parameter Conditions
LVDS RECEIVER DC SPECIFICATIONS (Note 2)
Min
Typ
Max
Units
VTH
Differential Input High Threshold
Voltage
VCM = 1.2V
LVDS
+100
mV
mV
VTL
Differential Input Low Threshold
Voltage
LVDS
–100
IIN
Input Current
VIN = = 3.6
VIN 6V
–10
–10
+10
+10
µA
µA
V
VIN
Input Voltage Range (Single-ended)
Differential Input Voltage
0
2.4
|VID|
VCM
0.100
0+|VID|/2
0.600
2.4−|VID|/2
V
Common Mode Voltage Offset
V
Note 2: LVDS Receiver DC parameters are measurunder static aneady state conditions which may not reflect the actual performance in the end application.
Definitions Using Single-End Signals
20101603
FIGURE 4. |VID| and VCM Allowable Operating Range
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RSDS TRANSMITTER OUTPUT (RSCKP/N, RSx[y]P/N; x = R, G, B y = 0, 1, 2)
Symbol
Parameter
Conditions
RL = 100Ω
RPI = 13 kΩ
Min
Typ
Max
Units
mV
V
VOD
Differential Output Voltage
±200
(Note 3) and
(Figure 5)
RSDS
VOS
Offset Voltage
1.1
1.3
1.5
RSDS
Note 3: VOSRSDS = (V(F&B)CLKP + V(F&B)CLKN)/2 or VOSRSDS = (V(F&B)XYP + V(F&B)XYN)/2.
VODRSDS = V(F&B)CLKP − V(F&B)CLKN or VODRSDS = V(F&B)XYP − V(F&B)XYN.
The load between the positive and negative output is 100Ω.
20101604
FIGURE 5. RSDS Waveform - Single d aDifferential
20101619
FIGURE 6. Typical RSDSVOD vs. RPI Response Curve
5
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AC Electrical Characteristics TA = 0°C to 70°C, VDD = 3.3V ± 0.3V, IPI = 100 µA (Unless otherwise specified).
LVDS Data Input
Symbol
Parameter
Conditions
Figure 9
Min
Max
Units
ms
RSCLKOUTDLY
FPD-Link Receiver Phase Lock Loop Wake-up
Time
10
RSKM
RxIN Skew Margin (Note 4) and (Figure 7)
f = 85 MHz, VDD = 3.3V
220
ps
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.
This margin takes into account transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window: RSPOS).
This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type and length of cable, and source clock (FPD-Link Transmitter
TxCLK IN) jitter (less than 190 ps). The specified RSKM minimum assumes a TPPOS max of 200 ps.
RSKM = cable skew (type, length) + source clock jitter (cycle to cycle) + remaining margin for data sampling (≥0)
This parameter is guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (Process, Voltage, Temperature) range.
20101605
FIGURE 7. FPD346B(FPD-Link Receiver) Input Skew Margin
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01606
Note 5: R/G/B[7]s are MSBs and R/G/B/[0]s are LSBs
FIGURE 8. FPD87346BXA (FPD-Link ReceivInData Mapping
20101607
FIGURE 9. FPD87346BXFPD-k Receiver) Phase Lock Loop Wake-up Time
7
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Output Timing
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TO1
TTL Output Rising from RSCLK
Rising
CL(TTL) = 15 pF, RT = 100Ω, CL(RSDS)
= 5 pF, IPI = 100 µA, f = 85 MHz
0.0
11.25
ns
TO2
TTL Output Falling from RSCK Rising
RSDS Clock (RSCK) High Period
RSDS Clock (RSCK) Low Period
CL(TTL) = 15 pF, RT = 100Ω, CL(RSDS)
= 5 pF, IPI = 100 µA, f = 85 MHz
0.0
11.25
ns
ns
ns
RCHP
RCLP
RSTU
RT = 100Ω, CL(RSDS) = 5 pF,
IPI = 100 µA, f = 85 MHz
5.7
5.8
RT = 100Ω, CL(RSDS) = 5 pF,
IPI = 100 µA, f = 85 MHz
RS(R,G,B) Setup to Falling or Rising
Edge of RSCK
RT = 100Ω, CL(RSDS) = 5 pF,
IPI = 100 µA, f = 85 MHz, RSDS[2:0]
= [000]
3.2
1.8
ns
ns
RHLD
RS(R,G,B) Hold from Falling or
Rising Edge of RSCK
RT = 100Ω, CL(RSDS) = 5 pF,
IPI = 100 µA, f = 85 MHz, RSDS[2:
= [000]
SPSTU
SPHLD
STH Rising to RSCK Falling
STH Falling to RSCK Falling
RT = 100Ω, CL(RSDS) = 5 pF,
IPI = 100 µA, f = 85 MHz
5.0
4.0
ns
ns
RT = 100Ω, CL(RSDS) = 5 F,
IPI = 100 µA, f = 85 M
TABLE 1.
Typical Simulation Results of RSDS Skew Control Values* (VDD = 3.3V; RT = 100ohms; IPI = 100 µA; 25°C)
f = 65 MHz
f = 85 MHz
RSDS[2:0]
Unit
RSTU
5.03
5.26
6.03
6.53
3.01
3.49
4.00
4.50
RHLD
1.8
1.
0.8
0.33
3.33
2.8
2.36
STU
3.23
3.75
4.23
4.73
1.21
1.69
2.20
2.70
RHLD
1.83
1.31
0.83
0.33
3.77
3.33
2.86
2.36
000
001
010
011
100
101
110
111
ns
ns
*The skew control value in the table are only saf a specific condition and is not a parametric value. Typical values on this table are measured
under Static and Steady state conditions which may flective of its performance in the end application.
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20101608
20101610
20101609
FIGURE 6BXA RSDS and TTL Output Timing Diagram
9
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20101611
Note: RSCKP/N, RSR[2:0]P/N, RSG[2:0nd RSB[2:0]P/N are differential outputs, STH is a single ended TTL output.
FIGURE 11. FPD87346BXA RSDS Output Data Mapping
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FPD87346BXA Failure Detect (Internal Bonding Option)
This function is valid in DE mode. As shown in Figure 12, invalid external DE pulse will not affect the internal operation during
failure zone.
20101612
FIGURE 12. FXA Failure Detection
11
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Input Signal Timing
SVGA
XGA
WXGA I
WXGA II
Signal
Item
Symbol
f
Unit
MHz
(800 x 600) (1024 x 768) (1280 x 768) (1280 x 800)
Clock Frequency
1/Tclk
typ
min
typ
40
620
628
664
–
65
772
806
850
–
82
772
806
850
–
69
804
816
900
–
Total
Active
Total
Tv
Tvact
Th
max
min
typ
Vertical Timing
Th
600
768
768
800
max
min
typ
–
–
–
–
1050
1056
1056
–
1050
1344
1800
–
1320
1688
2000
–
1320
1408
2000
–
max
min
typ
Horizontal Timing
Tclk
Active
Thact
800
1024
10
1280
max
–
–
–
Output Timing—TTL
DE (Data Enable) Mode Only
Display Mode WIDE(0/1) (Pin 57)
Parameter
Comments
SVGA
IDE=0)
XGA
(WIDE=0)
WXGA
(WIDE=1)
Remarks/
Unit
t1
t2
STH Rising to Active Data
2
1
2
1
2
1
RxCLKP/N
RxCLKP/N
High Duration of STH
t3
STH Rising to TP
1031
8
1031
8
1285
10
RxCLKP/N
t4
High Duration of TP
RxCLKP/N
t5
STH Rising to OE
904
159
1031
684
368
1
904
159
1031
684
368
1
1147
180
1283
724
565
1
RxCLKP/N
t6
High Duration of OE
RxCLKP/N
t7
STH Rising to CPV
RxCLKP/N
t8
High Duration of CPV
STH Rising to STV
RxCLKP/N
t9
RxCLKP/N
t10
t11
t12
t13
t14
High Duration of STV
H Line (Note 6)
RxCLKP/N
STH Rising to RES)
High/Low DuratHRVS)
STH Rising to R
High/Low Duration 2HRVS)
390
1
390
1
567
1
H Line (Note 6)
RxCLKP/N
371
2
371
2
567
2
H Line (Note 6)
Note 6: H Line: Hsync Cycle
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20101613
FIGURE 1FPD86BXA TTL Output Timing Diagram
13
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20101614
FPD87346BXA TTL Output Timing Diagram (continued)
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TABLE 2.
ROn (Sn) Configuration
(TA = 25°C; XGA: RxCLKP/N = 65 MHz; WXGA: RxCLKP/N = 85 MHz)
OE
TP
RO2
(S2)
RO1
(S1)
RO0
(S0)
REV
Unit
XGA
(Front)
WXGA
(Back)
XGA
WXGA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1HRVS
2HRVS
2HRVS
1HRVS
2HRVS
2HRVS
1HRVS
2HRVS
0.12
0.12
0.25
0.12
0.12
0.25
0.25
0.25
0.12
0.12
0.50
0.12
0.12
0.50
0.50
0.50
2.4
2.1
µs
2.9
3.4
2.6
3.1
20101616
20101617
FPD87346BXA ROn (Sn) Configuration Timing Diagrams
15
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Pin Connection
20101618
GURE 16. Pinout Assignments
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Pin Description
System Interface
Symbol
RxIN[0]P/N
Pin
3, 4
Type
LVDSI
LVDSI
LVDSI
LVDSI
LVDSI
Function
FPD-Link Data Differential Pair 0 Input
RxIN[1]P/N
RxIN[2]P/N
RxIN[3]P/N
RxCLKP/N
5, 6
FPD-Link Data Differential Pair 1 Input
FPD-Link Data Differential Pair 2 Input
FPD-Link Data Differential Pair 3 Input
PFD-Link Clock Differential Pair Input
7, 8
11, 12
9, 10
10
Sub-Total
Pin Count
Column Driver Interface
Symbol
R[2:0]P/N
Pin
26–31
36–41
42–47
34, 35
50
Type
RSO
Function
Red Reduced Swing Differential Outputo Column Drivers
Green Reduced Swing Differential Outs tColumn Drivers
Blue Reduced Swing Differential OutColuDrivers
Clock Reduced Swing DifferentiOutputs umn Drivers
Line Latch Signal Output to CDrivers
G[2:0]P/N
B[2:0]P/N
CLKP/N
TP
RSO
RSO
RSO
TO, 8mA
STH
52
TO, 24mA Horizontal Start Signal Output to Cn Drivers
REV
51
TO, 8mA
Alternative Signal Outpor each 1 or 2 Horizontal Line to Column Drivers and LC
Control
Sub-Total
Pin Count
23
Row Driver Interface
Symbol
Pin
53
54
55
3
Type
Function
STV
TO, 6mA Row Drlse
CPV
OE
TO, 6mA Row Dk
TO, 6mA Control lse Width to Row Drivers
Sub-Total
Pin Count
Control Pins
Symbol
Pin
T
Function
FRC
56
Dithering Option:
-Bit Input, Dithering (FRC)
: 6-Bit Input, Non Dithering (No FRC)
RSDS[2:0]
WIDE
20–22
57
RSDS Skew/Timing Control (See Table 1)
0: SVGA (800 x 600)
0: XGA (1024 x 768)
1: WXGA (1280 x 768/800)
RO[2:0]
60–62
I
Alternate each 1 Horizontal/2 Horizontal on REV with OE Timing
(See Table 2 and Figure 15)
RES
59
23
I
I
Reserved pin, tie to high (VDD)
TEST
0: Normal Operation
1: Test Mode
Sub-Total
Pin Count
10
17
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Power Supply
Symbol
Pin
17
Type
P
Function
Digital Power for Logic Core and LVDS Deserializer
Digital Ground for Logic Core and LVDS Deserializer
Digital I/O Power and RSDS Outputs
VDD
VSS
63
G
VDDIO
18, 32, 48,
49
P
VSSIO
16, 25, 33,
64
G
Digital I/O Ground and RSDS Outputs
VDDA
VDDD
VSSD
VSSP
VSSA
1
P
P
Power for LVDS PLL and Analog Bandgap
Digital Power for LVDS Input Buffer
2
13
15
14
15
G
G
G
Digital Ground for LVDS Input Buffer
Ground for LVDS PLL and Analog Bandgap
Ground for LVDS PLL and Analog Bandgap
Sub-Total
Pin Count
Other
Symbol
Pin
24
19
58
3
Type
Function
Reference for Reduced SwinDiffeal Outputs
System Reset; Active Lo
PI
I
I
I
RSTZ
NC
No Connect
Sub-Total
Pin Count
Total
Pin Count
64
System Interf= 10
Column Driver =
Row Driver
Contro
Power
Other =
Bonding Options (B/O)
Symbol Pin
FAIL_ON B/O
Type
Function
PD
Failure Dect Function ON/OFFLow : OFF (Default) High : ON
Pin Types
I
-Input (LVompa
-TTL OL-Compatible)
-Low ntial Signal Input
-Reducferential Output
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TO
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Physical Dimensions inches (millimeters) unless otherwise noted
64-pin TPackage
Order Number F7346AVS
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19
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FPD87346BXAVS 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| FPD87346VS | NSC | Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs | 获取价格 |
|
| FPD87346VS/NOPB | NSC | FPD87346VS/NOPB | 获取价格 |
|
| FPD87352 | TI | FPD87352CXA 3.3V TFT-LCD Timing Controller with Single LVDS Input/Dual RSDS Outputs Including RTC (Response Time Compensation) for TFT-LCD Monitors and TV (XGA/WXGA/HDTV I,II,-) | 获取价格 |
|
| FPD87352CXA | NSC | +3.3V TFT-LCD Timing Controller with Single LVDS Input/Dual RSDS Outputs Including RTC for TFT-LCD Monitors and TV | 获取价格 |
|
| FPD87370 | TI | FPD87370AXA Low EMI, Low Dynamic Power VGA/XGA/WXGA TFT-LCD Timing Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs | 获取价格 |
|
| FPD87370AXA | NSC | Low EMI Low Dynamic Power VGA/XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS Outputs | 获取价格 |
|
| FPD87370AXAVS | NSC | Low EMI Low Dynamic Power VGA/XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS Outputs | 获取价格 |
|
| FPD87392 | NSC | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) | 获取价格 |
|
| FPD87392AXA | NSC | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) | 获取价格 |
|
| FPD87392BXB | NSC | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) | 获取价格 |
|
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