GC5325SEK_技术文档

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

GC5325 Wideband Digital Predistortion Transmit Processor

1

FEATURES

•

Flexible DSP Algorithm Supports Existing and

Emerging Wireless Standards

23

•

Integrated CFR and DPD Functions

•

Supports Direct Interface to TI High-Speed

Data Converters

•

Up to 20-MHz Combined Signal Bandwidth

CFR: Typically Meets 3GPP TS 25.141 <6.5 dB

PAR, <8 dB PAR for 802.16e Signals

APPLICATIONS

•

DPD: Memory Compensation, Typical ACLR

Improvement of 20 dB to 30 dB or More

•

3GPP (W-CDMA, TD-SCDMA) Base Stations

3GPP2 (CDMA2000) Base Stations

WiMAX and WiBRO (OFDMA) Base Stations

Multicarrier Power Amplifiers (MCPAs)

•

Transmit- and Feedback-Channel Equalizers

352-Ball S-PBGA Package, 27 mm × 27 mm

1.2-V Core, 3.3-V I/O

Typical Power Consumption = 1.9 W

SYSTEM BLOCK DIAGRAM

DAC5682Z

TRF3703

DAC

I/Q

Modulator

GC5325

I/Q

HPA

Baseband

Input

LPA

CFR–DPD

LO

TRF3761

CDCM7005

ADC

ADS6149

THS9001

Mixer

'C6727

DSP

B0278-02

DESCRIPTION

The GC5325 is a wideband digital predistortion transmit processor that includes a crest factor reduction (CFR)

block and a digital predistortion (DPD) block with its associated feedback chain and capture buffers. The GC5325

processes composite input bandwidths of up to 20 MHz and processes DPD sample rates of up to 140 MHz. The

GC5325 accepts a composite signal over an interleaved parallel interface at a data rate of up to 140 MSPS. The

GC5325 CFR block reduces the peak-to-average ratio (PAR) of wideband digital signals provided in quadrature

(I/Q) format, such as those used in third-generation (3G) code division multiple access (CDMA) wireless and

orthogonal frequency division multiple access (OFDMA) applications. The GC5325 DPD block reduces

adjacent-channel leakage ratio (ACLR), or out-of-band energy, by 20 dB to 30 dB or more. The efficiency of

follow-on power amplifiers (PAs) is substantially improved by reducing the PAR and ACLR of digital signals. The

digital-to-RF conversion can be further simplified by the fractional interpolator between the CFR and the DPD

blocks, and a bulk upconverter (BUC) in the final stage of the GC5325. This feature typically eliminates the need

for superheterodyne (dual-stage) upconversion architectures. Transmit and feedback NCO/mixers provide

additional flexibility in the system frequency planning.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

TMS320C64x, C55x, C64x are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGED DEVICE⁽¹⁾

T_C

352-ball S-PBGA package, 27 mm × 27 mm

–40°C to 85°C

GC5325IZND

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

GC5325 FUNCTIONAL BLOCK DIAGRAM

TCK

TRSTB

TDI

TMS

RESETB SYNC SYNC INT UPDATA UPADDR OEB RDB WRB CEB

OUT

TDO

4

3

16

10

GC5325

MPU Interface

JTAG

BBin

16

BBFR

Fractional

Farrow

Resampler

Input

Interface

Circular

Limiter

CFR

MFIO[19:18]

2

(Optional;

additional

2 LSBs)

BBCLK

BB

PLL

DPDCLK

(LVDS)

DPD

PLL

FB

Real to Complex

(or Bypass)

Feedback

Equalizer

ADC

Interface

Feedback NL

Correction

(LVDS)

18 Pairs

SYNCD

(LVDS)

TX

Transmit

Equalizer

DAC

Interface

Bulk Interpolation

+ Mixer

DPD

(Diff.)

19 Pairs

Capture Buffers

BB Clock Domain

DPD Clock Domain

B0279-02

2

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

DETAILED DESCRIPTION

GC5325 Introduction

The GC5325 is a flexible transmit sector processor that includes a crest factor reduction (CFR) block and a

digital predistortion (DPD) block and its associated feedback chain. The GC5325 processes composite input

bandwidths of up to 40 MHz and processes DPD expansion bandwidths of up to 140 MHz (actual performance

may vary for signal bandwidths exceeding 23 MHz). By reducing both the peak-to-average ratio (PAR) of the

input signals using the CFR block and linearizing the power amplifier (PA) using the DPD block, the GC5325

reduces the costs of multicarrier PAs (MCPA) for wireless infrastructure applications. The GC5325 applies CFR

and DPD while a separate microprocessor (a Texas Instruments TMS320C6727 DSP) is used to optimize

performance levels and maintain target PA performance levels.

By including the GC5325 in their system architecture, manufacturers of BTS equipment can realize significant

savings on power amplifier bill of materials (BOM) and overall operational costs due to the PA efficiency

improvement. The GC5325 meets multicarrier 3G performance standards (PCDE, composite EVM, and ACLR) at

PAR levels down to 6.5 dB and improves the ACLR, at the PA output, by 20 dB to 30 dB or more. The GC5325

integrates easily into the transmit signal chain between baseband processors such as the Texas Instruments

TMS320C64x™ DSP family and their high-performance data converters.

A typical GC5325 system application would include the following transmit-chain components:

•

TMS320C6727 digital signal processor (DSP)

DAC5682 16-bit, 1-GSPS DAC (transmit path)

CDCM7005 clock generator

TRF3761 integrated VCO/PLL synthesizer

TRF3703 quadrature modulator

ADS5517 11-bit 200-MSPS or ADS6149 14-bit, 250-MSPS ADC (feedback path)

AMC7823 analog monitoring and control circuit with GPIO and SPI

Baseband Interface

The GC5325 BB interface block accepts baseband signals over an interleaved parallel interface at a data rate of

up to 140 MHz. The input interface supports up to 12 separate baseband carriers. The GC5325 input interface

can be programmed in a wideband mode in which users are required to channelize the data using an external

processor.

Gain/Pilot Insertion/AntCal Insertion/Power Meter

Baseband gain can be applied on a per-carrier basis to accurately control the individual channel power through

the system. Also present is the functionality for adding pilot codes to the data stream for antenna calibration

applications. Independent programmable RMS power meters for up to 12 channels are also included in this block

of the device.

Crest Factor Reduction (CFR)

The GC5325 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals provided

in quadrature (I and Q) format, such as those used in third-generation (3G) code division multiple access

(CDMA) wireless applications. The CFR block can reduce the PAR of W-CDMA Test Model 1 and Test Model 3

signals down to 6.5 dB output PAR while still meeting all 3GPP requirements for ACLR, composite EVM, and

peak code domain error (PCDE). The CFR block accepts input sampling rates up to 140 MSPS complex from the

input interface.

Submit Documentation Feedback

3

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

Fractional Farrow Resampler (FR)

The CFR block output signal bandwidth is up to 40 MHz wide, sampled at up to 70 MSPS. However; the DPD

block provides PA compensation over an expansion bandwidth of up to 140 MHz, using a complex sampling rate

of up to 140 MSPS. To provide the requisite sampling rate of up to 140 MSPS at the input to DPD, the output of

the CFR block must be resampled. The GC5325 performs this (nominally 2×) upsampling function using a

Farrow filter resampler. The user-programmable Farrow resampler supports upsampling rates from 1× to 64×,

with 16-bit precision on the interpolation ratio. It marks the transition of the input clock domain (driven by the

input interface clock) to the transmit domain (driven by the DAC sampling clock).

Digital Predistortion (DPD)

The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and

lengths of PA memory effects. The predistortion correction terms are computed by an external processor (for

example, TI TMS320C6727 DSP) based on PA feedback data captured in the GC5325. The external processor

reads the captured data buffers from the GC5325 and writes back the newly computed DPD correction terms on

a continuous basis. TI provides a base delivery of 'C6727 software to GC5325 customers that achieves a typical

ACLR improvement of 20 dB to 30 dB or more when compared to a PA without DPD. The standard EMIF bus

allows the user to provide an alternate DPD adaptation algorithm and DSP embodiment, if desired.

Bulk Upconverter (BUC)

The bulk upconverter block can interpolate the DPD block output by 1.5×, 2×, 3× with a complex output, or 6×

with a real output. The complex-to-real converter block optionally modifies the DPD complex output stream into a

real output stream. The bulk upconverter has flexible mixing options between its various interpolation stages.

When used in combination, the bulk upconverter and the complex-to-real functions allow the GC5325 to output a

16-bit real signal at up to 840 MSPS, or a complex signal at up to 420 MSPS. Next-generation data converters

can accept sampling rates as high as 1 GSPS and sample widths of 16 bits. In a typical application, the bulk

upconverter outputs a 737.28-MSPS real sampling rate (16 bits/sample) directly to the DAC on a modified center

frequency of 184.32 MHz (1/4 of the 737.28-MSPS sampling rate). The bulk upconverter has multiple

high-speed, low-voltage, single-ended/differential output interfaces to existing and future TI DACs.

Feedback Path (FB)

The feedback block accepts an external A/D converter input that represents the PA output signal. This feedback

signal is processed by a feedback path that adjusts for gain, frequency, and phase anomalies in the RF-to-IF

downconversion chain. The feedback path includes an 8-tap complex receive equalizer and lookup tables that

can compensate for the nonlinearities in the RF-to-IF part of the feedback chain. The block also includes a

real-to-complex conversion to facilitate signal processing. The GC5325 connects directly to the ADS5444,

ADS5545, ADS5546, and ADS5517 among others, without requiring external components. The GC5325

simplifies timing by providing a FIFO for each ADC port, sampling the input data using the ADC data-ready

signal.

Microprocessor Interface (MPU)

The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in

asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB,

and CEB control signals. The interface fully supports TI C55x™, C64x™ DSPs and, with minimal effort, supports

the low-cost 'C6727 floating-point DSP.

Smart Capture Buffers (SCB)

The GC5325 has two capture buffers, each 4096 complex words deep, which are periodically read by the

external coefficient update controller (DSP) in order to optimize the DPD coefficients. The first capture buffer can

be used to capture:

•

The output of the Farrow resampler; this is also called the reference signal.

The feedback output; this represents the waveform as seen by the PA.

The error output

Testbus(31:16)

The second capture buffer can be used to provide:

4

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

•

The output of the Farrow resampler; this is also called the reference signal.

The feedback output; this represents the waveform as seen by the PA.

The error output

Testbus(15:0)

The reference and feedback buffers are time-aligned by the GC5325, because there may be a delay of tens or

even hundreds of samples between the transmitted signal and the feedback signal from the PA output. The

capture controller can trigger a capture on several different metrics, including an above-threshold peak count or

an average signal power value.

Input and Output Syncs

The GC5325 features multiple-user programmable input syncs. These are typically used as trigger mechanisms

to activate features within the device. These triggers can be provided internally or through externally provided

inputs. The input syncs can be used to trigger:

•

Power measurements

Initializing/loading the feedback, equalizer, LUTs, etc.

Flush out data within the processing blocks of the device

Feedback path tuner alignment

Capturing and sourcing of data through SCBs

Programmable Power Meters

There are three power meter locations/functions within the GC5325. The first is a channel RMS power meter.

The second power meter is located at the output of the CFR block, and the final power detector is similar to the

CFR output power detector and is located at the Farrow resampler output. This power meter can measure RMS

power integrated up to a million samples at the DPD sample rate.

Submit Documentation Feedback

5

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

Pin Assignment and Descriptions

GND Package

(Bottom View)

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VDD

SHV

A

B

C

D

E

F

VSS1 VSS1 VSS1 VSS1 FB1 FB5 FB9 FB11 FB15 FB17 FB21 FB25 FB27

FB31 FB35 VSSA2 SYNCC BB15 BB11 BB7 BB3 BB0 VSS1 VSS1 VSS1

FB30 FB34 VDDA2 SYNCB BBFR BB12 BB8 BB4 BB1 VSS1 VSS1 VDD1

VDD

SHV

VDD1 VSS1 VSS1 VSS1 FB0 FB4 FB8 FB10 FB14 FB16 FB20 FB24 FB26

ADC

IREF

VDD

SHV

VSS1 VDD1 VSS1 VSS1 NC FB3 FB7 VDD1 FB13

VSS1 VSS1 VDD1 VSS1 NC FB2 FB6 VDD1 FB12

VSS1 VSS1 VSS1 VDD1

FB19 FB23 VDD1

FB29 FB33 VDD1 SYNCA BBCLK BB13 BB9 BB5 BB2 VSS1 VDD1 VSS1

ADC

VREF

VDD

SHV

SYNC

OUT

FB18 FB22 VDD1

FB28 FB32 VSS1

VDD1 BB14 BB10 BB6 VSS1 VDD1 VSS1 VSS1

VDD1 VSS1 VSS1 VSS1

VSS1 VSS1 VSS1 VDD1

VDD1 VDD1 VSS1 VSS1

VDD

VSS1 VSS1 VSS1

SHV

VDD

G

H

J

VSS1 VSS1 VSS1

SHV

UP

NC

NC VPP1 VDD1

VDD1

ADDR2 ADDR1 ADDR0

UP

VPP1 NC

NC VDD1

ADDR5 ADDR4 ADDR3

VDD

VDD1

SHV

UP

K

L

NC

ADDR8 ADDR7 ADDR6

VDD

SHV

UP

WRB

ADDR9

NC VDD1

M

N

P

R

T

VDD1 OEB CEB RDB

UP UP

UP

VDD

VDD1

SHV

VDD1

DATA2 DATA1 DATA0

VDD

NC MFIO18 VDD1

VSS1 VSS1

SHV

UP

MFIO19 NC

NC VDD1

DATA5 DATA4 DATA3

VDD

SHV

UP

NC

VPP2

DATA6

VDD

VDD1

SHV

UP

U

V

W

Y

VPP2

DATA8 DATA7

UP

NC VDD1

DATA11DATA10 DATA9

UP UP

UP

DATA14DATA13 DATA12

VDD

SHV

UP

VSS1 VSS1

DATA15

NC VSS1 VSS1 VDD1

AA VSS1 VSS1 VSS1 VDD1

AB VSS1 VSS1 VSS1 VDD1

VDD1 VSS1 VSS1 VSS1

VDD1 VDD1 VSS1 VSS1

RESET VDD DPD

SHV CLK

DAC

REFP

AC VSS1 VSS1 VDD1

VSS1 VDD1 TX2 TX6 TX10 TX14 VDDS VSS1

TX25 TX29 TX33 TX37 VSS1 VDD1 VDD2 VSS1 VDD1 VSS1 VSS1

B

DPD DPD

IREF CLKC

DAC

REFN

VDD

SHV

AD VSS1 VDD1 VSS1 VSS1

AE VDD1 VSS1 VSS1 VSS1

VSS1 VDDA1 TX3 TX7 TX11 TX15 VDDS VSS1

TX24 TX28 TX32 TX36

VDD1 VSS2 VSS1 VSS1 VDD1 VSS1

DPD

SYNCD

VREF

VDD

SHV

INTER-

TX0 TX4 TX8 TX12 TX16 VDDS TX19 TX21 TX23 TX27 TX31 TX35 TRSTB TDI

VSS1 VSS1 VSS1 VDD1

RUPT

SYNC

TEST

AF VSS1 VSS1 VSS1 VSS1 VSS1

VSSA1 TX1 TX5 TX9 TX13 TX17 VSS1 TX18 TX20 TX22 TX26 TX30 TX34 TMS TCK TDO

VSS1 VSS1 VSS1

DC

MODE

= Baseband Input

= Transmit Ouput

= Miscellaneous

= JTAG Interface

= Feedback Input

= Multi-Function Input/Output

= NC

= Microprocessor Interface

= Power and Biasing

P0077-01

6

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

Table 1. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

MICROPROCESSOR INTERFACE

OEB

M3

M2

M1

L2

I

Output enable

Chip enable

Read

CEB

RDB

WRB

Write

UPADDR[9:0]

L1, K3, K2, K1, J3, J2, J1, H3, H2, H1

Microprocessor address

Y1, W3, W2, W1, V3, V2, V1, U3, U2, T1, R3, R2, R1,

N3, N2, N1

UPDATA[15:0]

INTERRUPT

I/O

O

Microprocessor data

AE5

Microprocessor interrupt

POWER AND BIASING

B1, B26, C2, C10, C14, C19, C25, D3, D8, D14, D19,

D24, E4, E23, F3, F4, F23, H4, H23, J4, J23, K4, K23,

L4, L23, M4, M23, N4, N23, P4, P23, R4, R23, T4,

T23, U4, U23, V4, V23, W4, W23, Y23, AA4, AA23,

AB3, AB4, AB23, AC3, AC6, AC19, AC24, AD2, AD6,

AD25, AE1, AE26

VDD1

PWR 1.2-V supply

A1, A2, A3, A23, A24, A25, A26, B2, B3, B23, B24,

B25, C1, C3, C23, C24, C26, D1, D2, D4, D10, D23,

D25, D26, E1, E2, E3, E24, E25, E26, F1, F2, F24,

F25, F26, G1, G2, G3, G24, G25, G26, P1, P2, Y2,

Y3, Y24, Y25, AA1, AA2, AA3, AA24, AA25, AA26,

AB1, AB2, AB24, AB25, AB26, AC1, AC2, AC4, AC7,

AC13, AC20, AC25, AC26, AD1, AD3, AD4, AD13,

AD20, AD23, AD24, AD26, AE2, AE3, AE4, AE23,

AE24, AE25, AF1, AF2, AF3, AF14, AF22, AF23,

AF24, AF25, AF26

VSS1

PWR Ground

VDD2

VSS2

VDDS

AC5

NC

Do not connect

AD5

AC14, AD14, AE14

PWR 1.8-V supply

A13, B13, C13, D13, G4, G23, K24, L3, N24, P3, T3,

U24, Y4, AC22, AD7, AE20

VDDSHV

PWR 3.3-V supply

VDDA1

AD19

AF20

B10

PWR 1.2-V supply (requires filtering)

PWR Ground (requires filtering)

PWR 1.2-V supply (requires filtering)

PWR Ground (requires filtering)

PWR 1.2-V supply

VSSA1

VDDA2

VSSA2

A10

VPP1

H24, J26

T2, U1

AD22

AE22

AC12

AD12

C17

VPP2

PWR 1.2-V supply

DPDIREF

DPDVREF

DACREFP

DACREFN

ADCIREF

ADCVREF

PWR DPD bias 1 kΩ to VSS

PWR DPD bias to VDD

PWR DAC bias 50-Ω to VSS

PWR DAC bias 50-Ω to VDDS

PWR ADC bias 1 kΩ to VSS

PWR ADC bias to VDD

D17

BASEBAND INPUT

A8, D7, C7, B7, A7, D6, C6, B6, A6, D5, C5, B5, A5,

C4, B4, A4

BB[15:0]

I

Baseband input signal

BBCLK

C8

I

Baseband input clock

BBFR

B8

Baseband frame for sample and channel timing

LSBs for 18-bit baseband input signal [-2, -1]

MFIO[19:18]

R26, P24

MISCELLANEOUS

RESETB

AC23

I

Chip reset (active-low .Required.)

Submit Documentation Feedback

7

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

Table 1. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

SYNCA

NO.

C9

I

Programmable general-purpose sync

Complementary of SYNCD

SYNCB

B9

SYNCC

A9

I

SYNCD

AE21

AF21

D9

I

SYNCDC

SYNCOUT

DPDCLK

DPDCLKC

TESTMODE

I

O

I

Programmable general-purpose sync output

Clock to DPD

AC21

AD21

AF4

I

Complementary clock to DPD

Tie to ground

I

JTAG INTERFACE

TCK

AF6

I

JTAG clock

TDI

AE6

AF5

AE7

AF7

JTAG data in

TDO

TRSTB

TMS

O

I

JTAG data out

JTAG reset (active-low); pull down if JTAG is not used.

JTAG mode select

I

SIGNALS (See mode selection guide for pin assignment)

AC8, AD8, AE8, AF8, AC9, AD9, AE9, AF9, AC10,

AD10, AE10, AF10, AC11, AD11, AE11, AF11, AE12,

TX[37:0]

AF12, AE13, AF13, AF15, AE15, AD15, AC15, AF16,

AE16, AD16, AC16, AF17, AE17, AD17, AC17, AF18,

AE18, AD18, AC18, AF19, AE19

O

Transmit to DAC(s)

A11, B11, C11, D11, A12, B12, C12, D12, A14, B14,

A15, B15, C15, D15, A16, B16, C16, D16, A17, B17,

A18, B18, C18, D18, A19, B19, A20, B20, C20, D20,

A21, B21, C21, D21, A22, B22

FB[35:0]

NC

I

Feedback from ADC(s)

No connect

Y26, W24, W25, W26, V24, V25, V26, U25, U26, T24,

T25, T26, R24, R25, P25, P26, N25, N26, M24, M25,

M26, L24, L25, L26, K25, K26, J24, J25, H25, H26,

D22, C22

–

10 W

VDD1

VDDA1 or VDDA2

0.01 mF

1 mF

10 W

VSS1

VSSA1 or VSSA2

S0315-01

Figure 1. GC5325 PLL Power Supply Filter

The two PLLs require an analog supply. These can be generated by filtering the core digital supply (Vdd). A

representative filter is shown in Figure 1. The two PLLs should have separate filters and be located as close as

reasonable to their respective pins (especially the bypass capacitors). The ferrite beads should be series 50R

(similar to Murata P/N: BLM31P500SPT Description: IND FB BLM31P500SPT 50R 1206). In particular, supply

VDDA1 must be less than or equal to VDD1 when VDD1 is at the low end of the required range. The series

resistor assures this condition is met.

8

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

Table 2. GC5325 TX Interface Options

PIN FUNCTION

PIN NAME

I/O

DESCRIPTION

TX (Single-Channel HSTL)

TX10, TX6, TX2, TX0, TX4, TX8, TX12, TX16, TX23, TX27,

TX31, TX35, TX32, TX36, TX29, TX25

DAC[15:0]P

DAC[15:0]N

O

DAC positive output

DAC negative output

TX11, TX7, TX3, TX1, TX5, TX9, TX13, TX17, TX22, TX26,

TX30, TX34, TX33, TX37, TX28, TX24

DACCLK

TX21

TX20

TX14

TX15

O

Clock to DAC

DACCLKC

DACSYNCP

DACSYNCN

Complementary clock to DAC

Positive output data sync

Negative output data sync

Table 3. GC5325 FB Interface Options

PIN FUNCTION

PIN NAME

I/O

DESCRIPTION

Feedback (Single-Channel SDR LVDS or DDR LVDS)

FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16, FB20,

FB22, FB24, FB26, FB28, FB30, FB32, FB34

ADC[15:0]P

ADC[15:0]N

I

ADC positive feedback from PA output

ADC negative feedback from PA output

FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17, FB21,

FB23, FB25, FB27, FB29, FB31, FB33, FB35

ADCCLK

ADCLKC

FB0

FB1

I

Clock from ADC

Complementary clock from ADC

Feedback (Single- or Dual-Channel DDR LVDS)

ADCA[7:0]P

ADCA[7:0]N

ADCACLK

FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16

I

ADC-A positive feedback from PA output

ADC-A negative feedback from PA output

Clock from ADC-A

FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17

FB0

ADCACLKC

ADCB[7:0]P

ADCB[7:0]N

ADCBCLK

FB1

Complementary clock from ADC-A

ADC-B positive feedback from PA output

ADC-B negative feedback from PA output

Clock from ADC-B

FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34

FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35

FB18

FB19

ADCBCLKC

Complementary clock from ADC-B

MPU Interface Guidelines

The following section describes the hardware interface between the recommended microprocessor, external

memory, and the GC5325. Users may select a microprocessor that meets their specific system requirements.

Although the hardware can support multiple options, the recommended TMS320C6727 DSP is also fully

supported with host control and adaptation software. Figure 2 illustrates the hardware interface between the DSP

to GC5325 and SDRAM. The external memory is required to accommodate the computational efforts of the

adaptation algorithm. Although the system evaluation kit suggests dual parallel 64-Mb/PC133 (128-Mb) memory

modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are available. The processing

speed or convergence time of the adaptation algorithm is not strictly limited by the external memory speed rating.

The use of an external inverter, with minimal propagation delay, is required for OEB of the GC5325; this device is

necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in

the Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP External

Memory Interface (EMIF) user's guide (SPRU711).

Submit Documentation Feedback

9

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

EM_D[31:0]

EM_A[12:0]

EM_BA[1:0]

EM_CS[2]B

EM_RWB

EM_WEB

UPDATA[15:0]

UPADDR[9:1]

UPADDR[0]

CEB

GC5325

OEB

WRB

C6727 DSP

Asynchronous

Mode

EM_OEB

RDB

AXRO[7]

INTERRUPT

EM_CS[0]B

EM_WE_DQM[3:0]B

EM_CLK

DQ[31:16] / DQ[15:0]¹

A[11:0]

EM_CKE

CSB

EM_RASB

DQM[3:0]

EM_CASB

SDRAM

1M ´ 16 ´ 4

(64Mb) ´ 2

BA[1:0]

CLK

CKE

RASB

CASB

WEB

B0280-02

NOTE: Dual SDRAM modules are used, upper and lower EMIF data lines are split to access each respective memory

module.

Figure 2. DSP to GC5325/SDRAM Interface Specifications

In a typical implementation, the system configuration software resides locally (in nonvolatile memory) to ensure

proper operation at power up. The adaptation algorithm should also reside in the same location; at power up, the

host should transfer/load the software from the nonvolatile memory (FLASH) to the 'C6727 DSP. The size of the

software required to support the GC5325 and 'C6727 should be no more than 128 Mb (16 MB); however, this

allocation is subject to change pending algorithm improvements. The suggested host-to-DSP interface is through

the UHPI port. See Chapter 0.

The port can be configured into multiple modes of data transfer; the Multiplexed Host Address/Data Dual

Halfword Mode is suggested for this application.

Additional specifications and documents for the TMS320C6727 DSP are available from Texas Instruments at:

http://focus.ti.com/docs/prod/folders/print/tms320c6727b.html.

Typical Baseband Interface

The GC5325 baseband interface receives time-interleaved I and Q data for each channel over the 16- or 18-bit

input bus. The BB[15..0] bus is the 16-bit interface or the top 16 bits of the 18-bit interface. The frame strobe

BBFS signal is used to identify the first channel I data. The data is input in channel order, I then Q. The

baseband clock is used to register the interleaved IQ data and frame strobe.

The hardware sync signals SyncA, SyncB, and SyncC are used to time-align internal GC5325 operations. A

0-to-1 transition clocked by BBClock is an active sync signal.

10

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

Customer

Baseband-Data

Processor

GC5325

FRAME STROBE

BBFR

BASEBAND

DATA[15..0]

BB[15..0]

BASEBAND

DATA[–1..–2]

MFIO[19..18]

SYNC-HW1

SYNC-HW2

SYNC-HW3

SYNC A

SYNC B

SYNC C

BASEBAND

CLOCK

BB CLK

B0292-02

Figure 3. Typical Baseband Interface

GENERAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

VALUE

UNIT

V

V_DD, V_DDA

V_DDS

Core supply voltage

–0.3 to 1.32

–0.3 to 2

Digital supply voltage for TX

Digital supply voltage

V

V_DDSHV

V_IN

–0.3 to 3.6

–0.5 to V_DDSHV+ 0.5

–20 to 20

V

Input voltage (under/overshoot)

Clamp current for an input/output

Storage temperature

V

mA

°C

T_stg

–65 to 150

300

Lead soldering temperature, 10 seconds

ESD Classification Class 2 (Required 2-kV HBM, 500-V CDM) (Passed 2.5-kV

HBM, 500-V CDM, 200-V MM)

Moisture sensitivity Class 3 (1 week floor life at 30°C/60% H)

Reflow conditions JEDEC standard

260

＝C

Submit Documentation Feedback

11

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

V_DD, V_DDA2, V_PPCore supply voltages.

1.14

1.2

1.26

V

Note V_DDA2≤ V_DD

(1)

V_DDA1

V_DDS

Analog supply for DPD PLL

Digital supply voltage for TX

Digital supply voltage

See

1

1.71

3.15

1.1

1.8

3.3

VDD

1.89

3.45

V

V_DDSHV

I_DD, I_DDA1, I_DDA2

I_PP

,

Combined supply current for Vdd, Vdda1,

Vdda2, and V_PP

3

A

I_DDS

I_DDSHV

T_C

Digital supply current for TX

Digital supply current

Case temperature

0.25

0.3

85

A

(2)

(3)

See

-40

30

°C

T_J

Junction temperature

105

(1) VDDA1 must be less than VDD1 when VDD1 is low. See recommended filtering circuit in Figure 1. Maximum observed current on

VDDA1 is 8 mA.

(2) Chip specifications in are production tested to 90°C case temperature. QA tests are performed at 85°C.

(3) Thermal management may be required for full-rate operation. Sustained operation at elevated temperatures reduces long-term reliability.

Lifetime calculations based on maximum junction temperature of 105°C.

THERMAL CHARACTERISTICS

PARAMETER

Thermal resistance, junction-to-ambient (still air)

Theta junction to ambient (1 m/s)

352 BGA at 4 W

UNITS

°C/W

R_θJA

15

R_θJMA1

R_θJC

11.8

0.92

5.3

Thermal resistance, junction-to-case

Thermal resistance, junction-to-board

R_θJB

12

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

GENERAL ELECTRICAL CHARACTERISTICS

Describes the electrical characteristics for the baseband interface, multifunction I/O (MFIO), DPD clock and fast sync, MPU

and JTAG interfaces over recommended operating conditions. Device is production tested at 90＝C for the given specification

and characterized at –40＝C (unless otherwise noted).

PARAMETER

CMOS INTERFACE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IL

CMOS voltage input, low

CMOS voltage input, high

CMOS voltage output, low

CMOS voltage output, high

Pullup current

0.8

V_DDSHV

0.5

V

V_IH

V_OL

V_OH

2

I_OL= 2 mA

I_OH= –2 mA

V_IN= 0 V

V

2.4

40

V_DDSHV

200

V

|I_PU

|

100

µA

|I_IN

|

Leakage current

V_IN= 0 or V_IN= V_DDSHV

5

DAC INTERFACE (DAC P/N[15:0])

Output differential swing,

V_O(diff)

(1)

250

mV

| V_O(diff)| = | V_OH– V_OL

|

Common mode voltage,

(V_OH+ V_OL)/2

V_(COMM)

1000

LVDS INTERFACE (FB[35:0], DPDCLK/C, SYNCD/C)

V_i

Input voltage range

0

250

90

2000

mV

Ω

0 < V_i< 2000 mV

Input differential voltage,

|Vpos – Vneg|

V_i(diff)

1000 mV < V_i< 1400 mV, FB[35:0] only

R_IN

Input differential impedance

80

120

2.2

POWER SUPPLY

Idyn Core current

(2)

See

A

(1) HSTL output levels are measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360. Contact TI for

operations above 675 Mb/s.

(2) Operating at 280 MHz core, 840 TX port, maximum filtering, nominal supplies

Submit Documentation Feedback

13

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

GENERAL SWITCHING CHARACTERISTICS

Describes the electrical characteristics for the baseband interface, MFIO, Fast Sync, and MPU interfaces over recommended

operating conditions (unless otherwise noted)

PARAMETER

BASEBAND INTERFACE

TEST CONDITIONS

MIN

MAX

UNIT

f_CLK(BB)

Baseband input clock frequency

25

140

MHz

ns

BB[15:0], BBFR, SYNCA, SYNCB,

and SYNCC; MFIO18/19

t_su(BB)

Input data setup time before BBCLK↑

1.3

BB[15:0], BBFR, SYNCA, SYNCB,

and SYNCC; MFIO18/19

t_h(BB)

Input data hold time after BBCLK↑

1.5

2

ns

Valid for SYNCA, SYNCB, and

SYNCC

t_{h(SYNCA, -B, -C)}

Duty_CLK(BB)

t_jCLK(BB)

Duty cycle

30%

70%

Baseband input clock cycle-to-cycle jitter⁽¹⁾

–2.5%

2.5%

(1) Percent of baseband PLL clock period. The baseband PLL clock is typically 2×–4× the baseband clock frequency.

1/f_CLK(BB)

BBCLK

I(ch = 1, t = 1)

Q(ch = 1, t = 1)

Q(ch = N, t = 1)

I(ch = 1, t = 2)

BB[15:0]

t_su(BB)

t_h(BB)

BBFR

T0284-01

Figure 4. Baseband Timing Specifications (ex. Four Interleaved I/Q Channels)

14

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

Table 12. DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

100

30%

0.2

MAX

280

UNIT

f_CLK(DPD)

DPD input clock frequency

DPD input clock duty cycle

Input hold time after DPDCLK↑

Input setup time after DPDCLK↑

Input hold time after DPDCLK↑

Input setup time after DPDCLK↑

DPD clock cycle-to-cycle jitter

MHz

Duty_CLK(DPD)

t_h(SYNCD)

70%

See⁽¹⁾

ns

t_su(SYNCD)

0.4

t_{h(SYNCA, -B, -C)}

t_{su(SYNCA, -B, -C)}

t_jCLK(DPD)

2

0.4

–2.5%

2.5%

(1) SYNCD is the preferred sync for DPD clock and clock domain.

DPDCLK

DPDCLKC

SYNCDC

SYNCD

t_su(SYNCD)

t_h(SYNCD)

SYNCA

SYNCB

SYNCC

t_{su(SYNCA, -B, -C)}

t_{h(SYNCA, -B, -C)}

T0286-01

Figure 5. DPD Clock and Fast Sync Timing Specifications

Submit Documentation Feedback

15

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

MPU SWITCHING CHARACTERISTICS (READ)

PARAMETER

TEST CONDITIONS

WRB is HIGH.

MIN

5

MAX

UNIT

ns

t_su(AD)

t_su(CEB)

t_su(OEB)

t_d(RD)

ADDR setup time to RDB↓

CEB setup time to RDB↓

WRB is HIGH.

7

ns

OEB setup time to RDB↓

2

ns

DATA valid time after RDB↓

14

ns

t_h(RD)

ADDR hold time to RDB↑

2

0

2

7

ns

OEB, CEB hold time to RDB↑

OEB hold time to RDB↑

t_HIGH(RD)

t_Z(RD)

Time RDB must remain HIGH between READs.

DATA goes high-impedance after OEB↑ or RDB↑.

WRB is HIGH⁽¹⁾

.

ns

7

(1) Controlled by design and process and not directly tested

RDB

t_HIGH(RD)

WRB

t_h(OEB)

t_su(OEB)

OEB

t_su(CEB)

CEB

t_su(AD)

ADDR

3-State

DATA

t_d(RD)

t_Z(RD)

t_h(RD)

T0287-01

Figure 6. MPU READ Timing Specifications

16

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

MPU SWITCHING CHARACTERISTICS (WRITE)

PARAMETER

TEST CONDITIONS

MIN

5

MAX

UNIT

DATA and ADDR setup time to WRB↓

CEB setup time to WRB↓

t_su(WR)

OEB and RDB are HIGH.

7

ns

OEB setup time to WRB↓

2

DATA and ADDR hold time after WRB↑

OEB and CEB hold time after WRB↑

Time WRB and CEB must remain simultaneously LOW

Time CEB or WRB must remain HIGH between WRITEs.

2

t_h(WR)

OEB and RDB are HIGH.

ns

0

t_low(WR)

t_high(WR)

OEB and RDB are HIGH.

15

10

ns

RDB

t_low(WR)

t_high(WR)

WRB

OEB

t_h(WR)

t_su(WR)

CEB

ADDR

DATA

T0288-01

Figure 7. MPU WRITE Timing Specifications

Submit Documentation Feedback

17

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

JTAG SWITCHING CHARACTERISTICS

PARAMETER

JTAG clock frequency

TEST CONDITIONS

MIN

MAX

UNIT

MHz

ns

f_TCK

50

t_p(TCKL)

t_p(TCKH)

t_su(TDI)

t_h(TDI)

JTAG clock low period

10

1

JTAG clock high period

ns

Input data setup time before TCK↑

Input data hold time after TCK↑

Output data delay from TCK↓

Valid for TDI and TMS

ns

Valid for TDI and TMS

6

ns

t_d(TDO)

8

ns

1/f_TCK

TCK

t_p(TCKH)

t_p(TCKL)

TDI

t_su(TDI)

t_h(TDI)

TDO

t_d(TDO)

T0289-01

Figure 8. JTAG Timing Specifications

ELECTRICAL CHARACTERISTICS

TX SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HSTL MODE – DDR ex. DAC5682

(1)

f_CLK(DAC)

DAC output clock frequency

R_L= 100 Ω

420

MHz

(1) Because the output clock is DDR, this represents 840 MSPS real or 420 MSPS complex.

1/f_CLK(DAC)

DACCLKC

DACCLK

DAC[15:0]P

Q

I

DAC[15:0]N

T0290-02

Figure 9. TX Timing Specifications (HSTL – DDR)

18

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

LVDS SWITCHING CHARACTERISTICS

Over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM.

N means the number of differential pairs used to transmit data from one ADC and M means the number of bits sent serially

down each LVDS pair. Thus, 8x2 means 8 LVDS pairs each containing 2 bits of information sent serially.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16x1 SDR LVDS MODE ex. ADS5444

(1)

f_CLK(ADC)

t_su(ADC[#]P)

t_h(ADC[#]P)

ADC interface clock frequency

See

280

MHz

ps

(1) (2)

Input data setup time before CLK↑

Input data hold time after CLK↑

300

600

ps

16x1 DDR LVDS MODE ex. ADS5463

(1)

f_CLK(ADC)

t_su(ADC[#]P)

t_h(ADC[#]P)

ADC interface clock frequency

See

140

MHz

ps

(1) (2)

Input data setup time before CLK↑↓

Input data hold time after CLK↑↓

100

1200

ps

8x2 DDR LVDS MODE ex. ADS5545

(1)

f_CLK(ADCA)

ADCA interface clock frequency

See

280

MHz

ps

t_{su(ADCA[#/2]P)}

t_{h(ADCA[#/2]P)}

f_CLK(ADCB)

Input data setup time before CLK↑↓

Input data hold time after CLK↑↓

ADCB interface clock frequency

Input data setup time before CLK↑↓

Input data hold time after CLK↑↓

See ^{(1) (3)}. For port A

430

260

ps

(1)

See

MHz

ps

t_{su(ADCB[#/2]P)}

t_{h(ADCB[#/2]P)}

See ^{(1) (4)}. For port B

800

400

ps

(1) Specifications are limited by GC5325 performance and may exceed the example ADC capabilities for the given interface.

(2) Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (V_OD> 250 mV) to/from ADCCLK and ADCCLKC clock crossing (V_OD

=

0).

(3) Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (V_OD> 250 mV) to/from ADCACLK and ADCACLKC clock crossing

(V_OD= 0).

(4) Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (V_OD> 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing

(V_OD= 0).

1/f_CLK(ADC)

CLK

CLKC

ADC[15:0]P

ADC[15:0]N

t_su(ADC[#]P)

t_h(ADC[#]P)

T0286-02

Figure 10. LVDS Timing Specifications (16 × 1 SDR LVDS)

1/f_CLK(ADC)

CLK

CLKC

t_su(ADC[#]P)

ADC[15:0]P

ADC[15:0]N

t_h(ADC[#]P)

T0292-01

Figure 11. LVDS Timing Specifications (16 × 1 DDR LVDS)

Submit Documentation Feedback

19

Product Folder Link(s): GC5325

GC5325

SLWS215–JANUARY 2009.............................................................................................................................................................................................. www.ti.com

1/f_CLK(ADCx)

CLK

CLKC

ADC[# bits/2]P

Even Bits

Odd Bits

ADC[# bits/2]N

t_{su(ADCx[#/2]P)}

t_{h(ADCx[#/2]P)}

t = N

t = N + 1

T0293-01

Figure 12. LVDS Timing Specifications (8 × 2 DDR LVDS)

APPENDIX A

See the TMS320C672x DSP Universal Host Port Interface (UHPI) reference guide (SPRU719).

ADDR/DATA BUS (16-Bit)

DATA READY

UHPI_HD[15:0]

UHPI_HRDYB

HALFWORD STROBE

CHIP SELECT

UHPI_HD[16]/HHWIL

UHPI_HCS

BYTE ENABLE ⁽¹⁾

C6727 DSP

Asynchronous

Mode

UHPI_HBE[1:0]B

UHPI_HCNTL[1:0]

Host

Processor

CONTROL INPUT ⁽²⁾

FUNDAMENTAL STROBE

READ/WRITE CONTROL

DSP INTERRUPT

UHPI_HCSB/UHPI_HDS[2:1]B

UHPI_HRWB

AMUTE2/HINTB

AFSR2

HOST INTERRUPT

B0281-01

(1) Byte enables are aplicable to single HPID accesses. All byte enables must be active during HPID with post-increment

(burst) UHPI accesses.

(2) Control inputs selecting between HPIA, HPIC, HPID, and HPID with post-increment accesses.

Figure 13. Host-to-DSP Interface (Multiplexed Host Address/Data Dual Halfword)

GLOSSARY OF TERMS

3G

Third generation (refers to next-generation wideband cellular systems that use CDMA)

3GPP

3GPP2

ACLR

ACPR

ADC

Third generation partnership project (W-CDMA specification, www.3gpp.org)

Third generation partnership project 2 (cdma2000 specification, www.3gpp2.org)

Adjacent channel leakage ratio (measure of out-of-band energy from one CDMA carrier)

Adjacent channel power ratio

Analog-to-digital converter

BW

Bandwidth

20

Submit Documentation Feedback

Product Folder Link(s): GC5325

GC5325

www.ti.com .............................................................................................................................................................................................. SLWS215–JANUARY 2009

CCDF

CDMA

CEVM

CFR

CMOS

DAC

dB

Complementary cumulative distribution function

Code division multiple access (spread spectrum)

Composite error vector magnitude

Crest factor reduction

Complementary metal oxide semiconductor

Digital-to-analog converter

Decibels

dBm

DDR

DSP

EVM

FIR

Decibels relative to 1 mW (30 dBm = 1 W)

Dual data rate (ADC output format)

Digital signal processing or digital signal processor

Error vector magnitude

Finite impulse response (type of digital filter)

In-phase and quadrature (signal representation)

Intermediate frequency

I/Q

IF

IIR

Infinite impulse response (type of digital filter)

Joint Test Action Group (chip debug and test standard 1149.1)

Local oscillator

JTAG

LO

LSB

Least-significant bit

Mb

Megabits (divide by 8 for megabytes MB)

MSB

MSPS

PA

Most-significant bit

Megasamples per second (1×10⁶samples/s)

Power amplifier

PAR

PCDE

PDC

PDF

RF

Peak-to-average ratio

Peak code domain error

Peak detection and cancellation (stage)

Probability density function

Radio frequency

RMS

SDR

SEM

SNR

UMTS

W-CDMA

WiBRO

WiMAX

Root mean square (method to quantify error)

Single data rate (ADC output format)

Spectrum emission mask

Signal-to-noise ratio (usually measured in dB or dBm)

Universal mobile telephone service

Wideband code division multiple access (synonymous with 3GPP)

Wireless broadband (Korean initiative IEEE 802.16e)

Worldwide Interoperability of Microwave Access (IEEE 802.16e)

Submit Documentation Feedback

21

Product Folder Link(s): GC5325

PACKAGE OPTION ADDENDUM

www.ti.com

3-Feb-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

GC5325IZND

ACTIVE

BGA

ZND

352

40

Pb-Free

(RoHS)

SNAGCU

Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Medical

Security

Logic

Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt

power.ti.com

Transportation and

Automotive

www.ti.com/automotive

Microcontrollers

RFID

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

Wireless

www.ti.com/video

www.ti.com/wireless-apps

RF/IF and ZigBee® Solutions www.ti.com/lprf

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	GC5325SEK
厂家：	TEXAS INSTRUMENTS
描述：	GC5325 Wideband Digital Predistortion Transmit Processor
文件：	总24页 (文件大小：422K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GC5325SEK [TI]

相关型号：

GC5328

GC5328IZER

GC5330

GC5330IZEV

GC5337

GC5337IZEV

GC55

GC554M7FI

GC554M7JI

GC562

GC570

GC5732C42