GD75232PWRG4 [TI]
具有 +/-7.5V 输出和 +/-1.5kV ESD 保护的 5V 多通道 120kbps RS-232 线路驱动器/接收器 | PW | 20 | 0 to 70;
| 型号： | GD75232PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 +/-7.5V 输出和 +/-1.5kV ESD 保护的 5V 多通道 120kbps RS-232 线路驱动器/接收器 | PW | 20 | 0 to 70 PC 驱动 光电二极管 接口集成电路 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总18页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄꢆ ꢀ ꢁꢇ ꢃꢄ ꢅꢄ
ꢈ ꢉꢊꢋ ꢌꢍ ꢊꢎ ꢏꢐꢑ ꢄꢅ ꢄ ꢁꢏꢌ ꢒꢎ ꢏꢐ ꢓꢔꢁ ꢏꢎꢕ ꢎꢌ ꢒ ꢎ ꢏꢐ
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
GD65232, GD75232 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
D
Single Chip With Easy Interface Between
UART and Serial-Port Connector of IBM
PC/AT and Compatibles
V
V
CC
1
2
3
4
5
6
7
8
9
10
20
DD
D
D
D
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
19 RY1
18 RY2
17 RY3
Designed to Support Data Rates up to
120 kbit/s
16
15
14
13
12
11
DA1
DA2
RY4
DA3
RY5
GND
Pinout Compatible With SN75C185 and
SN75185
description/ordering information
V
SS
The GD65232 and GD75232 combine three
drivers
and
five
receivers
from
the
Texas Instruments trade-standard SN75188 and
SN75189 bipolar quadruple drivers and receivers, respectively. The pinout matches the flow-through design
of the SN75C185 to decrease the part count, reduce the board space required, and allow easy interconnection
of the UART and serial-port connector of an IBM PC/AT and compatibles. The bipolar circuits and processing
of the GD65232 and GD75232 provide a rugged, low-cost solution for this function at the expense of quiescent
power and external passive components relative to the SN75C185.
The GD65232 and GD75232 comply with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28
standards. These standards are for data interchange between a host computer and a peripheral at signaling
rates up to 20 kbit/s. The switching speeds of these devices are fast enough to support rates up to 120 kbit/s
with lower capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be expected
unless the designer has design control of the cable and the interface circuits at both ends. For interoperability
at signaling rates up to 120 kbit/s, use of TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards
is recommended.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP (N)
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
GD65232N
GD65232N
GD65232DW
GD65232DWR
GD65232DBR
GD65232PW
GD65232PWR
GD75232N
SOIC (DW)
SSOP (DB)
GD65232
GD65232
−40°C to 85°C
TSSOP (PW)
PDIP (N)
GD65232
GD75232N
GD75232DW
GD75232DWR
GD75232DBR
GD75232PW
GD75232PWR
SOIC (DW)
SSOP (DB)
GD75232
GD75232
0°C to 70°C
TSSOP (PW)
GD75232
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IBM is a trademark of International Business Machines Corporation.
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Copyright 2004, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢀꢁ ꢇꢃ ꢄꢅ ꢄ
ꢈ ꢉ ꢊꢋ ꢌ ꢍꢊ ꢎ ꢏ ꢐꢑꢄꢅ ꢄ ꢁꢏ ꢌ ꢒꢎ ꢏꢐ ꢓꢔ ꢁ ꢏꢎ ꢕꢎ ꢌꢒ ꢎꢏꢐ
ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
logic diagram (positive logic)
2
19
18
17
16
15
14
13
RA1
RA2
RY1
RY2
3
4
5
6
7
8
RA3
DY1
RY3
DA1
DY2
RA4
DY3
DA2
RY4
DA3
9
12
RA5
RY5
schematic (each driver)
To Other Drivers
V
DD
11.6 kΩ
9.4 kΩ
Input
DAx
75.8 Ω
320 Ω
Output
DYx
4.2 kΩ
GND
To Other
Drivers
10.4 kΩ
3.3 kΩ
68.5 Ω
V
SS
To Other Drivers
Resistor values shown are nominal.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄꢆ ꢀ ꢁꢇ ꢃꢄ ꢅꢄ
ꢈ ꢉꢊꢋ ꢌꢍ ꢊꢎ ꢏꢐꢑ ꢄꢅ ꢄ ꢁꢏꢌ ꢒꢎ ꢏꢐ ꢓꢔꢁ ꢏꢎꢕ ꢎꢌ ꢒ ꢎ ꢏꢐ
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ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
schematic (each receiver)
To Other Receivers
V
CC
9 kΩ
5 kΩ
1.66 kΩ
Output
RYx
2 kΩ
3.8 kΩ
Input
RAx
10 kΩ
GND
To Other Receivers
Resistor values shown are nominal.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1): V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V
CC
DD
SS
V
V
Input voltage range, V : Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 7 V
I
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 V to 30 V
Driver output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V
O
Receiver low-level output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OL
Package thermal impedance, θ (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. Maximum power dissipation is a function of T (max), q , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) − T )/q . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢀꢁ ꢇꢃ ꢄꢅ ꢄ
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
recommended operating conditions
MIN NOM
MAX
15
UNIT
V
V
V
V
V
Supply voltage (see Note 4)
7.5
−7.5
4.5
9
−9
5
V
V
V
V
V
DD
SS
CC
IH
Supply voltage (see Note 4)
−15
5.5
Supply voltage (see Note 4)
High-level input voltage (driver only)
Low-level input voltage (driver only)
1.9
0.8
−6
IL
Driver
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
OL
Receiver
Driver
−0.5
6
I
Receiver
GD65232
GD75232
16
−40
0
85
T
A
70
NOTE 4: When powering up the GD65232 and GD75232, the following sequence should be used:
1. V
2. V
3. V
SS
DD
CC
4. I/Os
Applying V
before V may allow large currents to flow, causing damage to the device. When powering down the GD65232 and
DD
CC
GD75232, the reverse sequence should be used.
supply currents over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
15
UNIT
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 9 V,
V
V
V
V
V
V
V
V
V
V
V
V
= −9 V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
= 12 V,
= 15 V,
= 9 V,
= −12 V
= −15 V
= −9 V
19
All inputs at 1.9 V,
All inputs at 0.8 V,
All inputs at 1.9 V,
No load
No load
No load
25
I
Supply current from V
mA
DD
DD
4.5
5.5
9
= 12 V,
= 15 V,
= 9 V,
= −12 V
= −15 V
= −9 V
−15
−19
−25
−3.2
−3.2
−3.2
38
= 12 V,
= 15 V,
= 9 V,
= −12 V
= −15 V
= −9 V
I
I
Supply current from V
Supply current from V
mA
mA
SS
SS
= 12 V,
= 15 V,
= −12 V
= −15 V
All inputs at 0.8 V,
All inputs at 5 V,
No load
No load,
GD65232
GD75232
V
CC
= 5 V
CC
CC
30
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
DRIVER SECTION
electrical characteristics over recommended operating free-air temperature range, V
= 9 V,
DD
V
= −9 V, V
= 5 V (unless otherwise noted)
SS
CC
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
TYP
7.5
V
V
High-level output voltage
Low-level output voltage (see Note 5)
High-level input current
V
V
= 0.8 V,
= 1.9 V,
R
R
= 3 kΩ,
= 3 kΩ,
See Figure 1
See Figure 1
6
OH
IL
L
L
−7.5
−6
10
V
OL
IH
I
IH
V = 5 V,
I
See Figure 2
See Figure 2
µA
mA
I
IL
Low-level input current
V = 0,
I
−1.6
High-level short-circuit output current
(see Note 6)
I
V
= 0.8 V,
= 2 V,
V
= 0,
= 0,
See Figure 1
See Figure 1
−4.5
−12 −19.5
12 19.5
mA
OS(H)
OS(L)
IL
O
I
Low-level short-circuit output current
Output resistance (see Note 7)
V
V
V
O
4.5
mA
IH
r
= V
DD
= V
= 0,
V = −2 V to 2 V
O
300
Ω
o
CC
SS
NOTES: 5. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only (e.g., if −10 V is maximum, the typical value is a more negative voltage).
6. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.
7. Test conditions are those specified by TIA/EIA-232-F and as listed above.
switching characteristics, V
= 5 V, V
= 12 V, V = −12 V, T = 25°C
CC
DD SS A
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TYP
Propagation delay time,
low- to high-level output
t
t
R
R
= 3 kΩ to 7 kΩ,
= 3 kΩ to 7 kΩ,
C
C
= 15 pF,
= 15 pF,
See Figure 3
315
500
ns
PLH
L
L
L
L
Propagation delay time,
high- to low-level output
See Figure 3
75
175
ns
PHL
C
C
C
C
= 15 pF,
See Figure 3
60
1.7
40
100
2.5
75
ns
µs
ns
µs
Transition time,
low- to high-level output
L
L
L
L
t
t
R
R
= 3 kΩ to 7 kΩ
= 3 kΩ to 7 kΩ
TLH
L
L
= 2500 pF,
= 15 pF,
See Figure 3 and Note 8
See Figure 3
Transition time,
high- to low-level output
THL
= 2500 pF,
See Figure 3 and Note 8
1.5
2.5
NOTE 8: Measured between 3-V and 3-V points of the output waveform (TIA/EIA-232-F conditions); all unused inputs are tied either high
or low.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢀꢁ ꢇꢃ ꢄꢅ ꢄ
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ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
1.75
1.55
0.75
0.5
MAX
2.3
UNIT
TYP
T
= 25°C,
See Figure 5
1.9
0.97
4
A
V
IT+
Positive-going input threshold voltage
Negative-going input threshold voltage
V
T
A
= 0°C to 70°C,
See Figure 5
2.3
V
V
1.25
V
V
IT−
Input hysteresis voltage (V
− V )
IT−
hys
IT+
V
= 0.75 V
2.6
5
IH
Inputs open
V
V
High-level output voltage
Low-level output voltage
I
I
= −0.5 mA
= 10 mA,
V
V
OH
OH
2.6
V = 3 V
I
0.2
0.45
11
OL
OL
GD65232
GD75232
3.6
3.6
V = 25 V,
See Figure 5
See Figure 5
I
8.3
I
High-level input current
mA
IH
V = 3 V,
0.43
−3.6
−3.6
−0.43
I
GD65232
GD75232
−11
V = −25 V,
See Figure 5
See Figure 5
I
−8.3
I
I
Low-level input current
mA
mA
IL
V = −3 V,
I
Short-circuit output current
See Figure 4
−3.4
−12
OS
†
All typical values are at T = 25°C, V
CC
= 5 V, V
DD
= 9 V, and V = −9 V.
SS
A
switching characteristics, V
= 5 V, V
= 12 V, V = −12 V, T = 25°C
CC
DD SS A
PARAMETER
TEST CONDITIONS
MIN
TYP
107
42
MAX
250
150
350
60
UNIT
ns
t
t
t
t
t
t
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Transition time, low- to high-level output
PLH
PHL
TLH
THL
PLH
PHL
TLH
THL
ns
C
C
= 50 pF,
= 15 pF,
R
R
= 5 kΩ,
See Figure 6
L
L
L
L
175
16
ns
Transition time, high- to low-level output
ns
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Transition time, low- to high-level output
100
60
160
100
175
50
ns
ns
= 1.5 kΩ, See Figure 6
90
ns
Transition time, high- to low-level output
15
ns
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄꢆ ꢀ ꢁꢇ ꢃꢄ ꢅꢄ
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ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
I
OS(L)
V
DD
V
or GND
or GND
DD
SS
V
CC
−I
OS(H)
V
V
I
V
O
R
= 3 kΩ
L
V
SS
Figure 1. Driver Test Circuit for V , V , I
, and I
OS(L)
OH OL OS(H)
V
DD
V
CC
I
IH
V
V
I
−I
IL
I
V
SS
Figure 2. Driver Test Circuit for I and I
IH
IL
3 V
0 V
1.5 V
Input
1.5 V
V
Input
DD
V
CC
t
t
PHL
PLH
90%
Pulse
Generator
V
V
OH
C
L
90%
R
L
See Note A
50%
10%
(see Note B)
50%
10%
Output
OL
V
SS
t
t
TLH
THL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: t = 25 µs, PRR = 20 kHz, Z = 50 Ω, t = t < 50 ns.
w
O
r
f
B.
C includes probe and jig capacitance.
L
Figure 3. Driver Test Circuit and Voltage Waveforms
7
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ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢀꢁ ꢇꢃ ꢄꢅ ꢄ
ꢈ ꢉ ꢊꢋ ꢌ ꢍꢊ ꢎ ꢏ ꢐꢑꢄꢅ ꢄ ꢁꢏ ꢌ ꢒꢎ ꢏꢐ ꢓꢔ ꢁ ꢏꢎ ꢕꢎ ꢌꢒ ꢎꢏꢐ
ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
DD
V
CC
V
I
V
SS
Figure 4. Receiver Test Circuit for I
OS
V
DD
V
CC
−I
OH
V
OH
V ,
IT
V
I
V
OL
I
OL
V
SS
Figure 5. Receiver Test Circuit for V , V , and V
IT OH
OL
4 V
50%
50%
Input
V
Input
DD
V
0 V
CC
t
t
PHL
PLH
90%
Pulse
Generator
V
V
OH
C
L
90%
R
L
See Note A
50%
10%
(see Note B)
50%
10%
Output
OL
V
SS
t
t
TLH
THL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: t = 25 µs, PRR = 20 kHz, Z = 50 Ω, t = t < 50 ns.
w
O
r
f
B.
C includes probe and jig capacitance.
L
Figure 6. Receiver Propagation and Transition Times
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄꢆ ꢀ ꢁꢇ ꢃꢄ ꢅꢄ
ꢈ ꢉꢊꢋ ꢌꢍ ꢊꢎ ꢏꢐꢑ ꢄꢅ ꢄ ꢁꢏꢌ ꢒꢎ ꢏꢐ ꢓꢔꢁ ꢏꢎꢕ ꢎꢌ ꢒ ꢎ ꢏꢐ
ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
DRIVER SECTION
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE TRANSFER CHARACTERISTICS
12
20
16
12
8
V
= 12 V, V
= −12 V
= −9 V
= −6 V
DD
SS
SS
SS
V
V
T
= 9 V
= −9 V
= 25°C
DD
SS
A
9
6
V
= 9 V, V
DD
V
OL
(V = 1.9 V)
I
V
= 6 V, V
DD
3
0
4
0
−4
−3
−6
−9
3-kΩ
Load Line
−8
−12
−16
−20
V
OH
(V = 0.8 V)
I
R
T
A
= 3 kΩ
= 25°C
L
−12
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
−16 −12
−8
−4
0
4
8
12
16
V − Input Voltage − V
I
V
O
− Output Voltage − V
Figure 7
Figure 8
SHORT-CIRCUIT OUTPUT CURRENT
SLEW RATE
vs
LOAD CAPACITANCE
vs
FREE-AIR TEMPERATURE
12
1000
V
= 9 V
= −9 V
= 3 kΩ
= 25°C
DD
SS
L
9
6
V
R
T
I
(V = 1.9 V)
I
OS(L)
A
100
10
1
3
0
V
V
V
= 9 V
= −9 V
= 0
DD
SS
O
−3
−6
−9
I
(V = 0.8 V)
I
OS(H)
−12
0
10
20
30
40
50
60
70
10
100
C − Load Capacitance − pF
L
1000
10000
T
A
− Free-Air Temperature − °C
Figure 9
Figure 10
9
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ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢀꢁ ꢇꢃ ꢄꢅ ꢄ
ꢈ ꢉ ꢊꢋ ꢌ ꢍꢊ ꢎ ꢏ ꢐꢑꢄꢅ ꢄ ꢁꢏ ꢌ ꢒꢎ ꢏꢐ ꢓꢔ ꢁ ꢏꢎ ꢕꢎ ꢌꢒ ꢎꢏꢐ
ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
2.4
2.2
2
1.8
1.6
1.4
1.2
1
V
IT+
2
1.8
1.6
1.4
1.2
1
V
IT+
V
IT−
0.8
0.6
0.4
0.2
0
V
IT−
0.8
0.6
0.4
0
10
20
30
40
50
60
70
2
3
4
5
6
7
8
9
10
T
A
− Free-Air Temperature − °C
V
CC
− Supply Voltage − V
Figure 11
Figure 12
NOISE REJECTION
6
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
V
T
= 5 V
CC
= 25°C
A
5
4
3
2
1
0
See Note A
16
14
C
= 300 pF
C
12
10
8
C
= 500 pF
C
C
= 12 pF
C
C
= 100 pF
C
6
4
2
10
40
100
400 1000
4000 10000
t
− Pulse Duration − ns
w
R
≥ 3 kΩ (from each output to GND)
L
0
NOTE A: This figure shows the maximum amplitude of
a
0
10
20
30
40
50
60
70
positive-going pulse that, starting from 0 V, does not cause
a change of the output level.
T
− Free-Air Temperature − °C
A
Figure 13
Figure 14
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢄꢆ ꢀ ꢁꢇ ꢃꢄ ꢅꢄ
ꢈ ꢉꢊꢋ ꢌꢍ ꢊꢎ ꢏꢐꢑ ꢄꢅ ꢄ ꢁꢏꢌ ꢒꢎ ꢏꢐ ꢓꢔꢁ ꢏꢎꢕ ꢎꢌ ꢒ ꢎ ꢏꢐ
ꢖ
ꢖ
SLLS206J − MAY 1995 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
Diodes placed in series with the V and V leads protect the GD65232 and GD75232 in the fault condition in which
DD
SS
the device outputs are shorted to 15 V and the power supplies are at low and provide low-impedance paths to ground
(see Figure 15).
V
DD
V
DD
Output
15 V
GD65232,
GD75232
GD65232,
GD75232
V
SS
V
SS
Figure 15. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA/EIA-232-F
TL16C450
−12 V
11
12
13
10
9
ACE
5
V
GND
RY5
SS
43
37
RI
RI
9
RA5
DY3
8
DTR
DTR
DA3
RY4
DA2
C3
40
13
36
14
15
16
7
6
5
CTS
TX
CTS
SO
RA4
DY2
DY1
TIA/EIA-232-F
DB9S
Connector
C2
GD65232,
GD75232
RTS
RTS
DA1
C1
11
41
42
17
18
19
4
3
2
RX
SI
RY3
RY2
RY1
RA3
DSR
DCD
6
DSR
DCD
RA2
RA1
1
20
1
12 V
5 V
V
CC
V
DD
Figure 16. Typical Connection
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
GD65232DBR
GD65232DW
GD65232DWR
GD65232N
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
20
20
20
20
20
20
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SOIC
SOIC
DW
DW
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
PDIP
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
GD65232PW
GD65232PWR
GD75232DB
GD75232DBR
GD75232DW
GD75232DWR
GD75232N
TSSOP
TSSOP
SSOP
SSOP
SOIC
PW
PW
DB
DB
DW
DW
N
70
Pb-Free
(RoHS)
2000
Pb-Free
(RoHS)
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
2000
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SOIC
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
PDIP
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
GD75232PW
GD75232PWR
TSSOP
TSSOP
PW
PW
70
Pb-Free
(RoHS)
2000
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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