HD3SS460IRHRR [TI]
USB Type-C 交替模式 4x6 差分开关 | RHR | 28 | -40 to 85;
| 型号： | HD3SS460IRHRR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB Type-C 交替模式 4x6 差分开关 | RHR | 28 | -40 to 85 开关 |
| 文件： | 总39页 (文件大小：2142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
HD3SS460 4 x 6 通道 USB Type-C™交替模式 MUX
1 特性
3 说明
•
•
•
提供面向 USB Type-CTM 生态系统的 MUX 解决方
HD3SS460 是一款高速双向无源开关，可采用复用或
1
案，其中包括交替模式 (AM)
解复用两种配置。该器件可通过负载点 (POL) 控制引
脚进行切换，从而适应连接器换向。该器件还可通过
AMSEL 控制引脚来实现双通道数据/双通道视频与所有
四通道视频的复用。
提供多种通道选择选项，其中包括 USBSS、双通
道 AM 和四通道 AM
与 5 Gbps USB3.1 第 1 代和包含 5.4 Gbps
DisplayPort 1.2a 的 AM 兼容
该器件还针对低速引脚提供了交叉点 MUX，可满足可
换向连接器实现的需求。
•
•
•
•
•
与源设备/主机和接收设备/设备应用 兼容
针对低速 SBU 引脚提供交叉点 MUX
双向“复用/解复用”差动开关
HD3SS460 是一款通用模拟差分无源开关，适用于所
有高速接口 应用， 前提条件是该应用在 0V 至 2V 共
模电压范围内发生偏置并且具有幅值高达 1800 mVpp
的差分信令。该器件采用自适应跟踪，可确保信道在整
个共模电压范围内保持不变。
支持 0V 至 2V 共模电压
功耗较低，关断电流和工作电流分别为 1μA 和
0.6mA
•
•
单电源电压 VCC：3.3V±10%
工业温度范围：–40°C 至 85°C
该器件具有出色的动态特性，可在信号眼图衰减最小的
情况下实现高速转换，并且附加抖动极少。该器件在工
作模式下的功耗 < 2mW，关断模式下的功耗 < 5µW
（可通过 EN 引脚切换模式）。
2 应用
•
•
•
•
可换向 USB Type-CTM 生态系统
平板电脑、笔记本电脑、监视器、电话
USB 主机和设备
器件信息(1)
扩展坞
器件型号
HD3SS460
封装
封装尺寸（标称值）
QFN (RHR) (28)
3.50mm x 5.50mm
HD3SS460I
HD3SS460
HD3SS460I
QFN (RNH) (30)
2.50mm x 4.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
sp
简化电路原理图
应用
SSRX SSTX
USB Device/
USB Host
Hub
C_SS[RX/TX][1/2]
SS RX/TX
SS RX/TX
CRX1
LnD
LnC
HD3SS460
HD3SS460
CTX1
CTX2
CRX2
High Speed
MUX
4-6
X-point
MUX
4-6
X-point
MUX
USB
TypeC
Switches
LnB
LnA
4/2 Ln DP
AUX
AUX
4/2 Ln DP
SBU1/2
AMSEL
POL
EN
DP Sink/ MST
Hub
DP Source
VCC
GND
SBU1
SBU2
Copyright © 2016, Texas Instruments Incorporated
Low Speed
MUX
CSBU1
CSBU2
Switches
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEM7
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 USB SS and DP as Alternate Mode ...................... 14
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 High Speed Port Performance Parameters .............. 8
7.7 High Speed Signal Path Switching Characteristics .. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 27
12.1 接收文档更新通知 ................................................. 27
12.2 社区资源................................................................ 27
12.3 商标....................................................................... 27
12.4 静电放电警告......................................................... 27
12.5 Glossary................................................................ 27
13 机械、封装和可订购信息....................................... 27
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (December 2016) to Revision D
Page
•
•
Deleted R187 from Figure 16 .............................................................................................................................................. 21
Deleted R187 from Figure 19. .............................................................................................................................................. 23
Changes from Revision B (June 2016) to Revision C
Page
•
•
•
•
已将 QFN (RNH) (30) 添加至器件信息表 ............................................................................................................................... 1
Added the RNH package option to the Device Comparison Table table ............................................................................... 4
Added the RNH package option to the Pin Configuration and Functions section.................................................................. 5
Changed the Description of pins LnBn, p, LnCn, p, LnDn, p, SSTXn, p, and SSRXn, p From: positive, negative To:
negative, positive in the Pin Functions table .......................................................................................................................... 5
•
•
•
Changed the Supply voltage MIN value From: 3.0 V To: 2.7 V in the Recommended Operating Conditions table.............. 6
Added the RNH package option to the Thermal Information table ....................................................................................... 6
Changed VIH to include a separate line entry for POL pin in the Electrical Characteristics table .......................................... 7
Changes from Revision A (March 2015) to Revision B
Page
•
•
•
•
•
•
•
•
Changed text and Figure 3, Figure 4 in the USB SS and DP as Alternate Mode section for clarity. ................................. 14
Added Figure 5 ..................................................................................................................................................................... 15
Added Figure 6 ..................................................................................................................................................................... 16
Deleted Table Pin Assignments for DP Source Pins and DP Sink Pins in the Detailed Design Procedure section............ 17
Added Table 2, Table 3, Table 4, and Table 5 .................................................................................................................... 17
Added Figure 8 through Figure 13 ...................................................................................................................................... 17
Changed image for Figure 16 .............................................................................................................................................. 21
Changed image for Figure 19............................................................................................................................................... 23
2
版权 © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
Changes from Original (January 2015) to Revision A
Page
•
Added full data sheet specification complement ................................................................................................................... 6
Copyright © 2015–2017, Texas Instruments Incorporated
3
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
5 Device Comparison Table(1)
OPERATING
PART NUMBER
PINS
TOP-SIDE MARKING
TEMPERATURE (°C)
0 to 70
–40 to 85
0 to 70
HD3SS460RHR
HD3SS460IRHR
HD3SS460RNH
HD3SS460IRNH
28
28
30
30
3SS460
3SS460I
460RNH
460IRNH
–40 to 85
(1) For all available packages, see the orderable addendum at the end of the data sheet. Package drawings, thermal data, and
symbolization are available at www.ti.com/packaging
4
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
6 Pin Configuration and Functions
RHR Package With Thermal Pad
(28-Pin WQFN)
RNH Package With Thermal Pad
(30-Pin WQFN)
Top View
Top View
CRX1p
CRX1n
POL
1
2
3
4
5
LnDp
LnDn
VCC
24
28 27 26 25
CRX1p
CRX1n
POL
1
2
3
4
5
LnDp
LnDn
VCC
25
30 29 28 27 26
23
22
24
23
CTX1p
CTX1n
CTX2p
CTX2n
AMSEL
CRX2p
CRX2n
LnCp
LnCn
CTX1p
CTX1n
CTX2p
CTX2n
AMSEL
CRX2p
CRX2n
LnCp
LnCn
21
20
19
22
21
20
Thermal Pad
GND
Thermal Pad
GND
LnBp
LnBn
LnBp
LnBn
6
7
6
7
19
18
18
17
EN
8
9
EN
8
9
LnAp
LnAn
17
LnAp
LnAn
16
10 11 12 13 14 15 16
10 11 12 13 14 15
Pin Functions
PIN
(1)
TYPE
DESCRIPTION
RHR
NO.
RNH
NO.
NAME
VCC
GND
POL
22
PAD
3
23
13, 28, PAD
3
P
Power
G
Ground
Input
Provides MUX control (Table 1)
3-Level
Input
AMSEL
EN
8
8
Provides MUX configurations (Table 1)
3-Level
Input
17
18
Enable signal; also provides MUX control (Table 1)
CRX1p, n
CTX1p, n
CTX2p, n
CRX2p, n
LnAn, p
1, 2
1, 2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
High Speed Signal Port CRX1 positive, negative
High Speed Signal Port CTX1 positive, negative
High Speed Signal Port CTX2 positive, negative
High Speed Signal Port CRX2 positive, negative
High Speed Signal Port LnA positive, negative
High Speed Signal Port LnB negative, positive
High Speed Signal Port LnC negative, positive
High Speed Signal Port LnD negative, positive
High Speed Signal Port SSTX negative, positive
High Speed Signal Port SSRX negative, positive
Low Speed Signal Port CSBU 1, 2
4, 5
4, 5
6, 7
6, 7
9, 10
9, 10
15, 16
18, 19
20, 21
23, 24
25, 26
27, 28
11, 12
13, 14
16, 17
19, 20
21, 22
24, 25
26, 27
29, 30
11, 12
14, 15
LnBn, p
LnCn, p
LnDn, p
SSTXn, p
SSRXn, p
CSBU1, 2
SBU1, 2
Low Speed Signal Port SBU 1, 2
(1) High speed data ports (CRX[1/2][p/n], Ln[A-D][p,n], and SS[T/R]X[p/n]) incorporate 20kΩ pull down resistors that are switched in when a
port is not selected and switched out when the port is selected.
Copyright © 2015–2017, Texas Instruments Incorporated
5
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
4
UNIT
V
Supply Voltage, VCC
Differential High Speed I/O Voltages, C[R/T]X[1/2][p/n], Ln[A-D][p/n], SS[R/T]X[p/n]
Low Speed I/O Voltages, CSBU[1/2], SBU[1/2]
Control signal voltages, POL, AMSEL, EN
2.5
4
V
V
4
V
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
3.3
25
MAX
3.6
70
UNIT
VCC
TA
Supply voltage
V
HD3SS460
HD3SS460I
Operating free air temperature
°C
–40
0
25
85
VCM
VIN
High speed port common mode voltage
Low Speed signal voltage
2
V
0
VCC
1.8
Vdiff
High speed port differential voltage
0
Vpp
7.4 Thermal Information
HD3SS460
QFN (RNH)
THERMAL METRIC(1)
QFN (RHR)
28 PINS
44.0
UNIT
30 PINS
51.6
37.5
17.5
0.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.8
14.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
17.3
6.8
24.5
RθJC(bot)
6.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
7.5 Electrical Characteristics
typical values for all parameters are at VDD = 3.3 V and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input low voltage, control pins POL,
AMSEL, EN
VIL
VIH
VIM
–0.1
0.4
Input high voltage, control pins
AMSEL, EN
VCC –0.4
1.7
VCC +0.1
VCC +0.1
V
Input high voltage, control pins POL
Input mid-level voltage, control pins
AMSEL, EN
VCC/2 –0.3
VCC/2 VCC/2 +0.3
Leakage current on active
ILK-DIFF-ACTIVE differential IO pins, VCC = 3.6 V,
pin at 0 or 2.4 V.
1
Leakage current on inactive
differential IO pins, VCC = 3.6V, pin
at 2.4 V.
ILK-DIFF-
INACTIVE
150
1
Input high current, control pins
POL, AMSEL, EN and signal pins
CSBU1/2, SBU1/2
IIH
µA
Input low current, control pins POL,
AMSEL, EN and signal pins
CSBU1/2, SBU1/2
IIL
1
1
Input mid-level current, control pins
AMSEL, EN
IIM
IOFF
IDD
Device shutdown current
1
5
Device active current, EN=H or M
0.6
0.9
mA
Switch ON resistance for high
speed differential signals
VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA
RON(HS)
RON(LS)
8
14
Switch ON resistance for low speed VCC = 3.3 V, VCM = 0-2 V,
signals
12
IO = - 8 mA
Ω
(RON(MAX) – RON(MIN)) over VCM
range VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA
High speed differential signals’ ON
resistance flatness for a channel
RFLAT(ON,HS)
1.5
1
High speed differential signals’
input capacitance
CON(HS)
pF
Copyright © 2015–2017, Texas Instruments Incorporated
7
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
7.6 High Speed Port Performance Parameters
under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
MIN
TYP
–23
–9
MAX
UNIT
100 Mhz SS Paths
2.5 Ghz SS Paths
RL
Differential return loss
100 MHz AM Paths
2. 7GHz AM Paths
100 Mhz SS Paths
2.5 Ghz SS Paths
100 MHz AM Paths
2.7 GHz AM Paths
100 Mhz
–23
–13
–0.7
–1.6
–0.7
–1.4
–50
–26
–25
–80
–30
–28
–50
–26
–25
4.2
IL
Differential insertion loss
Differential off isolation
dB
OI
2.5 Ghz
2.7 GHz
100 Mhz
Differential cross talk, Between
CRX1/2 and CTX1/2
2.5 Ghz
2.7 Ghz
Xtalk
100 Mhz
Differential cross talk, Between
CRX1 and CRX2 or CTX1 and
CTX2
2.5 Ghz
2.7 Ghz
BWSS
BWAM
BWSBU
Differential –3 dB BW SS Paths
Differential –3 dB BW AM Paths
Low-speed switch –3 dB BW
GHz
MHz
5.4
500
7.7 High Speed Signal Path Switching Characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
100
50
UNIT
tPD
Switch propagation delay
Inter-Pair output skew (CH-CH)
Intra-Pair output skew (bit-bit)
tSK(O)
tSK(b-b)
RSC and RLOAD = 50 Ω, Figure 2
ps
5
Control signals POL, AMSEL and
EN (H/M toggle) to switch ON time
tON
3
1
RSC and RLOAD = 50 Ω, Figure 1
µs
Control signals POL, AMSEL and
EN (H/M toggle) to switch OFF time
tOFF
Timing Diagrams
50%
POL, AMSEL, EN (H/M)
90%
10%
High/Low Speed Signals
Toff
Ton
Figure 1. Switch ON/OFF Time
8
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
Vcc
50 Ω
C[R/T]X[1/2]p
C[R/T]X[1/2]n
Ln[D-A]/SS[T/R]Xp
50 Ω
50 Ω
Ln[D-A]/SS[T/R]Xn
50 Ω
SEL
C[R/T]X[1/2]p
50%
50%
C[R/T]X[1/2]n
Ln[D-A]/SS[T/R]Xp
50%
50%
Ln[D-A]/SS[T/R]Xn
tP1
t2
tP2
t4
t1
t3
Ln[x]/SS[x]Xp
50%
Ln[x]/SS[x]Xn
Ln[y]/SS[y]Xp
tSK(O)
Ln[y]/SS[y]Xn
tPD= Max(tp1, tp2
)
tSK(O) = Difference between t PD for any two
pairs of outputs
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
Figure 2. Propagation Delay and Skew
Copyright © 2015–2017, Texas Instruments Incorporated
9
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
8 Detailed Description
8.1 Overview
The HD3SS460 is a high-speed bi-directional passive 4-6 cross-point switch in mux or demux configurations.
Based on control pin POL the device provides switching to accommodate USB Type-C plug flipping. The device
provides multiple signal switching options that allow system implementation flexibility.
The HD3SS460 is a generic analog, differential passive switch that can work for any high speed interface
applications as long as it is biased at a common mode voltage range of 0-2 V and has differential signaling with
differential amplitude up to 1800 mVpp. It employs an adaptive tracking that ensures the channel remains
unchanged for entire common mode voltage range
Excellent dynamic characteristics of the device allow high speed switching with minimum attenuation to the
signal eye diagram with very little added jitter.
8.2 Functional Block Diagram
SSRX SSTX
CRX1
LnD
LnC
CTX1
CTX2
CRX2
High Speed
MUX
Switches
LnB
LnA
AMSEL
POL
EN
VCC
GND
SBU1
SBU2
Low Speed
MUX
CSBU1
CSBU2
Switches
Copyright © 2016, Texas Instruments Incorporated
10
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
8.3 Feature Description
8.3.1 High Speed Differential Signal Switching
Based on control pin AMSEL the device provides muxing options of:
1. 1 port (RX and TX) USB3.1 SS data / 2Ch video (or any other Alternate Mode data)
2. All 4Ch video (or any other Alternate Mode data)
3. 1 port (RX and TX) USB3.1 SS data
4. 1 port (RX and TX) USB3.1 SS data / 2Ch video (or any other Alternate Mode data) with option of choosing
video from two different source/sink
5. 1 port (RX and TX) USB3.1 SS data / 2Ch video (or any other Alternate Mode data) with option of choosing
video 2 Ln Video or 1 Ln Video from two different source/sink
8.3.2 Low Speed SBU Signal Switching
The device also provides cross point muxing for low speed SBU signals as needed in USB Type-C flippable
connector implementation. The device provides the option to choose the USB only implementation where SBU
ports are in tri-state.
8.3.3 Output Enable and Power Savings
The HD3SS460 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very little current to save the maximum power. To enter standby mode, the
EN control pin is pulled low and must remain low. For active/normal operation, the EN control pin should be
pulled high to VDD through a resistor or dynamically controlled to switch between H or M.
HD3SS460 consumes <2 mW of power when operational and <5 µW in shutdown mode, exercisable by the EN
pin.
8.4 Device Functional Modes
8.4.1 Device High Speed Switch Control Modes
Table 1. MUX Control for High Speed and Low Speed SBU Channels
HIGH SPEED SIGNAL
POL
AMSEL
EN
CONFIGURATIONS
SBU SIGNAL FLOW
FLOW(1)
SSRX SSTX
CRX1
LnD
LnC
LnB
LnA
2CH USBSS + 2CH AM
(Normal)
CSBU1
SBU1
SBU2
L
L
H
CTX1
CTX2
CRX2
CSBU2
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
2CH USBSS + 2CH AM
(Flipped)
CSBU1
CSBU2
SBU1
SBU2
H
L
H
(1) All positive signals connect to positive and negative to negative
Copyright © 2015–2017, Texas Instruments Incorporated
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HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
Device Functional Modes (continued)
Table 1. MUX Control for High Speed and Low Speed SBU Channels (continued)
HIGH SPEED SIGNAL
FLOW(1)
POL
AMSEL
EN
CONFIGURATIONS
SBU SIGNAL FLOW
SSRX SSTX
CRX1
LnD
LnC
LnB
LnA
CSBU1
SBU1
SBU2
L
H
H
4CH AM (Normal)
CTX1
CTX2
CRX2
CSBU2
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
CSBU1
CSBU2
SBU1
SBU2
H
H
M
M
M
H
H
H
M
4CH AM (Flipped)
2CH USBSS (Normal)
2CH USBSS (Flipped)
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
All Low Speed SBU
L
Ports HighZ
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
All Low Speed SBU
Ports HighZ
H
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
2CH USBSS + 2CH AM
(Normal)
CSBU1
CSBU2
SBU1
SBU2
L
12
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
Device Functional Modes (continued)
Table 1. MUX Control for High Speed and Low Speed SBU Channels (continued)
HIGH SPEED SIGNAL
FLOW(1)
POL
AMSEL
EN
CONFIGURATIONS
SBU SIGNAL FLOW
SSRX SSTX
CRX1
LnD
LnC
LnB
LnA
2CH USBSS + 2CH AM
(Flipped)
CSBU1
SBU1
SBU2
H
M
M
CTX1
CTX2
CRX2
CSBU2
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
2CH USBSS + 2CH AM from
alternate GPU (Normal)
CSBU1
CSBU2
SBU1
SBU2
L
L
M
SSRX SSTX
CRX1
CTX1
CTX2
CRX2
LnD
LnC
LnB
LnA
2CH USBSS + 2CH AM from
alternate GPU (Flipped)
CSBU1
CSBU2
SBU1
SBU2
H
L
M
L
H
H
M
M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
H
All Low Speed SBU
Ports HighZ
X
X
L
All High Speed Ports HighZ
All High Speed Ports HighZ
Copyright © 2015–2017, Texas Instruments Incorporated
13
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
HD3SS460 can be utilized for a wide range of muxing needs. This is general purpose passive cross-point switch.
The channels have independent adaptive common mode tracking allowing flexibility. As long as recommended
electrical use conditions are met the device can be used number of ways as described in Table 1.
NOTE
HD3SS460 does not provide common mode biasing for the channel. Therefore it is
required that the device is biased from either side for all active channels.
9.2 USB SS and DP as Alternate Mode
HD3SS460 can be used USB Type-C ecosystem with DP as alternate mode in two distinct application
configurations – one is for DP Source/USB Host, the other one for the DP Sink/USB Device/Dock. Figure 3 and
Figure 4 illustrate typical application block diagrams for these two cases. Detail schematics are illustrated in
Detailed Design Procedure section. Other applications and or use cases possible where these examples can be
used as general guidelines.
Figure 3 and Figure 4 depict the AC coupling capacitor placement examples. TI recommends placing the
capacitors as shown in the illustrations for the backward compatibility and interoperability purposes as some of
the existing USB systems may present Vcm, exceeding the typical range of 0–2 V on SS differential pairs.
Ü{.3 Iost
bo !/ /oupling /aps
{{Çó {{wó
ꢀ[0+
ꢀ[0>
wó1+
wó1>
0ꢁ1 µC
0ꢁ1 µC
ꢀ[1+
ꢀ[1>
Çó1+
Çó1>
I53{{460
ꢀ[2+
ꢀ[2>
Çó2+
Çó2>
ꢀ[3+
ꢀ[3>
wó2+
wó2>
/opyright © 2016, Çexas Lnstruments Lncorporated
Figure 3. Block Diagram for a Type C Interface Using DP as Alternate Mode – Source/Host
14
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
USB SS and DP as Alternate Mode (continued)
Ü{.3 Üpstreꢀm ꢁort
bo !/ /oupling /ꢀps
{{wó {{Çó
wó1+
wó1>
a[0+
a[0>
0ꢂ1 µC
0ꢂ1 µC
Çó1+
Çó1>
a[1+
a[1>
5ꢁ {ink
I53{{460
Çó2+
Çó2>
a[2+
a[2>
wó2+
wó2>
a[3+
a[3>
/opyright © 2016, Çexꢀs Lnstruments Lncorporꢀted
Figure 4. Diagram for a Type C Interface Using DP as Alternate Mode – Sink/Device/Dock
Figure 5 and Figure 6 depict the AC coupling capacitor recommendations in case the upstream or downstream
port connected internally to the HD3SS460 presents Vcm greater than 2 V.
ëcm > 2.0 ë
ꢁ00 nC
ꢁ00 nC
100 lQ
100 lQ
100 lQ
100 lQ
{{Çó {{wó
I53{{460
0.1 µC
a[0+
a[0>
wó1+
wó1>
a[1+
a[1>
0.1 µC
0.1 µC
Çó1+
Çó1>
5ꢀ {ource
a[2+
a[2>
Çó2+
Çó2>
0.1 µC
a[3+
a[3>
wó2+
wó2>
/opyright © 2016, Çexꢂs Lnstruments Lncorporꢂted
Figure 5. HD3SS460 USB Host (DP Source with SS USB Vcm)
Copyright © 2015–2017, Texas Instruments Incorporated
15
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
USB SS and DP as Alternate Mode (continued)
ëcm > 2.0 ë
ꢁ00 nC
ꢁ00 nC
100 lQ
100 lQ
100 lQ
100 lQ
{{Çó {{wó
wó1+
wó1>
a[0+
a[0>
0.1 µC
0.1 µC
Çó1+
Çó1>
a[1+
a[1>
5ꢀ {ink
I53{{460
Çó2+
Çó2>
a[2+
a[2>
wó2+
wó2>
a[3+
a[3>
/opyright © 2016, Çexꢂs Lnstruments Lncorporꢂted
Figure 6. HD3SS460 USB Upstream (DP Sink Implementation Example)
9.2.1 Design Requirements
DESIGN PARAMETERS
VCC
EXAMPLE VALUES
3.3 V
Decoupling capacitors
0.1 µF
75-200nF (100nF shown) USBSS TX p and n lines require AC capacotprs. Alternate
mode signals may or may not require AC capacitors
AC Capacitors
Control pins
Controls pins can be dynamically controlled or pin-strapped. The POL signal is
controlled by CC logic in the Type-C ecosystem.
16
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
9.2.2 Detailed Design Procedure
The reference schematics shown in this document are based upon the pin assignment defined in the Alternate
mode over Type C specification as shown in Figure 7 below.
Figure 7. Pin Assignment – Alternate Mode Over Type C
Table 2 represents the example pin mapping to HD3SS460 for the DP Source pin assignments C, D, E and F,
DP Sink pin assignments C and D.
Table 2. SOURCE Pin Assignment Option C and E (AMSEL = H, EN = H)
460 PIN MAPPING TO DP SOURCE (GPU)
POL = L POL = H
LnA(ML0) LnD(ML3)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO
TYPE C CONNECTOR
A11/10
CRX2
CTX1
A2/3
B11/10
B2/3
A8
LnC(ML2)
LnB(ML1)
CRX1
CTX2
LnD(ML3)
LnA(ML0)
LnB(ML1)
LnC(ML2)
CSBU1
CSBU2
SBU1(AUXP)
SBU2(AUXN)
SBU2(AUXN)
SBU1(AUXP)
B8
HD3SS460
Video Source (GPU)
A11 / A10
A2 / A3
CRX2
CTX1
LnA/LnD
LnC/LnB
ML0/ML3
ML2/ML1
0.1 mF
0.1 mF
B11 / B10
B2 / B3
CRX1
CTX2
LnD/LnA
LnB/LnC
ML3/ML0
ML1/ML2
SBU1/2
SBU2/1
AUXN/N
AUXP/P
A8 / B8
CSBU1/2
Type-C
Connector
wed text indicates ꢀh[ = I
Ü{. {{ lines are internally
unconnected under tꢁis mode
xI/L Iost
Copyright © 2016, Texas Instruments Incorporated
Figure 8. SOURCE Pin Assignment Option C and E (AMSEL = H, EN = H)
Copyright © 2015–2017, Texas Instruments Incorporated
17
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
Table 3. SOURCE Pin Assignment Option D and F (AMSEL = L, EN = H)
460 PIN MAPPING TO DP SOURCE (GPU)
POL = L POL = H
LnA(ML0)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO
TYPE C CONNECTOR
A11/10
CRX2
CTX1
SSRX
A2/3
B11/10
B2/3
A8
SSTX
LnB(ML1)
LnA(ML0)
SSTX
CRX1
CTX2
SSRX
LnB(ML1)
SBU1(AUXP)
SBU2(AUXN)
CSBU1
CSBU2
SBU2(AUXN)
SBU1(AUXP)
B8
Space
HD3SS460
HD3SS460
Video Source (GPU)
Video Source (GPU)
A11 / A10
A2 / A3
CRX2
CTX1
LnA
LnC
A11 / A10
A2 / A3
CRX2
CTX1
CRX1
CTX2
LnA
LnC
ML1
ML3
ML0
ML2
0.1 mF
0.1 mF
0.1 mF
B11 / B10
B2 / B3
CRX1
CTX2
LnD
LnB
ML2
ML0
B11 / B10
B2 / B3
LnD
LnB
ML3
ML1
0.1 mF
SBU1
SBU2
SBU2
SBU1
AUXN
AUXP
AUXN
AUXP
A8 / B8
A8 / B8
CSBU1/2
CSBU1/2
Type-C
Type-C
Connector
Connector
[n/ and [n5 lines are internally
unconnected under this mode
[n/ and [n5 lines are internally
unconnected under this mode
xI/L Iost
xI/L Iost
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 9. SOURCE Pin Assignment Option D and F Figure 10. SOURCE Pin Assignment Option D and
(AMSEL = L, EN = H, POL = L) F (AMSEL = L, EN = H, POL = H)
Table 4. SINK Pin Assignment Option C (AMSEL = H, EN = H)
460 PIN MAPPING TO DP SOURCE (GPU)
POL = L POL = H
LnA(ML1) LnD(ML2)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO
TYPE C CONNECTOR
A11/10
CRX2
CTX1
A2/3
B11/10
B2/3
A8
LnC(ML3)
LnB(ML0)
CRX1
CTX2
LnD(ML2)
LnA(ML1)
LnB(ML0)
LnC(ML3)
CSBU1
CSBU2
SBU1(AUXN)
SBU2(AUXP)
SBU2(AUXP)
SBU1(AUXN)
B8
HD3SS460
Video Sink
ML1/ML2
A11 / A10
A2 / A3
CRX2
CTX1
LnA/LnD
LnC/LnB
0.1 mF
0.1 mF
ML3/ML0
B11 / B10
B2 / B3
CRX1
CTX2
LnD/LnA
LnB/LnC
ML2/ML1
ML0/ML3
SBU1/2
SBU2/1
AUXN/P
AUXP/N
A8 / B8
CSBU1/2
Type-C
Connector
wed text indicates ꢀh[ = I
Ü{. {{ lines are internally
unconnected under tꢁis mode
{{ IÜ./5evice
Copyright © 2016, Texas Instruments Incorporated
Figure 11. SINK Pin Assignment Option C (AMSEL = H, EN = H)
18
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
Table 5. SINK Pin Assignment Option D (AMSEL = L, EN = H)
460 PIN MAPPING TO DP SOURCE (GPU)
POL = L POL = H
LnA(ML1)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO
TYPE C CONNECTOR
A11/10
CRX2
CTX1
SSRX
A2/3
B11/10
B2/3
A8
SSTX
LnB(ML0)
LnA(ML1)
SSTX
CRX1
CTX2
SSRX
LnB(ML0)
SBU1(AUXN)
SBU2(AUXP)
CSBU1
CSBU2
SBU2(AUXP)
SBU1(AUXN)
B8
Space
HD3SS460
HD3SS460
Video Source (GPU)
Video Source (GPU)
A11 / A10
A2 / A3
CRX2
CTX1
LnA
LnC
A11 / A10
A2 / A3
CRX2
CTX1
CRX1
CTX2
LnA
LnC
ML1
ML3
ML0
ML2
0.1 mF
0.1 mF
0.1 mF
B11 / B10
B2 / B3
CRX1
CTX2
LnD
LnB
ML2
ML0
B11 / B10
B2 / B3
LnD
LnB
ML3
ML1
0.1 mF
SBU1
SBU2
SBU2
SBU1
AUXN
AUXP
AUXN
AUXP
A8 / B8
A8 / B8
CSBU1/2
CSBU1/2
Type-C
Type-C
Connector
Connector
[n/ and [n5 lines are internally
unconnected under this mode
[n/ and [n5 lines are internally
unconnected under this mode
xI/L Iost
xI/L Iost
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 12. SINK Pin Assignment Option D
(AMSEL = L, EN = H, POL=L)
Figure 13. SINK Pin Assignment Option D
(AMSEL = L, EN = H, POL=H)
Copyright © 2015–2017, Texas Instruments Incorporated
19
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
Schematic diagrams Figure 14, Figure 15, and Figure 16 show the DP Source/USB Host implementation; and,
Figure 17, Figure 18, and Figure 19 show the DP Sink/USB Device/HUSB Hub/Dock implementation,
respectively.
VBUS
TypeC Connector and Source Pin Mapping
J2
A4
A9
B4
B9
VBUS1
VBUS2
VBUS3
VBUS4
C8
10uF
GND
A1
A2
A3
GND
B12
B11
B10
A5
B5
CC1
CC2
CC1
CC2
ML2P SSTXP1
ML1P SSTXP2
SSRXP1 ML3P
SSRXP2 ML0P
A8
B8
CSBU1
CSBU2
SBU1
SBU2
ML2N SSTXN1
ML1N SSTXN2
SSRXN1 ML3N
SSRXN1 ML0N
Note: It is
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
USB2_N0
USB2_P0
A7
A6
DN1
DP1
VBUS A4
B9 VBUS
B6
B7
DP2
DN2
CC1
DP1
DN1
A5
A6
A7
B8 SBU2
AUXN
AUXP
A2
A3
CTX1P
CTX1N
SSTXP1
SSTXN1
B7 DN2
B6 DP2
B5 CC2
B4 VBUS
HD3SS460
device is off.
A11
A10
CRX2P
CRX2N
SSRXP2
SSRXN2
B2
B3
CTX2P
CTX2N
SSTXP2
SSTXN2
AUXP
AUXN
SBU1 A8
VBUS A9
B11
B10
CRX1P
CRX1N
SSRXP1
Shield6SSRXN1
Shield5
g6
g5
g4
g3
g2
g1
A1
A12
B1
Shield4 GND0
Shield3 GND1
Shield2 GND2
Shield1 GND3
ML0N SSRXN2
ML3N SSRXN1
B3 SSTXN2
SSTXN1
ML1N
ML2N
A10
A11
A12
B12
ML0P SSRXP2
ML3P SSRXP1
B2 SSTXP2
SSTXP1
ML1P
ML2P
USB_TypeC_Receptacle_
GND
B1 GND
CSBU1
CSBU2
pull-down
resistor
between 1MΩ-2MΩ
is recommended
on SBU1 and
SBU2.
R156
2MΩ
R158
2MΩ
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Schematic Implementations for DP Source/ USB Host (1 of 3)
20
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
ESD Components
Place in pass through manner with no stub
U8
1
2
3
4
5
10
9
8
7
6
CTX1N
CTX1P
D1
D1-
NC10
NC9
GND GND
CRX1N
CRX1P
NC7
NC6
D2+
D2-
TPD4E05U06
U9
1
2
3
4
5
10
9
8
7
6
CTX2P
CTX2N
D1
D1-
NC10
NC9
GND GND
CRX2P
CRX2N
NC7
NC6
D2+
D2-
TPD4E05U06
U12
CC1
CC2
USB2_P0
1
14
13
12
11
10
9
NC1
NC2
NC3
NC4
GND GND
NC5 D3+
NC6 D3-
D1+
2
3
4
5
6
7
D1-
D2+
D2-
USB2_N0
CSBU1
CSBU2
8
TPD6E05U06
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Schematic Implementations for DP Source/ USB Host (2 of 3)
3P3V
3P3V
C3
0.1uF
R188
10K
R6
10K
U2
Connect to control
logic to select
swtich
configuration(i.e. CC
control logic)
Connect to
Type C SSTX/RX
pins
POL
AMSEL
EN
POL
AMSEL
EN
AC Coupling caps to
accomodate higher Vcm
on some USB devices
USB3_TX0N
USB3_TX0P
SSTXN
SSTXP
Connect to USB
CRX1N
CRX1P
CRX1P
CRX1N
Host/Hub SS TX/RX
pairs
USB3_RX0N
USB3_RX0P
C49 0.1uF
SSRXN
SSRXP
CTX1N
CTX1P
CTX1P
CTX1N
C48 0.1uF
C51 0.1uF
ML0P
ML0N
LNAN
LNAP
CTX2N
CTX2P
CTX2P
CTX2N
C50 0.1uF
ML1P
ML1N
LNBN
LNBP
CRX2N
CRX2P
CRX2P
CRX2N
ML0..ML3:
Connect to
DP Source
MainLink
lanes
ML2P
ML2N
LNCN
LNCP
ML3P
ML3N
LNDN
LNDP
Connect to
Type C SBU
pins
CSBU1
CSBU2
SBU1
SBU2
CSBU1
CSBU2
SBU1
SBU2
Connect to
DP Source
AUX
Channels
HD3SS460
NOTE: ALL DIFF PAIRS ARE
ROUTED 85 TO 90 OHMS
DIFFERENTIAL AND 50 OHMS
COMMON MODE. ALL OTHER
TRACES ARE 50 OHM.
Copyright © 2017, Texas Instruments Incorporated
Figure 16. Schematic Implementations for DP Source/ USB Host (3 of 3)
Copyright © 2015–2017, Texas Instruments Incorporated
21
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
VBUS
TypeC Connector and Pin Mapping
J2
A4
A9
B4
B9
VBUS1
VBUS2
VBUS3
VBUS4
GND
A1
A2
GND
B12
B11
B10
C8
10uF
ML3P
ML0P
SSTXP1
SSTXP2
SSRXP1
SSRXP2
ML2P
ML1P
A5
B5
CC1
CC2
CC1 pg3
CC2 pg3
CC1
CC2
ML3N
ML0N
SSTXN1
SSTXN2
A3
SSRXN1
SSRXN1
ML2N
ML1N
A8
B8
CSBU1
CSBU2
SBU1
SBU2
Note: It is
VBUS
CC1
A4
B9 VBUS
USB2_N0
USB2_P0
A7
A6
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
HD3SS460
device is off.
DN1
DP1
A5
B8 SBU2
B7 DN1
B6 DP1
B5 CC2
B4 VBUS
AUXP
AUXN
B6
B7
DP2
DN2
DP1
A6
A2
A3
CTX1P
CTX1N
SSTXP1
SSTXN1
DN1
A7
A11
A10
CRX2P
CRX2N
SSRXP2
SSRXN2
AUXN
AUXP
SBU1
VBUS
A8
B2
B3
CTX2P
CTX2N
SSTXP2
SSTXN2
A9
B11
B10
CRX1P
CRX1N
SSRXP1
Shield6 SSRXN1
Shield5
g6
g5
g4
g3
g2
g1
ML1N
ML2N
SSRXN2
SSRXN1
B3 SSTXN2
SSTXN1
ML0N
ML3N
A10
A11
A12
A1
A12
B1
Shield4
Shield3
Shield2
Shield1
GND0
GND1
GND2
GND3
ML1P
ML2P
SSRXP2
SSRXP1
B2 SSTXP2
SSTXP1
ML0P
ML3P
B12
USB_TypeC_Receptacle_
GND
B1 GND
CSBU1
CSBU2
pull-down
resistor
between 1M-2M
is
R156
2M
R158
2M
recommended
on SBU1 and
SBU2.
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (1 of 3)
ESD Components
Place in pass through manner with no stub
U8
CTX1N
CTX1P
1
2
3
4
5
10
9
8
7
6
D1+ NC10
D1- NC9
GND GND
CRX1N
CRX1P
D2+
D2-
NC7
NC6
TPD4E05U06
U9
CTX2P
CTX2N
1
2
3
4
5
10
9
8
7
6
D1+ NC10
D1- NC9
GND GND
CRX2P
CRX2N
D2+
D2-
NC7
NC6
TPD4E05U06
U12
1
2
3
4
5
6
7
14
13
12
11
10
9
CC1
CC2
USB2_P0
NC1
NC2
NC3
NC4
GND GND
NC5
NC6
D1+
D1-
D2+
D2-
USB2_N0
CSBU1
CSBU2
D3+
D3-
8
TPD6E05U06
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (2 of 3)
22
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (3 of 3)
10 Power Supply Recommendations
There is no power supply sequence required for HD3SS460. However it is recommended that EN is asserted low
after device supply VCC is stable and within specification. It is also recommended that ample decoupling
capacitors are placed at the device VCC near the pin.
Copyright © 2015–2017, Texas Instruments Incorporated
23
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
High performance layout practices are paramount for board layout for high speed signals to ensure good signal
integrity. Even minor imperfection can cause impedance mismatch resulting reflection. Special care is warranted
for traces, connections to device, and connectors.
11.1.1 Critical Routing
The high speed differential signals must be routed with great care to minimize signal quality degradation between
the connector and the source or sink of the high speed signals by following the guidelines provided in this
document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum
speed of 5.4 Gbps. These signals are to be routed first before other signals with highest priority.
•
Each differential pair should be routed together with controlled differential impedance of 85 to 90-Ω and 50-Ω
common mode impedance. Keep away from other high speed signals. The number of vias should be kept to
minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width. Route
all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer. No 90
degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the angle of
the bend should be greater than 135 degrees.
•
Length matching:
–
–
Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
The inter-pair matching of the differential pairs is not as critical as intra-pair matching. The SSTX and
SSRX pairs do not have to match while they need to be routed as short as possible.
•
•
•
Keep high speed differential pair traces adjacent to ground plane.
Do not route differential pairs over any plane split
ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path. In order to control impedance for transmission lines, a
solid ground plane should be placed next to the high- speed signal layer. This also provides an excellent low-
inductance path for the return current flow.
–
Placement recommendation would be: Connector – ESD Components --- HD3SS460
•
For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS460 pins can be
swapped as long as the corresponding pairs are swapped on the other end of the switch The example is
shown in the reference EVM schematics section of this document. The P/N can be swapped on USB 3.1
connection of the switch for ease of routing purposes.
11.1.2 General Routing/Placement Rules
•
Route all high-speed signals first on un-routed PCB: SSTXP/N, SSRXT/N, LNAP/N, LNB P/N, LNC P/N, LND
P/N, CTX*P/N. The stub on USB2 D+ and D- pairs should not exceed 3.5mm.
•
Follow 20H rule (H is the distance to reference plane) for separation of the high-speed trace from the edge of
the plane
•
•
Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines
All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
•
•
All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for high-
frequency return current path
•
•
Route differential traces over a continuous plane with no interruptions.
Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
•
Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keep-
out distance where possible.
24
Copyright © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
Layout Guidelines (continued)
•
Decoupling capacitors should be placed next to each power terminal on the HD3SS460. Care should be
taken to minimize the stub length of the trace connecting the capacitor to the power pin.
•
•
•
•
Avoid sharing vias between multiple decoupling capacitors.
Place vias as close as possible to the decoupling capacitor solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
The VBUS traces/planes must be wide enough to carry maximum of 2 A current.
11.2 Layout Example
Figure 20, Figure 21, and Figure 22 illustrate some guidelines for layout. Actual layout should be optimized for
various factors such as board geometry, connector type, and application.
Figure 20. USB Type C Connector to HD3SS460 Signal Routing
Figure 21. Dual SMT Mid-Mount Type C Connector Layout Example Zoom-in
Copyright © 2015–2017, Texas Instruments Incorporated
25
HD3SS460
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
www.ti.com.cn
Layout Example (continued)
Figure 22. Dual-row SMT Mid-mount Type C with ESD Components
26
版权 © 2015–2017, Texas Instruments Incorporated
HD3SS460
www.ti.com.cn
ZHCSDI9D –JANUARY 2015–REVISED JANUARY 2017
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请访问 www.ti.com.cn 您器件对应的产品文件夹。点击右上角的提醒我 (Alert me) 注册后，
即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB-IF, Inc..
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2017, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HD3SS460IRHRR
HD3SS460IRHRT
HD3SS460IRNHR
HD3SS460IRNHT
HD3SS460RHRR
HD3SS460RHRT
HD3SS460RNHR
HD3SS460RNHT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHR
RHR
RNH
RNH
RHR
RHR
RNH
RNH
28
28
30
30
28
28
30
30
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
3SS460I
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
3SS460I
460IRNH
460IRNH
3SS460
3SS460
460RNH
460RNH
0 to 70
0 to 70
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HD3SS460IRHRR
HD3SS460IRHRT
HD3SS460IRNHR
HD3SS460IRNHT
HD3SS460RHRR
HD3SS460RHRT
HD3SS460RNHR
HD3SS460RNHT
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHR
RHR
RNH
RNH
RHR
RHR
RNH
RNH
28
28
30
30
28
28
30
30
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.8
3.8
2.8
2.8
3.8
3.8
2.8
2.8
5.8
5.8
4.8
4.8
5.8
5.8
4.8
4.8
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
HD3SS460IRHRR
HD3SS460IRHRT
HD3SS460IRNHR
HD3SS460IRNHT
HD3SS460RHRR
HD3SS460RHRT
HD3SS460RNHR
HD3SS460RNHT
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHR
RHR
RNH
RNH
RHR
RHR
RNH
RNH
28
28
30
30
28
28
30
30
3000
250
346.0
210.0
367.0
210.0
346.0
210.0
367.0
210.0
346.0
185.0
367.0
185.0
346.0
185.0
367.0
185.0
33.0
35.0
35.0
35.0
33.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHR 28
3.5 x 5.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4210249/B
www.ti.com
PACKAGE OUTLINE
RHR0028A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
0.5
0.3
5.6
5.4
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
2±0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
11
14
24X 0.5
10
15
2X
4.5
4±0.1
SEE TERMINAL
DETAIL
1
24
0.3
28X
28
25
0.5
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A
B
28X
0.3
0.05
4219075/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
SYMM
28X (0.6)
28X (0.25)
25
28
1
24
24X (0.5)
(0.66)
(5.3)
TYP
SYMM
(4)
(
0.2) TYP
VIA
15
10
11
14
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219075/A 11/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.55) TYP
28
25
28X (0.6)
28X (0.25)
1
24
24X (0.5)
SYMM
(1.32)
TYP
(5.3)
METAL
TYP
6X (1.12)
15
10
14
11
6X (0.89)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219075/A 11/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RNH0030A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
4.6
4.4
(0.2)
30.000
DETAIL A
OPTIONAL SIDE WALL
SEE DETAIL A
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2X 1.6
1.2 0.05
(0.1) TYP
4X (0.2)
EXPOSED
THERMAL PAD
11
15
26X 0.4
10
16
2X
3.6
3.2 0.05
1
25
0.25
30X
30
26
0.15
PIN 1 ID
0.1
C A B
0.35
30X
0.05
0.25
4221819/B 10/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNH0030A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.2)
(0.7) TYP
26
30
30X (0.5)
1
25
30X (0.2)
26X (0.4)
(1.2)
SYMM
(4.4)
(3.2)
(
0.2) TYP
VIA
(R0.05) TYP
16
10
4X (0.2)
11
15
SYMM
(2.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221819/B 10/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNH0030A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.13)
SYMM
30
26
30X (0.5)
1
25
30X (0.2)
26X (0.4)
2X
(1.39)
SYMM
(4.4)
(0.8)
METAL
TYP
(R0.05) TYP
16
10
4X (0.2)
11
15
(2.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4221819/B 10/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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