HPA02287PHPR_技术文档

TAS5717

TAS5719

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier

Check for Samples: TAS5717, TAS5719

1

FEATURES

2

•

Audio Input/Output

•

Benefits

–

TAS5717 Supports 2×10 W and TAS5719

Supports 2×15 W Output

–

EQ: Speaker Equalization Improves Audio

Performance

–

Wide PVDD Range, From 4.5 V to 26 V

–

DRC: Dynamic Range Compression. Can

Be Used As Power Limiter. Enables

Speaker Protection, Easy Listening,

Night-Mode Listening

Efficient Class-D Operation Eliminates

Need for Heatsinks

–

Requires Only 3.3 V and PVDD

–

DirectPath Technology: Eliminates Bulky

DC Blocking Capacitors

One Serial Audio Input (Two Audio

Channels)

I²C Address Selection via PIN (Chip Select)

Stereo Headphone/Stereo Line Drivers:

Adjust Gain via External Resistors,

Dedicated Active Headpone Mute Pin, High

Signal-to-Noise Ratio

–

Supports 8-kHz to 48-kHz Sample Rate

(LJ/RJ/I²S)

–

External Headphone-Amplifier Shutdown

Signal

–

Two-Band DRC: Set Two Different

Thresholds for Low- and High-Frequency

Content

–

Integrated CAP-Free Headphone Amplifier

Stereo Headphone (Stereo 2-V RMS Line

Driver) Outputs

DESCRIPTION

•

Audio/PWM Processing

The TAS5717/TAS5719 is a 10-W/15-W, efficient,

digital audio-power amplifier for driving stereo

bridge-tied speakers. One serial data input allows

processing of up to two discrete audio channels and

seamless integration to most digital audio processors

and MPEG decoders. The device accepts a wide

–

Independent Channel Volume Controls With

24-dB to Mute

–

Programmable Two-Band Dynamic Range

Control

–

14 Programmable Biquads for Speaker EQ

Programmable Coefficients for DRC Filters

DC Blocking Filters

range of input data and data rates.

programmable data path routes these channels to the

internal speaker drivers.

A fully

The TAS5717/9 is a slave-only device receiving all

clocks from external sources. The TAS5717/TAS5719

operates with a PWM carrier between a 384-kHz

0.125-dB Fine Volume Support

•

General Features

–

Serial Control Interface Operational Without

MCLK

switching rate and

a 352-KHz switching rate,

depending on the input sample rate. Oversampling

combined with a fourth-order noise shaper provides a

flat noise floor and excellent dynamic range from

20 Hz to 20 kHz.

Factory-Trimmed Internal Oscillator for

Automatic Rate Detection

Surface Mount, 48-Pin, 7-mm × 7-mm

HTQFP Package

–

AD, BD, and Ternary PWM-Mode Support

Thermal and Short-Circuit Protection

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

FilterPro is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TAS5717

TAS5719

SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

SIMPLIFIED APPLICATION DIAGRAM

3.3 V

4.5 V–26 V

PVDD

AVDD/DVDD/

HP_VDD

OUT_A

LRCLK

SCLK

MCLK

SDIN

Digital

Audio

Source

BST_A

BST_B

LC_BTL

OUT_B

OUT_C

I²C

Control

SDA

SCL

BST_C

BST_D

LC_BTL

RESET

PDN

Control

Inputs

OUT_D

PLL_FLTP

PLL_FLTM

Loop

Filter⁽¹⁾

HPL_OUT

HPR_OUT

HPL_IN

Headphone IN

(Single-Ended)

HPL_OUT

HP_SD

B0264-13

⁽¹⁾See the TAS5717/9 User's Guide for loop-filter values.

2

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

FUNCTIONAL VIEW

OUT_A

2´ HB

FET Out

4^th

Order

Noise

R

Serial

Audio

Port

OUT_B

SDIN

S

Digital Audio Processor

(DAP)

Shaper

and

PWM

C

OUT_C

OUT_D

2´ HB

FET Out

Protection

Logic

Click and Pop

Control

MCLK

SCLK

Sample Rate

Autodetect

and PLL

LRCLK

Microcontroller

Based

System

SDA

SCL

Serial

Control

Terminal Control

HPL_IN

HPR_IN

HPL_OUT

HPR_OUT

Charge Pump

Headphone Amp/Line Driver

B0262-08

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DAP PROCESS STRUCTURE

4

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

PIN ASSIGNMENT AND DESCRIPTIONS

PHP Package

(Top View)

48 47 46 45 44 43 42 41 40 39 38 37

HPL_IN

HPL_OUT

HPR_OUT

HPR_IN

BST_D

PVDD_CD

GVDD_OUT

HP_SD

SSTIMER

VREG

1

36

35

34

33

32

31

30

29

28

27

26

25

2

3

4

HPVSS

CPN

5

6

TAS5717

(TAS5719)

CPP

7

AGND

HPVDD

AVSS

8

GND

9

DVSS

PLL_FLTM

10

11

12

DVDD

PLL_FLTP

VR_ANA

STEST

RESET

13 14 15 16 17 18 19 20 21 22 23 24

P0075-11

PIN FUNCTIONS

NAME

AGND

5-V

TOLERANT

TYPE⁽¹⁾

TERMINATION⁽²⁾

DESCRIPTION

NO.

30

P

Analog ground for power stage

A_SEL

14

DIO

This pin is monitored on the rising edge of RESET. A value of 0

makes the I²C dev address 0x54, and a value of 1 makes it 0x56.

AVDD

AVSS

BST_A

BST_B

BST_C

BST_D

CPN

13

9

P

3.3-V analog power supply

Analog 3.3-V supply ground

45

41

40

36

6

P

High-side bootstrap supply for half-bridge A

High-side bootstrap supply for half-bridge B

High-side bootstrap supply for half-bridge C

High-side bootstrap supply for half-bridge D

Charge-pump flying-capacitor negative connection

Charge-pump flying-capacitor positive connection

3.3-V digital power supply

P

IO

P

CPP

7

DVDD

DVSS

DVSSO

GND

27

28

17

29

P

Digital ground

P

Oscillator ground

P

Analog ground for power stage

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic

levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).

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PIN FUNCTIONS (continued)

NAME

5-V

TOLERANT

TYPE⁽¹⁾

TERMINATION⁽²⁾

DESCRIPTION

NO.

34

1

GVDD_OUT

HPL_IN

HPL_OUT

HP_PWML

HP_PWMR

HPR_IN

HPR_OUT

HP_SD

P

AI

AO

DO

AI

AO

AI

P

Gate drive internal regulator output

Headphone left IN (single-ended, analog IN)

Headphone left OUT (single-ended, analog OUT)

PWM left-channel headphone out

PWM right-channel headphone out

Headphone right IN (single-ended, analog IN)

Headphone right OUT (single-ended, analog OUT)

Headphone shutdown (active-low)

Headphone supply

2

48

47

4

3

33

8

HPVDD

HPVSS

5

P

Headphone ground

LRCLK

20

15

16

44

42

39

37

19

DI

AO

O

5-V

Pulldown

Input serial audio data left/right clock (sample rate clock)

Master clock input

MCLK

OSC_RES

OUT_A

Oscillator trim resistor. Connect an 18-kΩ 1% resistor to DVSSO.

Output, half-bridge A

OUT_B

O

Output, half-bridge B

OUT_C

O

Output, half-bridge C

OUT_D

O

Output, half-bridge D

PDN

DI

5-V

Pullup

Power down, active-low. PDN prepares the device for loss of power

supplies by shutting down the noise shaper and initiating the PWM

stop sequence.

PGND_AB

PGND_CD

PLL_FLTM

PLL_FLTP

PVDD_AB

PVDD_CD

RESET

43

38

10

11

46

35

25

P

Power ground for half-bridges A and B

Power ground for half-bridges C and D

PLL negative loop-filter terminal

AO

P

PLL positive loop-filter terminal

Power-supply input for half-bridge output A

Power-supply input for half-bridge output C

P

DI

5-V

Pullup

Reset, active-low. A system reset is generated by applying a logic low

to this pin. RESET is an asynchronous control signal that restores the

DAP to its default conditions, and places the PWM in the hard-mute

(high-impedance) state.

SCL

24

21

DI

5-V

I²C serial control clock input

SCLK

Pulldown

Serial audio data clock (shift clock). SCLK is the serial audio port input

data bit clock.

I²C serial control data interface input/output

SDA

23

22

DIO

DI

5-V

SDIN

Serial audio data input. SDIN supports three discrete (stereo) data

formats.

SSTIMER

32

AI

Controls ramp time of OUT_X to minimize pop. Leave this pin floating

for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The

capacitor determines the ramp time.

STEST

26

12

DI

P

Factory test pin. Connect directly to DVSS.

VR_ANA

Internally regulated 1.8-V analog supply voltage. This pin must not be

used to power external devices.

VR_DIG

VREG

18

31

P

Internally regulated 1.8-V digital supply voltage. This pin must not be

used to power external devices.

Digital regulator output. Not to be used for powering external circuitry.

6

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.3 to 3.6

–0.3 to 30

–0.3 to 4.2

–0.5 to DVDD + 0.5

–0.5 to DVDD + 2.5⁽³⁾

–0.5 to AVDD + 2.5⁽³⁾

22⁽⁴⁾

UNIT

V

DVDD, AVDD, HPVDD

Supply voltage

PVDD_X

V

HPL_IN, HPR_IN

V

3.3-V digital input

Input voltage

V

5-V tolerant⁽²⁾digital input (except MCLK)

V

5-V tolerant MCLK input

OUT_x to PGND_x

V

BST_x to PGND_x

32⁽⁴⁾

V

Input clamp current, I_IK

±20

mA

°C

Output clamp current, I_OK

±20

Operating free-air temperature

Operating junction temperature range

Storage temperature range, T_stg

0 to 85

0 to 150

–40 to 125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.

(3) Maximum pin voltage should not exceed 6 V.

(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

THERMAL INFORMATION

TAS5717

THERMAL METRIC⁽¹⁾

PHP

48 PINS

35.2

UNIT

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

Junction-to-case (bottom) thermal resistance⁽⁴⁾

Junction-to-case (top) thermal resistance⁽⁵⁾

Junction-to-top characterization parameter⁽⁶⁾

Junction-to-board characterization parameter⁽⁷⁾

°C/W

θ_JB

10.9

θ_JC(bottom)

θ_JC(top)

ψ_JT

1.6

19.7

3.4

ψ_JB

10.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(6) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

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RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX

UNIT

V

Digital/analog supply voltage

Half-bridge supply voltage

High-level input voltage

DVDD, AVDD

3

4.5

2

3.3

3.6

PVDD_X

V

V_IH

V_IL

T_A

5-V tolerant

V

Low-level input voltage

0.8

85

V

Operating ambient temperature range

Operating junction temperature range

Load impedance

0

°C

Ω

(1)

T_J

125

R_L(BTL)

Output filter: L = 15 μH, C = 680 nF

4

8

Minimum output inductance under

short-circuit condition

4.7

L_O(BTL)

Output-filter inductance

μH

(1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

RECOMMENDED OPERATING CONDITIONS FOR HEADPHONE/LINE DRIVER

MIN NOM

MAX

UNIT

Digital/analog supply voltage

HPVDD

3

3.3

3.6

V

Headphone-mode load imedance

(HPL/HPR)

16

R_hp_L

R_ln_L

32

Ω

Line-diver-mode load impedance

(HPL/HPR)

0.6

10

kΩ

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER

TEST CONDITIONS

11.025/22.05/44.1-kHz data rate ±2%

48/24/12/8/16/32-kHz data rate ±2%

VALUE

352.8

384

UNIT

kHz

Output sample rate

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER

TEST CONDITIONS

MIN

2.8224

40%

TYP

MAX

24.576

60%

UNIT

f_MCLKI

MCLK Frequency

MHz

MCLK duty cycle

50%

tr /

tf_(MCLK)

Rise/fall time for MCLK

5

4

ns

LRCLK allowable drift before LRCLK reset

External PLL filter capacitor C1

External PLL filter capacitor C2

External PLL filter resistor R

MCLKs

nF

SMD 0603 Y5V

47

4.7

SMD 0603 Y5V

nF

SMD 0603, metal film

470

Ω

Fcp

Charge Pump Switching Frequency

500

700

KHz

8

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

ELECTRICAL CHARACTERISTICS

DC Characteristics

TA = 25°, PVCC_X = 13 V, DVDD = AVDD = 3.3 V, R_L= 8 Ω, BTL AD Mode, f_S= 48 KHz (unless otherwise noted)

PARAMETER

High-level output voltage

TEST CONDITIONS

MIN TYP

MAX

UNIT

V_OH

V_OL

FAULTZ and SDA

I_OH= –4 mA

DVDD = 3 V

2.4

V

Low-level output voltage

I_OL= 4 mA

DVDD = 3 V

0.5

75

V

V_I< V_IL; DVDD = AVDD

= 3.6V

I_IL

Low-level input current

High-level input current

μA

V_I> V_IH; DVDD =

AVDD = 3.6V

I_IH

Normal mode

48

21

70

32

3.3 V supply voltage (DVDD,

AVDD)

I_DD

3.3 V supply current

mA

mΩ

Reset (RESET = low,

PDN = high)

Normal mode

20

5

34

13

I_PVDD

Half-bridge supply current

No load (PVDD_X)

Reset (RESET = low,

PDN = high)

Drain-to-source resistance, LS T_J= 25°C, includes metallization resistance

200

(1)

r_DS(on)

Drain-to-source resistance,

HS

T_J= 25°C, includes metallization resistance

I/O Protection

V_uvp

Undervoltage protection limit

PVDD falling

PVDD rising

3.5

4.5

V

V_uvp,hyst

OTE⁽²⁾

Undervoltage protection limit

Overtemperature error

150

°C

Extra temperature drop

required to recover from error

(2)

OTE_HYST

30

°C

I_OC

Overcurrent limit protection

Overcurrent response time

Internal pulldown resistor at

4.5

A

I_OCT

150

ns

Connected when drivers are tristated to provide bootstrap

R_PD

3

kΩ

the output of each half-bridge capacitor charge.

(1) This does not include bond-wire or pin resistance.

(2) Specified by design

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AC Characteristics (BTL)

PVDD_X = 12 V, BTL AD mode, f_S= 48 KHz, R_L= 8 Ω, audio frequency = 1 kHz, (unless otherwise noted). All performance

is in accordance with recommended operating conditions, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

10

MAX UNIT

PVDD = 13 V, 10% THD, 1-kHz input

signal

P_O

Power output per channel

PVDD = 8 V, 10% THD, 1-kHz input signal

4.1

W

PVDD = 18 V, 10% THD, 1-kHz input

signal

15⁽¹⁾

PVDD = 13 V; P_O= 1 W

PVDD = 8 V; P_O= 1 W

0.13%

0.2%

56

THD+N

V_n

Total harmonic distortion + noise

Output integrated noise (rms)

Crosstalk

A-weighted

μV

P_O= 0.25 W, f = 1 kHz (BD mode)

P_O= 0.25 W, f = 1 kHz (AD mode)

–82

dB

–69

A-weighted, f = 1 kHz, maximum power at

THD < 1%

(2)

SNR

Signal-to-noise ratio

–105

dB

(1) 15 W is supported only in the TAS5719.

(2) SNR is calculated relative to 0-dBFS input level.

AC Characteristics (Headphone/Line Driver)

PVDD_X = 12 V, BTL AD mode, f_S= 48 KHz, R_L= 8 Ω, audio frequency = 1 kHz, (unless otherwise noted). All performance

is in accordance with recommended operating conditions, unless otherwise specified.

PARAMETER

TEST CONDITIONS

HP_VDD = 3.3 V (Rhp = 32 Ω; THD 1%)

Adjustable via Rin and Rfb

Rhp = 32 Ω

MIN

TYP

MAX UNIT

Po(hp)

Headphone power output per channel

25

mW

HP_gain Headphone gain

SNR_hp Sgnal-to-noise ratio (headphone mode)

101

105

dB

SNR_ln

Sgnal-to-noise ratio (line driver mode)

2-V rms output

10

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

f_SCLKIN

t_su1

Frequency, SCLK 32 × f_S, 48 × f_S, 64 × f_S

Setup time, LRCLK to SCLK rising edge

Hold time, LRCLK from SCLK rising edge

Setup time, SDIN to SCLK rising edge

Hold time, SDIN from SCLK rising edge

LRCLK frequency

C_L= 30 pF

1.024

10

12.288

MHz

ns

t_h1

10

ns

t_su2

10

ns

t_h2

10

ns

8

48

50%

48

60%

kHz

SCLK duty cycle

40%

LRCLK duty cycle

SCLK

edges

SCLK rising edges between LRCLK rising edges

LRCLK clock edge with respect to the falling edge of SCLK

Rise/fall time for SCLK/LRCLK

32

64

1/4

8

t_(edge)

SCLK

period

–1/4

t_r/

ns

t_{f(SCLK/LRCLK)}

t_r

t_f

SCLK

(Input)

t_(edge)

t_h1

t_su1

LRCLK

(Input)

t_h2

t_su2

SDIN

T0026-04

Figure 1. Slave Mode Serial Data Interface Timing

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I²C SERIAL CONTROL PORT OPERATION

Timing characteristics for I²C Interface signals over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

No wait states

MIN

MAX

UNIT

kHz

μs

f_SCL

t_w(H)

t_w(L)

t_r

Frequency, SCL

400

Pulse duration, SCL high

0.6

1.3

Pulse duration, SCL low

μs

Rise time, SCL and SDA

300

ns

t_f

Fall time, SCL and SDA

ns

t_su1

t_h1

Setup time, SDA to SCL

100

0

ns

Hold time, SCL to SDA

ns

t_(buf)

t_su2

t_h2

Bus free time between stop and start condition

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

Load capacitance for each bus line

1.3

0.6

μs

t_su3

C_L

μs

400

pF

t_w(H)

t_w(L)

t_r

t_f

SCL

t_su1

t_h1

SDA

T0027-01

Figure 2. SCL and SDA Timing

SCL

t_(buf)

t_h2

t_su2

t_su3

SDA

Start

Condition

Stop

Condition

T0028-01

Figure 3. Start and Stop Conditions Timing

12

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

RESET TIMING (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended

Use Model section on usage of all terminals.

PARAMETER

Pulse duration, RESET active

Time to enable I²C

MIN

TYP

MAX

UNIT

μs

t_w(RESET)

100

t_{d(I2C_ready)}

12

ms

RESET

t_w(RESET)

I²C Active

t_{d(I2C_ready)}

System Initialization.

Enable via I²C.

T0421-01

NOTES: 1. On power up, it is recommended that the TAS5717/9 RESET be held LOW for at least 100 μs after DVDD has

reached 3 V.

2. If RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs

after PDN is deasserted (HIGH).

Figure 4. Reset Timing

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω

SPACER

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

10

1

10

1

PV_DD= 8V

R_L= 8Ω

T_A= 25°C

PV_DD= 12V

R_L= 8Ω

T_A= 25°C

0.1

0.01

0.001

0.01

0.001

P_O= 1W

P_O= 2.5W

P_O= 5W

P_O= 1W

P_O= 2.5W

P_O= 5W

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

Figure 5.

Figure 6.

SPACER

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

10

1

10

1

PV_DD= 18V

R_L= 8Ω

T_A= 25°C

PV_DD= 24V

R_L= 8Ω

T_A= 25°C

0.1

0.01

0.001

0.01

0.001

P_O= 1W

P_O= 2.5W

P_O= 5W

P_O= 1W

P_O= 2.5W

P_O= 5W

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

Figure 7.

Figure 8.

14

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued)

SPACER

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

10

1

10

1

PV_DD= 8V

R_L= 8Ω

T_A= 25°C

PV_DD= 12V

R_L= 8Ω

T_A= 25°C

0.1

0.01

f = 20Hz

f = 1kHz

f = 20Hz

f = 1kHz

0.001

0.01

0.1

1

10 40

0.01

0.1

1

10 40

Output Power (W)

Figure 9.

Figure 10.

SPACER

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

10

1

10

1

PV_DD= 18V

R_L= 8Ω

T_A= 25°C

PV_DD= 24V

R_L= 8Ω

T_A= 25°C

0.1

0.01

f = 20Hz

f = 1kHz

f = 10kHz

f = 20Hz

f = 1kHz

0.001

0.01

0.1

1

10 40

0.01

0.1

1

10 40

Output Power (W)

Figure 11.

Figure 12.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued)

SPACER

TAS5717

OUTPUT POWER

vs

EFFICIENCY

vs

SUPPLY VOLTAGE

OUTPUT POWER

40

35

30

25

20

15

10

5

100

90

80

70

60

50

40

30

20

10

0

R_L= 8ꢀ

T_A= 25°C

PV_DD= 8V

PV_DD= 12V

PV_DD= 18V

PV_DD= 24V

R_L= 8ꢀ

T_A= 25°C

THD+N = 1%

THD+N = 10%

0

8

10

12

14

16

18

20

22

24

26

0

5

10

15

20

25

30

35

Supply Voltage (V)

Total Output Power (W)

NOTE: Dashed lines represent thermally limited region.

Figure 13.

Figure 14.

SPACER

TAS5719

OUTPUT POWER

EFFICIENCY

vs

SUPPLY VOLTAGE

OUTPUT POWER

40

100

90

80

70

60

50

40

30

R_L= 8ꢀ

T_A= 25°C

35

30

25

20

15

10

5

20

10

0

PV_DD= 8V

PV_DD= 12V

PV_DD= 18V

PV_DD= 24V

R_L= 8ꢀ

T_A= 25°C

THD+N = 1%

THD+N = 10%

0

8

10

12

14

16

18

20

22

24

26

0

5

10

15

20

25

30

35

Supply Voltage (V)

Total Output Power (W)

NOTE: Dashed lines represent thermally limited region.

Figure 15.

Figure 16.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued)

SPACER

CROSSTALK

vs

CROSSTALK

vs

FREQUENCY

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

P_O= 1W

PV_DD= 8V

R_L= 8Ω

P_O= 1W

PV_DD= 12V

R_L= 8Ω

Right to Left

Left to Right

Right to Left

Left to Right

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

T_A= 25°C

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

Figure 17.

Figure 18.

SPACER

CROSSTALK

vs

SPACER

CROSSTALK

vs

FREQUENCY

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

0

−10

P_O= 1W

PV_DD= 18V

R_L= 8Ω

P_O= 1W

PV_DD= 24V

R_L= 8Ω

Right to Left

Left to Right

Right to Left

Left to Right

−20

T_A= 25°C

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

Figure 19.

Figure 20.

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TYPICAL CHARACTERISTICS, HEADPHONE TESTS, SE CONFIGURATION, 32Ω

SPACER

ANALOG IN

PWM IN

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

10

1

10

1

HPV_DD= 3.3V

R_L= 32Ω

T_A= 25°C

HPV_DD= 3.3V

R_L= 32Ω

T_A= 25°C

0.1

0.01

0.001

0.01

0.001

P_O= 10mW

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

Figure 21.

Figure 22.

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TYPICAL CHARACTERISTICS, LINE DRIVER TESTS, SE CONFIGURATION, 5kΩ

SPACER

ANALOG IN

TOTAL HARMONIC DISTORTION + NOISE

PWM IN

TOTAL HARMONIC DISTORTION + NOISE

vs

FREQUENCY

OUTPUT VOLTAGE

10

1

10

1

HPV_DD= 3.3V

R_L= 5kΩ

T_A= 25°C

PV_DD=3.3V

R_L= 5kΩ

T_A= 25°C

0.1

0.01

0.001

0.01

V_O= 1Vrms

f = 1kHz

0.001

20

100

1k

10k 20k

10m

100m

1

4

Frequency (Hz)

Output Voltage (V)

Figure 23.

Figure 24.

SPACER

ANALOG IN

CROSSTALK

vs

FREQUENCY

0

V_O= 1Vrms

PV_DD= 3.3V

R_L= 5kΩ

Right to Left

Left to Right

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

T_A= 25°C

20

100

1k

10k 20k

Frequency (Hz)

Figure 25.

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DETAILED DESCRIPTION

POWER SUPPLY

To facilitate system design, the TAS5717/9 needs only a 3.3-V supply in addition to the (typical) 13-V

power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry.

Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by

built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is

designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins

(BST_X) and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are

derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to

their associated pins as possible. In general, inductance between the power-supply pins and decoupling

capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the

bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM

switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,

size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even

during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the

remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is

decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.

The TAS5717/9 is fully protected against erroneous power-stage turnon due to parasitic gate charging.

I²C CHIP SELECT/HP_SHUTDOWN

A_SEL/HP_SD is an input pin during power up. It can be pulled high or low. HIGH indicates an I²C subaddress

of 0x56, and LOW a subaddress of 0x54.

DEVICE PROTECTION SYSTEM

Overcurrent (OC) Protection With Current Limiting

The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The

detector outputs are closely monitored a protection system. If the high-current condition situation persists, i.e.,

the power stage is being overloaded, a protection system triggers a latching shutdown, resulting in the power

stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault

condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not

independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent

fault, half-bridges A, B, C, and D are shut down.

Overtemperature Protection

The TAS5717/9 has an overtemperature-protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the

high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5717/9 recovers automatically once the

temperature drops approximately 30°.

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Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5717/9 fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the PVDD and AVDD supply voltages reach 4.5 V and 2.7 V, respectively. Although PVDD

and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or on either

PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT

being asserted low.

CLOCK, AUTO DETECTION, AND PLL

The TAS5717/9 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register

.

The TAS5717/9 checks to verify that SCLK is a specific value of 32 f_S, 48 f_S, or 64 f_S. The DAP only supports a 1

× f_SLRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock-control logic to the appropriate settings for all supported clock

rates as defined in the clock control register.

TAS5717/9 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)

and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system autodetects the new rate and reverts to normal operation. During this process, the default volume is

restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly

(also called soft unmute) as defined in volume register (0x0E).

SERIAL DATA INTERFACE

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5717/9 DAP accepts serial data

in 16-, 20-, or 24-bit left-justified, right-justified, or I²S serial data format.

PWM Section

The TAS5717/9 DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve

high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise

shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from

the DAP and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1- and 48-kHz are included and can be

enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For detailed description of using audio processing features like DRC and EQ, see the User's Guide and

TAS570X GDE software development tool documentation. Also see the GDE software development tool for the

device data path.

I²C COMPATIBLE SERIAL CONTROL INTERFACE

The TAS5717/9 DAP has an I²C serial control slave interface to receive commands from a system controller. The

serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait

states. As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single-byte and multiple-byte read and write operations for status

registers and the general control registers associated with the PWM.

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SERIAL INTERFACE CONTROL AND TIMING

I²S Timing

I²S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × f_Sis used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit

clock. The DAP masks unused trailing data-bit positions.

2-Channel I²S (Philips Format) Stereo Input

32 Clks

LRCLK (Note Reversed Phase)

Right Channel

Left Channel

SCLK

MSB

LSB

MSB

LSB

24-Bit Mode

23 22

9

5

1

8

4

0

5

1

4

1

0

23 22

19 18

15 14

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18

0

16-Bit Mode

15 14

T0034-01

NOTE: All data presented in 2s-complement form with MSB first.

Figure 26. I²S 64-f_SFormat

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2-Channel I²S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB

1

MSB

LSB

24-Bit Mode

23 22

17 16

13 12

9

5

1

8

4

0

5

1

4

0

3

2

0

23 22

19 18

15 14

17 16

13 12

9

5

1

8

4

0

5

1

4

0

3

2

1

20-Bit Mode

19 18

16-Bit Mode

15 14

9

8

9

8

T0092-01

NOTE: All data presented in 2s-complement form with MSB first.

Figure 27. I²S 48-f_SFormat

2-Channel I²S (Philips Format) Stereo Input

16 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB

1

MSB

LSB

16-Bit Mode

15 14 13 12 11 10

9

8

5

4

3

2

0

15 14 13 12 11 10

9

8

5

4

3

2

1

T0266-01

NOTE: All data presented in 2s-complement form with MSB first.

Figure 28. I²S 32-f_SFormat

Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it

is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,

48, or 64 × f_Sis used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK

toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused

trailing data-bit positions.

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2-Channel Left-Justified Stereo Input

32 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

23 22

LSB

24-Bit Mode

23 22

9

5

1

8

4

0

5

1

4

0

1

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18

15 14

16-Bit Mode

15 14

T0034-02

NOTE: All data presented in 2s-complement form with MSB first.

Figure 29. Left-Justified 64-f_SFormat

2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)

24 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22 21

17 16

13 12

9

5

1

8

4

0

5

1

4

0

1

23 22 21

17 16

13 12

9

5

1

8

4

0

5

1

4

0

1

0

20-Bit Mode

19 18 17

16-Bit Mode

15 14 13

9

8

15 14 13

9

8

T0092-02

NOTE: All data presented in 2s-complement form with MSB first.

Figure 30. Left-Justified 48-f_SFormat

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2-Channel Left-Justified Stereo Input

16 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

16-Bit Mode

15 14 13 12 11 10

9

8

5

4

3

2

1

0

15 14 13 12 11 10

9

8

5

4

3

2

1

0

T0266-02

NOTE: All data presented in 2s-complement form with MSB first.

Figure 31. Left-Justified 32-f_SFormat

Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when

it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at

32, 48, or 64 × f_Sis used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for

24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before

LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks

unused leading data-bit positions.

2-Channel Right-Justified (Sony Format) Stereo Input

32 Clks

LRCLK

SCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

0

24-Bit Mode

23 22

19 18

15 14

1

0

23 22

19 18

15 14

1

20-Bit Mode

16-Bit Mode

0

T0034-03

Figure 32. Right-Justified 64-f_SFormat

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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)

24 Clks

LRCLK

Right Channel

Left Channel

SCLK

MSB

LSB MSB

LSB

24-Bit Mode

23 22

19 18

15 14

6

5

2

1

0

23 22

19 18

15 14

6

5

2

1

0

20-Bit Mode

16-Bit Mode

0

T0092-03

Figure 33. Right-Justified 48-f_SFormat

Figure 34. Right-Justified 32-f_SFormat

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I²C SERIAL CONTROL INTERFACE

The TAS5717/9 DAP has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and

supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-yte write and read operations.

This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The

control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation

(400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.

General I²C Operation

The I²C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 35. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5717/9 holds SDA low during the acknowledge

clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the

sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible

devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor

must be used for the SDA and SCL signals to set the high level for the bus.

8-Bit Register Data For

Address (N)

8-Bit Register Data For

Address (N)

R/

W

8-Bit Register Address (N)

7-Bit Slave Address

A

SDA

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SCL

Start

Stop

T0035-01

Figure 35. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 35.

The 7-bit address for TAS5717/9 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for

0x54 and pullup for 0x56).Stero device with Headphone should use 0x54 as its device address.

Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only

multiple-byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress

assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes

that are required for each specific subaddress. For example, if a write command is received for a biquad

subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been

received when a stop command (or another start command) is received, the data received is discarded.

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Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The

TAS5717/9 also supports sequential I²C addressing. For write transactions, if a subaddress is issued followed by

data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has taken place,

and the data for all 16 subaddresses is successfully received by the TAS5717/9. For I²C sequential write

transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,

before a stop or start is transmitted, determines how many subaddresses are written. As was true for random

addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data

is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is

accepted; only the incomplete data is discarded.

Single-Byte Write

As shown in Figure 36, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a data-write transfer, the read/write bit is 0. After receiving the correct I²C device address

and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or

bytes corresponding to the TAS5717/9 internal memory address being accessed. After receiving the address

byte, the TAS5717/9 again responds with an acknowledge bit. Next, the master device transmits the data byte to

be written to the memory address being accessed. After receiving the data byte, the TAS5717/9 again responds

with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte

data-write transfer.

Start

Condition

Acknowledge

R/W

A6 A5 A4 A3 A2 A1 A0

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

Data Byte

Stop

Condition

T0036-01

Figure 36. Single-Byte Write Transfer

Multiple-Byte Write

A multiple-byte data-write transfer is identical to a single-byte data write transfer except that multiple data bytes

are transmitted by the master device to the DAP as shown in Figure 37. After receiving each data byte, the

TAS5717/9 responds with an acknowledge bit.

Start

Condition

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4 A3

A1 A0 ACK D7

I²C Device Address and

Read/Write Bit

Subaddress

First Data Byte

Last Data Byte

Stop

Condition

Other Data Bytes

T0036-02

Figure 37. Multiple-Byte Write Transfer

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Single-Byte Read

As shown in Figure 38, a single-byte data-read transfer begins with the master device transmitting a start

condition followed by the I²C device address and the read/write bit. For the data-read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal

memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5717/9 address

and the read/write bit, TAS5717/9 responds with an acknowledge bit. In addition, after sending the internal

memory address byte or bytes, the master device transmits another start condition followed by the TAS5717/9

address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After

receiving the address and the read/write bit, the TAS5717/9 again responds with an acknowledge bit. Next, the

TAS5717/9 transmits the data byte from the memory address being read. After receiving the data byte, the

master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read

transfer.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

A0 ACK

Acknowledge

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4

A6 A5

A1 A0 R/W ACK D7 D6

D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and

Read/Write Bit

Data Byte

Stop

Condition

T0036-03

Figure 38. Single-Byte Read Transfer

Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes

are transmitted by the TAS5717/9 to the master device as shown in Figure 39. Except for the last data byte, the

master device responds with an acknowledge bit after receiving each data byte.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

D0 ACK D7

A6

A0 R/W ACK A7 A6 A5

A0 ACK

A6

A0 R/W ACK D7

D0 ACK D7

D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and First Data Byte

Read/Write Bit

Other Data Bytes

Last Data Byte

Stop

Condition

T0036-04

Figure 39. Multiple-Byte Read Transfer

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Dynamic Range Control (DRC)

The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the

high-band left/right channels and one DRC for the low-band left/right channels.

The DRC input/output diagram is shown in Figure 40.

See the GDE software tool for more description on the T, K, and O parameters.

K

1:1 Transfer Function

Implemented Transfer Function

T

Input Level (dB)

M0091-03

Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.

• Each DRC has adjustable threshold levels.

• Programmable energy, attack, and decay time constants

• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,

and decay times can be set slow enough to avoid pumping.

Figure 40. Dynamic Range Control

Attack

and

Decay

Filters

Energy

Filter

Threshold

Detect

Audio Input

DRC Coefficient

a, w

T

a_a, w_a/ a_d, w_d

0x3C

DRC1

DRC2

0x3B

0x3E

0x40

0x43

0x3F

Alpha Filter Structure

S

a

Z^–1

w

B0265-04

T = 9.23 format, all other DRC coefficients are 3.23 format

Figure 41. DRC Structure

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PWM LEVEL METER

The structure in Figure 42 shows the PWM level meter that can be used to study the power profile.

Post-DAP Processing

1 – a

Z^–1

32-Bit Level

rms

a

Ch1

Ch2

ABS

ADDR = 0x6B

I²C Registers

(PWM Level Meter)

1 – a

Z^–1

32-Bit Level

rms

ADDR = 0x6C

B0396-01

Figure 42. PWM Level Meter Structure

26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23

numbers means that there are 3 bits to the left of the binary point and 23 bits to the right of the binary point. This

is shown in Figure 43 .

2^–23Bit

2^–5Bit

2^–1Bit

2⁰Bit

2¹Bit

Sign Bit

S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx

M0125-01

Figure 43. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 43. If the

most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct

number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must

be inverted, a 1 added to the result, and then the weighting shown in Figure 44 applied to obtain the magnitude

of the negative number.

2¹Bit

2⁰Bit

2^–1Bit

2^–4Bit

2^–23Bit

(1 or 0) ´ 2¹+ (1 or 0) ´ 2⁰+ (1 or 0) ´ 2^–1+ ....... (1 or 0) ´ 2^–4+ ....... (1 or 0) ´ 2^–23

M0126-01

Figure 44. Conversion Weighting Factors—3.23 Format to Floating Point

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Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit

number (4-byte or 8-digit hexadecimal number) is shown in Figure 45

Fraction

Digit 6

Sign

Bit

Fraction

Digit 1

Fraction

Digit 2

Fraction

Digit 3

Fraction

Digit 4

Fraction

Digit 5

Integer

Digit 1

u

x

x.

x

x x x x

0

S

Coefficient

Digit 8

Coefficient

Digit 7

Coefficient

Digit 6

Coefficient

Digit 5

Coefficient

Digit 4

Coefficient

Digit 3

Coefficient

Digit 2

Coefficient

Digit 1

u = unused or don’t care bits

Digit = hexadecimal digit

M0127-01

Figure 45. Alignment of 3.23 Coefficient in 32-Bit I²C Word

Table 1. Sample Calculation for 3.23 Format

db

0

Linear

1

Decimal

8,388,608

14,917,288

4,717,260

Hex (3.23 Format)

80 0000

5

1.77

00E3 9EA8

–5

X

0.56

L = 10^(X/20)

0047 FACC

D = 8388608 × L H = dec2hex (D, 8)

Table 2. Sample Calculation for 9.17 Format

db

0

Linear

1

Decimal

131,072

Hex (9.17 Format)

20 000

5

1.77

231,997

38 A3D

–5

X

0.56

L = 10^(X/20)

73,400

11 EB8

D = 131,072 × L

H = dec2hex (D, 8)

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Table 3. Serial Control Interface Register Summary

NO. OF

BYTES

INITIALIZATION

VALUE

SUBADDRESS

REGISTER NAME

CONTENTS

A u indicates unused bits.

0x00

0x01

Clock control register

1

2

1

4

20

Description shown in subsequent section

Reserved⁽¹⁾

0x6C

0xC1

Device ID register

Error status register

System control register 1

Serial data interface register

System control register 2

Soft mute register

Master volume

0x02

0x00

0x03

0xA0

0x04

0x05

0x40

0x06

0x00

0x07

0x03FF (mute)

0x00C0 (0 dB)

0x08

Channel 1 vol

0x09

Channel 2 vol

0x0A

Channel 3 vol

0x0B–0x0D

0x0E

Volume configuration register

Description shown in subsequent section

Reserved⁽¹⁾

0xF0

0x0F

0x10

Modulation limit register

IC delay channel 1

IC delay channel 2

IC delay channel 3

IC delay channel 4

Description shown in subsequent section

Reserved⁽¹⁾

0x01

0xAC

0x54

0xAC

0x54

0x11

0x12

0x13

0x14

0x15–0x19

0x1A

Start/stop period register

Oscillator trim register

BKND_ERR register

0x68

0x82

0x57

0x1B

0x1C

0x1D–0x1F

0x20

Reserved⁽¹⁾

Input MUX register

Description shown in subsequent section

Reserved⁽¹⁾

0x0001 7772

0x0000 4303

0x21

Ch 4 source select register

0x22–0x24

0x25

PWM MUX register

ch1_bq[0]

Description shown in subsequent section

u[31:26], b0[25:0]

0x0102 1345

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x26

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x27

0x28

ch1_bq[1]

ch1_bq[2]

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

(1) Reserved registers should not be accessed.

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Table 3. Serial Control Interface Register Summary (continued)

NO. OF

BYTES

INITIALIZATION

SUBADDRESS

REGISTER NAME

ch1_bq[3]

CONTENTS

VALUE

0x29

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

ch1_bq[4]

ch1_bq[5]

ch1_bq[6]

ch1_bq[7]

ch1_bq[8]

ch1_bq[9]

ch2_bq[0]

ch2_bq[1]

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Table 3. Serial Control Interface Register Summary (continued)

NO. OF

BYTES

INITIALIZATION

VALUE

SUBADDRESS

REGISTER NAME

ch2_bq[2]

CONTENTS

0x32

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

Reserved⁽²⁾

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x33

0x34

0x35

0x36

0x37

0x38

0x39

ch2_bq[3]

ch2_bq[4]

ch2_bq[5]

ch2_bq[6]

ch2_bq[7]

ch2_bq[8]

ch2_bq[9]

0x3A

0x3B

4

8

DRC1 softening filter alpha

DRC1 softening filter omega

DRC1 attack rate

u[31:26], ae[25:0]

u[31:26], oe[25:0]

0x0008 0000

0x0078 0000

0x0000 0100

0xFFFF FF00

0x3C

8

DRC1 release rate

(2) Reserved registers should not be accessed.

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Table 3. Serial Control Interface Register Summary (continued)

NO. OF

BYTES

INITIALIZATION

SUBADDRESS

REGISTER NAME

CONTENTS

VALUE

0x3D

0x3E

8

Reserved⁽³⁾

DRC2 softening filter alpha

DRC2 softening filter omega

DRC2 attack rate

u[31:26], ae[25:0]

u[31:26], oe[25:0]

u[31:26], at[25:0]

u[31:26], rt[25:0]

0x0008 0000

0xFFF8 0000

0x0008 0000

0xFFF8 0000

0x0800 0000

0x3F

8

DRC2 release rate

0x40

0x41–0x42

0x43

DRC1 attack threshold

4

8

T1[31:0] (9.23 format)

Reserved⁽³⁾

DRC2 attack threshold

DRC control

T2[31:0] (9.23 format)

Reserved⁽³⁾

0x0074 0000

0x0002 0000

0x44–0x45

0x46

Description shown in subsequent section

Reserved⁽³⁾

0x47–0x4E

0x4F

PWM switching rate control

EQ control

u[31:4], src[3:0]

0x0000 0008

0x0F70 8000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x50

Description shown in subsequent section

Ch 1 output mix1[1]

Ch 1 output mix1[0]

Ch 2 output mix2[1]

Ch 2 output mix2[0]

Reserved⁽³⁾

0x51

Ch 1 output mixer

0x52

Ch 2 output mixer

8

0x53

0x54

0x56

0x57

0x58

16

4

Reserved⁽³⁾

Output post-scale

Output pre-scale

ch1_bq[10]

u[31:26], post[25:0]

u[31:26], pre[25:0] (9.17 format)

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

0x0080 0000

0x0002 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

4

20

0x59

0x5A

0x5B

ch1_bq[11]

ch4_bq[0]

ch4_bq[1]

20

(3) Reserved registers should not be accessed.

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Table 3. Serial Control Interface Register Summary (continued)

NO. OF

BYTES

INITIALIZATION

VALUE

SUBADDRESS

REGISTER NAME

ch2_bq[10]

CONTENTS

0x5C

20

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

u[31:26], b0[25:0]

u[31:26], b1[25:0]

u[31:26], b2[25:0]

u[31:26], a1[25:0]

u[31:26], a2[25:0]

Reserved⁽⁴⁾

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x5D

0x5E

0x5F

ch2_bq[11]

ch3_bq[0]

ch3_bq[1]

0x60–0x61

0x62

4

IDF post scale

0x0000 0080

0x63–0x6A

0x6B

Reserved⁽⁴⁾

Data[31:0]

Reserved⁽⁴⁾

Left channel PWM level meter

Right channel PWM level meter

4

0x0000 0000

0x6C

0x6D–0x6F

0x70

ch1 inline mixer

4

u[31:26], in_mix1[25:0]

u[31:26], in_mixdrc_1[25:0]

u[31:26], right_mix1[25:0]

u[31:26], left_mix_1[25:0]

u[31:26], in_mix2[25:0]

u[31:26], in_mixdrc_2[25:0]

u[31:26], left_mix1[25:0]

u[31:26], right_mix_1[25:0]

Reserved⁽⁴⁾

0x0080 0000

0x0000 0000

0x0080 0000

0x0000 0000

0x0080 0000

0x71

inline_DRC_en_mixer_ch1

ch1 right_channel mixer

ch1 left_channel_mixer

ch2 inline mixer

0x72

0x73

0x74

0x75

inline_DRC_en_mixer_ch2

ch2 left_chanel mixer

ch2 right_channel_mixer

0x76

0x77

0x78–0xF7

0xF8

Update dev address key

Update dev address reg

4

Dev Id Update Key[31:0] (Key =

0xF9A5A5A5)

0x0000 0000

0x0000 0054

0xF9

u[31:8],New Dev Id[7:0] (New Dev Id = 0x38

for TAS5717/9)

Reserved⁽⁴⁾

0xFA–0xFF

(4) Reserved registers should not be accessed.

All DAP coefficients are 3.23 format unless specified otherwise.

Registers 0x3B through 0x46 should be altered only during the initialization phase.

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CLOCK CONTROL REGISTER (0x00)

The clocks and data rates are automatically determined by the TAS5717/9. The clock control register contains

the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

Table 4. Clock Control Register (0x00)

D7

0

1

–

D6

0

1

0

1

–

D5

0

1

0

1

0

1

0

1

–

D4

–

0

1

–

D3

–

0

1

0

1

–

D2

–

0

1

0

1

0

1

0

1

–

D1

–

0

–

D0

–

0

FUNCTION

f_S= 32-kHz sample rate

Reserved

f_S= 44.1/48-kHz sample rate⁽¹⁾

f_S= 16-kHz sample rate

f_S= 22.05/24-kHz sample rate

f_S= 8-kHz sample rate

f_S= 11.025/12-kHz sample rate

(2)

MCLK frequency = 64 × f_S

(2)

MCLK frequency = 128 × f_S

(3)

MCLK frequency = 192 × f_S

(1)(4)

MCLK frequency = 256 × f_S

MCLK frequency = 384 × f_S

MCLK frequency = 512 × f_S

Reserved

Reserved⁽¹⁾

(1) Default values are in bold.

(2) Only available for 44.1-kHz and 48-kHz rates

(3) Rate only available for 32/44.1/48-KHz sample rates

(4) Not available at 8 kHz

DEVICE ID REGISTER (0x01)

The device ID register contains the ID code for the firmware revision.

Table 5. General Status Register (0x01)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

FUNCTION

Identification code⁽¹⁾

(1) Default values are in bold.

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ERROR STATUS REGISTER (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the

register (write zeroes) and then read them to determine if they are persistent errors.

Error definitions:

•

MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.

SCLK error: The number of SCLKs per LRCLK is changing.

LRCLK error: LRCLK frequency is changing.

Frame slip: LRCLK phase is drifting with respect to internal frame sync.

Table 6. Error Status Register (0x02)

D7

1

D6

-

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

FUNCTION

MCLK error

–

1

–

0

–

PLL autolock error

SCLK error

–

1

–

1

–

LRCLK error

Frame slip

–

1

–

1

–

Clip indicator

–

1

–

Overcurrent, overtemperature, overvoltage, or undervoltage error

Reserved

0

(1)

0

No errors

(1) Default values are in bold.

SYSTEM CONTROL REGISTER 1 (0x03)

System control register 1 has several functions:

Bit D7:

Bit D5:

If 0, the dc-blocking filter for each channel is disabled.

If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled.

If 0, use soft unmute on recovery from a clock error. This is a slow recovery. Unmute takes the

same time as the volume ramp defined in register 0x0E.

If 1, use hard unmute on recovery from clock error. This is a fast recovery, a single-step volume

ramp.

Bits D1–D0: Select de-emphasis

Table 7. System Control Register 1 (0x03)

D7

0

1

–

D6

–

0

–

D5

–

0

1

–

D4

–

1

–

D3

–

0

–

D2

–

0

–

D1

–

0

1

D0

–

0

1

0

1

FUNCTION

PWM high-pass (dc blocking) disabled

(1)

PWM high-pass (dc blocking) enabled

Reserved⁽¹⁾

Soft unmute on recovery from clock error⁽¹⁾

Hard unmute on recovery from clock error

Reserved⁽¹⁾

No de-emphasis⁽¹⁾

De-emphasis for f_S= 32 kHz

De-emphasis for f_S= 44.1 kHz

De-emphasis for f_S= 48 kHz

(1) Default values are in bold.

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SERIAL DATA INTERFACE REGISTER (0x04)

As shown in Table 8, the TAS5717/9 supports nine serial data modes. The default is 24-bit, I²S mode.

Table 8. Serial Data Interface Control Register (0x04) Format

RECEIVE SERIAL DATA

INTERFACE FORMAT

WORD

LENGTH

D7–D4

D3

D2

D1

D0

Right-justified

16

20

24

16

20

24

16

20

24

0000

000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Right-justified

I²S

I²S⁽¹⁾

0000

Left-justified

Reserved

(1) Default values are in bold.

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SYSTEM CONTROL REGISTER 2 (0x05)

When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs

are shut down (hard mute).

Table 9. System Control Register 2 (0x05)

D7 D6 D5

D4

–

D3

–

D2

–

D1

–

D0

–

FUNCTION

0

–

0

1

–

0

–

Reserved⁽¹⁾

–

Exit all-channel shutdown (normal operation)⁽²⁾

Enter all-channel shutdown (hard mute)⁽¹⁾

–

(1)

-

–

Reserved

1

–

Headphone Mode

0

–

Speaker Mode

1. In speaker mode, a value of 1 means device is in ternary modulation.

2. In headphone mode, a value of 1 means channel volume in headphone mode =

0x08/0x09 (same as speaker channel volume).

–

1

–

1. In speaker mode, a value of 0 means device is in not in ternary modulation (AD

or BD as defined in register 0x25).

0

2. In headphone mode, 0 means channel volume in headphone mode = 0x0C

(1)

(headphone volume register).

(1)

–

0

–

Reserved

–

0

A_SEL/HP_SD configured as input

A_SEL/HP_SD configured configured as output to use as external HP amplifier

shutdown signal

–

1

–

0

1

Internal power stage FAULT signal is the source of A_SEL/HP_SD pin

HPSDZ is the source of A_SEL/HP_SD pin (set this before switching to headphone

mode)

(1) Default values are in bold.

(2) When exiting all-channel shutdown, soft unmute is might not occur unless register 0x03, bit 5 is set to 1.

SOFT MUTE REGISTER (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

Table 10. Soft Mute Register (0x06)

D7 D6 D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

0

–

0

–

0

–

0

–

0

–

Reserved⁽¹⁾

1

–

Soft mute channel 3

Soft unmute channel 3⁽¹⁾

Soft mute channel 2

Soft unmute channel 2⁽¹⁾

Soft mute channel 1

Soft unmute channel 1⁽¹⁾

0

–

1

–

0

–

1

–

0

(1) Default values are in bold.

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VOLUME REGISTERS (0x07, 0x08, 0x09)

Step size is 0.125 dB and volume registers are 2 bytes.

Master volume

– 0x07 (default is mute)

– 0x08 (default is 0 dB)

– 0x09 (default is 0 dB)

– 0x0B (default is 0 dB)

Channel-1 volume

Channel-2 volume

Headphone volume

Table 11. Master Volume Table

Value

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

0x0013

0x0014

0x0015

0x0016

0x0017

0x0018

0x0019

0x001A

0x001B

0x001C

0x001D

0x001E

0x001F

0x0020

0x0021

0x0022

0x0023

0x0024

0x0025

Level

24.000

23.875

23.750

23.625

23.500

23.375

23.250

23.125

23.000

22.875

22.750

22.625

22.500

22.375

22.250

22.125

22.000

21.875

21.750

21.625

21.500

21.375

21.250

21.125

21.000

20.875

20.750

20.625

20.500

20.375

20.250

20.125

20.000

19.875

19.750

19.625

19.500

19.375

Value

0x0027

0x0028

0x0029

0x002A

0x002B

0x002C

0x002D

0x002E

0x002F

0x0030

0x0031

0x0032

0x0033

0x0034

0x0035

0x0036

0x0037

0x0038

0x0039

0x003A

0x003B

0x003C

0x003D

0x003E

0x003F

0x0040

0x0041

0x0042

0x0043

0x0044

0x0045

0x0046

0x0047

0x0048

0x0049

0x004A

0x004B

0x004C

Level

19.250

19.000

18.875

18.750

18.625

18.500

18.375

18.250

18.125

18.000

17.875

17.750

17.625

17.500

17.375

17.250

17.125

17.000

16.875

16.750

16.625

16.500

16.375

16.250

16.125

16.000

15.875

15.750

15.625

15.500

15.375

15.250

15.125

15.000

14.875

14.750

14.625

14.500

Value

0x004E

0x004F

0x0050

0x0051

0x0052

0x0053

0x0054

0x0055

0x0056

0x0057

0x0058

0x0059

0x005A

0x005B

0x005C

0x005D

0x005E

0x005F

0x0060

0x0061

0x0062

0x0063

0x0064

0x0065

0x0066

0x0067

0x0068

0x0069

0x006A

0x006B

0x006C

0x006D

0x006E

0x006F

0x0070

0x0071

0x0072

0x0073

Level

14.250

14.125

14.000

13.875

13.750

13.625

13.500

13.375

13.250

13.125

13.000

12.875

12.750

12.625

12.500

12.375

12.250

12.125

12.000

11.875

11.750

11.625

11.500

11.375

11.250

11.125

11.000

10.875

10.750

10.625

10.500

10.375

10.250

10.125

10.000

9.875

Value

0x0075

0x0076

0x0077

0x0078

0x0079

0x007A

0x007B

0x007C

0x007D

0x007E

0x007F

0x0080

0x0081

0x0082

0x0083

0x0084

0x0085

0x0086

0x0087

0x0088

0x0089

0x008A

0x008B

0x008C

0x008D

0x008E

0x008F

0x0090

0x0091

0x0092

0x0093

0x0094

0x0095

0x0096

0x0097

0x0098

0x0099

0x009A

Level

9.375

9.250

9.125

9.000

8.875

8.750

8.625

8.500

8.375

8.250

8.125

8.000

7.875

7.750

7.625

7.500

7.375

7.250

7.125

7.000

6.875

6.750

6.625

6.500

6.375

6.250

6.125

6.000

5.875

5.750

5.625

5.500

5.375

5.250

5.125

5.000

4.875

4.750

Value

0x009C

0x009D

0x009E

0x009F

0x00A0

0x00A1

0x00A2

0x00A3

0x00A4

0x00A5

0x00A6

0x00A7

0x00A8

0x00A9

0x00AA

0x00AB

0x00AC

0x00AD

0x00AE

0x00AF

0x00B0

0x00B1

0x00B2

0x00B3

0x00B4

0x00B5

0x00B6

0x00B7

0x00B8

0x00B9

0x00BA

0x00BB

0x00BC

0x00BD

0x00BE

0x00BF

0x00C0

0x00C1

Level

4.500

4.375

4.250

4.125

4.000

3.875

3.750

3.625

3.500

3.375

3.250

3.125

3.000

2.875

2.750

2.625

2.500

2.375

2.250

2.125

2.000

1.875

1.750

1.625

1.500

1.375

1.250

1.125

1.000

0.875

0.750

0.625

0.500

0.375

0.250

0.125

0.000

–0.125

Value

Level

–0.375

–0.500

–0.625

–0.750

–0.875

–1.000

–1.125

–1.250

–1.375

–1.500

–1.625

–1.750

–1.875

–2.000

–2.125

–2.250

–2.375

–2.500

–2.625

–2.750

–2.875

–3.000

–3.125

–3.250

–3.375

–3.500

–3.625

–3.750

–3.875

–4.000

–4.125

–4.250

–4.375

–4.500

–4.625

–4.750

–4.875

–5.000

0x00C3

0x00C4

0x00C5

0x00C6

0x00C7

0x00C8

0x00C9

0x00CA

0x00CB

0x00CC

0x00CD

0x00CE

0x00CF

0x00D0

0x00D1

0x00D2

0x00D3

0x00D4

0x00D5

0x00D6

0x00D7

0x00D8

0x00D9

0x00DA

0x00DB

0x00DC

0x00DD

0x00DE

0x00DF

0x00E0

0x00E1

0x00E2

0x00E3

0x00E4

0x00E5

0x00E6

0x00E7

0x00E8

9.750

9.625

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Table 11. Master Volume Table (continued)

Value

0x0026

0x00EA

0x00EB

0x00EC

0x00ED

0x00EE

0x00EF

0x00F0

0x00F1

0x00F2

0x00F3

0x00F4

0x00F5

0x00F6

0x00F7

0x00F8

0x00F9

0x00FA

0x00FB

0x00FC

0x00FD

0x00FE

0x00FF

0x0100

0x0101

0x0102

0x0103

0x0104

0x0105

0x0106

0x0107

0x0108

0x0109

0x010A

0x010B

0x010C

0x010D

0x010E

0x010F

0x0110

0x0111

0x0112

0x0113

0x0114

0x0115

0x0116

0x0117

Level

19.125

–5.250

–5.375

–5.500

–5.625

–5.750

–5.875

–6.000

–6.125

–6.250

–6.375

–6.500

–6.625

–6.750

–6.875

–7.000

–7.125

–7.250

–7.375

–7.500

–7.625

–7.750

–7.875

–8.000

–8.125

–8.250

–8.375

–8.500

–8.625

–8.750

–8.875

–9.000

–9.125

–9.250

–9.375

–9.500

–9.625

–9.750

–9.875

–10.000

–10.125

–10.250

–10.375

–10.500

–10.625

–10.750

–10.875

Value

0x004D

0x0119

0x011A

0x011B

0x011C

0x011D

0x011E

0x011F

0x0120

0x0121

0x0122

0x0123

0x0124

0x0125

0x0126

0x0127

0x0128

0x0129

0x012A

0x012B

0x012C

0x012D

0x012E

0x012F

0x0130

0x0131

0x0132

0x0133

0x0134

0x0135

0x0136

0x0137

0x0138

0x0139

0x013A

0x013B

0x013C

0x013D

0x013E

0x013F

0x0140

0x0141

0x0142

0x0143

0x0144

0x0145

0x0146

Level

Value

0x0074

0x0148

0x0149

0x014A

0x014B

0x014C

0x014D

0x014E

0x014F

0x0150

0x0151

0x0152

0x0153

0x0154

0x0155

0x0156

0x0157

0x0158

0x0159

0x015A

0x015B

0x015C

0x015D

0x015E

0x015F

0x0160

0x0161

0x0162

0x0163

0x0164

0x0165

0x0166

0x0167

0x0168

0x0169

0x016A

0x016B

0x016C

0x016D

0x016E

0x016F

0x0170

0x0171

0x0172

0x0173

0x0174

0x0175

Level

Value

0x009B

0x0177

0x0178

0x0179

0x017A

0x017B

0x017C

0x017D

0x017E

0x017F

0x0180

0x0181

0x0182

0x0183

0x0184

0x0185

0x0186

0x0187

0x0188

0x0189

0x018A

0x018B

0x018C

0x018D

0x018E

0x018F

0x0190

0x0191

0x0192

0x0193

0x0194

0x0195

0x0196

0x0197

0x0198

0x0199

0x019A

0x019B

0x019C

0x019D

0x019E

0x019F

0x01A0

0x01A1

0x01A2

0x01A3

0x01A4

Level

Value

0x00C2

0x01A6

0x01A7

0x01A8

0x01A9

0x01AA

0x01AB

0x01AC

0x01AD

0x01AE

0x01AF

0x01B0

0x01B1

0x01B2

0x01B3

0x01B4

0x01B5

0x01B6

0x01B7

0x01B8

0x01B9

0x01BA

0x01BB

0x01BC

0x01BD

0x01BE

0x01BF

0x01C0

0x01C1

0x01C2

0x01C3

0x01C4

0x01C5

0x01C6

0x01C7

0x01C8

0x01C9

0x01CA

0x01CB

0x01CC

0x01CD

0x01CE

0x01CF

0x01D0

0x01D1

0x01D2

0x01D3

Level

Value

0x00E9

0x01D5

0x01D6

0x01D7

0x01D8

0x01D9

0x01DA

0x01DB

0x01DC

0x01DD

0x01DE

0x01DF

0x01E0

0x01E1

0x01E2

0x01E3

0x01E4

0x01E5

0x01E6

0x01E7

0x01E8

0x01E9

0x01EA

0x01EB

0x01EC

0x01ED

0x01EE

0x01EF

0x01F0

0x01F1

0x01F2

0x01F3

0x01F4

0x01F5

0x01F6

0x01F7

0x01F8

0x01F9

0x01FA

0x01FB

0x01FC

0x01FD

0x01FE

0x01FF

0x0200

0x0201

0x0202

Level

14.375

9.500

4.625

–0.250

–5.125

–11.125

–11.250

–11.375

–11.500

–11.625

–11.750

–11.875

–12.000

–12.125

–12.250

–12.375

–12.500

–12.625

–12.750

–12.875

–13.000

–13.125

–13.250

–13.375

–13.500

–13.625

–13.750

–13.875

–14.000

–14.125

–14.250

–14.375

–14.500

–14.625

–14.750

–14.875

–15.000

–15.125

–15.250

–15.375

–15.500

–15.625

–15.750

–15.875

–16.000

–16.125

–16.250

–16.375

–16.500

–16.625

–16.750

–17.000

–17.125

–17.250

–17.375

–17.500

–17.625

–17.750

–17.875

–18.000

–18.125

–18.250

–18.375

–18.500

–18.625

–18.750

–18.875

–19.000

–19.125

–19.250

–19.375

–19.500

–19.625

–19.750

–20.875

–20.000

–20.125

–20.250

–20.375

–20.500

–20.625

–20.750

–20.875

–21.000

–21.125

–21.250

–21.375

–21.500

–21.625

–21.750

–21.875

–22.000

–22.125

–22.250

–22.375

–22.500

–22.625

–22.875

–23.000

–23.125

–23.250

–23.375

–23.500

–23.625

–23.750

–23.875

–24.000

–24.125

–24.250

–24.375

–24.500

–24.625

–24.750

–24.875

–25.000

–25.125

–25.250

–25.375

–25.500

–25.625

–25.750

–25.875

–26.000

–26.125

–26.250

–26.375

–26.500

–26.625

–26.750

–26.875

–27.000

–27.125

–27.250

–27.375

–27.500

–27.625

–27.750

–27.875

–28.000

–28.125

–28.250

–28.375

–28.500

–28.750

–28.875

–29.000

–29.125

–29.250

–29.375

–29.500

–29.625

–29.750

–29.875

–30.000

–30.125

–30.250

–30.375

–30.500

–30.625

–30.750

–30.875

–31.000

–31.125

–31.250

–31.375

–31.500

–31.625

–31.750

–31.875

–32.000

–32.125

–32.250

–32.375

–32.500

–32.625

–32.750

–32.875

–33.000

–33.125

–33.250

–33.375

–33.500

–33.625

–33.750

–33.875

–34.000

–34.125

–34.250

–34.375

–34.625

–34.750

–34.875

–35.000

–35.125

–35.250

–35.375

–35.500

–35.625

–35.750

–35.875

–36.000

–36.125

–36.250

–36.375

–36.500

–36.625

–36.750

–36.875

–37.000

–37.125

–37.250

–37.375

–37.500

–37.625

–37.750

–37.875

–38.000

–38.125

–38.250

–38.375

–38.500

–38.625

–38.750

–38.875

–39.000

–39.125

–39.250

–39.375

–39.500

–39.625

–39.750

–39.875

–40.000

–40.125

–40.250

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

www.ti.com

Table 11. Master Volume Table (continued)

Value

0x0118

0x0204

0x0205

0x0206

0x0207

0x0208

0x0209

0x020A

0x020B

0x020C

0x020D

0x020E

0x020F

0x0210

0x0211

0x0212

0x0213

0x0214

0x0215

0x0216

0x0217

0x0218

0x0219

0x021A

0x021B

0x021C

0x021D

0x021E

0x021F

0x0220

0x0221

0x0222

0x0223

0x0224

0x0225

0x0226

0x0227

0x0228

0x0229

0x022A

0x022B

0x022C

0x022D

0x022E

0x022F

0x0230

0x0231

Level

Value

0x0147

0x0233

0x0234

0x0235

0x0236

0x0237

0x0238

0x0239

0x023A

0x023B

0x023C

0x023D

0x023E

0x023F

0x0240

0x0241

0x0242

0x0243

0x0244

0x0245

0x0246

0x0247

0x0248

0x0249

0x024A

0x024B

0x024C

0x024D

0x024E

0x024F

0x0250

0x0251

0x0252

0x0253

0x0254

0x0255

0x0256

0x0257

0x0258

0x0259

0x025A

0x025B

0x025C

0x025D

0x025E

0x025F

0x0260

Level

Value

0x0176

0x0262

0x0263

0x0264

0x0265

0x0266

0x0267

0x0268

0x0269

0x026A

0x026B

0x026C

0x026D

0x026E

0x026F

0x0270

0x0271

0x0272

0x0273

0x0274

0x0275

0x0276

0x0277

0x0278

0x0279

0x027A

0x027B

0x027C

0x027D

0x027E

0x027F

0x0280

0x0281

0x0282

0x0283

0x0284

0x0285

0x0286

0x0287

0x0288

0x0289

0x028A

0x028B

0x028C

0x028D

0x028E

0x028F

Level

Value

0x01A5

0x0291

0x0292

0x0293

0x0294

0x0295

0x0296

0x0297

0x0298

0x0299

0x029A

0x029B

0x029C

0x029D

0x029E

0x029F

0x02A0

0x02A1

0x02A2

0x02A3

0x02A4

0x02A5

0x02A6

0x02A7

0x02A8

0x02A9

0x02AA

0x02AB

0x02AC

0x02AD

0x02AE

0x02AF

0x02B0

0x02B1

0x02B2

0x02B3

0x02B4

0x02B5

0x02B6

0x02B7

0x02B8

0x02B9

0x02BA

0x02BB

0x02BC

0x02BD

0x02BE

Level

Value

Level

Value

0x0203

0x02EF

0x02F0

0x02F1

0x02F2

0x02F3

0x02F4

0x02F5

0x02F6

0x02F7

0x02F8

0x02F9

0x02FA

0x02FB

0x02FC

0x02FD

0x02FE

0x02FF

0x0300

0x0301

0x0302

0x0303

0x0304

0x0305

0x0306

0x0307

0x0308

0x0309

0x030A

0x030B

0x030C

0x030D

0x030E

0x030F

0x0310

0x0311

0x0312

0x0313

0x0314

0x0315

0x0316

0x0317

0x0318

0x0319

0x031A

0x031B

0x031C

Level

–11.000

–40.500

–40.625

–40.750

–40.875

–41.000

–41.125

–41.250

–41.375

–41.500

–41.625

–41.750

–41.875

–42.000

–42.125

–42.250

–42.375

–42.500

–42.625

–42.750

–42.875

–43.000

–43.125

–43.250

–43.375

–43.500

–43.625

–43.750

–43.875

–44.000

–44.125

–44.250

–44.375

–44.500

–44.625

–44.750

–44.875

–45.000

–45.125

–45.250

–45.375

–45.500

–45.625

–45.750

–45.875

–46.000

–46.125

–16.875

–46.375

–46.500

–46.625

–46.750

–46.875

–47.000

–47.125

–47.250

–47.375

–47.500

–47.625

–47.750

–47.875

–48.000

–48.125

–48.250

–48.375

–48.500

–48.625

–48.750

–48.875

–49.000

–49.125

–49.250

–49.375

–49.500

–49.625

–49.750

–49.875

–50.000

–50.125

–50.250

–50.375

–50.500

–50.625

–50.750

–50.875

–51.000

–51.125

–51.250

–51.375

–51.500

–51.625

–51.750

–51.875

–52.000

–22.750

–52.250

–52.375

–52.500

–52.625

–52.750

–52.875

–53.000

–53.125

–53.250

–53.375

–53.500

–53.625

–53.750

–53.875

–54.000

–54.125

–54.250

–54.375

–54.500

–54.625

–54.750

–54.875

–55.000

–55.125

–55.250

–55.375

–55.500

–55.625

–55.750

–55.875

–56.000

–56.250

–56.125

–56.375

–56.500

–56.625

–56.750

–56.875

–57.000

–57.125

–57.250

–57.375

–57.500

–57.625

–57.750

–57.875

–28.625

–58.250

–58.125

–58.375

–58.500

–58.625

–58.750

–58.875

–59.000

–59.125

–59.250

–59.375

–59.500

–59.625

–59.750

–59.875

–60.000

–60.125

–60.250

–60.375

–60.500

–60.625

–60.750

–60.875

–61.000

–61.125

–61.250

–61.375

–61.500

–61.625

–61.750

–61.875

–62.000

–62.125

–62.250

–62.375

–62.500

–62.625

–62.750

–62.875

–63.000

–63.125

–63.250

–63.375

–63.500

–63.625

–63.750

0x01D4

0x02C0

0x02C1

0x02C2

0x02C3

0x02C4

0x02C5

0x02C6

0x02C7

0x02C8

0x02C9

0x02CA

0x02CB

0x02CC

0x02CD

0x02CE

0x02CF

0x02D0

0x02D1

0x02D2

0x02D3

0x02D4

0x02D5

0x02D6

0x02D7

0x02D8

0x02D9

0x02DA

0x02DB

0x02DC

0x02DD

0x02DE

0x02DF

0x02E0

0x02E1

0x02E2

0x02E3

0x02E4

0x02E5

0x02E6

0x02E7

0x02E8

0x02E9

0x02EA

0x02EB

0x02EC

0x02ED

–34.500

–64.000

–64.125

–64.250

–64.375

–64.500

–64.625

–64.750

–64.875

–65.000

–65.125

–65.250

–65.375

–65.500

–65.625

–65.750

–65.875

–66.000

–66.125

–66.250

–66.375

–66.500

–66.625

–66.750

–66.875

–67.000

–67.125

–67.250

–67.375

–67.500

–67.625

–67.750

–67.875

–68.000

–68.125

–68.250

–68.375

–68.500

–68.625

–68.750

–68.875

–69.000

–69.125

–69.250

–69.375

–69.500

–69.625

–40.375

–69.875

–70.000

–70.125

–70.250

–70.375

–70.500

–70.625

–70.750

–70.875

–71.000

–71.125

–71.250

–71.375

–71.500

–71.625

–71.750

–71.875

–72.000

–72.125

–72.250

–72.375

–72.500

–72.625

–72.750

–72.875

–73.000

–73.125

–73.250

–73.375

–73.500

–73.625

–73.750

–73.875

–74.000

–74.250

–74.125

–74.375

–74.500

–74.625

–74.750

–74.875

–75.000

–75.125

–75.250

–75.375

–75.500

44

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

Table 11. Master Volume Table (continued)

Value

0x0232

0x031E

0x031F

0x0320

0x0321

0x0322

0x0323

0x0324

0x0325

0x0326

0x0327

0x0328

0x0329

0x032A

0x032B

0x032C

0x032D

0x032E

0x032F

0x0330

0x0331

0x0332

0x0333

0x0334

0x0335

0x0336

0x0337

0x0338

0x0339

0x033A

0x033B

0x033C

0x033D

0x033E

0x033F

0x0340

0x0341

0x0343

Level

Value

0x0261

0x0344

0x0345

0x0346

0x0347

0x0348

0x0349

0x034A

0x034B

0x034C

0x034D

0x034E

0x034F

0x0350

0x0351

0x0352

0x0353

0x0354

0x0355

0x0356

0x0357

0x0358

0x0359

0x035A

0x035B

0x035C

0x035D

0x035E

0x035F

0x0360

0x0361

0x0362

0x0363

0x0364

0x0365

0x0366

0x0367

0x0368

0x0369

Level

Value

0x0290

0x036A

0x036B

0x036C

0x036D

0x036E

0x036F

0x0370

0x0371

0x0372

0x0373

0x0374

0x0375

0x0376

0x0377

0x0378

0x0379

0x037A

0x037B

0x037C

0x037D

0x037E

0x037F

0x0380

0x0381

0x0382

0x0383

0x0384

0x0385

0x0386

0x0387

0x0388

0x0389

0x038A

0x038B

0x038C

0x038D

0x038E

0x038F

Level

Value

0x02BF

0x0390

0x0391

0x0392

0x0393

0x0394

0x0395

0x0396

0x0397

0x0398

0x0399

0x039A

0x039B

0x039C

0x039D

0x039E

0x039F

0x03A0

0x03A1

0x03A2

0x03A3

0x03A4

0x03A5

0x03A6

0x03A7

0x03A8

0x03A9

0x03AA

0x03AB

0x03AC

0x03AD

0x03AE

0x03AF

0x03B0

0x03B1

0x03B2

0x03B3

0x03B4

0x03B5

Level

Value

Level

Value

Level

–46.250

–75.750

–75.875

–76.000

–76.125

–76.250

–76.375

–76.500

–76.625

–76.750

–76.875

–77.000

–77.125

–77.250

–77.375

–77.500

–77.625

–77.750

–77.875

–78.000

–78.125

–78.250

–78.375

–78.500

–78.625

–78.750

–78.875

–79.000

–79.125

–79.250

–79.375

–79.500

–79.625

–79.750

–79.875

–80.000

–80.250

–80.375

–52.125

–80.500

–80.625

–80.750

–80.875

–81.000

–81.125

–81.250

–81.375

–81.500

–81.625

–81.750

–81.875

–82.000

–82.125

–82.250

–82.375

–82.500

–82.625

–82.750

–82.875

–83.000

–83.125

–83.250

–83.375

–83.500

–83.625

–83.750

–83.875

–84.000

–84.125

–84.250

–84.375

–84.500

–84.625

–84.750

–84.875

–85.000

–85.125

–58.000

–85.250

–85.375

–85.500

–85.625

–85.750

–85.875

–86.000

–86.125

–86.250

–86.375

–86.500

–86.625

–86.750

–86.875

–87.000

–87.125

–87.250

–87.375

–87.500

–87.625

–87.750

–87.875

–88.000

–88.125

–88.250

–88.375

–88.500

–88.625

–88.750

–88.875

–89.000

–89.125

–89.250

–89.375

–89.500

–89.625

–89.750

–89.875

–63.875

–90.000

–90.125

–90.250

–90.375

–90.500

–90.625

–90.750

–90.875

–91.000

–91.125

–91.250

–91.375

–91.500

–91.625

–91.750

–91.875

–92.000

–92.125

–92.250

–92.375

–92.500

–92.625

–92.750

–92.875

–93.000

–93.125

–93.250

–93.375

–93.500

–93.625

–93.750

–93.875

–94.000

–94.125

–94.250

–94.375

–94.500

–94.625

0x02EE

0x03B6

0x03B7

0x03B8

0x03B9

0x03BA

0x03BB

0x03BC

0x03BD

0x03BE

0x03BF

0x03C0

0x03C1

0x03C2

0x03C3

0x03C4

0x03C5

0x03C6

0x03C7

0x03C8

0x03C9

0x03CA

0x03CB

0x03CC

0x03CD

0x03CE

0x03CF

0x03D0

0x03D1

0x03D2

0x03D3

0x03D4

0x03D5

0x03D6

0x03D7

0x03D8

0x03D9

0x03DA

0x03DB

–69.750

–94.750

–94.875

–95.000

–95.125

–95.250

–95.375

–95.500

–95.625

–95.750

–95.875

–96.000

–96.125

–96.250

–96.375

–96.500

–96.625

–96.750

–96.875

–97.000

–97.125

–97.250

–97.375

–97.500

–97.625

–97.750

–97.875

–98.000

–98.125

–98.250

–98.375

–98.500

–98.625

–98.750

–98.875

–99.000

–99.125

–99.250

–99.375

0x031D

0x03DC

0x03DD

0x03DE

0x03DF

–75.625

–99.500

–99.625

–99.750

–99.875

0x03E0 –100.000

0x03E1 –100.125

0x03E2 –100.250

0x03E3 –100.375

0x03E4 –100.500

0x03E5 –100.625

0x03E6 –100.750

0x03E7 –100.875

0x03E8 –101.000

0x03E9 –101.125

0x03EA –101.250

0x03EB –101.375

0x03EC –101.500

0x03ED –101.625

0x03EE –101.750

0x03EF –101.875

0x03F0 –102.000

0x03F1 –102.125

0x03F2 –102.250

0x03F3 –102.375

0x03F4 –102.500

0x03F5 –102.625

0x03F6 –102.750

0x03F7 –102.875

0x03F8 –103.000

0x03F9 –103.125

0x03FA –103.250

0x03FB –103.375

0x03FC –103.500

0x03FD –103.625

0x03FE –103.750

0x03FF

Mute

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SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

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VOLUME CONFIGURATION REGISTER (0x0E)

Bits

Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the

D2–D0: number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of

the I²S data as follows:

Sample rate (kHz)

8/16/32

Approximate ramp rate

125 μs/step

11.025/22.05/44.1

12/24/48

90.7 μs/step

83.3 μs/step

Table 12. Volume Configuration Register (0x0E)

D7 D6 D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

1

–

0

–

0

–

1

–

0

–

Reserved⁽¹⁾

0

Volume slew 512 steps (43 ms volume ramp time at 48 kHz)⁽¹⁾

Volume slew 1024 steps (85-ms volume ramp time at 48 kHz)

Volume slew 2048 steps (171-ms volume ramp time at 48 kHz)

Volume slew 256 steps (21-ms volume ramp time at 48 kHz)

Reserved

0

1

0

1

0

1

X

(1) Default values are in bold.

MODULATION LIMIT REGISTER (0x10)

Table 13. Modulation Limit Register (0x10)

D7

0

D6

0

D5

0

D4

0

D3

0

D2

–

D1

–

D0

–

MODULATION LIMIT

Reserved

99.2%

–

0

–

0

1

98.4%

–

0

1

0

97.7%⁽¹⁾

–

0

1

96.9%

–

1

0

96.1%

–

1

0

1

95.3%

–

1

0

94.5%

–

1

93.8%

(1) Default values are in bold.

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INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

Table 14. Channel Interchannel Delay Register Format

BITS DEFINITION

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

–

D0

–

FUNCTION

Minimum absolute delay, 0 DCLK cycles

Maximum positive delay, 31 × 4 DCLK cycles

Maximum negative delay, –32 × 4 DCLK cycles

Reserved

0

1

–

1

0

–

0

SUBADDRESS

0x11

D7

1

D6

0

D5

1

D4

0

D3

1

D2

1

D1

–

D0 Delay = (value) × 4 DCLKs

–

Default value for channel 1⁽¹⁾

Default value for channel 2⁽¹⁾

Default value for channel 1⁽¹⁾

Default value for channel 2⁽¹⁾

0x12

0

1

0

1

0

1

–

0x13

1

0

1

0

1

–

0x14

0

1

0

1

0

1

–

(1) Default values are in bold.

ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk, etc.) Therefore,

appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD

mode, then update these registers before coming out of all-channel shutdown.

MODE

0x11

0x12

0x13

0x14

AD MODE

BD MODE

AC

54

B8

60

A0

48

AC

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PWM SHUTDOWN GROUP REGISTER (0x19)

Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and

0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the

state of bit D5 in the system control register.

This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group

register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is

set to 0 in system control register 2, 0x05).

Table 15. PWM Shutdown Group Register (0x19)

D7

0

–

D6

–

0

–

D5

–

1

–

D4

–

1

–

D3

–

0

1

–

D2

–

0

1

–

D1

–

0

1

–

D0

–

0

1

FUNCTION

Reserved⁽¹⁾

PWM channel 4 does not belong to shutdown group.⁽¹⁾

PWM channel 4 belongs to shutdown group.

PWM channel 3 does not belong to shutdown group.⁽¹⁾

PWM channel 3 belongs to shutdown group.

PWM channel 2 does not belong to shutdown group.⁽¹⁾

PWM channel 2 belongs to shutdown group.

PWM channel 1 does not belong to shutdown group.⁽¹⁾

PWM channel 1 belongs to shutdown group.

(1) Default values are in bold.

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START/STOP PERIOD REGISTER (0x1A)

This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown

command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times

are only approximate and vary depending on device activity level and I²S clock stability.

Table 16. Start/Stop Period Register (0x1A)

D7 D6 D5 D4 D3

D2

–

0

1

0

1

0

1

D1

–

0

1

0

1

0

1

0

1

0

1

0

1

D0

–

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FUNCTION

0

1

–

0

–

0

–

0

1

–

0

1

0

1

SSTIMER enabled⁽¹⁾

SSTIMER disabled

Reserved⁽¹⁾

No 50% duty cycle start/stop period

16.5-ms 50% duty cycle start/stop period

23.9-ms 50% duty cycle start/stop period

31.4-ms 50% duty cycle start/stop period

40.4-ms 50% duty cycle start/stop period

53.9-ms 50% duty cycle start/stop period

70.3-ms 50% duty cycle start/stop period

94.2-ms 50% duty cycle start/stop period

125.7-ms 50% duty cycle start/stop period⁽¹⁾

164.6-ms 50% duty cycle start/stop period

239.4-ms 50% duty cycle start/stop period

314.2-ms 50% duty cycle start/stop period

403.9-ms 50% duty cycle start/stop period

538.6-ms 50% duty cycle start/stop period

703.1-ms 50% duty cycle start/stop period

942.5-ms 50% duty cycle start/stop period

1256.6-ms 50% duty cycle start/stop period

1728.1-ms 50% duty cycle start/stop period

2513.6-ms 50% duty cycle start/stop period

3299.1-ms 50% duty cycle start/stop period

4241.7-ms 50% duty cycle start/stop period

5655.6-ms 50% duty cycle start/stop period

7383.7-ms 50% duty cycle start/stop period

9897.3-ms 50% duty cycle start/stop period

13,196.4-ms 50% duty cycle start/stop period

(1) Default values are in bold.

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OSCILLATOR TRIM REGISTER (0x1B)

The TAS5717/9 PWM processor contains an internal oscillator to support autodetect of I²S clock rates. This

reduces system cost because an external reference is not required. Currently, TI recommends a reference

resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

Note that trim must always be run following reset of the device.

Table 17. Oscillator Trim Register (0x1B)

D7

1

D6

–

D5 D4 D3

D2

–

D1

–

D0

–

FUNCTION

–

0

–

0

–

0

–

Reserved⁽¹⁾

–

0

–

Oscillator trim not done (read-only)⁽¹⁾

Oscillator trim done (read only)

Reserved⁽¹⁾

–

1

–

0

–

0

–

Select factory trim (Write a 0 to select factory trim; default is 1.)

Factory trim disabled⁽¹⁾

–

1

–

0

Reserved⁽¹⁾

(1) Default values are in bold.

BKND_ERR REGISTER (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset, stopping all

PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 18 before attempting

to re-start the power stage.

Table 18. BKND_ERR Register (0x1C)

D7 D6 D5 D4 D3

D2

–

0

1

0

D1

–

1

0

1

0

D0

–

0

1

0

1

0

1

0

FUNCTION

0

1

–

0

1

0

1

–

0

1

0

1

0

1

0

1

–

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

0

1

Headphone enable time = 0 ms

Headphone enable time = 2 ms

Headphone enable time = 4 ms

Headphone enable time = 6 ms

Headphone enable time = 8 ms

Headphone enable time = 10 ms⁽¹⁾

Headphone enable time = 12 ms

Headphone enable time = 14 ms

Headphone enable time = 16 ms

Headphone enable time = 18 ms

Headphone enable time = 20 ms

Headphone enable time = 22 ms

Headphone enable time = 24 ms

Headphone enable time = 26 ms

Headphone enable time = 28 ms

Headphone enable time = 30 ms

Set back-end reset period to 299 ms⁽¹⁾

Set back-end reset period to 449 ms

Set back-end reset period to 598 ms

Set back-end reset period to 748 ms

Set back-end reset period to 898 ms

Set back-end reset period to 1047 ms

Set back-end reset period to 1197 ms

(1) Default values are in bold.

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Table 18. BKND_ERR Register (0x1C) (continued)

D7 D6 D5 D4 D3

D2

0

D1

0

D0

1

FUNCTION

–

1

Set back-end reset period to 1346 ms

Set back-end reset period to 1496 ms

0

1

X

1

X

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INPUT MULTIPLEXER REGISTER (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal

channels.

Table 19. Input Multiplexer Register (0x20)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Channel-1 AD mode⁽¹⁾

Channel-1 BD mode

SDIN-L to channel 1⁽¹⁾

SDIN-R to channel 1

Reserved

Reserved⁽¹⁾

D23

0

D22

–

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

1

–

0

–

0

1

–

0

1

0

–

0

1

–

Reserved

–

1

0

–

Reserved

–

1

0

1

–

Reserved

–

1

0

–

Ground (0) to channel 1

Reserved

–

1

–

0

–

Channel 2 AD mode⁽¹⁾

Channel 2 BD mode

SDIN-L to channel 2

SDIN-R to channel 2⁽¹⁾

Reserved

–

1

–

0

–

0

1

–

0

1

0

–

0

1

Reserved

–

1

0

Reserved

–

1

0

1

Reserved

–

1

0

Ground (0) to channel 2

Reserved

–

1

D15

0

D14

1

D13

1

D12

1

D11

0

D10

1

D9

1

D8

1

FUNCTION

Reserved⁽¹⁾

D7

0

D6

1

D5

1

D4

1

D3

0

D2

0

D1

1

D0

0

FUNCTION

(1) Default values are in bold.

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CHANNEL 4 SOURCE SELECT REGISTER (0x21)

This register selects the channel 4 source.

Table 20. Subchannel Control Register (0x21)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

0

D14

1

D13

0

D12

0

D11

0

D10

0

D9

1

D8

–

Reserved⁽¹⁾

–

0

(L + R)/2

–

1

Left-channel post-BQ⁽¹⁾

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

1

D0

1

FUNCTION

Reserved⁽¹⁾

(1) Default values are in bold.

PWM OUTPUT MUX REGISTER (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be

output to any external output pin.

Bits D21–D20:

Bits D17–D16:

Bits D13–D12:

Bits D09–D08:

Selects which PWM channel is output to OUT_A

Selects which PWM channel is output to OUT_B

Selects which PWM channel is output to OUT_C

Selects which PWM channel is output to OUT_D

Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.

Table 21. PWM Output Mux Register (0x25)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

1

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

–

D20

–

D19

–

D18

–

D17

–

D16

–

FUNCTION

Reserved⁽¹⁾

–

0

–

Multiplex channel 1 to OUT_A⁽¹⁾

Multiplex channel 2 to OUT_A

Multiplex channel 1 to OUT_A

Multiplex channel 2 to OUT_A

Reserved⁽¹⁾

–

0

1

–

1

0

–

1

–

0

–

0

Multiplex channel 1 to OUT_B

Multiplex channel 2 to OUT_B

Multiplex channel 1 to OUT_B⁽¹⁾

Multiplex channel 2 to OUT_B

–

0

1

–

1

0

–

1

(1) Default values are in bold.

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Table 21. PWM Output Mux Register (0x25) (continued)

D15

0

D14

0

D13

–

D12

–

D11

–

D10

–

D9

–

D8

–

FUNCTION

Reserved⁽²⁾

–

0

–

Multiplex channel 1 to OUT_C

–

0

1

–

Multiplex channel 2 to OUT_C⁽²⁾

Multiplex channel 1 to OUT_C

Multiplex channel 2 to OUT_C

Reserved⁽²⁾

–

1

0

–

1

–

0

–

0

Multiplex channel 1 to OUT_D

Multiplex channel 2 to OUT_D

Multiplex channel 1 to OUT_D

Multiplex channel 2 to OUT_D⁽²⁾

–

0

1

–

1

0

–

1

D7

0

D6

1

D5

0

D4

0

D3

0

D2

1

D1

0

D0

1

FUNCTION

Reserved⁽²⁾

(2) Default values are in bold.

DRC CONTROL REGISTER (0x46)

Table 22. DRC Control Register (0x46)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

–

D4

–

D3

–

D2

–

D1

–

D0

–

Reserved⁽¹⁾

–

0

–

Reserved

–

1

–

Reserved

–

0

–

Reserved⁽¹⁾

–

0

–

Reserved⁽¹⁾

–

0

–

Reserved⁽¹⁾

–

0

–

DRC2 turned OFF⁽¹⁾

DRC2 turned ON

DRC1 turned OFF⁽¹⁾

DRC1 turned ON

–

1

–

0

–

1

(1) Default values are in bold.

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PWM SWITCHING RATE CONTROL REGISTER (0x4F)

PWM switching rate should be selected through the register 0x4F before coming out of all-channnel shutdown.

Table 23. PWM Switching Rate Control Register (0x4F)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Reserved⁽¹⁾

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

–

D6

–

D5

0

D4

0

D3

–

D2

–

D1

–

D0

–

Reserved⁽¹⁾

SRC = 6⁽¹⁾

SRC = 7

–

0

1

0

–

0

1

–

1

0

SRC = 8

–

1

0

1

SRC = 9

–

1

0

1

0

Reserved

–

1

–

(1) Default values are in bold.

EQ CONTROL (0x50)

Table 24. EQ Command (0x50)

D31

0

D30

0

D29

0

D28

0

D27

0

D26

0

D25

0

D24

0

FUNCTION

Reserved⁽¹⁾

EQ ON⁽¹⁾

D23

0

D22

0

D21

0

D20

0

D19

0

D18

0

D17

0

D16

0

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

D5

D4

D3

D2

D1

D0

1

–

0

–

0

1

–

EQ OFF (bypass BQ 0–7 of channels 1 and 2)

Reserved⁽¹⁾

L and R can be written independently.⁽¹⁾

–

0

–

L and R are ganged for EQ biquads; a write to the left-channel

biquad is also written to the right-channel biquad. (0x29–0x2F is

ganged to 0x30–0x36. Also, 0x58–0x5B is ganged to 0x5C–0x5F.

–

1

–

0

–

0

1

–

0

1

X

–

0

1

X

Reserved⁽¹⁾

Reserved

(1) Default values are in bold.

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USING HEADPHONE AMPLIFIER IN TAS5717

This device has a stereo output which can be used as a line driver or a headphone driver that can output 2-Vrms

stereo. An audio system can be set up for different applications using this device.

Case 1 – Headphone (HP)/Line Drive With Analog Input:

The device can be represented as shown in Figure 46: analog inputs (single-ended) as HPL_IN (pin 1) and

HPR_IN (pin 4) with the outputs HPL_OUT (pin 2) and HPR_OUT (pin 3).

R₂

R₁

V_IN

V_OUT

HPL_IN

HPL_OUT

S0490-01

Figure 46. Headphone/Line Driver with Analog Input

HP_SD pin can be used turn ON/OFF the headphone amplifier/line driver.

Speaker channels are independent of headphone/line driver in this mode.

Case 2 – Headphone With I²S Input:

Hardware setup: The HP_PWML and HP_PWMR signals should be fed into a low-pass filter (LPF), and the

output of the LPF is fed to analog inputs (HPL_IN and HPR_IN). The A_SEL pin has a 15-kΩ pulldown to ground

and should be routed to headphone amplifier enable (HP_SDZ pin 33).

Software setup: Write to register 0x05 bits D4 = 1, D1 = 1, and D0 = 1 (13 hex). When D4 and D1 are set to 1,

the A_SEL pin goes high and thus enables the headphone output. When register 0x05 D4 = 1, the device is in

headphone mode and the speaker outputs are in shutdown.

NOTE: The speaker and headphone cannot be used at the same time as they both share the same digital

channel. DAP can be used for headphone volume.

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APPLICATION INFORMATION

LINE DRIVER AMPLIFIERS

Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in

Figure 47 illustrates the conventional line driver amplifier connection to the load and output signal.

DC blocking capacitors for headphone amps are often large in value, and a mute circuit is needed during power

up to minimize click and pop for both headphone and line driver. The output capacitors and mute circuits

consume PCB area and increase cost of assembly, and can reduce the fidelity of the audio output signal.

Conventional Solution

9–12 V

VDD

+

Mute Circuit

C_o

+

–

Output

VDD/2

+

OPAMP

GND

MUTE

TAS5717 Solution

3.3 V

DirectPath

VDD

+

–

Output

Mute Circuit

GND

TAS5717

VSS

HP_SD

S0445-01

Figure 47. Conventional and DirectPath HP and Line Driver

The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump

to provide a negative voltage rail.

Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what

is effectively a split supply mode.

The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail,

combining this with the build in click and pop reduction circuit, the DirectPath™ amplifier requires no output dc

blocking capacitors.

The bottom block diagram and waveform of Figure 47 illustrate the ground-referenced headphone and line driver

architecture. This is the architecture of the TAS5717/9.

COMPONENT SELECTION

Charge Pump

The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.

The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge

transfer. Low ESR capacitors are an ideal selection, and a value of 1µF is typical. Capacitor values that are

smaller than 1µF can not be recommended for the HP section as it will limit the negative voltage swing in low

impedance loads.

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Decoupling Capacitors

The TAS5717/9 is a DirectPath™ amplifier that requires adequate power supply decoupling to ensure that the

noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic

capacitor, typically 1µF, placed as close as possible to the device PVDD leads works best. Placing this

decoupling capacitor close to the TAS5717/9 is important for the performance of the amplifier. For filtering lower

frequency noise signals, a 10µF or greater capacitor placed near the audio power amplifier would also help, but it

is not required in most applications because of the high PSRR of this device.

Gain Setting Resistors Ranges

The gain setting resistors, R_inand R_fb, must be chosen so that noise, stability and input capacitor size of the

TAS5717/9 is kept within acceptable limits. Voltage gain is defined as R_fbdivided by R_in. Selecting values that

are too low demands a large input ac-coupling capacitor, C_IN. Selecting values that are too high increases the

noise of the amplifier. Table 25 lists the recommended resistor values for different gain settings.

Table 25. Recommended Resistor Values

INPUT RESISTOR

VALUE, R_in

FEEDBACK RESISTOR

VALUE, R_fb

DIFFERENTIAL

INPUT GAIN

INVERTING INPUT

GAIN

NON INVERTING

INPUT GAIN

10 kΩ

4.7 kΩ

10 kΩ

15 kΩ

20 kΩ

47 kΩ

1.0 V/V

1.5 V/V

2.0 V/V

10.0 V/V

–1.0 V/V

–1.5 V/V

–2.0 V/V

–10.0 V/V

2.0 V/V

2.5 V/V

3.0 V/V

11.0 V/V

C_in

R_in

–In

R_fb

–

+

S0446-01

Figure 48. Inverting Gain Configuration

Input-Blocking Capacitors

DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the

TAS5717/9. These capacitors block the DC portion of the audio source and allow the TAS5717/9 inputs to be

properly biased to provide maximum performance. The input blocking capacitors also limit the DC gain to 1,

limiting the DC-offset voltage at the output.

These capacitors form a high-pass filter with the input resistor, R_in. The cutoff frequency is calculated using

Equation 1. For this calculation, the capacitance used is the input-blocking capacitor and the resistance is the

input resistor chosen from Table 25, then the frequency and/or capacitance can be determined when one of the

two values is given.

1

fc_in

=

C_in=

2p ´ R_in´ C_in

2p ´ fc_in´ R_in

(1)

Using the TAS5717/9 as a 2nd order filter

Several audio DACs used today require an external low-pass filter to remove out of band noise. This is possible

with the TAS5717/9 as it can be used like a standard OPAMP. Several filter topologies can be implemented both

single ended and differential. In the figure below a Multi Feed Back (MFB), with differential input and single

ended input is shown.

An AC-coupling capacitor to remove dc-content from the source is shown, it serves to block any dc content from

the source and lowers the dc-gain to 1 helping reducing the output dc-offset to minimum.

58

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TAS5717

TAS5719

www.ti.com

SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

The component values can be calculated with the help of the TI FilterPro™ program available on the TI website

at:

http://focus.ti.com/docs/toolsw/folders/print/filterpro.html

Inverting Input

R2

C3

R1

C1

R3

–In

–

TAS5717

C2

+

S0447-01

Figure 49. Second-Order Active Low-Pass Filter

The resistor values should have a low value for obtaining low noise, but should also have a high enough value to

get a small size ac-coupling cap. C2 can be split in two with the midpoint connected to GND, this can increase

the common-mode attenuation.

Pop-Free Power Up

Pop-free power up is ensured by keeping the HP_SD low during power supply ramp up and down. The pin

should be kept low until the input AC-coupling capacitors are fully charged before asserting the HP_SD pin high,

this way proper pre-charge of the ac-coupling is performed and pop-less power-up is achieved. Figure 50

illustrates the preferred sequence.

Supply

HP_SD

Supply Ramp

Time for AC-Coupling

Capacitors to Charge

T0463-01

Figure 50. Power-Up/Down Sequence

Submit Documentation Feedback

59

Product Folder Link(s): TAS5717 TAS5719

TAS5717

TAS5719

SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

www.ti.com

REVISION HISTORY

Changes from Original (November 2010) to Revision A

Page

•

Changed the SNR typ value from 70°C to 105°C ............................................................................................................... 10

Deleted sub section titled 11.12 BANK SWITCHING ......................................................................................................... 31

Changed Table 3 rows 0x01, 0x03, 0x0E, 0x10, 0x1A, and 0x1C Initialization Values ..................................................... 33

Changed Table 3 rows 0x07, 0x08, 0x09, and 0x1A No of Bytes and Initialization Values ............................................... 33

Changed Table 3 row 0x46 and 0x4F Initialization Values ................................................................................................ 36

Changed Table 3 row 0x50 register name From: Bank switch control To: EQ control ...................................................... 36

Changed Table 3 row 0xF9 Initialization Value .................................................................................................................. 37

Changed Section 11.34 BANK SWITCH AND EQ CONTROL (0x50) to EQ CONTROL 90x50) ...................................... 55

Changed Table 24. Bank Switching Command (0x50) to EQ Command (0x50) ............................................................... 55

Changed the Function descriptions to: Reserved for D5, D2, D1, and D0 ......................................................................... 55

60

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Product Folder Link(s): TAS5717 TAS5719

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS5717PHPR

TAS5719PHPR

HTQFP

PHP

48

1000

330.0

16.4

9.6

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TAS5717PHPR

TAS5719PHPR

HTQFP

PHP

48

1000

367.0

38.0

Pack Materials-Page 2

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型号：	HPA02287PHPR
厂家：	TEXAS INSTRUMENTS
描述：	10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier 10 W / 15 W数字音频功率放大器集成无电容耳机放大器放大器功率放大器
文件：	总68页 (文件大小：1253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HPA02287PHPR [TI]

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