INA204AIDGST [TI]
带双路比较器的 -16V 至 80V、500kHz 电流感应放大器 | DGS | 10 | -40 to 125;型号: | INA204AIDGST |
厂家: | TEXAS INSTRUMENTS |
描述: | 带双路比较器的 -16V 至 80V、500kHz 电流感应放大器 | DGS | 10 | -40 to 125 放大器 光电二极管 比较器 |
文件: | 总39页 (文件大小:2148K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INA203, INA204, INA205
ZHCSFN6F –MARCH 2007 –REVISED JUNE 2021
INA20x –16-V 至80-V、500-kHz 电流感测放大器,带双比较器
1 特性
3 说明
• 完整的电流检测解决方案
• 有三种增益可供选择:
INA203、INA204 和 INA205 是一系列单向电流分流监
控器,具有电压输出、两个比较器和电压基准。
INA203、INA204 和INA205 能够在 -16V 至80V 范围
内的共模电压下检测分流器两端的压降。INA203、
INA204 和 INA205 可提供三种输出电压级别:
20V/V、50V/V 和100V/V,带宽高达500kHz。
– INA203 = 20V/V
– INA204 = 50V/V
– INA205 = 100V/V
• 两个比较器:
– 具有锁存功能的比较器1
– 带可选延迟的比较器2
• 共模范围:-16V 至80V
• 高准确度:过温条件下为3.5%(最大值)
• 带宽:500kHz
• 静态电流:1.8mA
• 封装:SO-14、TSSOP-14、VSSOP-10
INA203、INA204 和 INA205 还整合了两个带 0.6V 内
部基准的开漏比较器。14 引脚版本的比较器基准可用
外部输入覆盖。比较器 1 具有锁存功能,而比较器 2
的延迟可由用户通过编程设定。此外,14 引脚版本还
提供1.2V 基准输出。
INA203、INA204 和 INA205 由 2.7V 至 18V 单电源供
电。它们的额定工作温度范围为-40°C 至125°C。
2 应用
器件信息(1)
• 笔记本电脑
• 手机
• 电信设备
• 汽车
• 电源管理
• 电池充电器
• 焊接设备
封装尺寸(标称值)
器件型号
INA203、
INA204、
INA205
封装
SOIC (14)
8.65mm × 3.91mm
3.00mm × 3.00mm
5.00mm × 4.40mm
VSSOP (10)
TSSOP (14)
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
VIN+
VS
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN-
1.2V REF
1.2V REF OUT
CMP1 OUT
CMP2 OUT
CMP2 DELAY
CMP1 RESET
CMP1 IN-/0.6V REF
CMP1 IN+
CMP2 IN+
CMP2 IN-/0.6V REF
GND
8
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBOS393
INA203, INA204, INA205
ZHCSFN6F –MARCH 2007 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................25
11.1 Related Links.......................................................... 25
11.2 接收文档更新通知................................................... 25
11.3 支持资源..................................................................25
11.4 Trademarks............................................................. 25
11.5 Electrostatic Discharge Caution..............................25
11.6 术语表..................................................................... 25
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Current-Shunt Monitor.......6
6.6 Electrical Characteristics: Comparator........................7
6.7 Electrical Characteristics: Reference..........................9
6.8 Electrical Characteristics: General..............................9
6.9 Typical Characteristics..............................................10
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagrams....................................... 14
Information.................................................................... 25
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision E (November 2015) to Revision F (June 2021)
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Changed maximum input voltage for accurate measurements from: (VSHUNT –0.25) / Gain to: (VOUT
0.25) / Gain.......................................................................................................................................................15
Page
–
Changes from Revision D (May 2009) to Revision E (November 2015)
Page
• 添加了ESD 等级表、特性说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器
件和文档支持部分以及机械、封装和可订购信息部分.......................................................................................1
• Moved thermal values from Electrical Characteristics: General to Thermal Information table. Removed
duplicate storage temperature parameter...........................................................................................................9
Changes from Revision C (October 2007) to Revision D (May 2009)
Page
• Changed 图6-1 ................................................................................................................................................. 7
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Device Comparison
表5-1. Device Gain
DEVICE
INA203
INA204
INA205
GAIN
20 V/V
50 V/V
100 V/V
表5-2. Related Products
FEATURES
PRODUCT
Variant of INA203–INA205 Comparator 2 polarity
Current-shunt monitor with single Comparator and VREF
Current-shunt monitor only
INA206–INA208
INA200–INA202
INA193–INA198
INA270–INA271
Current-shunt monitor with split stages for filter options
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5 Pin Configuration and Functions
VIN+
VS
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN-
1.2V REF
1.2V REF OUT
CMP1 OUT
CMP2 OUT
CMP2 DELAY
CMP1 RESET
CMP1 IN-/0.6V REF
CMP1 IN+
CMP2 IN+
CMP2 IN-/0.6V REF
GND
8
图5-1. D and PW Packages 14-Pin SOIC and TSSOP Top View
VIN+
VS
OUT
1
2
3
4
5
10
9
VIN-
CMP1 OUT
CMP2 OUT
CMP1 RESET
CMP1 IN+
CMP2 IN+
GND
8
7
6
0.6V REF
图5-2. DGS Package 10-Pin VSSOP Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
VS
SOIC, TSSOP
VSSOP
1
2
1
2
I
Power Supply
Output voltage
OUT
O
Comparator 1 negative input, can be used to override the internal 0.6-
V reference
CMP1 IN-/0.6-V Ref
3
I
—
CMP1 IN+
CMP2 IN+
CMP2 IN–
4
5
3
I
I
I
Comparator 1 positive input
Comparator 2 positive input
Comparator 2 negative input
—
4
—
Comparator 2 negative input, can be used to override the internal 0.6-
V reference
6
I
CMP2 IN–/0.6-V Ref
—
GND
7
5
6
I
I
Ground
CMP1 RESET
CMP2 DELAY
CMP2 OUT
CMP1 OUT
1.2-V REF OUT
VIN–
8
Comparator 1 output reset, active low
Connect an optional capacitor to adjust comparator 2 delay
Comparator 2 output
9
I
—
7
10
11
12
13
14
O
O
O
I
8
Comparator 1 output
1.2-V reference output
—
9
Connect to shunt low side
Connect to shunt high side
VIN+
10
I
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN
MAX
UNIT
V
Supply Voltage, VS
18
18
V
Differential (VIN+) –(VIN–
Common-Mode
)
–18
Current-Shunt Monitor Analog
Inputs, VIN+ and VIN–
80
V
–16
Comparator Analog Input and Reset Pins
Analog Output, Out Pin
(VS) + 0.3
(VS) + 0.3
18
V
GND –0.3
GND –0.3
GND –0.3
GND –0.3
V
Comparator Output, Out Pin
VREF and CMP2 Delay Pin
Input Current Into Any Pin
Operating Temperature
V
10
V
5
mA
°C
°C
°C
150
–55
–65
–65
Junction Temperature
150
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–16
2.7
NOM
12
MAX
80
UNIT
V
VCM
VS
Common-mode input voltage
Operating supply voltage
12
18
V
TA
Operating free-air temperature
25
125
°C
–40
6.4 Thermal Information
INA20x
DGS (VSSOP) PW (TSSOP)
THERMAL METRIC (1)
D (SOIC)
14 PINS
84.9
UNIT
10 PINS
161.3
36.8
14 PINS
112.6
37.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44
39.4
82.3
55.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.3
1.3
2.7
ψJT
39.1
80.8
54.7
ψJB
RθJC(bot)
150
200
150
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: Current-Shunt Monitor
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN–= GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT
Full-Scale Sense Input
Voltage
(VS –0.25)/
VSENSE
0.15
V
V
VSENSE = VIN+ –VIN–
Gain
Common-Mode Input
Range
VCM
80
TA = –40°C to 125°C
VCM = –16 V to 80 V
VCM = 12 V to 80 V
–16
80
Common-Mode Rejection
Ratio
CMRR
100
dB
dB
TA = –40°C to
CMRR over Temperature
100
123
125°C
±0.5
±2.5
±3
mV
mV
mV
Offset Voltage, RTI (1)
25°C to 125°C
VOS
±3.5
–40°C to 25°C
Offset Voltage, RTI (1) vs.
Temperature
TA = –40°C to
125°C
dVOS/dT
PSR
IB
TMIN to TMAX
5
2.5
±9
μV/°C
μV/V
μA
Offset Voltage, RTI (1) vs.
Power Supply
VOUT = 2 V,
VCM = 18 V, 2.7 V
TA = –40°C to
125°C
100
±16
Input Bias Current,
VIN– Pin
TA = –40°C to 125°C
OUTPUT (VSENSE ≥20 mV)
INA203
INA204
INA205
20
50
V/V
V/V
V/V
G
Gain
100
Gain Error
VSENSE = 20 mV to 100 mV
±0.2%
±1%
±2%
Gain Error over
Temperature
VSENSE = 20 mV to
100 mV
TA = –40°C to
125°C
VSENSE = 120 mV,
VS = 16 V
Total Output Error (2)
±0.75%
±2.2%
±3.5%
Total Output Error (2) over
Temperature
VSENSE = 120 mV,
VS = 16 V
TA = –40°C to
125°C
Nonlinearity Error (3)
VSENSE = 20 mV to 100 mV
±0.002%
1.5
RO
Output Impedance, Pin 2
Ω
Maximum Capacitive Load No Sustained Oscillation
OUTPUT (VSENSE < 20 mV) (4)
INA203, INA204, INA205
10
nF
300
mV
–16 V ≤VCM < 0 V
output
INA203 output
INA204 output
INA205 output
0.4
1
V
V
V
0 V ≤VCM ≤VS, VS = 5 V
0 V ≤VCM ≤VS, VS = 5 V
0 V ≤VCM ≤VS, VS = 5 V
2
INA203, INA204, INA205
output
300
mV
VS < VCM ≤80 V
VOLTAGE OUTPUT (5)
Output Swing to the
Positive Rail
VIN– = 11 V,
VIN+ = 12 V
TA = –40°C to
125°C
V
V
(Vs) –0.15
(Vs) –0.25
VIN– = 0 V,
VIN+ = –0.5 V
TA = –40°C to
125°C
Output Swing to GND (6)
(VGND) + 0.004 (VGND) + 0.05
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At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN–= GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FREQUENCY RESPONSE
INA203; CLOAD = 5 pF
500
300
200
40
kHz
kHz
kHz
BW
Bandwidth
INA204; CLOAD = 5 pF
INA205; CLOAD = 5 pF
CLOAD < 10 nF
Phase Margin
Slew Rate
SR
1
V/μs
μs
VSENSE = 10 mVPP to 100 mVPP
CLOAD = 5 pF
,
Settling Time (1%)
2
NOISE, RTI
Output Voltage Noise
Density
nV/√
Hz
40
(1) Offset is extrapolated from measurements of the output at 20 mV and 100 mV VSENSE
.
(2) Total output error includes effects of gain error and VOS
(3) Linearity is best fit to a straight line.
.
(4) For details on this region of operation, see the Accuracy Variations as a Result Of VSENSE and Common-Mode Voltage section in the
Application and Implementation.
(5) See Typical Characteristic curve Positive Output Voltage Swing vs. Output Current (图6-8).
(6) Specified by design; not production tested.
6.6 Electrical Characteristics: Comparator
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Comparator Common-Mode Voltage =
Threshold Voltage
Offset Voltage
2
mV
Offset Voltage Drift,
Comparator 1
±2
TA = –40°C to 125°C
μV/°C
Offset Voltage Drift,
Comparator 2
5.4
TA = –40°C to 125°C
TA = 25°C
μV/°C
mV
Threshold
590
586
608
620
625
Threshold over
Temperature
mV
TA = –40°C to 125°C
Hysteresis (1), CMP1
Hysteresis (1), CMP2
mV
mV
TA = –40°C to 85°C
TA = –40°C to 85°C
–8
8
INPUT BIAS CURRENT (2)
CMP1 IN+, CMP2 IN+
0.005
10
15
nA
nA
CMP1 IN+, CMP2 IN+ vs.
Temperature
TA = –40°C to 125°C
INPUT IMPEDANCE
Pins 3 and 6 (14-pin
packages only)
10
kΩ
INPUT RANGE
CMP1 IN+ and CMP2
IN+
V
V
0 V to VS –1.5 V
0 V to VS –1.5 V
Pins 3 and 6 (14-pin
packages only) (3)
OUTPUT
Large-Signal Differential
Voltage Gain
CMP VOUT 1 V to 4 V, RL ≥15 kΩ
Connected to 5 V
200
V/mV
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At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.0001
220
MAX
1
UNIT
μA
mV
High-Level Output
Current
VID = 0.4 V, VOH = VS
Low-Level Output Voltage
300
VID = –0.6 V, IOL = 2.35 mA
RESPONSE TIME (4)
RL to 5 V, CL = 15 pF, 100-mV Input Step
with 5-mV Overdrive
Comparator 1
Comparator 2
1.3
1.3
μs
μs
RL to 5 V, CL = 15 pF, 100-mV Input Step
with 5-mV Overdrive, CDELAY Pin Open
RESET
RESET Threshold (5)
Logic Input Impedance
1.1
2
V
MΩ
Minimum RESET Pulse
Width
1.5
3
μs
μs
RESET Propagation
Delay
Comparator 2 Delay
Equation (6)
CDELAY = tD/5
0.5
μF
tD
Comparator 2 Delay
s
CDELAY = 0.1 μF
(1) Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the
noninverting input of the comparator; refer to 图6-1.
(2) Specified by design; not production tested.
(3) See the Comparator Maximum Input Voltage Range section in the Application and Implementation.
(4) The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
(5) The CMP1 RESET input has an internal 2-MΩ (typical) pulldown. Leaving the CMP1 RESET open results in a LOW state, with
transparent comparator operation.
(6) The Comparator 2 delay applies to both rising and falling edges of the comparator output.
VTHRESHOLD
0.592 0.6
VTHRESHOLD
0.6 0.608
Input Voltage
Input Voltage
Hysteresis = VTHRESHOLD - 8mV
a) CMP1
Hysteresis = VTHRESHOLD - 8mV
b) CMP2
图6-1. Comparator Hysteresis
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6.7 Electrical Characteristics: Reference
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE VOLTAGE
1.2-VREFOUT Output
Voltage
1.188
1.2
1.212
100
V
40
dVOUT/dT
Reference Drift
ppm/°C
v
TA = –40°C to 85°C
0.6-VREF Output
Voltage
0.6
Pins 3 and 6 of 14-pin packages only
40
100
2
dVOUT/dT
Reference Drift
ppm/°C
TA = –40°C to 85°C
LOAD REGULATION
Sourcing
dVOUT/dILOAD
0mA < ISOURCE < 0.5mA
0mA < ISINK < 0.5mA
0.4
0.4
1
mV/mA
mV/mA
mA
Sinking
ILOAD
Load Current
Line Regulation
30
dVOUT/dVS
2.7 V < VS < 18 V
μV/V
CAPACITIVE LOAD
Reference Output
10
10
Maximum Capacitive No Sustained Oscillations
Load
nF
OUTPUT IMPEDANCE
Output Impedance
Pins 3 and 6 of 14-Pin Packages Only
kΩ
6.8 Electrical Characteristics: General
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each
connected from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN–= GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Operating power supply
Quiescent current
2.7
18
V
TA = –40°C to 125°C
VOUT = 2 V
1.8
2.2
mA
Quiescent current over
temperature
VSENSE = 0 mV
2.8
mA
V
Comparator power-on
reset threshold (1)
1.5
TEMPERATURE
Specified temperature
Operating temperature
125
150
°C
°C
–40
–55
(1) The INA203, INA204, and INA205 are designed to power-up with the comparator in a defined reset state as long as CMP1 RESET is
open or grounded. The comparator will be in reset as long as the power supply is below the voltage shown here. The comparator
assumes a state based on the comparator input above this supply voltage. If CMP1 RESET is high at power-up, the comparator output
comes up high and requires a reset to assume a low state, if appropriate.
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6.9 Typical Characteristics
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, and VSENSE = 100 mV, unless otherwise noted.
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
CLOAD = 1000pF
G = 100
G = 50
G = 100
G = 50
G = 20
G = 20
10k
100k
1M
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
图6-2. Gain vs. Frequency
图6-3. Gain vs. Frequency
20
18
16
14
12
10
8
140
130
120
110
100
90
100V/V
CMR
50V/V
PSR
80
20V/V
70
6
60
4
50
2
40
0
10
100
1k
10k
100k
20 100 200 300 400 500 600 700 800 900
VDIFFERENTIAL (mV)
Frequency (Hz)
图6-5. Common-Mode and Power-Supply
图6-4. Gain Plot
Rejection vs. Frequency
4.0
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
50
100 150 200
VSENSE (mV)
250 300
350 400 450
500
-8 -4
0
16 20
...
76
80
-16 -12
4
8
12
Common-Mode Voltage (V)
图6-6. Total Output Error vs. VSENSE
图6-7. Total Output Error vs. Common-Mode
Voltage
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3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
11
VS = 12V
Sourcing Current
10
9
8
7
6
5
4
3
2
1
0
+25°C
-40°C
+125°C
VS = 3V
Sourcing Current
-40°C
+25°C
Output stage is designed
to source current. Current
sinking capability is
approximately 400mA.
+125°C
5
10
20
25
0
15
30
1
2
0
3
4
5
6
7
8
9
10
Output Current (mA)
Output Voltage (V)
图6-8. Positive Output Voltage Swing vs. Output
图6-9. Quiescent Current vs. Output Voltage
Current
2.00
34
VSENSE = 100mV
-40°C
30
1.75
+25°C
VS = 2.7V
VS = 12V
26
1.50
1.25
1.00
0.75
0.50
+125°C
22
18
14
10
VS = 12V
VS = 2.7V
VSENSE = 0mV
6
-8 -4
0
4
20 24 28 32
36
-16 -12
8
12 16
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 17 18
VCM (V)
Supply Voltage (V)
图6-10. Quiescent Current vs. Common-Mode
图6-11. Output Short-Circuit Current vs. Supply
Voltage
Voltage
G = 20
G = 20
VSENSE = 20mV to 30mV
VSENSE = 20mV to 110mV
Time (2ms/div)
Time (2ms/div)
图6-12. Step Response
图6-13. Step Response
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G = 20
G = 50
G = 100
G = 50
VSENSE = 90mV to 100mV
VSENSE = 20mV to 30mV
Time (5ms/div)
Time (2ms/div)
图6-15. Step Response
图6-14. Step Response
G = 50
VSENSE = 20mV to 110mV
VSENSE = 90mV to 100mV
Time (5ms/div)
Time (5ms/div)
图6-16. Step Response
图6-17. Step Response
600
500
400
300
200
100
0
VSENSE = 20mV to 110mV
Time (10ms/div)
0
1
2
3
4
5
6
.
ISINK (mA)
图6-18. Step Response
图6-19. Comparator VOL vs. ISINK
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600
599
598
597
596
595
594
593
592
591
602
601
600
599
598
597
596
590
2
4
6
8
10
12
14
16
-25
0
25
50
18
-50
75
100
125
Supply Voltage (V)
Temperature (°C)
图6-20. Comparator Trip Point vs. Supply Voltage
图6-21. Comparator Trip Point vs. Temperature
200
1.2
175
150
125
100
75
1.0
0.8
0.6
0.4
0.2
0
50
0
20
40
60
80 100 120 140 160 180 200
2
4
6
8
10
12
14
16
18
Overdrive Voltage (mV)
Supply Voltage (V)
图6-22. Comparator 1 Propagation Delay vs.
图6-23. Comparator Reset Voltage vs. supply
Overdrive Voltage
Voltage
300
275
250
225
200
175
150
125
Input
200mV/div
Output
2V/div
VOD = 5mV
-50
-25
0
25
50
75
100
125
2ms/div
Temperature (°C)
.
图6-25. Comparator Propagation Delay
图6-24. Comparator Propagation Delay vs.
Temperature
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7 Detailed Description
7.1 Overview
The INA203, INA204, and INA205 are a family of unidirectional current-shunt monitors with voltage output, dual
comparators, and voltage reference. The INA203, INA204, and INA205 can sense drops across shunts at
common-mode voltages from –16 V to 80 V. The INA203, INA204, and INA205 are available with three output
voltage scales: 20 V/V, 50 V/V, and 100 V/V, with up to 500-kHz bandwidth. The INA203, INA204, and INA205
also incorporate two open-drain comparators with internal 0.6-V references. On 14-pin versions, the comparator
references can be overridden by external inputs. Comparator 1 includes a latching capability, and Comparator 2
has a user-programmable delay. 14-pin versions also provide a 1.2-V reference output. The INA203, INA204,
and INA205 operate from a single 2.7-V to 18-V supply. They are specified over the extended operating
temperature range of –40°C to 125°C.
7.2 Functional Block Diagrams
VIN+
VS
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
VIN-
1.2V REF
1.2V REF OUT
CMP1 OUT
CMP2 OUT
CMP2 DELAY
CMP1 RESET
CMP1 IN-/0.6V REF
CMP1 IN+
CMP2 IN+
CMP2 IN-/0.6V REF
GND
8
图7-1. SO-14, TSSOP-14 Functional Block Diagram
VIN+
VS
OUT
1
2
3
4
5
10
9
VIN-
CMP1 OUT
CMP2 OUT
CMP1 RESET
CMP1 IN+
CMP2 IN+
GND
8
7
6
0.6V REF
图7-2. VSSOP-10 Functional Block Diagram
7.3 Feature Description
7.3.1 Basic Connections
图 7-3 shows the basic connections of the INA203, INA204, and INA205. The input pins, VIN+ and VIN–, should
be connected as closely as possible to the shunt resistor to minimize any resistance in series with the shunt
resistance.
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
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RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
VIN+
VIN-
INA203
RPULL-UP
4.7kW
RPULL-UP
4.7kW
x20
OUT
Current Shunt
Monitor Output
1.2V REF
CMP1 IN-/0.6 REF
1.2V REF OUT
CMP1 OUT
CMP1 IN+
CBYPASS
CMP2 IN+
CMP2 OUT
0.01mF
CMP2 IN-/0.6 REF
CMP2 DELAY
Optional Delay
Capacitor
0.2mF
GND
CMP1 RESET
Transparent/Reset
Latch
图7-3. INA20x Basic Connection
7.3.2 Selecting RSHUNT
The value chosen for the shunt resistor, RSHUNT, depends on the application and is a compromise between
small-signal accuracy and maximum permissible voltage loss in the measurement line. High values of RSHUNT
provide better accuracy at lower currents by minimizing the effects of offset, while low values of RSHUNT minimize
voltage loss in the supply line. For most applications, best performance is attained with an RSHUNT value that
provides a full-scale shunt voltage range of 50 mV to 100 mV. Maximum input voltage for accurate
measurements is (VOUT –0.25) / Gain.
7.3.3 Comparator
The INA203, INA204, and INA205 devices incorporate two open-drain comparators. These comparators typically
have 2 mV of offset and a 1.3-μs (typical) response time. The output of Comparator 1 latches and is reset
through the CMP1 RESET pin, as shown in 图 7-5. This configuration applies to both the 10- and 14-pin
versions. 图7-4 illustrates the comparator delay.
The 14-pin versions of the INA203, INA204, and INA205 devices include additional features for comparator
functions. The comparator reference voltage of both Comparator 1 and Comparator 2 can be overridden by
external inputs for increased design flexibility. Comparator 2 has a programmable delay.
7.3.4 Comparator Delay (14-Pin Version Only)
The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see 图
7-3. The capacitor value (in μF) is selected by using 方程式1:
tD
CDELAY (in mF) =
5
(1)
A simplified version of the delay circuit for Comparator 2 is shown in 图 7-4. The delay comparator consists of
two comparator stages with the delay between them. I1 and I2 cannot be turned on simultaneously; I1
corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1
output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120 nA to CDELAY. The voltage at U2 +IN
begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while
the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value of
the delay specified for CDELAY). This entire sequence is reversed when the comparator outputs go low, so that
returning to low exhibits the same delay.
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1.2V
I2
120nA
U1
U2
I1
120nA
0.6V
CDELAY
图7-4. Simplified Model of the Comparator 2 Delay Circuit
0.6V
VIN
0V
CMP Out
RESET
图7-5. Comparator Latching Capability
Take care to note what will happen if events occur more rapidly than the delay timeout; for example, when the
U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6-V transition for
U2. The voltage at U2 +IN ramps back down at a rate determined by the value of CDELAY, and only returns to
zero if given sufficient time.
In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the
model shown in 图7-4.
7.3.5 Comparator Maximum Input Voltage Range
The maximum voltage at the comparator input for normal operation is up to (Vs) – 1.5 V. There are special
considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough to
drive 1 mA back into the reference introduces errors into the reference. 图7-6 shows the basic input structure. A
general guideline is to limit the voltage on both inputs to a total of 20 V. The exact limit depends on the available
voltage and whether either or both inputs are subject to the large voltage. When making this determination,
consider the 20 kΩ from each input back to the comparator. 图7-7 shows the maximum input voltage that avoids
creating a reference error when driving both inputs (an equivalent resistance back into the reference of 10 kΩ).
£ 1mA
1.2V
20kW
20kW
CMP1 IN-
CMP2 IN+
图7-6. Limit Current Into Reference ≤1 mA
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RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
VIN+
VIN-
INA203
RPULL-UP
4.7kW
RPULL-UP
4.7kW
x20
OUT
Current Shunt Monitor Output
V < 11.2
1.2V REF
CMP1 IN-/0.6 REF
1.2V REF OUT
CMP1 OUT
CMP1 IN+
CBYPASS
0.01mF
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
Optional Delay
Capacitor
0.2mF
GND
CMP1 RESET
Transparent/Reset
Latch
图7-7. Overdriving Comparator Inputs Without Generating a Reference Error
Raychem
Polyswitch
Load
< 18V
+5V Supply
Battery
3.3kW
VS+
VIN+
VIN-
INA203
Pull-Up
x20
OUT
Resistors
1.2V REF
CMP1 IN-
1.2V REF OUT
CMP1 OUT
CMP1 IN+
Overlimit(1)
Warning(1)
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
图7-8. Polyswitch Warning and Fault Detection Circuit
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RSHUNT
0.02W
Load
Q2
NDS8434A
R1
100kW
+5V Supply
R7
1kW
Q1
2N3904
VS+
VIN+
VIN-
INA203
x20
OUT
R2
1kW
1.2V REF
CMP1 IN-
1.2V REF OUT
CMP1 OUT
R5
R3
CMP1 IN+
100kW
14kW
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
R6
R4
GND
CMP1 RESET
Reset
6.04kW
6.04kW
CBYPASS
0.01mF
Latch
图7-9. Lead-Acid Battery Protection Circuit
7.4 Device Functional Modes
7.4.1 Input Filtering
An obvious and straightforward location for filtering is at the output of the INA203, INA204, and INA205 series;
however, this location negates the advantage of the low output impedance of the internal buffer. The only other
option for filtering is at the input pins of the INA203, INA204, and INA205, which is complicated by the internal 5
kΩ + 30% input impedance; this configuration is illustrated in 图 7-10. Using the lowest possible resistor values
minimizes both the initial shift in gain and effects of tolerance. Use 方程式2 to calculate the effect on initial gain.
5kW
Gain Error % = 100 - 100 ´
5kW + RFILT
(2)
Total effect on gain error can be calculated by replacing the 5-kΩ term with 5 kΩ – 30%, (or 3.5 kΩ) or 5 kΩ +
30% (or 6.5 kΩ). The tolerance extremes of RFILT can also be inserted into the equation. If a pair of 100 Ω 1%
resistors are used on the inputs, the initial gain error will be 1.96%. Worst-case tolerance conditions will always
occur at the lower excursion of the internal 5-kΩ resistor (3.5 kΩ), and the higher excursion of RFILT –3% in this
case.
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RSHUNT << RFILTER
3mW
VSUPPLY
Load
RFILTER < 100W
RFILTER <100W
CFILTER
INA203-INA205
VIN+
14
VIN-
VS
OUT
1
2
3
4
5
6
7
13
1.2V REF
1.2V REF OUT
CMP1 IN-/0.6V REF
CMP1 IN+
12
11
10
9
CMP1 OUT
f-3dB
CMP2 OUT
CMP2 IN+
1
f-3dB
=
CMP2 DELAY
CMP1 RESET
2p(2RFILTER)CFILTER
CMP2 IN-/0.6V REF
GND
8
SO-14, TSSOP-14
图7-10. Input Filter (Gain Error: 1.5% to –2.2%)
The specified accuracy of the INA203, INA204, and INA205 must then be combined in addition to these
tolerances. While this discussion treated accuracy worst-case conditions by combining the extremes of the
resistor values, it is appropriate to use geometric mean or root sum square calculations to total the effects of
accuracy variations.
7.4.2 Accuracy Variations as a Result Of VSENSE and Common-Mode Voltage
The accuracy of the INA203, INA204, and INA205 current shunt monitors is a function of two main variables:
V
SENSE (VIN+ – VIN–) and common-mode voltage, VCM, relative to the supply voltage, VS. VCM is expressed as
(VIN+ + VIN–) / 2; however, in practice, VCM is seen as the voltage at VIN+ because the voltage drop across
VSENSE is usually small.
This section addresses the accuracy of these specific operating regions:
• Normal Case 1: VSENSE ≥20 mV, VCM ≥VS
• Normal Case 2: VSENSE ≥20 mV, VCM < VS
• Low VSENSE Case 1: VSENSE < 20 mV, –16 V ≤VCM < 0
• Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤VCM ≤VS
• Low VSENSE Case 3: VSENSE < 20 mV, VS < VCM ≤80 V
7.4.2.1 Normal Case 1: VSENSE ≥20 mV, VCM ≥VS
This region of operation provides the highest accuracy. Here, the input offset voltage is characterized and
measured using a two-step method. First, the gain is determined by 方程式3.
VOUT1 - VOUT2
G =
100mV - 20mV
(3)
where
• VOUT1 = Output Voltage with VSENSE = 100 mV.
• VOUT2 = Output Voltage with VSENSE = 20 mV.
Then the offset voltage is measured at VSENSE = 100 mV and referred to the input (RTI) of the current shunt
monitor, as shown in 方程式4.
VOUT1
VOSRTI (Referred-To-Input) =
- 100mV
G
(4)
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In the Typical Characteristics, 图6-7 shows the highest accuracy for this region of operation. In this plot, VS = 12
V; for VCM ≥ 12 V, the output error is at its minimum. This case is also used to create the VSENSE ≥ 20-mV
output specifications in the Electrical Characteristics: Current-Shunt Monitor table.
7.4.2.2 Normal Case 2: VSENSE ≥20 mV, VCM < VS
This region of operation has slightly less accuracy than Normal Case 1 as a result of the common-mode
operating area in which the part functions, as seen in 图 6-7. As noted, for this graph VS = 12 V; for VCM < 12 V,
the Output Error increases as VCM becomes less than 12 V, with a typical maximum error of 0.005% at the most
negative VCM = –16 V.
7.4.2.3 Low VSENSE Case 1
• VSENSE < 20 mV, –16 V ≤VCM< 0;
• Low VSENSE Case 3:
• VSENSE < 20 mV, VS < VCM ≤80 V
Although the INA203 family of devices are not designed for accurate operation in either of these regions, some
applications are exposed to these conditions; for example, when monitoring power supplies that are switched on
and off while VS is still applied to the INA203, INA204, or INA205. Take care to know what the behavior of the
devices will be in these regions.
As VSENSE approaches 0 mV, in these VCM regions, the device output accuracy degrades. A larger-than-normal
offset can appear at the current shunt monitor output with a typical maximum value of VOUT = 300 mV for VSENSE
= 0 mV. As VSENSE approaches 20 mV, VOUT returns to the expected output value with accuracy as specified in
the Electrical Characteristics: Current-Shunt Monitor. 图 7-11 illustrates this effect using the INA205 (Gain =
100).
2.0
1.8
1.6
1.4
1.2
Actual
1.0
0.8
Ideal
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
VSENSE (mV)
图7-11. Example for Low VSENSE Cases 1 and 3 (INA205, Gain = 100)
7.4.2.4 Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤VCM ≤VS
This region of operation is the least accurate for the INA203 family. To achieve the wide input common-mode
voltage range, these devices use two op amp front ends in parallel. One operational amplifier front end operates
in the positive input common-mode voltage range, and the other in the negative input region. For this case,
neither of these two internal amplifiers dominates and overall loop gain is very low. Within this region, VOUT
approaches voltages close to linear operation levels for Normal Case 2. This deviation from linear operation
becomes greatest the closer VSENSE approaches 0 V. Within this region, as VSENSE approaches 20 mV, device
operation is closer to that described by Normal Case 2. 图 7-12 illustrates this behavior for the INA205. The
VOUT maximum peak for this case is tested by maintaining a constant VS, setting VSENSE = 0 mV, and sweeping
VCM from 0 V to VS. The exact VCM at which VOUT peaks during this test varies from part to part, but the VOUT
maximum peak is tested to be less than the specified VOUT Tested Limit.
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2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
INA205 VOUT Tested Limit(1)
VCM1
Ideal
VCM2
VCM3
VOUT Tested Limit at
VCM4
VSENSE = 0mV, 0 £ VCM1 £ VS
.
VCM2, VCM3, and VCM4 illustrate the variance
from part to part of the VCM that can cause
maximum VOUT with VSENSE < 20mV.
0
2
4
6
8
10 12 14 16 18 20 22 24
VSENSE (mV)
NOTE: (1) INA203 VOUT Tested Limit = 0.4V. INA204 VOUT Tested Limit = 1V.
图7-12. Example For Low VSENSE Case 2 (INA205, Gain = 100)
7.4.3 Transient Protection
The –16 V to 80 V common-mode range of the INA203, INA204, and INA205 is ideal for withstanding
automotive fault conditions ranging from 12-V battery reversal up to 80-V transients, since no additional
protective components are needed up to those levels. In the event that the INA203, INA204, and INA205 are
exposed to transients on the inputs in excess of their ratings, then external transient absorption with
semiconductor transient absorbers (Zeners or Transzorbs) are necessary. Use of metal oxide varistors (MOVs)
or video disk recorders (VDRs) is not recommended except when they are used in addition to a semiconductor
transient absorber. Select the transient absorber such that it will never allow the INA203, INA204, and INA205 to
be exposed to transients greater than 80 V (that is, allow for transient absorber tolerance, as well as additional
voltage because of transient absorber dynamic impedance). Despite the use of internal Zener-type ESD
protection, the INA203, INA204, and INA205 do not lend themselves to using external resistors in series with the
inputs because the internal gain resistors can vary up to ±30% but are closely matched. (If gain accuracy is not
important, then resistors can be added in series with the INA203, INA204, and INA205 inputs with two equal
resistors on each input.)
7.4.4 Output Voltage Range
The output of the INA203, INA204, and INA205 is accurate within the output voltage swing range set by the
power-supply pin, VS. This performance is best illustrated when using the INA205 (a gain of 100 version), where
a 100-mV full-scale input from the shunt resistor requires an output voltage swing of 10 V, and a power-supply
voltage sufficient to achieve 10 V on the output.
7.4.5 Reference
The INA203, INA204, and INA205 include an internal voltage reference that has a load regulation of 0.4 mV/mA
(typical), and not more than 100 ppm/°C of drift. Only the 14-pin package allows external access to reference
voltages, where voltages of 1.2 V and 0.6 V are both available. Output current versus output voltage is illustrated
in the Typical Characteristics section.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The INA203, INA204, and INA205 series is designed to enable easy configuration for detecting overcurrent
conditions and current monitoring in an application. This device is also incorporate two open-drain comparators
with internal 0.6-V references. On 14-pin versions, the comparator references can be overridden by external
inputs. Comparator 1 includes a latching capability, and Comparator 2 has a user-programmable delay. 14-pin
versions also provide a 1.2-V reference output. This device can also be paired with minimum additional devices
to create more sophisticated monitoring functional blocks.
8.2 Typical Application
Raychem
Polyswitch
Load
< 18V
+5V Supply
Battery
3.3kW
VS+
VIN+
VIN-
INA203
Pull-Up
x20
OUT
Resistors
1.2V REF
CMP1 IN-
1.2V REF OUT
CMP1 OUT
CMP1 IN+
Overlimit(1)
Warning(1)
CMP2 IN+
CMP2 OUT
CMP2 IN-
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
图8-1. Polyswitch Warning and Fault Detection Circuit
8.2.1 Design Requirements
The device measures current through a resistive shunt with current flowing in one direction, thus enabling
detection of an overlimit or warning event only when the differential input voltage exceeds the corresponding
threshold limits. When the current reaches the warning limit of 0.6 V, the output of CMP2 will transition high
indicating a warning condition. When the current further increases to or past the overlimit limit of 1.2 V, the
output of CMP1 will transition high indicating an overlimit condition. Optional CDELAY can be sized to add delay to
CMP1.
8.2.2 Detailed Design Procedure
图 8-1 shows the basic connections of the device. The input terminals, IN+ and IN–, should be connected as
closely as possible to the current-sensing resistor or polymeric switch to minimize any resistance in series with
the shunt resistance. Additional resistance between the current-sensing resistor and input terminals can result in
errors in the measurement. When input current flows through this external input resistance, the voltage
developed across the shunt resistor can differ from the voltage reaching the input terminals.
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8.2.3 Application Curves
6
6
5.5
5
RESET(V)
COMP1(V)
VOUT(V)
COMP1(V)
VOUT(V)
COMP2_No_Delay(V)
COMP2_Delay(V)
5.5
COMP2(V)
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
100
200
300
400
500
Time(mS)
600
700
800
900
1000
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500
Time(mS)
图8-2. Polyswitch Warning and Fault Detection
图8-3. Polyswitch Warning and Fault Detection
Circuit Response
Circuit With Delay Response
9 Power Supply Recommendations
The input circuitry of the INA203, INA204, and INA205 can accurately measure beyond the power-supply
voltage, VS. For example, the VS power supply can be 5 V, whereas the load power-supply voltage is up to 80 V.
The output voltage range of the OUT terminal, however, is limited by the voltages on the power-supply pin.
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10 Layout
10.1 Layout Guidelines
• Connect the input pins to the sensing resistor using a Kelvin or 4-wire connection. This connection technique
ensures that only the current-sensing resistor impedance is detected between the input pins. Poor routing of
the current-sensing resistor commonly results in additional resistance present between the input pins. Given
the very low ohmic value of the current resistor, any additional high-current carrying impedance can cause
significant measurement errors.
• The power-supply bypass capacitor should be placed as closely as possible to the supply and ground pins.
The recommended value of this bypass capacitor is 0.1 μF. Additional decoupling capacitance can be added
to compensate for noisy or high-impedance power supplies.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Supply Voltage
VIN+
Vs
Shunt Resistor
OUT
VIN-
Supply Bypass
Capacitor
CMP1 IN-
/0.6V Ref
1.2V REF
OUT
CMP1
IN+
CMP1 OUT
CMP2 OUT
CMP2
IN+
CMP2 IN-
/0.6V Ref
CMP2
DELAY
CMP1
RESET
GND
Pull-ups
图10-1. Layout Recommendation
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
INA203
INA204
INA205
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA203AID
INA203AIDGSR
INA203AIDGST
INA203AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
DGS
DGS
D
14
10
10
14
14
14
14
10
10
14
14
10
10
14
14
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
INA203A
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
50 RoHS & Green
BQN
BQN
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
INA203A
INA203A
INA203A
INA204A
BQO
INA203AIPW
INA203AIPWR
INA204AID
TSSOP
TSSOP
SOIC
PW
PW
D
INA204AIDGSR
INA204AIDGST
INA204AIDR
VSSOP
VSSOP
SOIC
DGS
DGS
D
2500 RoHS & Green Call TI | NIPDAUAG
250 RoHS & Green Call TI | NIPDAUAG
2500 RoHS & Green
50 RoHS & Green
BQO
NIPDAU
NIPDAU
INA204A
INA205A
BQP
INA205AID
SOIC
D
INA205AIDGSR
INA205AIDGST
INA205AIDR
VSSOP
VSSOP
SOIC
DGS
DGS
D
2500 RoHS & Green Call TI | NIPDAUAG
250
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
BQP
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
INA205A
INA205A
INA205A
INA205AIPW
INA205AIPWR
TSSOP
TSSOP
PW
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA203 :
Automotive : INA203-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA203AIDGSR
INA203AIDR
VSSOP
SOIC
DGS
D
10
14
14
14
10
14
14
2500
2500
2000
2500
250
330.0
330.0
330.0
330.0
180.0
330.0
330.0
12.4
16.4
12.4
16.4
12.4
16.4
12.4
5.3
6.5
6.9
6.5
5.3
6.5
6.9
3.4
9.0
5.6
9.0
3.4
9.0
5.6
1.4
2.1
1.6
2.1
1.4
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
INA203AIPWR
INA204AIDR
TSSOP
SOIC
PW
D
INA205AIDGST
INA205AIDR
VSSOP
SOIC
DGS
D
2500
2000
INA205AIPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA203AIDGSR
INA203AIDR
VSSOP
SOIC
DGS
D
10
14
14
14
10
14
14
2500
2500
2000
2500
250
367.0
356.0
367.0
356.0
210.0
356.0
367.0
367.0
356.0
367.0
356.0
185.0
356.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
INA203AIPWR
INA204AIDR
TSSOP
SOIC
PW
D
INA205AIDGST
INA205AIDR
VSSOP
SOIC
DGS
D
2500
2000
INA205AIPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
INA203AID
INA203AIPW
INA204AID
INA205AID
INA205AIPW
D
PW
D
SOIC
TSSOP
SOIC
14
14
14
14
14
50
90
50
50
90
506.6
530
8
10.2
8
3940
3600
3940
3940
3600
4.32
3.5
506.6
506.6
530
4.32
4.32
3.5
D
SOIC
8
PW
TSSOP
10.2
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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