INA212-Q1 [TI]
36-V, Single-Supply, 10-MHz, Rail-to-Rail Output Operational Amplifiers; 36 -V ，单电源， 10 - MHz的轨至轨输出运算放大器
| 型号： | INA212-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36-V, Single-Supply, 10-MHz, Rail-to-Rail Output Operational Amplifiers |
| 文件： | 总29页 (文件大小：3007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA172
OPA2172
OPA4172
www.ti.com
SBOS618 –DECEMBER 2013
36-V, Single-Supply, 10-MHz, Rail-to-Rail Output
Operational Amplifiers
Check for Samples: OPA172, OPA2172, OPA4172
1
FEATURES
DESCRIPTION
The OPA172, OPA2172 and OPA4172 (OPAx172)
23
•
Wide Supply Range: +4.5 V to +36 V, ±2.25 V to
±18 V
are family of 36-V, single-supply, low-noise
a
operational amplifiers with the ability to operate on
supplies ranging from +4.5 V (±2.25 V) to +36 V (±18
V). This latest addition of high voltage CMOS
operational amplifiers, in conjunction with the
•
Low Offset Voltage: ±0.2 mV
Low Offset Drift: ±0.3 µV/°C
•
•
•
•
•
•
•
•
•
•
•
Gain Bandwidth: 10 MHz
OPAx171 and OPAx170 provide
a
family of
Low Input Bias Current: ±8 pA
Low Quiescent Current: 1.6 mA per Amplifier
Low Noise: 6 nV/√Hz
bandwidth, noise, and power options to meet the
needs of a wide variety of applications. The OPAx172
are available in micropackages and offer low offset,
drift, and quiescent current. These devices also offer
wide bandwidth, fast slew rate, and high output
current drive capability. The single, dual, and quad
versions all have identical specifications for maximum
design flexibility.
EMI and RFI Filtered Inputs
Input Range Includes the Negative Supply
Input Range Operates to Positive Supply
Rail-to-Rail Output
Unlike most op amps, which are specified at only one
supply voltage, the OPAx172 family is specified from
+4.5 V to +36 V. Input signals beyond the supply rails
do not cause phase reversal. The input can operate
100 mV below the negative rail and within 2 V of the
top rail during normal operation. Note that these
devices can operate with full rail-to-rail input 100 mV
beyond the top rail, but with reduced performance
within 2 V of the top rail.
High Common-Mode Rejection: 120 dB
Industry-Standard Packages:
–
–
–
–
8-Pin SOIC
8-Pin MSOP
14-Pin SOIC
14-Pin TSSOP
•
microPackages:
Single in SC-70, SOT-23
–
The OPAx172 series of op amps are specified from
–40°C to +125°C.
APPLICATIONS
PRODUCT FAMILY
•
•
•
•
•
•
•
•
•
Tracking Amplifier in Power Modules
Merchant Power Supplies
Transducer Amplifiers
Bridge Amplifiers
DEVICE
PACKAGE
SC-70, SOT23-5, SO-8
SO-8, MSOP-8
OPA172 (single)(1)
OPA2172 (dual)
OPA4172 (quad)
TSSOP-14, SO-14
Temperature Measurements
Strain Gauge Amplifiers
Precision Integrators
AMPLIFIER SELECTION TABLE
QUIESCENT
CURRENT
(IQ)
GAIN
BANDWIDTH
(GBW)
VOLTAGE
NOISE DENSITY
(en)
Battery-Powered Instruments
Test Equipment
DEVICE
OPAx172
OPAx171
OPAx170
1600 µA
475 µA
110 µA
10 MHz
3.0 MHz
1.2 MHz
6 nV/√Hz
14 nV/√Hz
19 nV/√Hz
(1) OPA172 SO-8 package is production data. All other devices
are product preview.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
OPA172
OPA2172
OPA4172
SBOS618 –DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
V
Supply voltage
±20 (+40 single supply)
Common-mode
Differential
(V–) – 0.5 to (V+) + 0.5
V
Voltage(2)
Current
Signal input
terminals
±0.5
±10
V
mA
Output short circuit(3)
Operating temperature
Storage temperature
Junction temperature
Continuous
–55 to +150
–65 to +150
+150
°C
°C
°C
kV
Electrostatic
discharge (ESD)
ratings:
Human body model (HBM)
Charged device model (CDM)
4
1
kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Transient conditions that exceed these voltage ratings should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
2
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SBOS618 –DECEMBER 2013
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS/2, and RL = 10 kΩ connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
Over temperature
Drift
±0.2
±1
±1.15
±1.5
±3
mV
mV
TA = –40°C to +125°C
dVOS/dT
PSRR
TA = –40°C to +125°C
TA = –40°C to +125°C
±0.3
±1
µV/°C
µV/V
vs power supply
INPUT BIAS CURRENT
IB
Input bias current
±8
±2
±15
±14
±15
±1
pA
nA
pA
nA
Over temperature
Input offset current
Over temperature
TA = –40°C to +125°C
TA = –40°C to +125°C
IOS
NOISE
En
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 100 Hz
1.2
8.6
6
µVPP
nV/√Hz
nV/√Hz
Input voltage noise
density
en
in
f = 1 kHz
Input current noise
density
f = 1 kHz
1.6
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
VCM
(V–) – 0.1 V
(V+) – 2 V
V
range(1)
VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
90
104
120
dB
dB
Common-mode rejection
ratio
CMRR
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C
110
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
100 || 4
6 || 4
MΩ || pF
1013Ω || pF
(V–) + 0.35 V < VO < (V+) – 0.35 V, RL = 10 kΩ,
TA = –40°C to +125°C
110
130
116
dB
dB
AOL
Open-loop voltage gain
(V–) + 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ,
TA = –40°C to +125°C
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
10
10
MHz
V/µs
µs
Slew rate
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V step
VIN × Gain > VS
2
tS
Settling time
3.2
200
µs
Overload recovery time
ns
Total harmonic distortion
+ noise
THD+N
VS = +36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS
0.00005
%
(1) The input range can be extended beyond (V+) – 2 V up to (V+) + 0.1 V. See the Typical Characteristics and Application Information
sections for additional information.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS/2, and RL = 10 kΩ connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
75
330
80
400
20
mV
mV
mV
mV
mV
mV
mV
mV
mA
pF
VS = +36 V
VS = +4.5V
VS = +36 V
VS = +4.5 V
Voltage output swing
from rail
VO
10
40
50
105
110
530
20
480
Over temperature
15
55
70
ISC
Short-circuit current
Capacitive load drive
+75/–75
CLOAD
See Typical Characteristics
60
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
+4.5
+36
1.8
2
V
Quiescent current per
amplifier
IO = 0 A
1.6
mA
mA
Over temperature
IO = 0 A, TA = –40°C to +125°C
TEMPERATURE
Specified range
Operating range
–40
–55
+125
+150
°C
°C
THERMAL INFORMATION: OPA172
OPA172
THERMAL METRIC(1)
D (SO)
8 PINS
126.5
80.6
DBV (SOT23)
5 PINS
227.9
115.7
65.9
DCK (SC-70)
UNITS
5 PINS
285.2
60.5
78.9
0.8
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
67.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
31.0
10.7
ψJB
66.6
65.3
77.9
N/A
θJC(bottom)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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OPA172
OPA2172
OPA4172
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SBOS618 –DECEMBER 2013
PIN CONFIGURATIONS
DCK PACKAGE: OPA172
SC-70
D AND DGK PACKAGES: OPA2172
SO-8 AND MSOP-8
(TOP VIEW)
(TOP VIEW)
V+
IN+
V-
1
2
3
5
4
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
OUT
IN-
DBV PACKAGE: OPA172
SOT23-5
(TOP VIEW)
D AND PW PACKAGES: OPA4172
SO-14 AND TSSOP-14
(TOP VIEW)
V+
OUT
V-
1
2
3
5
4
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
-IN
+IN
D PACKAGE: OPA172
SO-8
+IN B
-IN B
OUT B
10 +IN C
(TOP VIEW)
9
8
-IN C
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC(1)
V+
OUT C
OUT
NC(1)
(1) No internal connection.
NOTE: OPA172 D package is production data. All other packages are product preview.
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SBOS618 –DECEMBER 2013
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TYPICAL CHARACTERISTICS: TABLE OF GRAPHS
Table 1. List of Typical Characteristics
DESCRIPTION
Offset Voltage Production Distribution
FIGURE
Figure 1
Offset Voltage Drift Distribution
Offset Voltage vs Temperature (VS = ±18 V)
Offset Voltage vs Common-Mode Voltage (VS = ±18 V)
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Offset Voltage vs Power Supply
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
IB vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to Input)
CMRR vs Temperature
Figure 8
Figure 9
Figure 10
Figure 11
PSRR vs Temperature
Figure 12
0.1-Hz to 10-Hz Noise
Figure 13
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
Figure 14
Figure 15
THD+N vs Output Amplitude
Figure 16
Quiescent Current vs Temperature
Quiescent Current vs Supply Voltage
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Figure 17
Figure 18
Figure 19
Figure 20
Open-Loop Gain vs Temperature
Figure 21
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Positive Overload Recovery
Figure 22
Figure 23, Figure 24
Figure 25, Figure 26
Figure 27, Figure 28
Figure 29, Figure 30
Figure 31, Figure 32
Figure 33, Figure 34
Figure 35
Negative Overload Recovery
Small-Signal Step Response (10 mV)
Small-Signal Step Response (100 mV)
Large-Signal Step Response (1 V)
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
No Phase Reversal
Figure 36
Figure 37
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
EMIRR vs Frequency
Figure 38
Figure 39
Figure 40
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SBOS618 –DECEMBER 2013
TYPICAL CHARACTERISTICS
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
25
25
20
15
10
5
Distribution Taken From 5185 Amplifiers
Distribution Taken From 47 Amplifiers
Temperature = -40C to 125C
20
15
10
5
0
0
Offset Voltage Drift (µV/C)
Offset Voltage (mV)
C013
C013
Figure 1. OFFSET VOLTAGE PRODUCTION DISTRIBUTION
Figure 2. OFFSET VOLTAGE DRIFT PRODUCTION
DISTRIBUTION
250
225
5 Typical Units Shown
VS = ±18 V
5 Typical Units Shown
VS = ±18 V
200
150
75
VCM =16V
150
100
50
VCM = -18.1V
0
0
±50
±100
±150
±200
±250
±75
±150
±225
±75 ±50 ±25
0
25
50
75
100 125 150
±20
±15
±10
±5
0
5
10
15
20
Temperature (C)
C001
VCM (V)
C001
Figure 3. OFFSET VOLTAGE vs TEMPERATURE
(VS = ±18 V)
Figure 4. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
(VS = ±18 V)
500
20
10
5 Typical Units Shown
5 Typical Units Shown
VS = ±18 V
400
VS = ±2.25V to 18V
Vs = ±2.25V
300
0
200
100
-10
-20
-30
-40
-50
0
±100
±200
±300
±400
±500
0.0
2.0
4.0
6.0 8.0 10.0 12.0 14.0 16.0 18.0
VSUPPLY (V)
14
15
16
17
18
VCM (V)
C001
C001
Figure 5. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
Figure 6. OFFSET VOLTAGE vs POWER SUPPLY
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
12
10
8
8000
6000
4000
2000
0
IB+
IB -
Ios
IbP
6
IbN
4
2
0
±2
±4
Ios
TA = 25°C
±2000
±18.0 ±13.5 ±9.0 ±4.5
0.0
4.5
9.0
13.5 18.0
±50
±25
0
25
50
75
100
125
150
VCM (V)
Temperature (C)
C001
C001
Figure 7. INPUT BIAS CURRENT vs COMMON-MODE
VOLTAGE
Figure 8. INPUT BIAS CURRENT vs TEMPERATURE
160.0
18
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
- 40C
12
+25°C
6
0
+85C
+125
-6
+PSRR
-PSRR
CMRR
+125°C
-12
-18
- 40°C
1
10
100
1k
10k
100k
1M
0
10 20 30 40 50 60 70 80 90 100 110
C012
Frequency (Hz)
Iout (mA)
C001
Figure 9. OUTPUT VOLTAGE SWING vs OUTPUT
CURRENT (Maximum Supply)
Figure 10. CMRR AND PSRR vs FREQUENCY
(Referred-to-Input)
30
20
10
8
VS = ±2.25V, -ꢅꢂꢆꢇ9ꢃꢃ9CM ꢃꢈꢂꢅꢇ9
6
10
4
2
0
0
VS = 18 V, -ꢀꢁꢂꢀ9ꢃꢃ9CM ꢃꢀꢄ9
±10
±2
±75 ±50 ±25
0
25
50
75
100 125 150
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (C)
Temperature (C)
C001
C001
Figure 11. CMRR vs TEMPERATURE
Figure 12. PSRR vs TEMPERATURE
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SBOS618 –DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
1000
100
10
Peak-to-Peak Noise = 1.20 ꢀVpp
1
Time (1 s/div)
0.1
1
10
100
1k
10k
100k
C001
C002
Frequency (Hz)
Figure 13. 0.1-Hz TO 10-Hz NOISE
Figure 14. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.01
0.001
-80
0.1
0.01
-60
G = +1 V/V, RL = 10 kꢀ
G = +1 V/V, RL = 2 kꢀ
G = +1 V/V, RL = 600 ꢀ
G = -1 V/V, RL = 10 kꢀ
G = -1 V/V, RL = 2 kꢀ
G = -1 V/V, RL = 600 ꢀ
G = +1 V/V, RL = 10 kꢀ
G = +1 V/V, RL = 2 kꢀ
G = +1 V/V, RL = 600 ꢀ
G = -1 V/V, RL = 10 kꢀ
G = -1 V/V, RL = 2 kꢀ
G = -1 V/V, RL = 600 ꢀ
-80
-100
-120
-140
0.001
-100
-120
-140
0.0001
0.00001
0.0001
VOUT = 3.5 VRMS
BW = 80 kHz
f = 1 kHz
BW = 80 kHz
0.00001
10
100
1k
10k
0.01
0.1
1
10
Frequency (Hz)
Output Amplitude (VRMS)
C007
C008
Figure 15. THD+N RATIO vs FREQUENCY
Figure 16. THD+N vs OUTPUT AMPLITUDE
2.0
1.8
1.6
1.4
1.2
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Vs = ±18V
Vs = ±2.25V
±75 ±50 ±25
0
25
50
75
100 125 150
0
4
8
12
16
20
24
28
32
36
Temperature (C)
Supply Voltage (V)
C001
C001
Figure 17. QUIESCENT CURRENT vs TEMPERATURE
Figure 18. QUIESCENT CURRENT vs SUPPLY VOLTAGE
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
140
120
100
80
180
135
90
25.0
20.0
15.0
10.0
5.0
CLOAD = 15 pF
Open-Loop Gain
Phase
60
0.0
40
±5.0
±10.0
±15.0
±20.0
20
45
G = +1
G = -10
G = -1
0
±20
0
1
10
100
1k
10k
100k
1M
10M
1000
10k
100k
1M
10M
Frequency (Hz)
C004
C003
Frequency (Hz)
Figure 19. OPEN-LOOP GAIN AND PHASE vs FREQUENCY
Figure 20. CLOSED-LOOP GAIN vs FREQUENCY
2.0
1000
100
10
1
1.5
1.0
Vs = 4.5 V
0.5
Vs = 36 V
0.0
RL = 10k
±0.5
0
±75 ±50 ±25
0
25
50
75
100 125 150
10
100
1k
10k
100k
1M
10M
100M
Temperature (C)
Frequency (Hz)
C001
C016
Figure 21. OPEN-LOOP GAIN vs TEMPERATURE
Figure 22. OPEN-LOOP OUTPUT IMPEDANCE vs
FREQUENCY
60
50
40
30
20
10
0
50
40
30
20
10
0
RI
=
1
kꢀ
RF
=
+
1 kꢀ
G = +1
G = -1
18
V
V
±
ROUT
+
OPA172
VIN
= 100mV
+
CL
±
±
18
+
18
V
V
ROUT = 0 ꢀ
ROUT= 0 ꢀ
±
ROUT
OPA172
+
+
RL
CL
R
= 25 ꢀ
RO = 25
RRO ==2255ꢀ
OUT
VIN = 100mV
OUT
±
18
±
RRO ==5500 ꢀ
RO = 50
ROUT= 50 ꢀ
OUT
0p
100p
200p
300p
400p
500p
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
Capacitive Load (F)
C013
C013
Figure 23. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE
LOAD (100-mV Output Step)
Figure 24. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE
LOAD (100-mV Output Step)
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
RI = 1 kꢁ
RF = 10 kꢁ
+ 18 V
±
+
OPA172
VOUT
VIN = 2V
+
VOUT
±
± 18 V
RI
=
1
kꢁ
RF = 10 kꢁ
+
18
V
VOUT
±
+
OPA172
VOUT
VIN
= 2V
+
±
±
18
V
VIN
VIN
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C009
C010
C006
C009
C010
C014
Figure 25. POSITIVE OVERLOAD RECOVERY
Figure 26. POSITIVE OVERLOAD RECOVERY
(Zoomed In)
VIN
VIN
RI
=
1
kꢁ
RF = 10 kꢁ
+
18
V
±
+
OPA172
VOUT
VIN
= 2V
+
±
±
18
V
VOUT
RI
=
1 kꢁ
RF
=
10 kꢁ
+
18 V
VOUT
±
+
OPA172
VOUT
VIN
= 2V
+
±
± 18 V
Time (1 ꢀs/div)
Time (1 ꢀs/div)
Figure 27. NEGATIVE OVERLOAD RECOVERY
Figure 28. NEGATIVE OVERLOAD RECOVERY
(Zoomed In)
+ 18 V
RL ꢀꢁN
CL = 10pF
CL = 10pF
±
OPA172
+
+
CL
VIN = 10mV
± 18 V
±
RI
=
1
kꢀ
RF
=
+
1 kꢀ
18
V
±
+
OPA172
VIN
= 10mV
+
RL
CL
±
±
18
V
Time (200 ns/div)
Time (200 ns/div)
Figure 29. SMALL-SIGNAL STEP RESPONSE
(10 mV, G = –1)
Figure 30. SMALL-SIGNAL STEP RESPONSE
(10 mV, G = +1)
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
+ 18 V
CL = 10pF
RL ꢀꢁN
CL = 10pF
±
OPA172
+
+
CL
VIN = 100mV
± 18 V
±
RI
=
1
kꢀ
RF
=
+
1 kꢀ
18
V
±
+
OPA172
VIN
= 100mV
+
RL
CL
±
±
18
V
Time (200 ns/div)
Time (200 ns/div)
C006
C014
Figure 31. SMALL-SIGNAL STEP RESPONSE
(100 mV, G = –1)
Figure 32. SMALL-SIGNAL STEP RESPONSE
(100 mV, G = +1)
+ 18 V
RL ꢀꢁN
CL = 10 pF
CL = 10pF
±
OPA172
+
+
CL
VIN = 10V
± 18 V
±
RI
=
1
kꢀ
RF
=
+
1 kꢀ
18
V
±
+
OPA172
VIN
= 10V
+
RL
CL
±
±
18
V
Time (500 ns/div)
Time (500 ns/div)
C005
C014
Figure 33. LARGE-SIGNAL STEP RESPONSE
(10 V, G = –1)
Figure 34. LARGE-SIGNAL STEP RESPONSE
(10 V, G = +1)
20
15
10
5
20
15
10
5
G = +1
CL = 10 pF
G = +1
CL = 10 pF
0
0
-5
-5
0.1% Settling = ±10 mV
0.1% Settling = ±10 mV
-10
-15
-20
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (ꢀs)
Time (ꢀs)
C034
C034
Figure 35. LARGE-SIGNAL SETTLING TIME
(10-V Positive Step)
Figure 36. LARGE-SIGNAL SETTLING TIME
(10-V Negative Step)
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
100
+ 18 V
±
OPA172
VOUT
VOUT
+
+
75
50
25
0
± 18 V
37 VPP
ISC, Sink 18V
±
Sine Wave
(±18.5V)
I
SC, Source ±18V
VIN
Time (200 ꢀs/div)
±75 ±50 ±25
0
25
50
75
100 125 150
C011
Temperature (C)
C001
Figure 37. NO PHASE REVERSAL
Figure 38. SHORT-CIRCUIT CURRENT vs TEMPERATURE
160.0
30
25
20
15
10
5
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
VS = ±15 V
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
Maximum output voltage without
slew-rate induced distortion.
VS = ±5 V
VS = ±2.25 V
0
10k
100k
1M
Frequency (Hz)
10M
10M
100M
Frequency (Hz)
1G
10G
C017
C033
Figure 39. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Figure 40. EMIRR vs FREQUENCY
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APPLICATION INFORMATION
The OPAx172 family of operational amplifiers provide high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL and THD.
OPERATING CHARACTERISTICS
The OPAx172 family of amplifiers is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.
EMI REJECTION
The OPAx172 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx172 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 41 shows the results of this testing on the OPAx172. Table 2 shows the EMIRR IN+ values for the
OPAx172 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 can be centered on or operated near the particular frequency shown. Detailed information can also be
found in Application Report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download
from www.ti.com.
160.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
Frequency (Hz)
1G
10G
C017
Figure 41. EMIRR Testing
Table 2. OPAx172 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh frequency
(UHF) applications
400 MHz
47.6 dB
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
900 MHz
1.8 GHz
2.4 GHz
58.5 dB
68 dB
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-
band (2 GHz to 4 GHz)
69.2 dB
3.6 GHz
5.0 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
82.9 dB
114 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
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GENERAL LAYOUT GUIDELINES
For best operational performance of the device, good printed circuit board (PCB) layout practices are
recommended. Including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-
supply applications.
•
•
•
In order to reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
A ground plane helps distribute heat and reduces EMI noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic
errors (such as the Seebeck effect) from occurring.
•
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
COMMON-MODE VOLTAGE RANGE
The input common-mode voltage range of the OPAx172 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 3.
Table 3. Typical Performance Range (VS = ±18V)
PARAMETER
Input Common-Mode Voltage
Offset voltage
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
5
10
70
60
4
mV
vs Temperature (TA = –40°C to +125°C)
Common-mode rejection
Open-loop gain
µV/°C
dB
dB
GBW
MHz
V/µs
nV/√Hz
Slew rate
4
Noise at f = 1 kHz
22
PHASE-REVERSAL PROTECTION
The OPAx172 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPAx172 prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 42.
+ 18 V
±
OPA172
VOUT
VOUT
+
+
± 18 V
37 VPP
±
Sine Wave
(±18.5V)
VIN
Time (200 ꢀs/div)
C011
Figure 42. No Phase Reversal
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CAPACITIVE LOAD AND STABILITY
The dynamic characteristics of the OPAx172 have been optimized for commonly-encountered operating
conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of
the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated
from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω)
in series with the output. Figure 43 and Figure 44 illustrate graphs of small-signal overshoot versus capacitive
load for several values of ROUT. Also, refer to Application Bulletin SBOA015 (AB-028), Feedback Plots Define Op
Amp AC Performance, available for download from www.ti.com, for details of analysis techniques and application
circuits.
60
RI
=
1
kꢀ
RF
=
+
1 kꢀ
G = -1
18
V
±
ROUT
50
40
30
20
10
0
+
OPA172
VIN
= 100mV
+
CL
±
±
18
V
ROUT = 0 ꢀ
R
= 25 ꢀ
RO = 25
OUT
RRO ==5500 ꢀ
OUT
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
C013
Figure 43. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
50
G = +1
40
30
20
+
18
V
V
ROUT= 0 ꢀ
±
ROUT
OPA172
10
0
+
+
RL
CL
RRO ==2255ꢀ
VIN
= 100mV
OUT
±
18
±
RO = 50
ROUT= 50 ꢀ
0p
100p
200p
300p
400p
500p
Capacitive Load (F)
C013
Figure 44. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
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ELECTRICAL OVERSTRESS
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 45 for an illustration of the ESD circuits contained in the OPAx172 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
TVS
RF
+VS
VDD
OPA172
R1
RS
250ꢀ
250ꢀ
IN-
IN+
Power supply
ESD cell
ID
VIN
RL
+
±
VSS
-VS
TVS
Figure 45. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx172
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
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When the operational amplifier connects into a circuit (such as the one Figure 45 depicts), the ESD protection
components are intended to remain inactive and do not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current.
Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 45 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current can be supplied by the input source through the current-steering diodes. This state is not
a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the
supply pins, as shown in Figure 45. Select the zener voltage so that the diode does not turn on during normal
operation. However, the zener voltage should be low enough so that the zener diode conducts if the supply pin
begins to rise above the safe-operating, supply-voltage level.
The OPAx172 input terminals are protected from excessive differential voltage with back-to-back diodes, as
shown in Figure 45. In most circuit applications, the input protection circuitry has no effect. However, in low-gain
or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier
cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias
condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an
input series resistor can be used to limit the input signal current. This input series resistor degrades the low-noise
performance of the OPAx172. Figure 45 shows an example configuration that implements a current-limiting
feedback resistor.
OVERLOAD RECOVERY
Overload recovery is defined as the time it takes for the op amp output to recover from the saturated state to the
linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices need time to return back to the normal state. After the
charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx172 is approximately 200 ns.
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APPLICATION EXAMPLES
The following application examples highlight only a few of the circuits where the OPAx172 can be used.
BI-DIRECTIONAL CURRENT SOURCE
The improved Howland current pump topology shown in Figure 46 provides excellent performance due to the
extremely tight tolerances of the on chip resistors of the INA132. By buffering the output using and OPA172, the
output current the circuit is able to deliver is greatly extended.
The circuit dc transfer function is show in Equation 1:
IOUT = VIN / R1
(1)
The OPA172 can also be used as the feedback amplifier because the low bias current will minimize error
voltages produced across R1. However, for improved performance, a FET-input device with extremely low offset
can be selected, such as the OPA192, OPA140, or OPA188 for the feedback amplifier.
IN-
40k
40k
SENSE
-
+
OUTPUT
OPA172
VIN
+
-
+
40k
40k
REF
IN+
INA132
R1
OPA172
+
-
+
I OUT
Figure 46. Bidirectional Current Source
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JFET-INPUT LOW-NOISE AMPLIFIER
A low-noise composite amplifier can be built adding a low noise JFET pair (Q1 and Q2) as an input preamplifier
for the OPA172 as shown in Figure 47. Transistors Q3 and Q4 form a 2-mA current sink that biases each JFET
with 1 mA of drain current. Using 3.9-kΩ drain resistors produces a gain of approximately 10 in the input
amplifier, making the extremely-low, broadband-noise spectral density of the LSK489 the dominant noise source
of the amplifier. The output impedance of the input differential amplifier is large enough that a FET-input amplifier
such as the OPA172 provides superior noise performance over bipolar-input amplifiers.
The gain of the composite amplifier is given by Equation 2:
AV = (1 + R3 / R4 )
(2)
The resistances shown are standard 1% resistor values that produce a gain of approximately 100 (99.26) with
68° of phase margin. Gains less than 10 may require additional compensation methods to provide stability.
Seleect low resistor values to minimize the resistor thermal noise contribution to the total output noise.
V1 15
V2 15
VEE
OPA172
-
VO
+
+
VCC
Q1
Q2
LSK489
R6 27.4k
Q3
MMBT4401
R5 300
Q4
MMBT4401
VEE
Figure 47. JFET-Input Low-Noise Amplifier
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2013
PACKAGING INFORMATION
Orderable Device
OPA172ID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOT-23
SOT-23
SC70
D
8
5
5
5
5
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
OPA172
OPA172IDBVR
OPA172IDBVT
OPA172IDCKR
OPA172IDCKT
OPA172IDR
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
DBV
DBV
DCK
DCK
D
3000
250
Green (RoHS
& no Sb/Br)
OUWQ
OUWQ
SIU
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
SIU
SOIC
2500
Green (RoHS
& no Sb/Br)
OPA172
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2013
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA172IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
OPA172IDR
D
8
2500
Pack Materials-Page 2
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相关型号：
INA2126E
DUAL INSTRUMENTATION AMPLIFIER, 500uV OFFSET-MAX, 0.2MHz BAND WIDTH, PDSO16, GREEN, PLASTIC, SSOP-16
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