INA351ABSIDSGR [TI]
Tiny (1.5-mm × 2-mm) low-power (110 µA) instrumentation amplifier with integrated reference buffer | DSG | 8 | -40 to 125;
| 型号： | INA351ABSIDSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Tiny (1.5-mm × 2-mm) low-power (110 µA) instrumentation amplifier with integrated reference buffer | DSG | 8 | -40 to 125 |
| 文件： | 总43页 (文件大小：3386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INA351
ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
INA351 具有集成基准缓冲器、成本和尺寸经优化的低功耗1.8V 至5.5V 可选增
益仪表放大器
1 特性
3 说明
• 专为尺寸、成本和功耗敏感型应用而设计
• 具有集成基准缓冲器的可选增益选项
– G = 10 或G = 20 (INA351ABS)
– G = 30 或G = 50 (INA351CDS)
• 节省空间的超小型封装选项
– 10 引脚X2QFN (RUG) –3mm2
– 8 引脚WSON (DSG) –4mm2
– 8 引脚SOT23-THN (DDF) –4.64mm2
• 针对10 位至14 位系统的优化性能
INA351 是一款具有集成基准缓冲器的可选增益仪表放
大器， 可在采用小型封装的 INA351ABS 和
INA351CDS 型号中提供四种增益选项。INA351ABS
具有增益选项 10 或 20，INA351CDS 具有增益选项
30 或 50。可以通过切换增益选择 (GS) 引脚来选择这
些增益选项。INA351 是桥式感应以及差分至单端转换
应用的理想选择。
INA351 采用精密匹配的集成电阻器构建而成，无需使
用精密或高度匹配的外部电阻器，从而节省了 BOM 成
本、贴片机器处理成本和布板空间。INA351 可直接连
接到低速 10 位至 14 位模数转换器 (ADC)，非常适合
替换使用商用放大器和分立式电阻器构建的仪表放大器
的分立式方案。
– CMRR：所有增益均为95dB（典型值）
– 失调电压：所有增益均为0.2mV（典型值）
– 增益误差（典型值）：
• G = 10、G = 50 时为0.015%
• G = 20、G = 30 时为0.020%
INA351 的设计采用三放大器架构，能够提供更好的性
能。该器件在所有增益选项下可实现 86dB 的最小
CMRR 和 0.1% 精度的最大增益误差，以及 1.3mV 的
最大失调电压，而仅消耗 135µA 的最大静态电流。
INA351 有一个集成关断选项，可在空闲时关闭放大
器，从而在电池供电应用中进一步节省电能。
• 带宽：G = 10 时为100kHz（典型值）
• 驱动500pF，过冲小于20%（典型值）
• 优化的静态电流：110µA（典型值）
• 适用于功耗敏感型应用的关断选项
• 电源电压范围：1.8V (±0.9V) 至5.5V (±2.75V)
• 额定温度范围：–40°C 至125°C
封装信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
• 桥接网络传感
• 差分至单端转换
• 称重计
DSG（WSON，8） 2.00mm × 2.00mm
DDF（SOT-23，8） 1.60mm × 2.90mm
(2)
INA351ABS
• 模拟输入模块
• 流量变送器
RUG（X2QFN，
10）
1.50mm × 2.00mm
• 可穿戴健身和活动监测仪
• 血糖监控
• 压力和温度传感
DSG（WSON，8） 2.00mm × 2.00mm
DDF（SOT-23，8） 1.60mm × 2.90mm
(2)
INA351CDS
V+
7
RUG（X2QFN，
1.50mm × 2.00mm
10）
IN
60 k
2
1
+
–
60 k
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 此封装为仅预发布状态。
–
+
90 k / 145 k
90 k / 145 k
RG
GS
6
5
OUT
REF
–
+
–
+
60 k
60 k
+IN
3
8
4
_____
SHDN
V
注意：INA351ABS 为90kΩ，INA351CDS 为145kΩ
简化版内部原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAD5
INA351
www.ti.com.cn
ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
Table of Contents
8.4 Device Functional Modes..........................................26
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Applications.................................................. 29
9.3 Power Supply Recommendations.............................31
9.4 Layout....................................................................... 32
10 Device and Documentation Support..........................34
10.1 Device Support....................................................... 34
10.2 Documentation Support.......................................... 34
10.3 接收文档更新通知................................................... 34
10.4 支持资源..................................................................34
10.5 Trademarks.............................................................34
10.6 静电放电警告.......................................................... 34
10.7 术语表..................................................................... 34
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................8
8 Detailed Description......................................................21
8.1 Overview...................................................................21
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................22
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (February 2023) to Revision C (May 2023)
Page
• 删除了封装信息 中INA351 RUG RTM 的预发布标签........................................................................................ 1
• Deleted the preview tag from Device Comparison Table for INA351 RUG RTM................................................3
• Deleted preview footnote from Thermal Information table for INA351 X2QFN (RUG) RTM...............................5
Changes from Revision A (December 2022) to Revision B (February 2023)
Page
• 删除了封装信息 中INA351CDSIDSGR RTM 的预发布标签.............................................................................. 1
• Deleted the preview tag from Device Comparison Table for INA351CDSIDSGR RTM......................................3
• Deleted preview footnote from Electrical Characteristics and Thermal Information table for
INA351CDSIDSGR RTM....................................................................................................................................5
Changes from Revision * (December 2022) to Revision A (December 2022)
Page
• Added footnote for Reference gain error specification in Electrical Characteristics table.................................. 5
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOSAD5
2
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INA351
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
5 Device Comparison Table
PACKAGE LEADS
NO. OF
CHANNELS
DEVICE
SOT-23-8
DDF(1)
WSON
DSG
X2QFN
RUG
INA351ABS
INA351CDS
1
1
8
8
8
8
8
8
(1) Package is preview only.
6 Pin Configuration and Functions
GS
IN–
IN+
V–
1
2
3
4
8
7
6
5
SHDN
GS
IN–
IN+
V–
1
2
3
4
8
7
6
5
SHDN
V+
V+
Thermal
Pad
OUT
REF
OUT
REF
Not to scale
Not to scale
图6-1. DDF Package,
8-Pin SOT-23
Note: Connect Thermal Pad to (V−)
图6-2. DSG Package,
8-Pin WSON With Exposed Thermal Pad
(Top View)
(Top View)
表6-1. Pin Functions
PIN
TYPE(1)
NO.
DESCRIPTION
NAME
IN–
IN+
2
3
6
I
Negative (inverting) input
Positive (non-inverting) input
Output
O
—
OUT
Reference input. This pin internally connects to a reference buffer amplifier in G = 1, unity
gain follower configuration.
REF
GS
5
—
Gain select –logic low (G = 10 for INA351ABS and G = 30 for INA351CDS)
Gain select –logic high (G = 20 for INA351ABS and G = 50 for INA351CDS)
Gain select –no connect (G = 20 for INA351ABS and G = 50 for INA351CDS)
1
I
Shutdown –logic high (device enabled)
Shutdown –logic low (device disabled)
Shutdown –no connect (device enabled)
SHDN
8
I
4
7
Negative supply
Positive supply
V–
—
—
V+
(1) I = input, O = output
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English Data Sheet: SBOSAD5
INA351
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
GS
IN–
IN+
V–
1
2
3
4
9
8
7
6
SHDN
V+
OUT
REF
Not to scale
图6-3. RUG Package,
10-Pin X2QFN
(Top View)
表6-2. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
IN–
IN+
NO.
2
I
Negative (inverting) input
Positive (noninverting) input
Output
3
O
—
OUT
7
Reference input. This pin internally connects to a reference buffer amplifier in G = 1, unity
gain follower configuration.
REF
GS
6
1
—
Gain select –logic low (G = 10 for INA351ABS and G = 30 for INA351CDS)
Gain select –logic high (G = 20 for INA351ABS and G = 50 for INA351CDS)
Gain select –no connect (G = 20 for INA351ABS and G = 50 for INA351CDS)
I
Shutdown –logic high (device enabled)
Shutdown –logic low (device disabled)
Shutdown –no connect (device enabled)
SHDN
9
I
4
8
Negative supply
Positive supply
No connect
V–
V+
—
—
—
NC
5, 10
(1) I = input, O = output
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English Data Sheet: SBOSAD5
INA351
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
6
UNIT
V
Supply voltage, VS = (V+) –(V–)
Common mode voltage(2)
(V+) + 0.5
VS + 0.2
10
V
(V–) –0.5
Signal input pins
Differential voltage(3)
Current(2)
V
mA
–10
Output short-circuit(4)
Continuous
Operating Temperature, TA
Junction Temperature, TJ
Storage Temperature, Tstg
150
150
150
–55
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less
(3) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage above the maximum
specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.
(4) Short-circuit to VS / 2.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
MAX
5.5
UNIT
Single-supply
Dual-supply
V
Supply voltage VS = (V+) –(V–)
±0.9
(V–)
–40
±2.75
(V+)
125
Input Voltage Range
Specified temperature
V
Specified temperature
°C
7.4 Thermal Information
INA351ABS, INA351CDS
THERMAL METRIC(1)
DDF (SOT-23-THN)(2) DSG (WSON) RUG (X2QFN)
UNIT
8 PINS
172.1
90.1
88.2
7.3
8 PINS
80.3
100.4
46.4
5.3
10 PINS
174.7
63.2
99.6
1.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
88.0
n/a
46.4
21.9
99.2
n/a
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package is for preview only.
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English Data Sheet: SBOSAD5
INA351
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.5 Electrical Characteristics
For VS = (V+) –(V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, VREF = VS/2, G = 10, RL = 10 kΩconnected to VS /
2, VCM = [(VIN+) + (VIN–)] / 2 = VS / 2, VIN = (VIN+) –(VIN–) = 0 V and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Offset Voltage, RTI(1)
VS = 5.5 V, G = 10, 20, 30, 50
TA = 25°C
±0.2
±1.3
±1.4
mV
mV
Offset Voltage over T,
RTI(1)
VS = 5.5 V, G = 10, 20, 30, 50
VS = 5.5 V, G = 10, 20, 30, 50
G = 10, 20, 30, 50
VOSI
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
Offset temp drift, RTI(2)
±0.65
20
µV/°C
µV/V
Power-supply rejection
ratio
PSRR
ZIN-DM
ZIN-CM
75
Differential Impedance
100 || 5
100 || 9
GΩ|| pF
GΩ|| pF
Common Mode
Impedance
Input Stage Common
Mode Range(3)
VCM
(V+)
V
(V–)
G = 10, 20, 30, 50, VCM = (V–) +
0.1 V to (V+) –1 V, High CMRR
Region
VS = 5.5 V, VREF = VS/2
86
95
CMRR
DC
Common-mode rejection G = 10, 20, 30, 50, VCM = (V–) +
dB
ratio, RTI
VS = 3.3 V, VREF = VS/2
VS = 5.5 V, VREF = VS/2
94
75
0.1 V to (V+) –1 V, High CMRR
Region
G = 10, 20, 30, 50, VCM = (V–) +
0.1 V to (V+) –0.1 V
62
BIAS CURRENT
IB
Input bias current
Input offset current
VCM = VS / 2
VCM = VS / 2
±0.65
±0.25
pA
pA
IOS
NOISE VOLTAGE
G = 10, 20, 30, 50
G = 10, 20, 30, 50
f = 1 kHz
36
35
Input referred voltage
eNI
ENI
nV/√Hz
noise density(5)
f = 10 kHz
Input referred voltage
noise(5)
G = 10, fB = 0.1 Hz to 10 Hz
f = 1 kHz
3.2
22
µVPP
in
Input current noise
f = 1 kHz
fA/√Hz
GAIN
G = 10, VREF = VS/2
G = 20, VREF = VS/2
G = 30, VREF = VS/2
G = 50, VREF = VS/2
±0.015
±0.020
±0.020
±0.015
±0.10
±0.10
±0.10
±0.10
Gain error(4)
Gain error(4)
VO = (V–) + 0.1 V to
(V+) –0.1V
GE
%
OUTPUT
VOH
Positive rail headroom
Negative rail headroom
15
15
30
30
mV
mV
pF
RL = 10 kΩ to VS/2
VOL
RL = 10 kΩ to VS/2
CL Drive Load capacitance drive
VO = 100 mV step, Overshoot < 20%
500
Closed-loop output
impedance
ZO
f = 10 kHz
VS = 5.5 V
51
Ω
ISC
Short-circuit current
±20
mA
FREQUENCY RESPONSE
G = 10
G = 20
G = 30
G = 50
100
50
Bandwidth, –3 dB
BW
VIN = 10 mVpk-pk
kHz
%
40
Bandwidth, –3 dB
25
Total harmonic distortion + VS = 5.5 V, VCM = 2.75 V, VO = 1 VRMS, G = 10, RL = 100 kΩ
THD + N
0.035
noise
ƒ= 1 kHz, 80-kHz measurement BW
Electro-magnetic
interference rejection ratio
EMIRR
SR
f = 1 GHz, VIN_EMIRR = 100 mV
96
dB
Slew rate
VS = 5 V, VO = 2 V step, G = 10, 20, 30, 50
0.20
V/µs
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOSAD5
6
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.5 Electrical Characteristics (continued)
For VS = (V+) –(V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, VREF = VS/2, G = 10, RL = 10 kΩconnected to VS /
2, VCM = [(VIN+) + (VIN–)] / 2 = VS / 2, VIN = (VIN+) –(VIN–) = 0 V and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
14
24
20
30
30
40
45
55
8
MAX
UNIT
G = 10, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 10, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 20, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 20, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 30, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 30, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 50, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
G = 50, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF
VIN = 1 V, G = 10
Settling time
tS
µs
Settling time
Overload recovery
µs
REFERENCE BUFFER
REF -
VIN
Linear input voltage range VS = 5.5 V
V
V/V
%
(V–) + 0.1
(V+) –0.1
REF - G Reference gain to output
1
REF -
Reference gain error(4)
GE
VS = 5.5 V
VS = 5.5 V
VS = 5.5 V
±0.015
±0.10
REF -
Input impedance
ZIN
100 || 5
±0.65
GΩ|| pF
Reference pin bias
REF - IB
current
pA
POWER SUPPLY
Single-supply
Dual-supply
1.7
5.5
±2.75
135
VS
Power-supply voltage
Quiescent current
V
±0.85
VIN = 0 V
110
IQ
µA
147
TA = –40°C to 125°C
Quiescent current per
amplifier
IQSD
VIL
VIH
tON
0.85
1.5
µA
V
All amplifiers disabled, SHDN = V–
Logic low threshold
voltage (Gain Select)
(V–) + 0.2
G = 10 for INA351ABS, G = 30 for INA351CDS
G = 20 for INA351ABS, G = 50 for INA351CDS
V
Logic high threshold
voltage (Gain Select)
V
(V–) + 1 V
G = 10, VCM = VS / 2, VO = 0.9 × VS / 2,
RL connected to V–
Amplifier enable time (full
shutdown) (6)
100
5
µs
µs
nA
nA
G = 10, VCM = VS / 2, VO = 0.1 × VS / 2,
RL connected to V–
tOFF
Amplifier disable time (6)
SHDN pin input bias
current (per pin)
10
(V+) ≥SHDN ≥(V–) + 1 V
(V–) ≤SHDN ≤(V–) + 0.2 V
SHDN pin input bias
current (per pin)
175
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2]
(3) Input common mode voltage range of the just the input stage of the instrumentation amplifier. The entire INA351 input range depends
on the combination input common-mode voltage, differential voltage, gain, reference voltage and power supply voltage. Typical
Characteristic curves will be added with more information.
(4) Min and Max values are specified by characterization.
(5) Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2]
(6) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
32
28
24
20
16
12
8
28
24
20
16
12
8
4
4
0
0
H05_
H06_
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
G = 10, 20, 30, 50
N = 36
μ= 23 μV σ= 0.180 mV
μ= 0.23
σ= 0.36
μV/°C
G = 10, 20, 30, 50 N = 36
μV/°C
图7-1. Typical Distribution of Input Referred Offset Voltage
图7-2. Typical Distribution of Input Referred Offset Drift
50
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
0
H13_
H15_
Input Bias Current (pA)
Input Offset Current (pA)
TA = 25°C
N = 72
μ= 0.33 pA σ= 0.43 pA
μ= –0.40
TA = 25°C
N = 36
σ= 0.47 pA
pA
图7-3. Typical Distribution of Input Bias Current
图7-4. Typical Distribution of Input Offset Current
50
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
0
H14_
H16_
Input Bias Current (pA)
Input Offset Current (pA)
TA = 85°C
N = 72
TA = 85°C
N = 36
μ= 3.3 pA
σ= 0.53 pA
μ= 0.05 pA σ= 0.30 pA
图7-5. Typical Distribution of Input Bias Current
图7-6. Typical Distribution of Input Offset Current
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
24
21
18
15
12
9
28
24
20
16
12
8
6
4
3
0
0
H17_
H18_
Input Common-Mode Rejection Ratio (uV/V)
Input Common-Mode Rejection Ratio (uV/V)
μ= -0.30
σ= 7.10
μV/V
μ= -0.27
σ= 7.20
μV/V
G = 10
N = 36
G = 20
N = 36
μV/V
μV/V
图7-7. Typical Distribution of CMRR
图7-8. Typical Distribution of CMRR
24
21
18
15
12
9
21
18
15
12
9
6
6
3
3
0
0
H19_
H20_
Input Common-Mode Rejection Ratio (µV/V)
Input Common-Mode Rejection Ratio (uV/V)
μ= –1.23
μV/V
σ= 7.52
μV/V
σ= 7.62
μV/V
G = 30
N = 36
G = 50
N = 36
μ= –1.16 μV/V
图7-9. Typical Distribution of CMRR
图7-10. Typical Distribution of CMRR
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
H21_
H22_
Gain Error (%)
N = 36
Gain Error (%)
N = 36
G = 20
μ= -0.02 %
σ= 0.02 %
G = 10
μ= 0.002 %
σ= 0.02 %
图7-12. Typical Distribution of Gain Error
图7-11. Typical Distribution of Gain Error
32
28
24
20
16
12
8
40
36
32
28
24
20
16
12
8
4
4
0
0
H21_
H22_
Gain Error (%)
Gain Error (%)
G = 30
N = 36
G = 50
N = 36
μ= 0.0067 % σ= 0.011 %
μ= 0.0035 % σ= 0.012 %
图7-13. Typical Distribution of Gain Error
图7-14. Typical Distribution of Gain Error
1250
1000
750
0.4
0.3
0.2
0.1
0
IB-
IB+
500
250
0
-250
-500
-750
-1000
-1250
-0.1
-0.2
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
T01_
T05_
G = 10, 20, 30, 50
图7-16. Input Bias Current vs Temperature
图7-15. Input Referred Offset Voltage vs Temperature
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
55
45
35
25
15
5
110
105
100
95
Vs = 1.8 V
Vs = 3.3 V
Vs = 5.5 V
-5
90
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
T06_
T07_
图7-17. Input Offset Current vs Temperature
图7-18. Quiescent Current vs Temperature
1700
1500
1300
1100
900
60
40
Vs = 1.8 V
Vs = 3.3 V
Vs = 5.5 V
ISC (-), VS = 3.3 V
ISC (-), VS = 5.5 V
ISC (+), VS = 3.3 V
ISC (+), VS = 5.5 V
20
0
700
-20
-40
-60
500
300
100
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
T13_
T08_
图7-20. Short Circuit Current vs Temperature
图7-19. Shutdown Quiescent Current vs Temperature
0.1
130
110
90
G=10
G=20
G=30
G=50
0.05
0
70
-0.05
G=10
G=20
G=30
G=50
50
-0.1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
T12_
T10_
图7-22. CMRR vs Temperature
图7-21. Gain Error vs Temperature
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
2000
1500
1000
500
2000
1500
1000
500
0
0
-500
-1000
-1500
-2000
-500
-1000
-1500
-2000
-2.75
-2
-1.25
-0.5
0.25
1
Input Common-Mode Voltage (V)
1.75
2.5
-1.65
-1.15
-0.65
-0.15
0.35
Input Common-Mode Voltage (V)
0.85
1.35 1.65
C01_
C02_
V+ = 2.75 V and V–= –2.75 V
V+ = 1.65 V and V–= –1.65 V
图7-23. Input Referred Offset Voltage vs Input Common-Mode
图7-24. Input Referred Offset Voltage vs Input Common-Mode
Voltage
Voltage
10
5
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
-0.25
-0.5
-0.75
-1
-1.25
-1.5
-1.75
-2
-5
-10
IB-
IB+
-15
-2.75
-2
-1.25
-0.5
0.25
1
Input Common-Mode Voltage (V)
1.75
2.5
-2.75
-2
-1.25
-0.5
0.25
1
Input Common-Mode Voltage (V)
1.75
2.5
C04_
C05_
V+ = 2.75 V and V–= –2.75 V
V+ = 2.75 V and V–= –2.75 V
图7-25. Input Bias Current vs Input Common-Mode Voltage
图7-26. Input Offset Current vs Input Common-Mode Voltage
170
1200
900
600
160
150
140
130
120
110
100
300
0
-300
-600
-900
-1200
-2.75
-2
-1.25
Input Common-Mode Voltage (V)
-0.5
0.25
1
1.75
2.5
1.75
2.25
2.75
3.25
Supply Voltage (V)
3.75
4.25
4.75
5.25
C03_
C06_
G = 10
V+ = 2.75 V and V–= –2.75 V
图7-28. Input Referred Offset Voltage vs Supply Voltage
图7-27. Quiescent Current vs Input Common-Mode Voltage
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
3
2.5
2
120
110
100
90
Vs = 1.8 V
Vs = 5.5 V
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
80
1.6
0
5
10
15
Output Current (mA)
20
25
30
2
2.4 2.8 3.2 3.6 4
Supply Voltage (V)
4.4 4.8 5.2 5.6
C10_
C07_
图7-30. Output Voltage vs Output Current (Sourcing)
图7-29. Quiescent Current vs Supply Voltage
4
48
G = 10
G = 20
3.5
3
42
G = 30
G = 50
36
30
2.5
2
1.5
1
24
18
12
6
0.5
0
-0.5
-1
-1.5
-2
0
Vs = 1.8 V
Vs = 5.5 V
-2.5
-3
-6
-12
10
0
5
10
15
Output Current (mA)
20
25
30
100
1k 10k
Frequency (Hz)
100k
1M
C11_
A01_
图7-31. Output Voltage vs Output Current (Sinking)
图7-32. Closed-Loop Gain vs Frequency
150
150
G = 10
G = 20
G = 30
G = 50
G = 10
135
120
105
90
135
120
105
90
G = 20
G = 30
G = 50
75
75
60
60
45
45
30
30
15
15
0
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k 10k
Frequency (Hz)
100k
1M
A02_
A04_
图7-33. CMRR (Referred to Input) vs Frequency
图7-34. PSRR+ (Referred to Input) vs Frequency
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
150
135
120
105
90
100
90
80
70
60
50
40
30
20
10
0
G = 10
G = 20
G = 30
G = 50
G = 10
G = 20
G = 30
G = 50
75
60
45
30
15
0
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k
Frequency (Hz)
10k
100k
A05_
A06_
图7-35. PSRR–(Referred to Input) Vs Frequency
图7-36. Input Referred Voltage Noise Spectral Density
3
2000
G = 10
1000
2.4
500
1.8
1.2
0.6
0
200
100
50
-0.6
-1.2
-1.8
-2.4
-3
20
10
5
2
1
100
1k
10k
Frequency (Hz)
100k
Time (1s/div)
A10_
A12_
图7-37. 0.1 Hz to 10 Hz Voltage Noise in Time Domain
图7-38. Closed-Loop Output Impedance vs Frequency
6
-38
Vs = 5.5 V
Vs = 3.3 V
G = 10
5.4
-42
-46
-50
-54
-58
-62
-66
-70
-74
G = 20
G = 30
G = 50
4.8
4.2
3.6
3
2.4
1.8
1.2
0.6
0
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10
100
1k
Frequency (Hz)
10k
A13_
A15_
图7-39. Maximum Output Voltage vs Frequency
VS = 5.5 V
BW = 80 kHz
VCM = 2.75 V
VOUT = 0.5 VRMS
RL = 10 kΩ
图7-40. THD + N Frequency
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
-34
-40
-46
-52
-58
-64
-70
-76
-82
110
100
90
G = 10
G = 20
G = 30
G = 50
G = 10
G = 20
G = 30
G = 50
80
70
60
50
10
100
1k
Frequency (Hz)
10k
1M
10M
100M
Frequency (Hz)
1G
A16_
A14_
图7-42. Electromagnetic Interference Rejection Ratio Referred
VS = 5.5 V
BW = 80 kHz
VCM = 2.75 V
to Noninverting Input (EMIRR+) vs Frequency
VOUT = 1 VRMS
RL = 100 kΩ
图7-41. THD + N Frequency
20
15
10
5
4
RISO = 0 W, Overshoot (+)
RISO = 0 W, Overshoot (-)
RISO = 50 W, Overshoot (+)
RISO = 50 W, Overshoot (-)
RISO = 0 W, Overshoot (+)
RISO = 0 W, Overshoot (-)
RISO = 50 W, Overshoot (+)
RISO = 50 W, Overshoot (-)
3
2
1
0
0
0
150
300
450 600
Capacitive Load (pF)
750
900
1050
0
150
300
450 600
Capacitive Load (pF)
750
900
1050
TR01
TR02
VS = 5.5 V
G = 10
VOUT = 100 mVPP
VS = 5.5 V
G = 20
VOUT = 100 mVPP
图7-43. Small-Signal Overshoot vs Capacitive Load
图7-44. Small-Signal Overshoot vs Capacitive Load
2
0.8
RISO = 0 W, Overshoot (+)
RISO = 0 W, Overshoot (-)
RISO = 50 W, Overshoot (+)
RISO = 0 W, Overshoot (+)
RISO = 0 W, Overshoot (-)
RISO = 50 W, Overshoot (+)
RISO = 50 W, Overshoot (-)
RISO = 50 W, Overshoot (-)
1.5
1
0.7
0.6
0.5
0.4
0.5
0
0
150
300
450 600
Capacitive Load (pF)
750
900
1050
0
150
300
450 600
Capacitive Load (pF)
750
900
1050
TR03
TR04
VS = 5.5 V
G = 30
VOUT = 100 mVPP
VS = 5.5 V
G = 50
VOUT = 100 mVPP
图7-45. Small-Signal Overshoot vs Capacitive Load
图7-46. Small-Signal Overshoot vs Capacitive Load
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
1.5
VIN
VOUT
1
0.5
0
-0.5
-1
-1.5
Time (200 µs/div)
Time (5µs/div)
TR05
TR14
V–= –2.75
V–= –2.75
V+ = 2.75 V
G = 10
VOUT = 2 VPP
V+ = 2.75 V
G = 10
VOUT = 2 VPP
V
V
图7-47. Large Signal Step Response
图7-48. Large Signal Settling Time (Falling Edge)
1.5
VIN
VOUT
1
0.5
0
-0.5
-1
-1.5
0
200
400 600
Time (200 µs/div)
800
1000
Time (5µs/div)
TR06
TR13
V–= –2.75
V–= –2.75
V+ = 2.75 V
G = 50
VOUT = 2 VPP
V+ = 2.75 V
G = 10
VOUT = 2 VPP
V
V
图7-50. Large Signal Step Response
图7-49. Large Signal Settling Time (Rising Edge)
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
0.075
0.075
VIN
VOUT
VIN
VOUT
0.05
0.05
0.025
0
0.025
0
-0.025
-0.05
-0.075
-0.025
-0.05
-0.075
Time (200 µs/div)
Time (200 µs/div)
TR07
TR10
V–= –2.75
V–= –2.75
V+ = 2.75 V
G = 10
VOUT = 0.1 VPP
V+ = 2.75 V
G = 50
VOUT = 0.1 VPP
V
V
图7-51. Small-Signal Step Response
图7-52. Small-Signal Step Response
4.5
3
4.5
3
1.5
0
1.5
0
-1.5
-3
-1.5
-3
VIN
VOUT
VIN
VOUT
Time (10 µs/div)
Time (10 µs/div)
TR11
TR11
V–= –2.75
V–= –2.75
V+ = 2.75 V
G = 10
VIN = 1 VPP
V+ = 2.75 V
G = 10
VIN = 1 VPP
V
V
图7-53. Over-Load Recovery (Rising Edge)
图7-54. Over-Load Recovery (Falling Edge)
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
3
1.5
0
3
2.5
2
VIN
VOUT
Shutdown Voltage
Output Voltage
1.5
1
0.5
0
-0.5
-1
-1.5
-3
-1.5
-2
-2.5
-3
Time (500 µs/div)
Time (100 µs/div)
TR12
TR15
V+ = +2.75 V
图7-56. Enable Response
G = 10
V–= –2.75
V–= –2.75 V
V+ = 2.75 V
G = 10
VIN = 0.6 VPP
V
图7-55. No Phase Reversal
3
2.5
2
3.6
Shutdown Voltage
Output Voltage
VS = 3.3 V
3.2
2.8
2.4
2
1.5
1
0.5
0
1.6
1.2
0.8
0.4
0
-0.5
-1
-1.5
-2
-2.5
-3
-0.4
Time (100 µs/div)
-0.4
0
0.4 0.8 1.2 1.6 2
Output Voltage (V)
2.4 2.8 3.2 3.6
TR16
D01_
V+ = +2.75 V
G = 10
V–= –2.75 V
VS = 3.3 V
G = 10, 20, 30, 50
VREF = VS / 2
图7-57. Disable Response
图7-58. Input Common-Mode Voltage vs Output Voltage (High
CMRR Region)
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
6
5.4
4.8
4.2
3.6
3
3.6
3.2
2.8
2.4
2
VS = 5.5 V
VS = 3.3 V
1.6
1.2
0.8
0.4
0
2.4
1.8
1.2
0.6
0
-0.6
-0.4
-0.6
0
0.6 1.2 1.8 2.4
3
Output Voltage (V)
3.6 4.2 4.8 5.4
6
-0.4
0
0.4 0.8 1.2 1.6 2
Output Voltage (V)
2.4 2.8 3.2 3.6
D01_
D09_
VS = 5.5 V
G = 10, 20, 30, 50
VREF = VS / 2
VS = 3.3 V
G = 10, 20, 30, 50
VREF = 0 V
图7-59. Input Common-Mode Voltage vs Output Voltage (High
图7-60. Input Common-Mode Voltage vs Output Voltage (High
CMRR Region)
CMRR Region)
6
3.6
VS = 5.5 V
VS = 3.3 V
5.4
3.2
4.8
4.2
3.6
3
2.8
2.4
2
1.6
1.2
0.8
0.4
0
2.4
1.8
1.2
0.6
0
-0.4
-0.6
-0.4
0
0.4 0.8 1.2 1.6 2
Output Voltage (V)
2.4 2.8 3.2 3.6
-0.6
0
0.6 1.2 1.8 2.4
3
Output Voltage (V)
3.6 4.2 4.8 5.4
6
D05_
D09_
VS = 3.3 V
G = 10, 20, 30, 50
VREF = VS / 2
VS = 5.5 V
G = 10, 20, 30, 50
VREF = 0 V
图7-62. Input Common-Mode Voltage vs Output Voltage
图7-61. Input Common-Mode Voltage vs Output Voltage (High
CMRR Region)
6
3.6
VS = 5.5 V
VS = 3.3 V
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
-0.4
-0.4
-0.4
0.4
1.2
2
Output Voltage (V)
2.8
3.6
4.4
5.2
6
-0.4
0
0.4 0.8 1.2 1.6 2
Output Voltage (V)
2.4 2.8 3.2 3.6
D05_
D13_
VS = 5.5 V
G = 10, 20, 30, 50
VREF = VS / 2
VS = 3.3 V
G = 10, 20, 30, 50
VREF = 0 V
图7-63. Input Common-Mode Voltage vs Output Voltage
图7-64. Input Common-Mode Voltage vs Output Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = (V+) –(V–) = 5.5 V, VIN = (VIN+) –(VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +
(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)
6
VS = 5.5 V
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
-0.4
-0.4
0.4
1.2
2
2.8
3.6
Output Voltage (V)
4.4
5.2
6
D13_
VS = 5.5 V
G = 10, 20, 30, 50
VREF = 0 V
图7-65. Input Common-Mode Voltage vs Output Voltage
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8 Detailed Description
8.1 Overview
INA351 is a selectable gain instrumentation amplifier with integrated reference buffer designed to provide an
integrated, small size, cost-effective solution for applications employing general purpose INAs or discrete
implementation of INAs using commodity amplifiers and resistors. The device incorporates a three op amp INA
architecture integrating three operational amplifiers and seven precision matched integrated resistors. INA351 is
suitable for use in 10-bit to 14-bit systems without any additional effort, but calibrating offset and gain error at a
system level can further improve system resolution and accuracy, enabling use in precision applications.
One of the key features of INA351 is that the device does not need any external resistors to set the gain. Often
these external resistors require tighter tolerance and careful routing, which adds to system complexity and cost.
INA351 is offered in four gain options across two variants. INA351ABS has two gain options of 10 and 20.
INA351CDS has two other gain options of 30 and 50. Gains can be selected by connecting the GS pin to logic
high or logic low. Note that the GS pin can be left floating as well, as the pin is designed with an internal pull up
to default to the same configuration as GS tied logic high.
The INA351 is designed for industrial applications leveraging pressure and temperature sensing via bridge-type
sensor networks and load cells. The device can also be used in space-constrained applications such as patient
monitoring, sleep diagnostics, electronic hospital beds, and blood glucose monitoring for voltage sensing and
differential to single-ended conversion. INA351 can enable these applications to reduce their overall size through
the use of tiny packages, including a 2-mm × 1.5-mm X2QFN package and a 2-mm × 2-mm WSON package.
8.2 Functional Block Diagram
V+
7
IN
60 k
2
1
+
–
60 k
–
+
90 k / 145 k
90 k / 145 k
RG
GS
6
5
OUT
REF
–
+
–
+
60 k
60 k
+IN
3
8
4
_____
SHDN
V
Note: 90 kΩfor INA351ABS and 145 kΩfor INA351CDS
Simplified Internal Schematic
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8.3 Feature Description
8.3.1 Gain-Setting
The gain equation of INA351ABS can be given by 方程式1:
180 kΩ
G = 1 +
(1)
(2)
(3)
(4)
R
G
The value of the internal gain resistor RG for INA351ABS can then be derived from the gain equation:
180 kΩ
R
=
G − 1
G
Similarly The gain equation of INA351CDS can be given by 方程式3:
290 kΩ
G = 1 +
R
G
The value of the internal gain resistor RG for INA351CDS can then be derived from the gain equation:
290 kΩ
R
=
G − 1
G
表 8-1 provides how to choose different gain options across INA351ABS and INA351CDS. The 60-kΩ, 90-kΩ,
and 145-kΩresistors mentioned are all typical values of the on-chip resistors.
表8-1. Gain Selection Table
DEVICE
GAIN SELECT (GS)
High or No Connect
Low
SELECTED GAIN
20
10
50
30
INA351ABS
High or No Connect
Low
INA351CDS
8.3.1.1 Gain Error and Drift
Gain error in INA351 is limited by the mismatch of the integrated precision resistors and is specified based on
characterization results. Gain error of maximum 0.1% can be expected for all gains of 10, 20, 30 and 50. Gain
drift in INA351 is limited by the slight mismatch of the temperature coefficient of the integrated resistors. Since
these integrated resistors are precision matched with low temperature coefficient resistors to begin with, the
overall gain drift is much better in comparison to discrete implementation of the instrumentation amplifiers built
using external resistors.
8.3.2 Input Common-Mode Voltage Range
INA351 has two gain stages, the first stage has a common-mode gain of 1 and a differential gain set by the GS
pin. The second stage is configured in a difference-amplifier configuration with differential gain of 1 and ideally
rejects all of the input common mode completely. The second stage also provides a gain of 1 from REF pin to set
the output common-mode voltage.
The linear input voltage range of the INA351, even for a rail-to-rail first stage, is dictated by both the signal swing
at output of the first stage as well as the input common-mode voltage range output swing of the second stage. In
order to maximize performance, it is critical to keep the INA351 within its linear range for a given combination of
gain, reference, and input common-mode voltage for a particular input differential. Input common-mode voltage
(VCM) vs output voltage graphs (VOUT) in this section show a particular reference voltage and gain configuration
to outline the linear performance region of INA351. A good common-mode rejection can be expected when
operating with in the limits of the VCM vs VOUT graph. Note that the INA351 linear input voltage cannot be close
to or extend beyond the supply rails, as the output of the first stage will be driven into saturation.
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The common-mode range for the most common operating conditions is outlined as follows. 图 8-1 shows the
region of operation where a minimum of 86 dB can be achieved. 图 8-2 has much wider region of operation with
a lower minimum CMRR of 62 dB, because the input signal crosses over the transition region of the input pairs
to achieve rail-to-rail operation. The common-mode range for other operating conditions is best calculated with
the INA VCM vs VOUT tool located under the Amplifiers and Comparators section of the Analog Engineer's
Calculator on ti.com. INA351-HCM model can be specifically used for applications requiring high CMRR and
corresponds to performance shown in 图 8-1. INA351xxS model can be used for applications where the input
common mode can be expected to vary rail-to-rail and the model corresponds to performance shown in 图 8-2
where CMRR drops to 62-dB minimum.
6
5.4
4.8
4.2
3.6
3
6
5.4
4.8
4.2
3.6
3
2.4
1.8
1.2
0.6
0
2.4
1.8
1.2
0.6
0
-0.6
-0.6
-0.6
0
0.6 1.2 1.8 2.4
3
Output Voltage (V)
3.6 4.2 4.8 5.4
6
-0.6
0
0.6 1.2 1.8 2.4
3
Output Voltage (V)
3.6 4.2 4.8 5.4
6
D01_
D05_
VS = 5.5 V
G = 10, 20, 30, 50
VREF = VS / 2
VS = 5.5 V
G = 10, 20, 30, 50
VREF = VS / 2
图8-1. Input Common-Mode Voltage vs Output
图8-2. Input Common-Mode Voltage vs Output
Voltage (High CMRR Region)
Voltage
8.3.3 EMI Rejection
The INA351 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the INA351 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 8-3
shows the results of this testing on the INA351. 表 8-2 provides the EMIRR IN+ values for the INA351 at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance relating to op
amps and is available for download from www.ti.com.
110
G = 10
G = 20
G = 30
G = 50
100
90
80
70
60
50
1M
10M
100M
Frequency (Hz)
1G
A14_
图8-3. EMIRR Testing
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表8-2. INA351 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
92 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
96 dB
100 dB
108 dB
106.5 dB
105 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
8.3.4 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier to design a more robust circuit. Due
to natural variation in process technology and manufacturing procedures, every specification of an amplifier
exhibits some amount of deviation from the ideal value, like an amplifier's input offset voltage. These deviations
often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this information to
guard band their system, even when there is not a minimum or maximum specification in the Electrical
Characteristics table.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
图8-4. Ideal Gaussian Distribution
图 8-4 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is
the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-
thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ –σto µ + σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule, if a specification naturally has a nonzero mean (for example,
like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a
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mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation
(µ + σ) to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, the INA351
typical input voltage offset is 200 µV, so 68.2% of all INA351 devices are expected to have an offset from –200
µV to +200 µV. At 4 σ (±800 µV), 99.9937% of the distribution has an offset voltage less than ±800 µV, which
means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are verified by TI, and units outside these limits
are removed from production material. For example, the INA351 family has a maximum offset voltage of 1.3 mV
at 25°C, and even though this corresponds to 6 σ (≈1 in 500 million units), which is extremely unlikely, TI
verifies that any unit with larger offset than 1.3 mV are removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guard band for your application, and design worst-case conditions using this value. As stated earlier,
the 6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and can be an
option as a wide guard band to design a system around. In this case, the INA351 family does not have a
maximum or minimum for offset voltage drift, but based on 图 7-2 and the typical value of 0.65 µV/°C in the
Electrical Characteristics table, the 6-σ value for offset voltage drift can be calculated to 3.9 µV/°C. When
designing for worst-case system conditions, this value can be used to estimate the worst possible offset drift
without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot verify the performance of a
device. This information must be used only to estimate the performance of a device.
8.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. 图 8-5 shows the ESD circuits contained in the INA351 devices. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal power
supply lines, where these diodes meet at an absorption device internal to the operational amplifier. This
protection circuitry is intended to remain inactive during normal circuit operation.
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V+
Power Supply
ESD Cell
+IN
+
–
OUT
– IN
_____
SHDN
GS
REF
V–
图8-5. Equivalent Internal ESD Circuitry
8.4 Device Functional Modes
The INA351 has a shutdown or disable mode to enable power savings in battery powered applications. The
shutdown mode has a maximum quiescent current of just 1.25 µA, which is 100 times lower from the quiescent
current when the amplifier is powered-on or enabled.
INA351 enters disable mode when the SHDN pin is tied low. INA351 is enabled when the SHDN pin is tied high.
A no connection or a floating SHDN pin enables or powers-on the INA as the pin has an internal pull up current
to default to the same configuration as SHDN pin tied high.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Reference Pin
The output voltage of the INA351 is developed with respect to the voltage on the reference pin (REF). Often in
dual-supply operation, REF pin connects to the system ground. However, In single-supply operation, offsetting
the output signal to a precise mid-supply level is useful and required (for example, 2.75-V in a 5.5-V supply
environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the
output so that the INA can drive a single-supply ADC. Traditionally, this is accomplished using an external
reference buffer as shown in 图9-1.
INA351 has an integrated reference buffer amplifier configured in unity gain, voltage follower configuration
internal to the amplifier as shown in 图 8-1. This allows INA351 to be directly connected to a resistive divider
without any need for an external reference buffer amplifier as shown in 图9-2.
5 V
+IN
INA350
OUT
–IN
5 V
5 V
100 k
+
TLV9041
1
F
–
100 k
图9-1. INA350 / Traditional INA –External Reference Buffer Required
5 V
+IN
INA351
OUT
5 V
–IN
100 k
100 k
1 µF
图9-2. INA351 with Integrated Reference Buffer –No External Reference Buffer Required
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9.1.2 Input Bias Current Return Path
The input impedance of the INA351 is extremely high, but a path must be provided for the input bias current of
both inputs. This input bias current is typically a few pico amps but at high temperature this can be a few nano
amps. High input impedance means that the input bias current changes little with varying input voltage.
For proper operation, input circuitry must provide a path for this input bias current. 图 9-3 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA351, and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path connects to one input (as shown in the thermocouple example in 图 9-3). With a
higher source impedance, use two equal resistors to provide a balanced input, with the possible advantages of a
lower input offset voltage as a result of bias current, and better high-frequency common-mode rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
图9-3. Providing an Input Common-Mode Current Path
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9.2 Typical Applications
9.2.1 Resistive-Bridge Pressure Sensor
The INA351 is an integrated instrumentation amplifier that measures small differential voltages while
simultaneously rejecting larger common-mode voltages. The device offers a low power consumption of 110 µA
(typical) and has a smaller form factor.
The device is designed for portable applications where sensors measure physical parameters, such as changes
in fluid, pressure, temperature, or humidity. An example of a pressure sensor used in the medical sector is in
portable infusion pumps or dialysis machines.
The pressure sensor is made of a piezo-resistive element that can be derived as a classical 4-resistor
Wheatstone bridge.
Occlusion (infusion of fluids, medication, or nutrients) happens only in one direction, and therefore can only
cause the resistive element (R) to expand. This expansion causes a change in voltage on one leg of the
Wheatstone bridge, which induces a differential voltage VDIFF
.
图 9-4 shows an example circuit for an occlusion pressure sensor application, as required in infusion pumps.
When blockage (occlusion) occurs against a set-point value, the tubing depresses, thus causing the piezo-
resistive element to expand (Node AD: R + ΔR). The signal chain connected to the bridge downstream
processes the pressure change and can trigger an alarm.
VS = 5.5 V
VEXT = 5 V
1
F
1
F
REF
A
0.1
F
D
Pressure
Occlusion
Sensor
B
–
+
VOUT
VDIFF
ADC
µC
INA351
C
R1
GND
图9-4. Resistive-Bridge Pressure Sensor
Low-tolerance bridge resistors must be used to minimize the offset and gain errors.
Given that there is only a positive differential voltage applied, this circuit is laid out in single-ended supply mode.
The excitation voltage, VEXT, to the bridge must be precise and stable; otherwise, measurement errors can be
introduced.
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9.2.1.1 Design Requirements
For this application, the design requirements are as provided in 表9-1.
表9-1. Design Requirements
DESCRIPTION
VALUE
Single supply voltage
VS = 5.5 V
Excitation voltage
VEXT = 5.0 V
Occlusion pressure range
Occlusion pressure sensitivity
Occlusion pressure impedance (R)
Total pressure sampling rate
Full-scale range of ADC
P = 1 psi to 12 psi, increments of P = 0.5 psi
S = 2 ±0.5 (25%) mV/V/psi
R = 4.99 kΩ±50 Ω(0.1%)
Sr = 20 Hz
VADC(fs) = VOUT = 3.0 V
9.2.1.2 Detailed Design Procedure
This section provides basic calculations to lay out the instrumentation amplifier with respect to the given design
requirements.
One of the key considerations in resistive-bridge sensors is the common-mode voltage, VCM. If the bridge is
balanced (no pressure, thus no voltage change), VCM(zero) is half of the bridge excitation (VEXT). In this example
VCM (zero) is 2.5 V. For the maximum pressure of 12 psi, the bridge common-mode voltage, VCM(MAX), is
calculated by:
V
DIFF
2
V
=
+ V
(5)
(6)
(7)
(8)
CM MAX
CM zero
where
mV
V
= S
× V
× P = 2.5
MAX
× 5 V × 12 psi = 150 mV
V × psi
DIFF
MAX
EXT
Thus, the maximum common-mode voltage applied results in:
150 mV
V
=
+ 2.5 V = 2.575 V
CM MAX
2
Similarly, the minimum common-mode voltage can be calculated as,
−150 mV
V
=
+ 2.5 V = 2.425 V
CM MIN
2
The next step is to calculate the gain required for the given maximum sensor output voltage span, VDIFF, in
respect to the required VOUT, which is the full-scale range of the ADC.
The following equation calculates the gain value using the maximum input voltage and the required output
voltage:
V
OUT
3.0 V
150 mV
G =
=
= 20 V/V
(9)
V
DIFF MAX
Considering, INA351 is a selectable gain INA with gain options of 10, 20, 30, 50, the INA351ABS with GS tied
high enables G = 20 maintaining the maximum output signal swing for the ADC.
Next, let us make sure that the INA351 can operate within this range checking the Input Common-Mode Voltage
vs Output Voltage curves in the Typical Characteristics section. The relevant figure is also in this section for
convenience. Looking at 图9-5, we can confirm that a output signal swing of 3 V is supported for the input signal
swing between 2.425 V and 2.575 V, thus making sure of the linear operation.
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6
5.4
4.8
4.2
3.6
3
2.4
1.8
1.2
0.6
0
-0.6
-0.6
0
0.6 1.2 1.8 2.4
3
Output Voltage (V)
3.6 4.2 4.8 5.4
6
D09_
VS = 5.5 V
G = 10, 20, 30, 50
VREF = 0 V
图9-5. Input Common-Mode Voltage vs Output Voltage (High CMRR Region)
An additional series resistor in the Wheatstone bridge string (R1) may or may not be required, and can be
decided based on the intended output voltage swing for a particular combination of supply voltage, reference
voltage and the selected gain for an input common mode voltage range. R1 helps adjust the input common-
mode voltage range, and thus can help accommodate the intended output voltage swing. In this particular
example, it is not required and can be shorted out.
9.2.1.3 Application Curves
The following typical characteristic curve is for the circuit in 图9-4.
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
0.30
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
VOUT
VDIFF
5000 5200 5400 5600 5800 6000 6200 6400 6600 6800 7000
Bridge Resistance R + DR (W)
D100
图9-6. Input Differential Voltage, Output Voltage vs Bridge Resistance
9.3 Power Supply Recommendations
The nominal performance of the INA351 is specified with a supply voltage of ±2.75 V and midsupply reference
voltage. The device also operates using power supplies from ±0.85 V (1.7 V) to ±2.75 V (5.5 V) and non-
midsupply reference voltages with excellent performance. Parameters can vary significantly with operating
voltage and reference voltage.
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English Data Sheet: SBOSAD5
INA351
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9.4 Layout
9.4.1 Layout Guidelines
Attention to good layout practices is always recommended. For best operational performance of the device, use
the following PCB layout practices:
• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting
common-mode signals into differential signals.
• Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing
in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the traces as short as possible.
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9.4.2 Layout Example
+V
C2
R2
+IN
–IN
INA351ABS
OUT
R1
C1
Ground plane
removed at gain
–V
resistor to minimize
parasitic capacitance
Use ground pours for
shielding the input
signal pairs
+V
GND
GND
_____
C2
R1
1
2
3
4
GS
SHDN
VS+
8
7
6
5
–IN
+IN
–IN
+IN
VS
Input traces routed
adjacent to each other
OUT
REF
OUT
R2
Low-impedance
connection for
reference terminal
GND
C1
Place bypass
capacitors as close to
IC as possible
–V
图9-7. Example Schematic and Associated PCB Layout
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Product Folder Links: INA351
English Data Sheet: SBOSAD5
INA351
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ZHCSR64C –DECEMBER 2022 –REVISED MAY 2023
10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
• SPICE-based analog simulation program —TINA-TI software folder
• Analog Engineers Calculator
10.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOSAD5
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PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA351ABSIDSGR
INA351CDSIDSGR
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
2TMH
2TNH
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA351ABSIDSGR
INA351CDSIDSGR
WSON
WSON
DSG
DSG
8
8
3000
3000
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA351ABSIDSGR
INA351CDSIDSGR
WSON
WSON
DSG
DSG
8
8
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
INA351CDSIDSGR
Tiny (1.5-mm × 2-mm) low-power (110 µA) instrumentation amplifier with integrated reference buffer | DSG | 8 | -40 to 125
TI
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