ISO1044BD [TI]
采用小型封装的隔离式 CAN FD 收发器 | D | 8 | -40 to 125;
| 型号： | ISO1044BD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用小型封装的隔离式 CAN FD 收发器 | D | 8 | -40 to 125 电信 光电二极管 电信集成电路 |
| 文件： | 总38页 (文件大小：2469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO1044
ZHCSL04A – MARCH 2020 – REVISED JULY 2020
ISO1044 隔离式 CAN FD 收发器（采用小型封装）
1 特性
3 说明
•
•
符合 ISO 11898-2:2016 物理层标准
ISO1044B 器件是一款符合 ISO11898-2 (2016) 标准规
格的电隔离控制器局域网 (CAN) 收发器。ISO1044B
器件提供 ±58V 直流总线故障保护电压和 ±12V 共模电
压范围。该器件在 CAN FD 模式下最高支持 5Mbps 数
据速率，与经典 CAN 相比可实现更为快速的载荷传
输。该器件采用二氧化硅 (SiO2) 绝缘隔栅，可承受
3000VRMS 的电压和 450VRMS 的工作电压。电磁兼容
性得到了显著增强，可实现系统级 ESD、EFT 和浪涌
并符合辐射标准。与隔离式电源一起使用，此器件可抵
御高电压冲击，并防止总线的噪声电流进入本地接地。
ISO1044B 器件支持 –40°C 至 +125°C 的宽环境温度
范围。该器件可采用小型 SOIC-8 (D) 封装，与使用光
耦合器隔离 CAN 收发器的传统方法相比，能显著降低
解决方案尺寸。
支持高达 1Mbps 的经典 CAN 和高达 5Mbps 的 FD
（灵活数据速率）
保护特性
•
– 直流总线故障保护电压：±58V
– 总线引脚的 IEC ESD 容差：±8kV
– 总线引脚的 HBM ESD 容差：±10kV
– 驱动器显性超时 (TXD DTO)
– VCC1 和 VCC2 欠压保护
•
•
•
共模电压范围：±12V
未上电时的理想无源、高阻抗总线终端
高 CMTI：85kV/µs（最小值）
• VCC1 电压范围：1.71V 至 5.5V
– 支持连接到 CAN 控制器的 1.8V、2.5V、3.3V
和 5.0V 逻辑接口
器件信息
器件型号(1)
ISO1044B
封装尺寸（标称值）
封装
• VCC2 电压范围：4.5V 至 5.5V
SOIC (8)
4.90mm × 3.91mm
•
优异的电磁兼容性 (EMC)
– 系统级 ESD、EFT 和浪涌抗扰性
– 低辐射
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
环境温度范围：–40°C 至 +125°C
VCC2
8
VCC1
1
VCC1
VCC2
• 8-SOIC 封装
VDD
6
5
•
安全相关认证：
– 所有计划认证
2
3
CANH
CANL
TXD
MCU
RXD
TXD
RXD
ISO1044
Galvanic
CAN Bus
– 符合 DIN VDE V 0884-11:2017-01 标准的 VDE
增强型绝缘
DGND
4
GND2
7
GND1
– UL 1577 组件认证计划
– IEC 60950-1、IEC 62368-1、IEC 61010-1 和
GB 4943.1-2011 认证
Digital
Ground
ISO
Ground
Isolation Barrier
Copyright © 2017, Texas Instruments Incorporated
2 应用
应用图表
•
•
交流和伺服驱动器
光伏逆变器
• PLC 和 DCS 通信模块
•
•
•
升降机和自动扶梯
工业电源
电池充电和管理
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFB0
ISO1044
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ZHCSL04A – MARCH 2020 – REVISED JULY 2020
Table of Contents
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout...........................................................................26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................28
12.1 Documentation Support.......................................... 28
12.2 Receiving Notification of Documentation Updates..28
12.3 Support Resources................................................. 28
12.4 Trademarks.............................................................28
12.5 Electrostatic Discharge Caution..............................28
12.6 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions—8 Pins.......................................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics - DC Specification...............8
6.10 Switching Characteristics........................................11
6.11 Insulation Characteristics Curves............................12
6.12 Typical Characteristics............................................12
7 Parametric Measurement Information.........................15
8 Detailed Description......................................................18
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
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5 Pin Configuration and Functions
VCC1
TXD
1
2
3
4
8
7
6
5
VCC2
GND2
CANH
CANL
RXD
GND1
Not to scale
图 5-1. D Package 8-Pin SOIC Top View
Pin Functions—8 Pins
PIN
NAME
VCC1
I/O
DESCRIPTION
1
2
3
4
5
6
7
8
Digital-side supply voltage, Side 1
—
I
TXD
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
Digital-side ground connection, Side 1
RXD
O
GND1
CANL
CANH
GND2
VCC2
—
I/O
I/O
Low-level CAN bus line
High-level CAN bus line
Transceiver-side ground connection, Side 2
Transceiver-side supply voltage, Side 2
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
-0.5
-0.5
MAX
UNIT
V
VCC1
VCC2
Supply voltage, side 1
Supply voltage, side 2
6
6
V
Logic input and output voltage range (TXD and
RXD)
VIO
-0.5
VCC1+0.5(3)
V
IO
Output current on RXD pin
-15
-58
-45
-40
-65
15
58
mA
V
VBUS
VBUS_DIFF
TJ
Voltage on bus pins (CANH, CANL)
Differential voltage on bus pins (CANH-CANL)
Junction temperature
45
V
150
150
℃
℃
TSTG
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
UNIT
Electrostatic discharge
All pins(1)
±4000
V
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001
CANH and CANL to GND2(1)
±10000
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
V
All pins(2)
±750
Powered, CANH, CANL to bus side
ground (GND2)
±8000
V
V
IEC 61000-4-2 System Level Electrostatic
discharge (tested directly on device pins
with no external components on PCB) (3)
V(IEC_ESD)
Unpowered, CANH, CANL to bus side
ground (GND2)
±12000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) External components on bus pins may lead to different results
6.3 Recommended Operating Conditions
MIN
MAX
1.89
5.5
UNIT
Supply Voltage, Side 1, 1.8 V operation
Supply Voltage, Side 1, 2.5 V, 3.3 V and 5.5 V operation
Supply Voltage, Side 2
1.71
2.25
4.5
-4
V
VCC1
VCC2
V
5.5
V
High-Level Output current, VCC1 = 5 V
High-Level Output current, VCC1 = 3.3 V
High-Level Output current, VCC1 = 2.5 V, 1.8 V
Low-level output current, VCC1 = 5 V
Low-level output current, VCC1 = 3.3 V
Low-level output current, VCC1 = 2.5 V, 1.8 V
Operating ambient temperature
mA
mA
mA
mA
mA
mA
°C
IOH(RXD)
-2
-1
4
2
IOL(RXD)
1
TA
-40
125
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6.4 Thermal Information
ISO1044B
THERMAL METRIC(1)
D (SOIC)
8 PINS
119.5
44.8
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
56.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.7
ΨJT
55.3
ΨJB
RΘJC(bot)
-
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL =
60 Ω , TXD with 5V, 5Mbps 50% duty
square wave
PD
Maximum power dissipation (both sides)
146
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL =
60 Ω , TXD with 5V, 5Mbps 50% duty
square wave
PD1
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
15
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL =
60 Ω , TXD with 5V, 5Mbps 50% duty
square wave
PD2
131
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6.6 Insulation Specifications
PARAMETER
SPECIFIC
ATIONS
TEST CONDITIONS
UNIT
D-8
IEC 60664-1
CLR
CPG
DTI
External clearance(1)
Side 1 to side 2 distance through air
> 4
mm
mm
µm
V
External Creepage(1)
Side 1 to side 2 distance across package surface > 4
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
>17
>600
I
CTI
According to IEC 60664-1
I-IV
I-III
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
637
450
637
4242
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent dielectric
breakdown (TDDB) test;
VIOWM
Maximum isolation working voltage
DC voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
1.2 × VIOTM, t = 1 s (100% production)
=
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 8 kVPK
(qualification)
VIOSM
5000
≤ 5
≤ 5
≤ 5
VPK
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10
s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM , tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
~1
pF
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤ TA ≤ 150°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
40/125/
21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST = 1.2
× VISO , t = 1 s (100% production)
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) ISO1044B is suitable for safe electrical insulation within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Plan to certify according to UL
1577 Component Recognition
Program
Plan to certify according to DIN V Plan to certify according to IEC
Plan to certify according to
GB4943.1-2011
VDE V 0884-11:2017- 01
60950-1, IEC 62368-1
Maximum transient isolation
voltage,
400 VRMS basic insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., for pollution
degree 2, material group I
4242 VPK
;
Basic Insulation, Altitude ≤ 5000
m, Tropical Climate, 400 VRMS
maximum working voltage
Maximum repetitive peak
isolation voltage,
Single protection,
3000 VRMS
637 VPK
;
Maximum surge isolation voltage,
5000 VPK
Certificate planned
Certificate planned
Certificate planned
Certificate planned
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOIC-8 PACKAGE
R
θJA = 119.5 °C/W, VI = 5.5 V, TJ =
190
290
380
553
mA
mA
mA
mA
150°C, TA = 25°C, see Figure 6-1
θJA = 119.5 °C/W, VI = 3.6 V, TJ =
150°C, TA = 25°C, see Figure 6-1
θJA = 119.5 °C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C, see Figure 6-1
θJA = 119.5 °C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C, see Figure 6-1
θJA = 119.5 °C/W, TJ = 150°C, TA =
25°C, see Figure 6-2
R
IS
Safety input, output, or supply current
R
R
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
1044
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics - DC Specification
Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CHARACTERISTICS
VCC1 =1.71 V to 1.89 V, TXD = 0 V, bus
dominant
2.3
2.4
1.2
1.3
1.8
1.8
3.5
3.5
2.1
2.1
2.7
2.7
mA
mA
mA
mA
mA
mA
VCC1 = 2.25 V to 5.5 V, TXD = 0 V, bus
dominant
VCC1 = 1.71 V to 1.89 V, TXD = VCC1, bus
recessive
ICC1
Supply current Side 1
VCC1 = 2.25 V to 5.5 V, TXD = VCC1, bus
recessive
VCC1=4.5 to 5.5V, TXD= 1Mbps 50% duty
square wave
VCC1=4.5 to 5.5V, TXD= 5Mbps 50% duty
square wave
52
70
9
mA
mA
TXD = 0 V, bus dominant, RL = 60 Ω
TXD = VCC1, bus recessive, RL = 60 Ω
5.9
VCC2=4.5 to 5.5V, TXD= 1Mbps 50% duty
square wave, RL= 60 ohm
ICC2
Supply current Side 2
29.5
29.5
38
39
mA
mA
V
VCC2=4.5 to 5.5V, TXD= 5Mbps 50% duty
square wave, RL= 60 ohm
Rising under voltage detection, Side
1
UVVCC1+
UVVCC1-
VHYS(UVCC1)
UVVCC2+
1.7
Falling under voltage detection, Side
1
1.0
V
Hysterisis voltage on VCC1
undervoltage lock-out
80.0
125
4.2
4.0
mV
V
Rising under voltage detection, side 2
4.45
4.25
Falling under voltage detection, side
2
UVVCC2-
3.8
V
Hysterisis voltage on
VCC2 undervoltage lock-out
VHYS(UVCC2)
200
mV
TXD TERMINAL
VIH
VIL
IIH
High level input voltage
0.7×VCC1
V
V
Low level input voltage
0.3×VCC1
1
High level input leakage current
Low level input leakage current
TXD = VCC1
TXD = 0V
µA
µA
IIL
-20
VIN = 0.4 x sin(2 x π x 1E+6 x t) + 1.65
V, VCC1 = 3.3 V
CI
Input capacitance
2
pF
RXD TERMINAL
See Figure 7-4, IO = -4 mA for 4.5 V ≤
-0.4
-0.2
-0.1
-0.1
-0.2
-0.06
-0.04
-0.04
V
V
V
V
V
CC1 ≤ 5.5 V
See Figure 7-4, IO = -2 mA for 3.0 V ≤
CC1 ≤ 3.6 V
See Figure 7-4, IO = -1 mA for 2.25 V ≤
CC1 ≤ 2.75 V
See Figure 7-4, IO = -1 mA for 1.71 V ≤
CC1 ≤ 1.89 V
V
VOH - VCC1
High level output voltage
V
V
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Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 7-4, IO = 4 mA for 4.5 V ≤
0.2
0.4
V
V
CC1 ≤ 5.5 V
See Figure 7-4, IO = 2 mA for 3.0 V ≤
CC1 ≤ 3.6 V
See Figure 7-4, IO = 1 mA for 2.25 V ≤
CC1 ≤ 2.75 V
See Figure 7-4, IO = 1 mA for 1.71 V ≤
CC1 ≤ 1.89 V
0.07
0.035
0.04
0.2
0.1
0.1
V
V
V
V
VOL
Low level output voltage
V
V
DRIVER ELECTRICAL CHARACTERISTICS
See Figure 7-1 and Figure 7-2 , TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, and CL = open
Bus output voltage(Dominant), CANH
VO(DOM)
2.75
0.5
4.5
2.25
3.0
V
V
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, and CL = open
Bus output voltage(Dominant), CANL
Bus output voltage(recessive), CANH See Figure 7-1 and Figure 7-2 ,TXD =
0.5 x
VCC2
VO(REC)
2.0
V
and CANL
VCC1 and RL = open
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, 45 Ω ≤ RL ≤ 70 Ω, and CL = open
Differential output voltage(dominant)
1.4
3.3
V
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, and CL = open
VOD(DOM)
Differential output voltage(dominant)
Differential output voltage(dominant)
Differential output voltage(recessive)
Differential output voltage(recessive)
1.5
3.0
V
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, RL = 2240 Ω, and CL = open
1.5
5.0
V
See Figure 7-1 and Figure 7-2 ,TXD =
VCC1, RL = 60 Ω, and CL = open
-120.0
-50.0
-400.0
-115.0
12.0
50.0
400.0
mV
mV
mV
mA
mA
mA
VOD(REC)
See Figure 7-1 and Figure 7-2 ,TXD =
VCC1, RL = open, and CL = open
See Figure 7-1 and Figure 7-2 ,RL = 60
Ω and CL = open
Output symmetry (VCC2 - VO(CANH)
VO(CANL)
-
VSYM_DC
)
See Figure 7-8 , -15 V < CANH < 40 V,
CANL = open, and TXD = 0V
Short circuit current steady state
output current, dominant
IOS(SS_DOM)
See Figure 7-8 , -15 V < CANL < 40 V,
CANH = open, and TXD = 0V
115.0
5.0
Short circuit current steady state
output current, recessive
See Figure 7-8 , -27 V < VBUS < 32 V,
VBUS = CANH = CANL, and TXD = VCC1
IOS(SS_REC)
-5.0
RECEIVER ELECTRICAL CHARACTERISTICS
See Figure 7-4 and Table 7-1 , -12 V ≤
VIT
Differential input threshold voltage
500.0
900.0
mV
mV
V
V
CM ≤ 12 V
See Figure 7-4 and Table 7-1 , -12 V ≤
CM ≤ 12 V
See Figure 7-4 and Table 7-1 , -12 V ≤
CM ≤ 12 V
See Figure 7-4 and Table 7-1 , -12 V ≤
CM ≤ 12 V
Hysteresis voltage for differential
input threshold
VHYS
100
V
Dominant state differential input
voltage range
VDIFF(DOM)
0.9
9
V
Recessive state differential input
voltage range
VDIFF(REC)
VCM
-4
0.5
12
5
V
V
V
Input common mode range
See Figure 7-4 and Table 7-1
-12
CANH = CANL = 5V, VCC to GND via 0Ω
and 47kΩ resistor
IOFF(LKG)
power-off bus input leakage current
µA
Input capacitance to ground (CANH
or CANL)
CI
TXD = VCC1
TXD = VCC1
20
10
90
pF
pF
CID
RID
Differential input capacitance
TXD = VCC1 ; -12 V ≤ VCM ≤ +12 V ;
RID = RCAN_H + RCAN_L
Differential input resistance
40
kΩ
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Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXD = VCC1 ; -12 V ≤ VCM ≤ +12 V ;
RCAN_H or RCAN_L = Δ V / Δ I
RIN
Input resistance (CANH or CANL)
20
45
kΩ
Input resistance matching: (1 -
RIN(CANH)/RIN(CANL)) x 100%
RIN(M)
VCANH = VCANL = 5 V
-1
1
%
THERMAL SHUTDOWN
TTSD
Thermal shutdown temperature
Thermal shutdown hysteresis
190
8
℃
℃
TTSD_HYST
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6.10 Switching Characteristics
Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE SWITCHING CHARACTERISTICS
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤
150
203
ns
V
CC1 ≤ 1.89 V
Total loop delay, driver input TXD to
tPROP(LOOP1)
receiver RXD, recessive to dominant
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
150
175
175
199
219
ns
ns
ns
to 90%) on TXD =1 ns; 2.25 V ≤ VCC1
5.5 V
≤
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤ VCC1
1.89 V
≤
Total loop delay, driver input TXD to
tPROP(LOOP2)
receiver RXD, dominant to recessive
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤ VCC1
212
≤
5.5 V
Time for device to return to normal
operation from VCC1 or VCC2 under
voltage event
Re-enable time after Undervoltage
event
tUV_RE_ENABLE
300.0
µs
TXD=VCC1 or GND1, VCM
1200VPK , See Figure 7-9
=
CMTI
Common mode transient immunity
85
kV/µs
DRIVER SWITCHING CHARACTERISTICS
Propagation delay time, Low-to-High
TXD edge to driver recessive
tpHR
85
70
105
105
Propagation delay time, High-to-Low
TXD edge to driver dominant
tpLD
See Figure 7-3 , RL = 60 Ω and CL = 100
pF; input rise/fall time (10% to 90%) on
TXD =1 ns
ns
tsk(p)
tR
pulse skew (|tpHR - tpLD|)
12.5
27
Differential output signal rise time
Differential output signal fall time
tF
42
See Figure 7-3 and Figure 9-3 ,
RTERM =60 Ω, CL =open, CSPLIT= 4.7nF,
TXD= Dominant or receissive or toggling
at 250 kHz, 1 MHz
Driver symmetry (VO(CANH)
VO(CANL))/VCC
+
VSYM
0.9
1.2
1.1
3.8
V/V
ms
See Figure 7-7 , RL = 60 Ω and CL =
open
tTXD_DTO
Dominant time out
RECEIVER SWITCHING CHARACTERISTICS
Propagation delay time, bus
tpRH
dominant-to-recessive input edge to
RXD high output
90
71
130
110
ns
ns
Propogation delay time, bus
recessive-to-dominant input edge to
RXD low output
See Figure 7-5 , CL(RXD) = 15 pF,
tpDL
tR
tF
Output signal rise time(RXD)
Output signal fall time(RXD)
1
1
ns
ns
FD TIMING PARAMETERS
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on CAN bus output pins with
tBIT(TXD) = 500 ns
435.0
155.0
530.0
210.0
ns
ns
tBIT(BUS)
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on CAN bus output pins with
tBIT(TXD) = 200 ns
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Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pin with
tBIT(TXD) = 500 ns
400
550.0
ns
tBIT(RXD)
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pin with
tBIT(TXD) = 200 ns
120.0
-65.0
220.0
40.0
ns
ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD)
- tBIT(BUS)
Receiver timing symmetry with
tBIT(TXD) = 500 ns
∆tREC
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC =
tBIT(RXD) - tBIT(BUS)
Receiver timing symmetry with
tBIT(TXD) = 200 ns
-45.0
15.0
ns
6.11 Insulation Characteristics Curves
600
1200
VCC = 5.5 V
VCC = 3.6 V
VCC = 2.75 V
VCC = 1.89 V
1000
800
600
400
200
0
500
400
300
200
100
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D002
D001
图 6-2. Thermal Derating Curve for Limiting Power
图 6-1. Thermal Derating Curve for Limiting Current
per VDE for 8-D Package
per VDE for 8-D Package
6.12 Typical Characteristics
2.3
40
ICC2 (VCC2 = 4.5V)
ICC2 (VCC2 = 5V)
ICC2 (VCC2 = 5.5V)
38
2.2
2.1
2
ICC1 (VCC1 = 1.8V)
ICC1 (VCC1 = 2.5V)
ICC1 (VCC1 = 3.3V)
ICC1 (VCC1 = 5V)
36
34
32
30
28
26
24
22
20
1.9
1.8
1.7
1.6
1.5
1.4
0
0.5
1
1.5
2
Data Rate (Mbps)
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
Data Rate (Mbps)
2.5
3
3.5
4
4.5
5
D001
D002
图 6-3. Side 1 Supply Current vs Datarate
图 6-4. Side 2 Supply Current vs Datarate
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6.12 Typical Characteristics (continued)
3
40
36
32
28
24
20
16
12
8
Recessive
250 kbps
500 kbps
1 Mbps
2 Mbps
5 Mbps
2.75
2.5
2.25
2
Recessive
250 kbps
500 kbps
1 Mbps
2 Mbps
5 Mbps
1.75
1.5
1.25
1
4
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Temperature (èC)
D003
D004
图 6-5. Side 1 Supply Current vs Ambient Temperature
图 6-6. Side 2 Supply Current vs Ambient Temperature
170
165
160
2.4
2.3
2.2
2.1
2
155
tPROP(LOOP1)
tPROP(LOOP2)
150
145
140
135
130
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D005
D006
图 6-7. Loop Delay vs Ambient Temperature
图 6-8. Dominant state differential output voltage vs Ambient
Temperature
3
2.8
2.6
2.4
2.2
2
1
0.9
0.8
0.7
0.6
0.5
VIT(falling)
VIT(rising)
VHYS
1.8
1.6
1.4
1.2
1
0.4
0.3
0.2
0.1
0
4.5 4.6 4.7 4.8 4.9
5
VCC2 (V)
5.1 5.2 5.3 5.4 5.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D007
D008
图 6-9. Dominant state differential output voltage vs Side2
图 6-10. Receiver differential threshold voltage vs Ambient
supply voltage
Temperature
2.5
2.45
2.4
2.35
2.3
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (èC)
D009
图 6-11. Dominant timeout vs Ambient Temperature
图 6-12. Glitch Free Power Up on VCC1 – CAN Bus Remains
Recessive
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6.12 Typical Characteristics (continued)
图 6-13. Glitch Free Power Up on VCC2 – CAN Bus Remains
图 6-14. Typical TXD, RXD, CANH and CANL Waveforms at 2
Mbps
Recessive
图 6-15. Typical TXD, RXD, CANH and CANL Waveforms at 500 kbps
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7 Parametric Measurement Information
IO(CANH)
CANH
II
0 or
Vcc1
VOD
RL
VO(CANH)
V
O(CANL)
+
2
TXD
CANL
IO(CANL)
GND1
GND2
VI
VOC
VO(CANH)
VO(CANL )
GND1
GND2
图 7-1. Driver Voltage, Current and Test Definitions
Dominant
V
O
(CANH)
» 3.5 V
Recessive
2.5 V
»
V
1.5 V
O (CANL)
»
图 7-2. Bus Logic State Voltage Definitions
Vcc
0 V
CANH
CANL
V
Vcc/2
Vcc/2
I
TXD
RL
VO
CL
t
t
PLH
PHL
V
O(D)
90%
10%
0.9V
VI
V
O
0.5V
(SEE NOTE A)
V
t
t
f
O(R)
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty
cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
图 7-3. Driver Test Circuit and Voltage Waveforms
CANH
IO
VI(CANH) VI(CANL)
RXD
+
VIC
VID
CANL
=
2
VI(CANH)
VO
VI(CANL)
GND2
GND1
图 7-4. Receiver Voltage and Current Definitions
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CANH
I
O
3.5 V
RXD
V
2.4 V
I
2 V
CANL
1.5 V
pHL
t
t
pLH
0.7 Vcc 1
V
V
OH
O
V
I
CL(RXD)
90 %
10 %
(SEE NOTE A)
1 .5 V
0.3 Vcc 1
V
O
V
t
t
f
OL
r
GND 1
GND 2
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
图 7-5. Receiver Test Circuit and Voltage Waveforms
表 7-1. Receiver Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
-11.5 V
12.5 V
-8.55 V
9.45 V
-8.75 V
9.25 V
-11.8 V
12.2 V
Open
VCANL
-12.5 V
11.5 V
-9.45 V
8.55 V
-9.25 V
8.75 V
-12.2 V
11.8 V
Open
|VID|
1000 mV
1000 mV
900 mV
900 mV
500 mV
500 mV
400 mV
400 mV
X
RXD
L
L
VOL
L
L
H
H
H
H
H
VOH
VI
70%
TXD
CANH
30%
30%
0V
tBIT(TXD)
TXD
5 x tBIT
VI
CL
RL
CANL
tBIT(BUS)
900 mV
VDIFF
RXD
500 mV
CL(RXD)
GND1
VO
VOH
70%
RXD
30%
tBIT(RXD)
VOL
图 7-6. tLOOP and CAN FD Timing Parameter Measurement
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Vcc
V
I
CANH
CANL
TXD
0 V
R
V
C
OD
L
L
V
OD(D)
(see Note A )
900 mV
V
I
V
OD
500 mV
tTXD_DTO
0 V
GND 1
A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
图 7-7. Dominant Time-out Test Circuit and Voltage Waveforms
IOS
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
+
VBUS
CANL
VBUS
0V
0V
œ
GND2
or
VBUS
VBUS
图 7-8. Driver Short-Circuit Current Test Circuit and Waveforms
C = 0.1 F
m
1%
V
V
CC 1
CC2
V
CC 1
±
CANH
60 W
C = 0.1 F ±1%
m
+
GND1
TXD
GND
2
V
V
OL
OH
or
S1
CANL
0 V
RXD
V
V
OL
OH
or
GND 1
GND 2
C
L
= 15 pF
(includes probe and
jig capacitance )
V
CM
图 7-9. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO1044B device is a digitally isolated CAN transceiver that offers ±58-V DC bus fault protection and ±12-V
common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much
faster transfer of payload compared to classic CAN. The ISO1044B device has an isolation withstand voltage of
3000 VRMS with a surge isolation voltage of 5kVPK. The device can operate from 1.8-V, 2.5-V, 3.3-V, and 5-V
supplies on side 1 and a 5-V supply on side 2. This supply range is of particular advantage for applications
operating in harsh industrial environments because the low voltage on side 1 enables the connection to low-
voltage microcontrollers for power conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio
of the bus signals.
8.2 Functional Block Diagram
VCC1
VCC2
CANH
CANL
+
RXD
œ
TXD
GND1
GND2
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8.3 Feature Description
8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node uses the TXD pin to drive the bus and receives data from the
bus on the RXD pin. See 图 8-1 and 图 8-2.
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4
3
2
1
CANH
Vdiff(D)
Vdiff(R)
CANL
Time (t)
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
图 8-1. Bus States (Physical Bit Representation)
CANH
RXD
VCC / 2
CANL
图 8-2. Simplified Recessive Common Mode Bias and Receiver
8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,
and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.
8.3.3 Protection Features
8.3.3.1 TXD Dominant Timeout (DTO)
The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware
or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit
timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge
occurs before the timeout period expires, which frees the bus for communication between other nodes on the
network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD
DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased
to the recessive level during a TXD dominant timeout.
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TXD fault stuck dominant
Example: PCB failure or bad software
Fault is repaired and transmission
capability is restored
TXD
(driver)
tTXD_DTO
Driver disabled freeing bus for other nodes
Bus would be stuck dominant, blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the tTXD_DTO time.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus nodes
Communication from
repaired nodes
RXD
(receiver)
Communication from
local node
Communication from
other bus nodes
Communication from
repaired nodes
图 8-3. Example Timing Diagram for TXD DTO
Note
The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD) for the worst case, where five successive dominant bits are
followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum
data rate. Calculate the minimum transmitted data rate with 方程式 1.
Minimum Data Rate = 11 / tTXD_DTO
(1)
8.3.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits, blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYST) below the thermal shutdown temperature (TTSD) of the device.
8.3.3.3 Undervoltage Lockout and Default State
The supply pins have undervoltage detection that places the device in protected or default mode which protects
the bus during an undervoltage event on the VCC1 or VCC2 supply pins. If the bus-side power supply, VCC2, is
less than about 4 V, the power shutdown circuits in the ISO1044B device disable the transceiver to prevent false
transmissions because of an unstable supply. If the VCC1 supply is still active when this occurs, the receiver
output (RXD) goes to a default HIGH (recessive) value. 表 8-1 summarizes the undervoltage lockout and fail-
safe behavior.
表 8-1. Undervoltage Lockout and Default State
VCC1
VCC2
DEVICE STATE
BUS OUTPUT
Per Device State and TXD
Recessive
RXD
> UVVCC1
<UVVCC1
>UVVCC1
> UVVCC2
> UVVCC2
< UVVCC2
Functional
Mirrors Bus
Protected
Undetermined
Protected
High Impedance
Recessive (Default High)
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Note
After an undervoltage condition is cleared and the supplies have returned to valid levels, the device
typically resumes normal operation in 300 µs.
8.3.3.4 Floating Pins
The ISO1044B has internal pull-ups on critical pins which places the device into known states if the pin floats.
This internal bias should not be relied upon by design though, especially in noisy environments, but instead
should be considered a failsafe protection feature.
When a CAN controller supporting open drain outputs is used, an adequate external pull-up resistor must be
used to ensure that the TXD output of the CAN controller maintains adequate bit timing to the input of the CAN
transceiver.
8.3.3.5 Unpowered Device
The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which
is critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
8.3.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit
fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the
second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant
state during a system fault. During CAN communication the bus switches between dominant and recessive
states, therefore the short circuit current may be viewed either as the instantaneous current during each bus
state or as an average current of the two states. For system current (power supply) and power considerations in
the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the
ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and
PHY that force either recessive or dominant at certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high
percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant
bits and their respective short circuit currents. Use Equation 2 to calculate the average short circuit current.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive ×
IOS(SS)_REC
(2)
]
where
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
Note
Consider the short circuit current and possible fault cases of the network when sizing the power
ratings of the termination resistance and other network components.
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8.4 Device Functional Modes
表 8-2 and 表 8-3 list the driver and receiver functions. 表 8-4 lists the functional modes for the ISO1044B
device.
表 8-2. Driver Function Table
INPUT
TXD(1)
L
OUTPUTS
DRIVEN BUS STATE
CANH(1)
CANL(1)
H
Z
L
Z
Dominant
Recessive
H
(1) H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See 图 8-1 and 图 8-2
for bus state and common mode bias information.
表 8-3. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
Normal
BUS STATE
RXD PIN(1)
(3)
VID = VCANH – VCANL
ID ≥ VIT(MAX)
VIT(MIN) < VID < VIT(MAX)
ID ≤ VIT(MIN)
Dominant
Undefined
Recessive
Open
L
V
Undefined
H
H
V
Open (VID ≈ 0 V)
(1) H = high level, L = low level
表 8-4. Function Table
DRIVER(1)
OUTPUTS
RECEIVER
INPUTS
TXD
L(2)
DIFFERENTIAL INPUTS
VID = CANH–CANL(3)
OUTPUT
RXD
BUS STATE
BUS STATE
CANH
CANL
H
Z
Z
L
Z
Z
DOMINANT
RECESSIVE
RECESSIVE
L
Undefined
H
DOMINANT
Undefined
V
ID ≥ VIT(MAX)
VIT(MIN) < VID < VIT(MAX)
ID ≤ VIT(MIN)
H
Open
RECESSIVE
V
X if VCC1 supply
< UVVCC1
Z
Z
RECESSIVE
H
RECESSIVE
Open (VID ≈ 0 V)
(1) H = high level; L = low level; X = irrelevant; Z = high impedance
(2) Logic low pulses to prevent dominant time-out.
(3) See Receiver Electrical Characteristics section for input thresholds.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO1044B device can be used with other components from Texas Instruments such as a microcontroller, a
transformer driver, and a linear voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
4
8
1
3
5
4
GND
D2
IN
OUT
NC
EN
SN6505
3
2
7
6
3.3 V
TPS76350
EN
VCC
2
GND
1
5
CLK
D1
8
3.3 V
1
VCC1
TXD
VCC2
100 nF
100 nF
VDD
7
6
GND2
2
3
TXD
MCU
RXD
ISO
Ground
ISO1044
RXD
CANH
CANL
DGND
Optional bus
protection
circuitry
4
5
GND1
Galvanic
Isolation Barrier
Digital
Ground
CANH
CANL
CMC
Optional bus
protection
circuitry
图 9-1. Application Circuit With ISO1044 in 8-SOIC Package
ISO1044B is optimized for small solution size and meets 8 kV contact ESD (Electrostatic discharge) per IEC
61000-4-2 standalone with no external components on bus. If the application requires the usage of Common
mode choke (CMC) as shown in 图 9-1, then use of Transient voltage suppressor (TVS) is a must to achieve
8kV IEC ESD. Test results with CMC Part number: ACT45B-101-2P-TL003 and TVS Part number: CPDT-12V
show 8 kV IEC ESD (Level 4) pass.
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1044B device only requires external bypass capacitors to operate.
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9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A large number of nodes requires transceivers with high input impedance such as the ISO1044B
transceiver.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable
length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen,
DeviceNet, and NMEA2000.
The ISO1044B device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst case
including parallel transceivers. The differential input resistance of the ISO1044B device is a minimum of 30 kΩ. If
100 ISO1044B transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω differential load
worst case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading of 50 Ω.
Therefore, the ISO1044B device theoretically supports up to 100 transceivers on a single bus segment.
However, for CAN network design margin must be given for signal loss across the system and cabling, parasitic
loadings, network imbalances, ground offsets and signal integrity, therefore a practical maximum number of
nodes is typically much lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m
by careful system design and data-rate tradeoffs. For example, CANopen network design guidelines allow the
network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes, and a
significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the
responsibility of good network design and balancing these tradeoffs.
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed
from the bus.
Node 1
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
图 9-2. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used.
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(See 图 9-3). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM / 2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM / 2
CANL
CANL
图 9-3. CAN Bus Termination Concepts
10 Power Supply Recommendations
To make sure operation is reliable at all data rates and supply voltages, a 0.1-µF bypass capacitor is
recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to
the supply pins as possible. In addition, a bulk capacitance, typically 4.7 μF, can be placed near the VCC2
supply pin. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6505B. For such
applications, detailed power supply design, and transformer selection recommendations are available in the
SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 节 11.2 Figure 11-1). Layer
stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and
low-frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Suggested placement and routing of ISO1044B bypass capacitors and optional TVS diodes is shown in 图 11-2.
In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as possible, and
complete the connection to the VCC2 and GND2 pins without using vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over lower-
cost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater
strength and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图 11-1. Recommended Layer Stack
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图 11-2. 8-D Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, ISO1044 Isolated CAN Transceiver Evaluation Module User's Guide
• Texas Instruments, Isolate your CAN systems without compromising on performance or space TI TechNote
• Texas Instruments, Isolation Glossary
• Texas Instruments, High-voltage reinforced isolation: Definitions and test methodologies
• Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
• Texas Instruments, How to Design Isolated CAN Systems With Correct Bus Protection Application Report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSDE
METAL
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020，德州仪器 (TI) 公司
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO1044BD
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1044B
1044B
ISO1044BDR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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