ISO1211DR_技术文档

Support &

Community

Reference

Design

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

用于数字输入模块的 ISO121x 隔离式 24V 至 60V 数字输入接收器

1 特性

3 说明

1

•

符合 IEC 61131-2 针对 24V 隔离式数字输入的 1、

2、3 类特性标准

ISO1211 和 ISO1212 器件是隔离式 24V 至 60V 数字

输入接收器，符合 IEC 61131-2 1 类、2 类和 3 类特

性标准。这些器件可以在可编程逻辑控制器 (PLC)、电

机控制、电网基础设施和其他工业应用中实现 9V 至

300V 直流和交流数字输入模块。不同于具有分立式、

不精确电流限制电路的传统光耦合器解决方

•

支持 9V 至 300V 直流和交流数字输入设计（使用

外部电阻器）

通过精确电流限制实现低功耗：

–

对于 3 类，电流为 2.2mA 至 2.47mA

可调电流，最高为 6.5mA

案，ISO121x 器件提供具有精确电流限制的简单低功

耗解决方案，可实现紧凑型和高密度 I/O 模块的设计。

这些器件不需要现场侧电源，可配置为拉电流或灌电流

输入。

•

消除了对现场侧电源的需求

具有反极性保护功能的宽输入电压范围：±60V

断线检测（请参阅 TIDA-01509）

可配置为拉电流或灌电流输入

高数据速率：最高 4Mbps

ISO121x 器件的工作电压范围为 2.25V 至 5.5V，支持

2.5V、3.3V 和 5V 控制器。具有反极性保护的 ±60V

输入容差有助于确保输入引脚在可忽略的反向电流发生

故障时受到保护。这些器件支持高达 4Mbps 的数据速

率，可通过 150ns 的最小脉冲宽度，从而实现高速运

行。ISO1211 器件适用于需要通道间隔离功能的设

计，而 ISO1212 器件适用于多通道空间受限的设计。

多路复用器输出信号使能引脚

高瞬态抗扰性：±70kV/µs CMTI

宽电源电压范围 (V_CC1)：2.25V 至 5.5V

环境温度范围：–40°C 至 +125°C

紧凑型封装选项：

–

单通道 ISO1211，SOIC-8

双通道 ISO1212，SSOP-16

与传统解决方案相比，ISO121x 器件减少了组件数

量，简化了系统设计，提高了性能，降低了电路板温

度。有关详细信息，请参阅《如何简化隔离式 24V

PLC 数字输入模块设计》TI 技术手册、《如何提高电

机驱动中的隔离式数字输入的速度和可靠性》TI 技术

手册以及《如何设计用于 ±48V、110V 和 240V 直流

和交流检测的隔离式比较器》TI 技术手册。

•

安全相关认证：

–

符合 DIN V VDE V 0884-10 标准的基本绝缘

UL 1577 认证，2500V_RMS绝缘

可提供 CSA、CQC、TUV 认证

2 应用

•

可编程逻辑控制器 (PLC)

器件信息⁽¹⁾

–

数字输入模块

器件型号

ISO1211

ISO1212

封装

SOIC (8)

SSOP (16)

封装尺寸（标称值）

4.90mm × 3.91mm

4.90mm × 3.90mm

混合 I/O 模块

•

电机驱动 I/O 和位置反馈

CNC 控制

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

变电站自动化

数据采集

二进制输入模块

ISO121x 器件与传统解决方案相比可降低电路板温度

应用图表

T_A= 25°C

Field

PLC Digital Input Module

ISO1211

R_THR

V_CC1

OUT

SENSE

IN

Host

Controller

R_SENSE

Sensor/

Switch

24 V

FGND

GND1

a) 8-Ch With ISO1212 b) 8-Ch Traditional Solution Without Current Limit

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSEY7

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 18

Application and Implementation ........................ 19

9.1 Application Information............................................ 19

9.2 Typical Application .................................................. 19

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Power Ratings........................................................... 6

6.6 Insulation Specifications............................................ 7

6.7 Safety-Related Certifications..................................... 8

6.8 Safety Limiting Values .............................................. 9

6.9 Electrical Characteristics—DC Specification........... 10

6.10 Switching Characteristics—AC Specification........ 11

6.11 Insulation Characteristics Curves ......................... 12

6.12 Typical Characteristics.......................................... 13

Parameter Measurement Information ................ 14

7.1 Test Circuits ............................................................ 14

Detailed Description ............................................ 17

9

10 Power Supply Recommendations ..................... 30

11 Layout................................................................... 31

11.1 Layout Guidelines ................................................. 31

11.2 Layout Example .................................................... 31

12 器件和文档支持 ..................................................... 33

12.1 器件支持................................................................ 33

12.2 文档支持................................................................ 33

12.3 相关链接................................................................ 33

12.4 接收文档更新通知 ................................................. 33

12.5 社区资源................................................................ 33

12.6 商标....................................................................... 33

12.7 静电放电警告......................................................... 33

12.8 术语表 ................................................................... 34

13 机械、封装和可订购信息....................................... 34

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision D (March 2018) to Revision E

Page

•

已更改 V_IHand V_IHto V_ILand V_IHin the R_THRresistor description in the Setting Current Limit and Voltage Thresholds

section .................................................................................................................................................................................. 21

Changes from Revision C (February 2018) to Revision D

Page

•

更新了特性和应用部分。在说明和相关文档部分中添加了新的 TI 技术手册参考。............................................................ 1

Changed the unit for CPG from µm to mm in the Insulation Specifications table.................................................................. 7

已更改 the Functional Block Diagram................................................................................................................................... 17

已更改 V_ILfrom min to typ in the V_ILequation ...................................................................................................................... 22

已添加 the Designing for Input Voltages Greater Than 60 V section................................................................................... 24

已添加 the bidirectional implementation example to the Sourcing and Sinking Inputs section............................................ 30

Changes from Revision B (September 2017) to Revision C

Page

•

已添加将断线检测添加到特性部分........................................................................................................................................ 1

已添加将多路复用器输出信号使能引脚添加到了特性部分中，更改了所有需要为 DW 和 D 封装完成的认证 ...................... 1

已更改 R_THR= 5 kΩ to 4 kΩ in the High-Level Voltage Transition Threshold vs Ambient Temperature graph.................... 13

已更改 the Type 1 R_THvalue from 3 kΩ to 2.5 kΩ in the Surge, IEC ESD and EFT table................................................... 25

Changes from Revision A (September 2017) to Revision B

Page

•

已更改将状态从预告信息改为生产数据.................................................................................................................................. 1

2

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

5 Pin Configuration and Functions

ISO1211 D Package

8-Pin SOIC

Top View

V_CC1

SENSE

1

2

3

4

8

7

6

5

EN

IN

FGND

SUB

OUT

GND1

Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

V_CC1

—

Power supply, side 1

Output enable. The output pin on side 1 is enabled when the EN pin is high or open. The output pin on

side 1 is in the high-impedance state when the EN pin is low. In noisy applications, tie the EN pin to

2

EN

I

V_CC1

.

3

4

5

6

7

8

OUT

GND1

SUB

O

—

I

Channel output

Ground connection for V_CC1

Internal connection to input chip substrate. Leave this pin unconnected on the board.

FGND

IN

Field-side ground

Field-side current input

Field-side voltage sense

SENSE

I

3

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

ISO1212 DBQ Package

16-Pin SSOP

Top View

GND1

1

2

3

4

5

6

7

8

16 SENSE1

V_CC1

EN

15

IN1

14 FGND1

13 SUB1

OUT1

OUT2

NC

Functional Isolation

12 SUB2

11 SENSE2

NC

10

9

IN2

GND1

FGND2

Pin Functions

NAME

I/O

Description

NO.

1

GND1

V_CC1

—

Ground connection for V_CC1

Power supply, side 1

2

Output enable. The output pins on side 1 are enabled when the EN pin is high or open. The output

pins on side 1 are in the high-impedance state when the EN pin is low. In noisy applications, tie the EN

3

EN

I

pin to V_CC1

.

4

OUT1

OUT2

O

Channel 1 output

Channel 2 output

5

6

NC

—

Not connected

7

8

GND1

FGND2

IN2

—

I

Ground connection for V_CC1

9

Field-side ground, channel 2

10

11

12

13

14

15

16

Field-side current input, channel 2

SENSE2

SUB2

I

Field-side voltage sense, channel 2

—

I

Internal connection to input chip 2 substrate. Leave this pin unconnected on the board.

Internal connection to input chip 1 substrate. Leave this pin unconnected on the board.

Field-side ground, channel 1

SUB1

FGND1

IN1

Field-side current input, channel 1

SENSE1

I

Field-side voltage sense, channel 1

4

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_CC1

Supply voltage, control side

Voltage on OUTx pins and EN pin

Output current on OUTx pins

–0.5

6

V

V_OUTx

V_EN

,

–0.5

V_CC1+ 0.5⁽²⁾

V

I_O

–15

–60

–40

–65

15

60

mA

V

V_INx, V_SENSExVoltage on IN and SENSE pins

V_(ISO,FUNC)

Functional isolation between channels in ISO1212 on the field side

60

V

T_J

Junction temperature

Storage temperature

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

MAX

UNIT

V_CC1

V_INx

V_SENSEx

Supply voltage input side

2.25

5.5

V

,

Voltage on INx and SENSEx pins⁽¹⁾

–60

60

V

V_CC1= 5 V

–4

–3

–2

I_OH

High-level output current from OUTx pin

Low-level output current into OUTx pin

V_CC1= 3.3 V

V_CC1= 2.5 V

V_CC1= 5 V

mA

4

3

2

I_OL

V_CC1= 3.3 V

V_CC1= 2.5 V

t_UI

T_A

Minimum pulse width at SENSEx pins

Ambient temperature

150

–40

ns

°C

125

(1) See the Thermal Considerations section.

5

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

6.4 Thermal Information

ISO1211

D (SOIC)

8 PINS

146.1

63.1

ISO1212

DBQ (SSOP)

16 PINS

116.9

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

56.5

80

64.7

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

9.6

27.9

Ψ_JB

79

64.1

R_θJC(bot)

—

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ISO1211

V_SENSE= 60 V, V_CC1= 5.5 V, R_SENSE= 200 Ω,

R_THR= 0 Ω, T_J= 150°C

P_DMaximum power dissipation, both sides

450

20

mW

Maximum power dissipation, output side V_CC1= 5.5 V, C_L= 15 pF, Input 2-MHz 50% duty-

P_D1

P_D2

(side 1)

cycle square wave at SENSE pin, T_J= 150°C

Maximum power dissipation, field input V_SENSE= 60 V, V_CC1= 5.5 V, R_SENSE= 200 Ω,

430

side

R_THR= 0 Ω, T_J= 150°C

ISO1212

V_SENSEx= 60 V, V_CC1= 5.5 V, R_SENSE= 200 Ω,

R_THR= 0 Ω, T_J= 150°C

P_DMaximum power dissipation, both sides

900

40

mW

Maximum power dissipation, output side V_CC1= 5.5 V, C_L= 15 pF, Input 2-MHz 50% duty-

P_D1

P_D2

(side 1)

Maximum power dissipation, field input V_SENSEx= 60 V, V_CC1= 5.5 V, R_SENSE= 200 Ω,

side R_THR= 0 Ω, T_J= 150°C

cycle square wave at SENSEx pins, T_J= 150°C

860

6

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

6.6 Insulation Specifications

SPECIFICATION

UNIT

PARAMETER

TEST CONDITIONS

D-8

DBQ-16

CLR

CPG

External clearance⁽¹⁾

External Creepage⁽¹⁾

Shortest terminal-to-terminal distance through air

4

3.7

mm

Shortest terminal-to-terminal distance across the

package surface

4

3.7

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

10.5

> 600

I

10.5

> 600

I

µm

V

Rated mains voltage ≤ 150 V_RMS

I-IV

I-III

I-IV

I-III

Overvoltage category

Rated mains voltage ≤ 300 V_RMS

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾

Maximum repetitive peak isolation

voltage

V_IORM

AC voltage (bipolar)

566

V_PK

AC voltage (sine wave); time-dependent dielectric

breakdown (TDDB) test

400

566

400

566

V_RMS

V_DC

V_PK

V_IOWM

Maximum working isolation voltage

DC voltage

V_TEST= V_IOTM, t = 60 s (qualification),

V_TEST= V_IOTM, t= 1 s (100% production)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

3600

Test method per IEC 60065-1, 1.2/50 µs

waveform,

V_TEST= 1.3 × V_IOSM= 5200 V_PK(qualification)

V_IOSM

4000

< 5

4000

< 5

V_PK

Method a: After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.2 × V_IORM= 680 V_PK, t_m= 10 s

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.3 × V_IORM= 736 V_PK, t_m= 10 s

< 5

q_pd

Apparent charge⁽⁴⁾

pC

Method b1: At routine test (100% production) and

preconditioning (type test),

V_ini= V_IOTM, t_ini= 1 s;

< 5

V_pd(m)= 1.5 × V_IORM= 849 V_PK, t_m= 10 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾V_IO= 0.4 × sin (2 πft), f = 1 MHz

440

> 10¹²

> 10¹¹

> 10⁹

560

> 10¹²

> 10¹¹

> 10⁹

fF

V_IO= 500 V, T_A= 25°C

Insulation resistance, input to

V_IO= 500 V, 100°C ≤ T_A≤ 125 °C

output⁽⁵⁾

Ω

V_IO= 500 V at T_S= 150 °C

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 2500 V_RMS, t = 60 s (qualification);

V_ISO

Withstand isolation voltage

2500

V_RMS

V_TEST= 1.2 × V_ISO= 3000 V_RMS, t = 1 s (100%

production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall

be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

7

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

6.7 Safety-Related Certifications

VDE

CSA

UL

CQC

TUV

Certified according to

DIN V VDE V 0884-10

(VDE V 0884-10):2006-

12 and DIN EN 61010-1

(VDE 0411-1):2011-07

Certified according to EN

61010-1:2010 (3rd Ed) and

EN 60950-

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013

Recognized under UL

1577 Component

Recognition Program

Certified according to IEC

60950-1 and IEC 62368-1

Certified according to

GB4943.1-2011

Basic insulation per EN

61010-1:2010 (3rd Ed) up

to working voltage of 300

Basic Insulation,

Maximum Transient

Isolation Voltage, 3600

370 V_RMS(ISO1212) and

400 V_RMS(ISO1211) Basic

Insulation working voltage

per CSA 60950-1-07+A1 +

A2 and IEC 60950-1 2nd

Ed. + A1 + A2

300 V_RMSBasic Insulation

working voltage per CSA

62368-1-14 and IEC 62368-

1 2nd Ed.

V_RMS

,

V_PK

,

Basic Insulation, Altitude ≤

5000m, Tropical Climate,

400 V_RMSmaximum

working voltage

Basic insulation per EN

60950-

Single protection, 2500

V_RMS

Maximum Repetitive

Peak Isolation Voltage,

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013 up to

working voltage of 370

V_RMS(ISO1212) and 400

V_RMS(ISO1211)

566 V_PK

,

Maximum Surge

Isolation Voltage, 4000

V_PK

ISO1211 Certificate

number:

CQC15001121656,

ISO1212 Certification

Planned

Certificate number:

40016131

Master contract number:

220991

File number: E181974

Client ID number: 77311

8

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ISO1211

R

_θJA= 146.1°C/W, V_I= 2.75 V, T_J= 150°C,

310

237

155

35

T_A= 25°C, see 图 1

_θJA= 146.1°C/W, V_I= 3.6 V, T_J= 150°C,

T_A= 25°C, see 图 1

_θJA= 146.1°C/W, V_I= 5.5 V, T_J= 150°C,

T_A= 25°C, see 图 1

_θJA= 146.1°C/W, V_I= 24 V, T_J= 150°C,

T_A= 25°C, see 图 1

_θJA= 146.1°C/W, V_I= 36 V, T_J= 150°C,

T_A= 25°C, see 图 1

_θJA= 146.1°C/W, V_I= 60 V, T_J= 150°C,

T_A= 25°C, see 图 1

_θJA= 146.1°C/W, T_J= 150°C, T_A= 25°C,

see 图 2

Safety input, output, or supply

current - side 1

R

I_S

mA

R

I_S

Safety input current - field side

23

mA

R

14

Safety input, output, or total

power

R

P_S

855

150

mW

°C

T_S

Maximum safety temperature

ISO1212

R

_θJA= 116.9°C/W, V_I= 2.75 V, T_J= 150°C,

389

297

194

44

T_A= 25°C, see 图 3

Safety input, output, or supply

current - side 1

R_θJA= 116.9°C/W, V_I= 3.6 V, T_J= 150°C,

I_S

mA

T_A= 25°C, see 图 3

R_θJA= 116.9°C/W, V_I= 5.5 V, T_J= 150°C,

T_A= 25°C, see 图 3

R_θJA= 116.9°C/W, V_I= 24 V, T_J= 150°C,

T_A= 25°C, see 图 3

R

_θJA= 116.9°C/W, V_I= 36 V, T_J= 150°C,

I_S

Safety input current - field side

29

T_A= 25°C, see 图 3

R

_θJA= 116.9°C/W, V_I= 60 V, T_J= 150°C,

17

T_A= 25°C, see 图 3

Safety input, output, or total

power

R

_θJA= 116.9°C/W, T_J= 150°C, T_A= 25°C,

P_S

T_S

1070

150

mW

°C

see 图 4

Maximum safety temperature

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air

thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air

thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount

packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient

temperature plus the power times the junction-to-air thermal resistance.

9

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

MAX UNIT

6.9 Electrical Characteristics—DC Specification

(Over recommended operating conditions unless otherwise noted).

PARAMETER

V_CC1VOLTAGE SUPPLY

Positive-going UVLO threshold voltage

(V_CC1

V_{IT– (UVLO1)}Negative-going UVLO threshold (V_CC1

V_{HYS (UVLO1)}UVLO threshold hysteresis (V_CC1

TEST CONDITIONS

MIN

TYP

V_{IT+ (UVLO1)}

2.25

V

)

1.7

V

)

0.2

0.6

1.2

ISO1211

ISO1212

1

V_CC1supply

quiescent current

I_CC1

EN = V_CC1

mA

1.9

LOGIC I/O

Positive-going input logic threshold

voltage for EN pin

0.7 ×

V_CC1

V_{IT+ (EN)}

V

Negative-going input logic threshold

voltage for EN pin

0.3 ×

V_CC1

V_{IT– (EN)}

0.1 ×

V_CC1

V_HYS(EN)

I_IH

V_OH

Input hysteresis voltage for EN pin

Low-level input leakage at EN pin

V

EN = GND1

–10

μA

V_CC1= 4.5 V; I_OH= –4 mA

V_CC1= 3 V; I_OH= –3 mA

V_CC1= 2.25 V; I_OH= –2 mA, see 图 10

V_CC1

– 0.4

High-level output voltage on OUTx

Low-level output voltage on OUTx

V

V_CC1= 4.5 V; I_OH= 4 mA

V_CC1= 3 V; I_OH= 3 mA

V_OL

0.4

V_CC1= 2.25 V ; I_OH= 2 mA, see 图 10

CURRENT LIMIT

I_{(INx+SENSEx),}Typical sum of current drawn from IN

R_THR= 0 Ω, R_SENSE= 562 Ω, V_SENSE= 24 V,

–40°C < T_A< 125°C, see 图 11

2.2

2.47 mA

µA

and SENSE pins across temperature

TYP

R_THR= 0 Ω, R_SENSE= 562 Ω ± 1%;

–60 V < V_SENSE< 0 V, see 图 11

–0.1

R_THR= 0 Ω, R_SENSE= 562 Ω ± 1%;

5 V < V_SENSE< V_IL, see 图 11

1.9

2.05

2.1

2.5

R_THR= 0 Ω, R_SENSE= 562 Ω ± 1%;

V_IL< V_SENSE< 30 V, see 图 11

2.75

mA

R_THR= 0 Ω, R_SENSE= 562 Ω ± 1%;

30 V < V_SENSE< 36 V, see 图 11

2.83

Sum of current drawn from IN and

R_THR= 0 Ω, R_SENSE= 562 Ω ± 1%;

36 V < V_SENSE< 60 V⁽¹⁾, see 图 11

I_(INx+SENSEx)

SENSE pins

2.1

3.1

µA

6.8

R_THR= 0 Ω, R_SENSE= 200 Ω ± 1%;

–60 V < V_SENSE< 0 V, see 图 11

–0.1

R_THR= 0 Ω, R_SENSE= 200 Ω ± 1%;

5 V < V_SENSE< V_IL, see 图 11

5.3

5.5

R_THR= 0 Ω, R_SENSE= 200 Ω ± 1%;

V_IL< V_SENSE< 36 V⁽¹⁾, see 图 11

7

mA

R_THR= 0 Ω, R_SENSE= 200 Ω ± 1%;

36 V < V_SENSE< 60 V⁽¹⁾, see 图 11

7.3

(1) See the Thermal Considerations section.

10

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

Electrical Characteristics—DC Specification (continued)

(Over recommended operating conditions unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VOLTAGE TRANSITION THRESHOLD ON FIELD SIDE

R_SENSE= 562 Ω, R_THR= 0 Ω, see 图 11

R_SENSE= 562 Ω, R_THR= 1 kΩ, see 图 11

R_SENSE= 562 Ω, R_THR= 4 kΩ, see 图 11

R_SENSE= 562 Ω, R_THR= 0 Ω, see 图 11

R_SENSE= 562 Ω, R_THR= 1 kΩ, see 图 11

R_SENSE= 562 Ω, R_THR= 4 kΩ, see 图 11

R_SENSE= 562 Ω, R_THR= 0 Ω, see 图 11

R_SENSE= 562 Ω, R_THR= 1 kΩ, see 图 11

R_SENSE= 562 Ω, R_THR= 4 kΩ, see 图 11

6.5

8.7

7

9.2

Low level threshold voltage at module

input (including R_THR) for output high

V_IL

V

15.2

15.8

8.2

8.55

High level threshold voltage at module

input (including R_THR) for output low

V_IH

10.4 10.95

V

17 18.25

1

1.2

Threshold voltage hysteresis at module

V_HYS

input

6.10 Switching Characteristics—AC Specification

(Over recommended operating conditions unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output signal rise and fall time,

OUTx pins

t_r, t_f

t_PLH

t_PHL

Input rise and fall times = 10 ns, see 图 10

3

ns

Propagation delay time for low to

high transition

110

140

ns

Propagation delay time for high

to low transition

10

15

t_sk(p)

t_UI

Pulse skew |t_PHL- t_PLH

|

Input rise and fall times = 10 ns, see 图 10

Input rise and fall times = 125 ns, see 图 10

102

130

ns

Minimum pulse width

150

Disable propagation delay, high-

to-high impedance output

t_PHZ

t_PLZ

t_PZH

t_PZL

See 图 13

See 图 12

See 图 13

See 图 12

See 图 14

17

3

40

ns

Disable propagation delay, low-

to-high impedance output

Enable propagation delay, high

impedance-to-high output

8.5

40

µs

Enable propagation delay, high

impedance-to-low output

17

70

ns

Common mode transient

immunity

CMTI

25

kV/µs

11

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

6.11 Insulation Characteristics Curves

900

800

700

600

500

400

300

200

100

0

350

V_CC1= 2.75 V

V_CC1= 3.6 V

V_CC1= 5.5 V

V_INx= 24 V

V_INx= 36 V

V_INx= 60 V

300

250

200

150

100

50

0

50

100

150

200

0

50

100

150

200

Ambient Temperature (èC)

D002

D001

图 2. Thermal Derating Curve for Safety Limiting Power per

图 1. Thermal Derating Curve for Safety Limiting Current per

VDE for D-8 Package

450

1200

1000

800

600

400

200

0

V_CC1= 2.75 V

400

350

300

250

200

150

100

50

V_CC1= 3.6 V

V_CC1= 5.5 V

V_INx= 24 V

V_INx= 36 V

V_INx= 60 V

0

50

100

150

200

0

50

100

150

200

Ambient Temperature (èC)

D004

D003

图 4. Thermal Derating Curve for Safety Limiting Power per

图 3. Thermal Derating Curve for Safety Limiting Current per

VDE for DBQ-16 Package

12

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

6.12 Typical Characteristics

2.75

2.5

2.25

2

3

2.75

2.5

-40èC

25èC

85èC

105èC

115èC

125èC

1.75

1.5

1.25

1

œ40°C

25°C

85°C

105°C

115°C

125°C

0.75

0.5

0.25

0

2.25

2

0

5

10

15

20

25

30

35

40

45

50

55

60

Input Voltage (V)

D006

R_SENSE= 562 Ω

R_THR= 0 Ω

R_SENSE= 562 Ω

R_THR= 0 Ω

图 5. Input Current vs Input Voltage

图 6. Input Current vs Input Voltage

20

19

18

17

16

15

14

13

12

11

10

9

18

17

16

15

14

13

12

11

10

9

R_THR= 0 kW

R_THR= 1 kW

R_THR= 2 kW

R_THR= 3 kW

R_THR= 4 kW

8

7

6

R_THR= 0 kW

R_THR= 1 kW

R_THR= 2 kW

R_THR= 3 kW

R_THR= 4 kW

8

5

7

4

-50

-30

-10

10

30

50

70

90

110 130

-50

-30

-10

10

30

50

70

90

110 130

Temperature (èC)

D007

D008

R_SENSE= 562 Ω

图 7. High-Level Voltage Transition Threshold vs Ambient

图 8. Low-Level Voltage Transition Threshold vs Ambient

Temperature

7

6

5

4

3

2

1

0

-40èC

25èC

85èC

105èC

115èC

125èC

0

10

20

30

40

50

60

70

Input Voltage (V)

D009

R_SENSE= 200 Ω

R_THR= 0 Ω

图 9. Input Current vs Input Voltage

13

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

7 Parameter Measurement Information

7.1 Test Circuits

SENSE

18 V

V

50%

I

50%

0 V

R_SENSE

Capacitive

Isolation

IN

V_CC1

Signal

t

PHL

PLH

V_I

Generator

100 nF

V

OH

OL

90%

10%

50%

V

O

t

r

t

f

FGND

OUT

C_L

15 pF

V_O

GND1

图 10. Switching Characteristics Test Circuit and Voltage Waveforms

R_THR

SENSE

I_(Inx+SENSEx)

R_SENSE

Capacitive

Isolation

IN

V_CC1

100 nF

Signal

V_I

Generator

FGND

OUT

C_L

15 pF

V_O

GND1

图 11. Input Current and Voltage Threshold Test Circuit

14

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

Test Circuits (接下页)

SENSE

0 V

R_SENSE

V

CC1

0 V

Capacitive

Isolation

IN

V_CC1

V

/ 2

CC1

V

/ 2

CC1

V

I

R_L

t

PLZ

PZL

1 kꢀ

V

OH

0.5 V

V

O

V_O

50%

FGND

OUT

OL

C_L

EN1

15 pF

GND1

Signal

50 ꢀ

V_I

Generator

图 12. Enable and Disable Propagation Delay Time Test Circuit and Waveform—Logic Low State

15

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

Test Circuits (接下页)

SENSE

24 V

V

CC1

R_SENSE

Capacitive

Isolation

IN

V

/ 2

CC1

V_CC1

V

/ 2

CC1

V

I

0 V

t

PZH

V

OH

50%

0.5 V

V

O

V_O

FGND

OUT

0 V

t

PHZ

C_L

15 pF

R_L

1 kꢀ

EN1

GND1

Signal

Generator

50 ꢀ

V_I

图 13. Enable and Disable Propagation Delay Time Test Circuit and Waveform—Logic High State

S1

SENSE

+

24 V

œ

R_SENSE

Capacitive

Isolation

IN

V_CC1

100 nF

FGND

OUT

C_L

15 pF

V_OHor V_OL

GND1

FGND

GND1

+ V_CM

œ

(1) Pass Criterion: The output must remain stable.

图 14. Common-Mode Transient Immunity Test Circuit

16

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

8 Detailed Description

8.1 Overview

The ISO1211 and ISO1212 devices are fully-integrated, isolated digital-input receivers with IEC 61131-2 Type 1,

2, and 3 characteristics. The devices receive 24-V to 60-V digital-input signals and provide isolated digital

outputs. No field-side power supply is required. An external resistor, R_SENSE, on the input-signal path precisely

sets the limit for the current drawn from the field input based on an internal feedback loop. The voltage transition

thresholds are compliant with Type 1, 2, and 3 and can be increased further using an external resistor, R_THR. For

more information on selecting the R_SENSEand R_THRresistor values, see the Detailed Design Procedure section.

The ISO121x devices use an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a

silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to

represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the

signal after advanced signal conditioning and produces the output through a buffer stage. The conceptual block

diagram of the ISO121x device is shown in the Functional Block Diagram section.

8.2 Functional Block Diagram

R_THR

SENSE

IN

INPUT

R_SENSE

CURRENT

LIMIT

OUT

REF

FGND

8.3 Feature Description

The ISO121x devices receive 24-V to 60-V digital input signals and provide isolated digital outputs. An external

resistor, R_SENSE, connected between the INx and SENSEx pins, sets the limit for the current drawn from the field

input. Internal voltage comparators connected to the SENSEx pins determine the input-voltage transition

thresholds.

The output buffers on the control side are capable of providing enough current to drive status LEDs. The EN pin

is used to enable the output buffers. A low state on the EN pin puts the output buffers in a high-impedance state.

The ISO121x devices are capable of operating up to 4 Mbps. Both devices support an isolation withstand voltage

of 2500 V_RMSbetween side 1 and side 2. 表 1 provides an overview of the device features.

表 1. Device Features

PART NUMBER

CHANNELS

MAXIMUM DATA RATE

PACKAGE

RATED ISOLATION

2500 V_RMS

3600 V_PK

,

ISO1211

1

4 Mbps

8-pin SOIC (D)

2500 V_RMS

3600 V_PK

,

ISO1212

2

4 Mbps

16-pin SSOP (DBQ)

17

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

8.4 Device Functional Modes

表 2 lists the functional modes for the ISO121x devices.

表 2. Function Table⁽¹⁾

SIDE 1 SUPPLY

V_CC1

INPUT

(INx, SENSEx)

OUTPUT ENABLE

(EN)

OUTPUT

(OUTx)

COMMENTS

H

L

H or Open

H

L

Channel output assumes the logic state of channel

input.

When INx and SENSEx are open, the output of the

corresponding channel goes to Low.

PU

PD

Open

X

H or Open

L

Z

A low value of output enable causes the outputs to

be high impedance.

When V_CC1is unpowered, a channel output is

undetermined⁽²⁾. When V_CC1transitions from

unpowered to powered up; a channel output

assumes the logic state of the input.

X

Undetermined

(1) V_CC1= Side 1 power supply; PU = Powered up (V_CC1≥ 2.25 V); PD = Powered down (V_CC1≤ 1.7 V); X = Irrelevant; H = High level; L =

Low level; Z = High impedance

(2) The outputs are in an undetermined state when 1.7 V < V_CC1< 2.25 V.

18

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO1211 and ISO1212 devices are fully-integrated, isolated digital-input receivers with IEC 61131-2 Type 1,

2, and 3 characteristics. These devices are suitable for high-channel density, digital-input modules for

programmable logic controllers and motor control digital input modules. The devices receive 24-V to 60-V digital-

input signals and provide isolated digital outputs. No field side power supply is required. An external resistor,

R_SENSE, on the input signal path precisely sets the limit for the current drawn from the field input. This current limit

helps minimize power dissipated in the system. The current limit can be set for Type 1, 2, or 3 operation. The

voltage transition thresholds are compliant with Type 1, 2, and 3 and can be increased further using an external

resistor, R_THR. For more information on selecting the R_SENSEand R_THRresistor values, see the Detailed Design

Procedure section. The ISO1211 and ISO1212 devices are capable of high speed operation and can pass

through a minimum pulse width of 150 ns. The ISO1211 device has a single receive channel. The ISO1212

device has two receive channels that are independent on the field side.

Type 1

Type 2

Type 3

30

25

20

15

10

5

30

25

20

15

10

5

30

25

20

15

10

5

ON

OFF

0

œ3

0

5

10

15

0

5

10

15

I_IN(mA)

20

25

30

0

5

10

15

I_IN(mA)

图 15. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches

9.2 Typical Application

9.2.1 Sinking Inputs

图 16 shows the design for a typical multichannel, isolated digital-input module with sinking inputs. Push-button

switches, proximity sensors, and other field inputs connect to the host controller through an isolated interface.

The design is easily scalable from a few channels, such as 4 or 8, to many channels, such as 256 or more. The

R_SENSEresistor limits the current drawn from the input pins. The R_THRresistor is used to adjust the voltage

thresholds and limit the peak current during surge events. The C_INcapacitor is used to filter noise on the input

pins. For more information on selecting R_SENSE, R_THR, and C_IN, see the Detailed Design Procedure section.

The ISO121x devices derive field-side power from the input pins which eliminates the requirement for a field-

side, 24-V input power supply to the module. Similarly, an isolated dc-dc converter creating a field-side power

supply from the controller side back plane supply is also eliminated which improves flexibility of system design

and reduces system cost.

For systems requiring channel-to-channel isolation on the field side, use the ISO1211 device as shown in 图 17.

19

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

Typical Application (接下页)

PLC Digital Input Module

Field Side

PLC

5 V or 3.3 V or 2.5 V

Backplane supply

ISO1212

SENSE1

R_THR

V_CC

V_CC1

C_IN

R_SENSE

OUT1

IN1

FGND1

R_THR

SENSE2

C_IN

R_SENSE

OUT2

GND1

24 V

IN2

Power

Supply

0 V

FGND2

Host

Controller

Sensors and

Switches

ISO1212

R_THR

SENSE1

V_CC1

C_IN

R_SENSE

IN1

OUT1

FGND1

R_THR

SENSE2

C_IN

R_SENSE

OUT2

GND1

IN2

FGND2

GND

Field Ground

(FGND)

500 pF/2 kV

Protection

Earth (PE)

图 16. Typical Application Schematic With Sinking Inputs

20

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

Typical Application (接下页)

5 V or 3.3 V or 2.5 V

Backplane Supply

ISO1211

SENSE

R_THR

V_CC

V_CC1

OUT

C_IN

R_SENSE

+

24 V

œ

IN

FGND

GND1

Host

Controller

ISO1211

R_THR

V_CC1

OUT

SENSE

IN

C_IN

R_SENSE

+

24 V

œ

FGND

GND

GND1

图 17. Single-Channel or Channel-to-Channel Isolated Designs With ISO1211

9.2.1.1 Design Requirements

The ISO121x devices require two resistors, R_THRand R_SENSE, and a capacitor, C_IN, on the field side. For more

information on selecting R_SENSE, R_THR, and C_IN, see the Detailed Design Procedure section. A 100-nF decoupling

capacitor is required on V_CC1

.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Setting Current Limit and Voltage Thresholds

The R_SENSEresistor limits the current drawn from the field input. A value of 562 Ω for R_SENSEis recommended for

Type 1 and Type 3 operation, and results in a current limit of 2.25 mA (typical). A value of 200 Ω for R_SENSEis

recommended for Type 2 operation, and results in a current limit of 6 mA (typical). In each case, a (slightly) lower

value of R_SENSEcan be selected based on the need for a higher current limit or component availability. For more

information, see the Electrical Characteristics—DC Specification table and Typical Characteristics section. A 1%

tolerance is recommended on R_SENSEbut 5% resistors can also be used if higher variation in the current limit

value is acceptable. The relationship between the R_SENSEresistor and the typical current limit (I_L) is given by 公式

1.

2.25 mA ì 562 W

I_L=

R_SENSE

(1)

The R_THRresistor sets the voltage thresholds (V_ILand V_IH) as well as limits the surge current. A value of 1 kΩ is

recommended for R_THRin Type 3 systems (maximum threshold voltage required is 11 V). A value of 2.5 kΩ is

recommended for R_THRin Type 1 systems (maximum threshold voltage required is 15 V) and a value of 330 Ω is

recommended for R_THRin Type 2 systems. The Electrical Characteristics—DC Specification table lists and the

Typical Characteristics section describes the voltage thresholds with different values of R_THR. For other values of

R_THR, derive the values through linear interpolation. Use 公式 2 and 公式 3 to calculate the values for the typical

V_IHvalues and minimum V_ILvalues, respectively.

2.25 mA ì 562 W

V

(typ) = 8.25 V + R_THRì

IH

R_SENSE

(2)

21

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

Typical Application (接下页)

2.25 mA ì 562 W

V

(typ) = 7.1 V + R_THRì

IL

R_SENSE

(3)

The maximum voltage on the SENSE pins of the ISO121x device is 60 V. However, because the R_THRresistor

drops additional voltage, the maximum voltage supported at the module inputs is higher and given by 公式 4.

2.1mA ì 562 W

V

(max) = 60 V + R_THRì

IN

R_SENSE

(4)

Use the ISO121x Threshold Calculator for 9V to 300V DC and AC Voltage Detection to estimate the values of

the voltage transition thresholds, the maximum-allowed module input voltage, and module input current for the

given values of the R_SENSEand R_THRresistors.

A value of 0 Ω for R_THRalso meets Type 1, Type 2 and Type 3 voltage-threshold requirements. The value of

R_THRshould be maximized for best EMC performance while meeting the desired input voltage thresholds.

Because R_THRis used to limit surge current, 0.25 W MELF resistors must be used.

图 18 shows the typical input current characteristics and voltage transition thresholds for 562-Ω R_SENSEand 1-kΩ

R_THR

.

2.75

2.5

2.25

2

1.75

1.5

1.25

1

œ40°C

25°C

85°C

105°C

115°C

125°C

0.75

0.5

0.25

0

5

10

15

20

25

30

Input Voltage (V)

图 18. Transition Thresholds

9.2.1.2.2 Thermal Considerations

Thermal considerations constrain operation at different input current and voltage levels. The power dissipated

inside the ISO121x devices is determined by the voltage at the SENSE pin (V_SENSE) and the current drawn by the

device (I_(INx+SENSEx)). The internal power dissipated, when taken with the junction-to-air thermal resistance defined

in the Thermal Information table can be used to determine the junction temperature for a given ambient

temperature. The junction temperature must not exceed 150°C.

图 19 shows the maximum allowed ambient temperature for the ISO1211 device for different current limit and

input voltage conditions. The ISO1211 device can be used with a V_SENSEvoltage up to 60 V and an ambient

temperature of up to 125°C for an R_SENSEvalue of 562 Ω, which corresponds to a typical current limit of 2.25 mA.

At higher levels of current limit, either the ambient temperature or the maximum value of the V_SENSEvoltage must

be derated. In any design, the voltage drop across the external series resistor, R_THR, reduces the maximum

voltage received by the SENSE pin and helps extend the allowable module input voltage and ambient

temperature range.

22

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

Typical Application (接下页)

130

125

120

115

110

105

100

95

90

85

R_SENSE= 562 W, I_L= 2.25 mA

R_SENSE= 400 W, I_L= 3.2 mA

R_SENSE= 200 W, I_L= 6.3 mA

80

75

70

0

10

20

30

40

50

60

70

80

Voltage at SENSE (V)

D011

(1) This figure also applies to the ISO1212 device if only one of the two channels are expected to be active at a given

time.

图 19. Maximum Ambient Temperature Derating Curve for ISO1211 vs V_SENSE

图 20 shows the maximum allowed ambient temperature for the ISO1212 device for different current limit and

input voltage conditions. The ISO1212 device can be used with a V_SENSEvoltage up to 36 V and an ambient

temperature of up to 125°C for an R_SENSEvalue of 562 Ω, which corresponds to a typical current limit of 2.25 mA.

At higher current limit levels, either the ambient temperature or the maximum value of the V_SENSEvoltage must

be derated. Operation of the ISO1212 device with an R_SENSEvalue of 200 Ω and with both channels active is not

recommended beyond a V_SENSEvoltage of 36 V. In any design, the voltage drop across the series resistor, R_THR

,

reduces the maximum voltage received by the SENSE pin and helps extend the allowable module input voltage

and ambient temperature range.

130

125

120

115

110

105

100

95

90

85

R_SENSE= 562 W, I_L= 2.25 mA

R_SENSE= 400 W, I_L= 3.2 mA

R_SENSE= 200 W, I_L= 6.3 mA

80

75

70

0

10

20

30

40

50

60

70

80

Voltage at SENSE (V)

D012

(1) This figure only applies if both channels of the ISO1212 device are expected to be on at the same time. If only one

channel is expected to be on at a given time, refer to 图 19.

图 20. Maximum Ambient Temperature Derating Curve for ISO1212 vs V_SENSE

9.2.1.2.3 Designing for 48-V Systems

The ISO121x devices are suitable for 48-V digital input receivers. The current limit, voltage transition thresholds,

and maximum voltage supported at the module input are governed by 公式 1, 公式 2, 公式 3, and 公式 4. For 48-

V systems, a threshold voltage close to 25 V is desirable. The R_THRresistor can be adjusted to achieve this

higher threshold. For example, with an R_SENSEvalue of 562 Ω and an R_THRvalue of 7.5 k Ω, a V_IHvalue of

approximately 25 V can be achieved. With this setting, the R_THRresistor drops a voltage of approximately 17 V,

reducing the maximum value of the V_SENSEvoltage for any given module input voltage. This drop vastly increases

the allowable module input voltage and ambient temperature range as discussed in Thermal Considerations.

23

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

Typical Application (接下页)

9.2.1.2.4 Designing for Input Voltages Greater Than 60 V

The ISO121x devices are rated for 60 V on the SENSE and IN pins with respect to FGND. However, larger

voltages on the module input can be supported by dropping extra voltage across an external resistor, R_THR

.

Because the current drawn by the SENSE and IN pins is well controlled by the built-in current limit, the voltage

drop across R_THRis well controlled as well. However, increasing the R_THRresistance also correspondingly raises

the voltage transition threshold. An additional resistor, R_SHUNT(see 图 21), provides the flexibility to change the

voltage transition thresholds independently of the maximum input voltage. The current through the R_SHUNT

resistor is less near the voltage transition threshold, but increases with the input voltage, increasing the voltage

drop across the R_THRresistor, and preventing the voltage on the ISO121x pins from exceeding 60 V. With the

correct value selected for the R_THRand R_SHUNTresistors, the voltage transition thresholds and the maximum input

voltage supported can be adjusted independently.

A 1-nF or greater C_INcapacitor is recommended between the SENSE and FGND pins to slow down the

transitions on the SENSE pin, and to prevent overshoot beyond 60 V during transitions.

For more information, refer to the How to Design Isolated Comparators for ±48V, 110V and 240V DC and AC

Detection TI TechNote. Use the ISO121x Threshold Calculator for 9V to 300V DC and AC Voltage Detection to

estimate the values of voltage transition thresholds, the maximum-allowed module input voltage, and module

input current for given values of the R_SENSE, R_THR, and R_SHUNTresistors.

ISO1211

R_THR

SENSE

VCC1

R_SENSE

+

V_IN

R_SHUNT

C_IN

OUT

IN

œ

FGND

GND1

图 21. Increase ISO121x Input Voltage Range With R_SHUNT

Another way to increase the maximum module input voltage without changing the voltage transition thresholds is

to use a 60-V Zener diode to limit the voltage on the ISO121x pins to less than 60 V as shown in 图 22. In this

case, when the module input is greater than 60 V, the Zener diode must be designed to sink the additional

current, and the R_THRresistor must be designed to drop a higher voltage.

For example, with a 2.5-kΩ R_THRand 560-Ω R_SENSE, the voltage transition threshold is 15 V, and the ISO121x

input current is 2.25 mA. If the module voltage reaches 100 V, the voltage drop across the R_THRresistor is 40 V,

and the current through the Zener diode is approximately 14 mA.

ISO1211

R_THR

SENSE

VCC1

R_SENSE

+

V_IN

C_IN

OUT

IN

60 V

œ

FGND

GND1

图 22. Increase ISO121x Input Voltage Range Using a Zener Diode

9.2.1.2.5 Surge, ESD, and EFT Tests

Digital input modules are subject to surge (IEC 61000-4-5), electrostatic discharge or ESD (IEC 61000-4-2) and

electrical fast transient or EFT (IEC 61000-4-4) tests. The surge impulse waveform has the highest energy and

the widest pulse width, and is therefore the most stringent test of the three.

图 16 shows the application diagram for Type 1 and 3 systems. For a 1-kV_PPsurge test between the input

terminals and protection earth (PE), a value of 1 kΩ for R_THRand 10 nF for C_INis recommended. 表 3 lists a

summary of recommended component values to meet different levels of EMC requirements for Type 1 and 3

systems.

24

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

Typical Application (接下页)

表 3. Surge, IEC ESD and EFT

SURGE

IEC 61131-2

R_SENSE

562

R_TH

2.5 kΩ

1 kΩ

C_IN

IEC ESD

IEC EFT

TYPE

LINE-TO-PE

±1 kV

LINE-TO-LINE

±1 kV

LINE-TO-FGND

±1 kV

Type 1

10 nF

±6 kV

±4 kV

±1 kV

±500 V

Type 3

562

330 nF

±1 kV

图 23 shows the test setup and application circuit used for surge testing. A noise filtering capacitor of 500 pF is

recommended between the FGND pin and PE (earth). The total value of effective capacitance between the

FGND pin and any other ground potential (including PE) must not exceed 500 pF for optimum surge

performance. For line-to-PE test (common-mode test), the FGND pin is connected to the auxiliary equipment

(AE) through a decoupling network.

5 V or 3.3 V or 2.5 V

Backplane supply

ISO1212

R_THR

20 mH

IN1

IN2

V_CC

SENSE1

V_CC1

C_IN

R_SENSE

OUT1

IN1

FGND1

R_THR

20 mH

SENSE2

C_IN

R_SENSE

OUT2

GND1

IN2

FGND2

Host

Controller

Decoupling

Network

Auxiliary

Equipment

(AE)

ISO1212

R_THR

20 mH

INN-1

SENSE1

V_CC1

C_IN

R_SENSE

IN1

OUT1

FGND1

R_THR

INN

SENSE2

C_IN

R_SENSE

OUT2

GND1

IN2

FGND2

GND

Field Ground

(FGND)

FGND⁽¹⁾

PE

500 pF⁽²⁾

2 kV

PE

Protection

Earth (PE)

(1) For line-to-PE test, FGND is connected to the auxiliary equipment (AE) through a decoupling network.

(2) A noise filtering capacitor of about 500 pF is recommended between the FGND pin and PE (earth). The total value of

effective capacitance between the FGND pin and any other ground potential (including PE) must not exceed 500 pF

for optimum performance.

图 23. Setup and Application Circuit Used for Surge Test

25

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

For higher voltage levels of surge tests or for faster systems that cannot use a large value for C_IN, TVS diodes or

varistors can be used to meet EMC requirements. Type 2 systems that use a smaller value for R_THRmay also

require TVS diodes or varistors for surge protection. 图 24 shows an example usage of TVS diodes for surge

protection. The recommended components for surge protection are VCAN26A2-03S (TVS, Vishay), EZJ-

P0V420WM (Varistor, Panasonic), and GSOT36C (TVS, Vishay).

Use of the R_THRresistor also reduces the peak current requirement for the TVS diodes, making them smaller and

cost effective. For example, a 2-kV surge through a 1-kΩ R_THRresistor creates only 2-A peak current. Also,

because of voltage drop across the R_THRresistor in normal operation, the working voltage requirement for the

varistor or TVS diodes is reduced. For example, for a R_THRvalue of 1 kΩ and an R_SENSEvalue of 562 Ω, a

module designed for 30-V inputs only requires 28-V TVS diodes because the R_THRresistor drops more than 2 V.

5 V or 3.3 V or 2.5 V

Backplane Supply

ISO1211

R_THR

V_CC1

OUT

V_CC

SENSE

IN

24 V

0 V

R_SENSE

Host

Controller

TVS

FGND

GND

GND1

图 24. TVS Diodes Used Instead of a Filtering Capacitor for Surge Protection in Faster Systems

9.2.1.2.6 Multiplexing the Interface to the Host Controller

The ISO121x devices provide an output-enable pin on the controller side (EN). Setting the EN pin to 0 causes

the output buffers to be in the high-impedance state. This feature can be used to multiplex the outputs of multiple

ISO121x devices on the same host-controller input, reducing the number of pins on the host controller.

In the example shown in 图 25, two sets of 8-channel inputs are multiplexed, reducing the number of input pins

required on the controller from 16 to 10. Similarly, if four sets of 8-channel inputs are multiplexed, the number of

pins on the controller is reduced from 32 to 12.

26

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

ISO1212

SENSE1

ISO1212

R_THR

IN1

IN2

IN9

SENSE1

R_SENSE

OUT1

IN1

SENSE2

IN2

R_THR

IN10

SENSE2

R_SENSE

IN2

OUT2

EN

OUT2

EN

ISO1212

R_THR

IN7

IN8

IN15

IN16

SENSE1

R_SENSE

OUT1

IN1

OUT1

IN1

R_THR

SENSE2

IN2

R_SENSE

OUT2

EN

IN2

OUT2

EN

Host

Controller

图 25. Using the Output Enable Option to Multiplex the Interface to the Host Controller

9.2.1.2.7 Status LEDs

The outputs of the ISO121x devices can be used to drive status LEDs on the controller side as shown in 图 26.

The output buffers of the ISO121x can provide 4-mA, 3-mA, and 2-mA currents while working at V_CC1values of 5

V, 3.3 V, and 2.5 V respectively.

In some cases, placing the LED on the field side is desirable although it is powered from V_CC1. In such cases, the

signal carrying current to the LED can be routed in an inner layer without compromising the isolation of the

digital-input module. For more information, see the Layout Guidelines section.

5 V or 3.3 V or 2.5 V

Backplane Supply

ISO1211

R_THR

V_CC

V_CC1

OUT

24 V

0 V

SENSE

IN

R_SENSE

C_IN

Host

Controller

Power

Supply

FGND

GND

GND1

Status

LED

图 26. Using ISO121x Outputs to Drive Status LEDs

27

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

9.2.1.3 Application Curve

2.75

2.5

2.25

2

1.75

1.5

1.25

1

œ40°C

25°C

85°C

105°C

115°C

125°C

0.75

0.5

0.25

0

5

10

15

20

25

30

Input Voltage (V)

R_SENSE= 562 Ω

R_THR= 0 Ω

图 27. Input Current vs Input Voltage

28

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

9.2.2 Sourcing Inputs

The ISO121x devices can be configured as sourcing inputs as shown in 图 28. In this configuration, all the

SENSE pins are connected to the common voltage (24 V), and the inputs are connected to the individual FGND

pins.

24-V

Common

5 V or 3.3 V or 2.5 V

Backplane supply

ISO1212

V_CC

SENSE1

V_CC1

C_IN

R_SENSE

OUT1

IN1

R_THR

FGND1

Current Flow

SENSE2

C_IN

R_SENSE

OUT2

GND1

24 V

0 V

IN2

R_THR

Power

Supply

FGND2

Host

Controller

ISO1212

SENSE1

V_CC1

Sensors and

Switches

C_IN

R_SENSE

IN1

OUT1

R_THR

FGND1

Current Flow

SENSE2

C_IN

R_SENSE

OUT2

GND1

IN2

R_THR

FGND2

GND

500 pF/2 kV

PE

Protection

Earth (PE)

图 28. Typical Application Circuit With Sourcing Inputs

29

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

9.2.3 Sourcing and Sinking Inputs (Bidirectional Inputs)

The ISO1212 device can be used to create a bidirectional input module that can sink and source current as

shown in 图 29. In this configuration, channel 1 is active if the COM terminal is connected to ground for sinking

inputs, and channel 2 is active if the COM terminal is connected to 24 V for sourcing input. The digital input is

considered high if either the OUT1 or OUT2 pin is high.

5 V or 3.3 V or 2.5 V

Backplane supply

ISO1212

IN

R_THR

V_CC

SENSE1

V_CC1

C_IN

R_SENSE

OUT1

IN1

FGND1

Host

Controller

SENSE2

±24 V

R_SENSE

OUT2

GND1

IN2

GND

FGND2

COM

Current for positive polarity

Current for negative polarity

图 29. Application Circuit—ISO1212 With Sourcing and Sinking Inputs

A bidirectional input module can also be built with the ISO121x devices using low-cost Schottky diodes as shown

in 图 30.

IN

R_THR

BAT54CLT1G

ISO1211

±24 V

SENSE

IN

VCC1

OUT

Host

Controller

R_SENSE

COM

C_IN

FGND

GND1

图 30. Bidirectional Implementation With ISO1211 and Bridge Rectifier

10 Power Supply Recommendations

To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended

on the side 1 supply pin (V_CC1). The capacitor should be placed as close to the supply pins as possible.

30

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

11 Layout

11.1 Layout Guidelines

The board layout for ISO1211 and ISO1212 can be completed in two layers. On the field side, place R_SENSE, C_IN,

and R_THRon the top layer. Use the bottom layer as the field ground (FGND) plane. TI recommends using R_SENSE

and C_INin 0603 footprint for a compact layout, although larger sizes (0805) can also be used. The C_INcapacitor

is a 50-V capacitor and is available in the 0603 footprint. Keep C_INas close to the ISO121x device as possible.

The SUB pin on the ISO1211 device and the SUB1 and SUB2 pins on the ISO1212 device should be left

unconnected. For group isolated design, use vias to connect the FGND pins of the ISO121x device to the bottom

FGND plane. The placement of the R_THRresistor is flexible, although the resistor pin connected to external high

voltage should not be placed within 4 mm of the ISO121x device pins or the C_INand R_SENSEpins to avoid

flashover during EMC tests.

Only a decoupling capacitor is required on side 1. Place this capacitor on the top-layer, with the bottom layer for

GND1.

If a board with more than two layers is used, placing two ISO121x devices on the top-and bottom layers (back-to-

back) is possible to achieve a more compact board. The inner layers can be used for FGND.

图 31 and 图 32 show the example layouts.

In some designs, placing the LED on the field side is desirable although it is powered from V_CC1. In such cases,

the signal carrying current to the LED can be routed in an inner layer without compromising the isolation of the

digital-input module as shown in 图 33. The LED must be placed with at least 4-mm spacing between other

components and connections on side 1 to ensure adequate isolation.

11.2 Layout Example

2 mm maximum

from V_CC

V_CC

R_THR

0.1 ꢀF

C

R

V_CC1

SENSE

C

R

High Voltage Input

EN

IN

FGND

SUB

MCU

OUT

GND1

Plane

FGND

Plane

图 31. Layout Example With ISO1211

31

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

Layout Example (接下页)

2 mm Maximum

from V_CC

V_CC

INP1

R

R_THR

R

C

0.1 ꢀF

C

SENSE1

IN1

GND1

V_CC1

EN

FGND

INP2

FGND

SUB1

High Voltage

Input

OUT1

OUT2

MCU

R_THR

R

SUB2

SENSE1

IN1

NC

R

C

FGND

GND1

Plane

FGND

Plane

图 32. Layout Example With ISO1212

2 mm maximum

from V_CC

V_CC

R_THR

R

0.1 ꢀF

C

V_CC1

SENSE

C

R

High Voltage Input

EN

IN

FGND

SUB

MCU

OUT

GND1

FGND

Plane

4 mm minimum

LED

R

GND1

Plane

图 33. Layout Example With LED Placed on the Field Side But Driven From V_CC1Power Domain

32

ISO1211, ISO1212

www.ti.com.cn

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

有关开发支持，请参阅：

•

低于 1W 的 16 通道隔离数字输入模块参考设计

采用光学开关的断线检测参考设计

用于在变速驱动器中实现安全转矩关闭的冗余双通道参考设计

12.2 文档支持

12.2.1 相关文档

如需相关文档，请参阅：

•

德州仪器 (TI)，《如何提高电机驱动中的隔离式数字输入的速度和可靠性》TI 技术手册

德州仪器 (TI)，《如何设计用于 ±48V、110V 和 240V 直流和交流检测的隔离式比较器》TI 技术手册

德州仪器 (TI)，《如何简化隔离式 24V PLC 数字输入模块设计》TI 技术手册

德州仪器 (TI)，《隔离相关术语》

德州仪器 (TI)，《用于 9V 至 300V 直流和交流电压检测的 ISO121x 阈值计算器》

德州仪器 (TI)，《ISO1211 隔离式数字输入接收器评估模块》用户手册

德州仪器 (TI)，《ISO1212 隔离式数字输入接收器评估模块》用户手册

12.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 4. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

ISO1211

ISO1212

12.4 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.5 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.6 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

33

ISO1211, ISO1212

ZHCSGU8E –JUNE 2017–REVISED AUGUST 2018

www.ti.com.cn

12.8 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

34

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ISO1211DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

ISO1212DBQR

SSOP

DBQ

16

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ISO1211DR

SOIC

D

8

2500

350.0

43.0

ISO1212DBQR

SSOP

DBQ

16

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ISO1211D

D

SOIC

8

75

505.46

6.76

3810

4

ISO1212DBQ

DBQ

SSOP

16

Pack Materials-Page 3

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBQ0016A

SSOP - 1.75 mm max height

SCALE 2.800

SHRINK SMALL-OUTLINE PACKAGE

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

14X .0250

[0.635]

16

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.175

[4.45]

8

9

16X .008-.012

[0.21-0.30]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.007 [0.17]

C A

B

.005-.010 TYP

[0.13-0.25]

SEE DETAIL A

.010

[0.25]

GAGE PLANE

.004-.010

[0.11-0.25]

0 - 8

.016-.035

[0.41-0.88]

DETAIL A

TYPICAL

(.041 )

[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 inch, per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MO-137, variation AB.

www.ti.com

EXAMPLE BOARD LAYOUT

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SEE

DETAILS

SYMM

1

16

16X (.016 )

[0.41]

14X (.0250 )

[0.635]

8

9

(.213)

[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

.002 MAX

[0.05]

ALL AROUND

.002 MIN

[0.05]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SYMM

1

16

16X (.016 )

[0.41]

SYMM

14X (.0250 )

[0.635]

9

8

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ISO1211DR
厂家：	TEXAS INSTRUMENTS
描述：	用于数字输入模块的单通道隔离式 24V 至 60V 数字输入接收器 \| D \| 8 \| -40 to 125
文件：	总46页 (文件大小：1963K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO1211DR [TI]

相关型号：

ISO1212

ISO1212DBQ

ISO1212DBQR

ISO121BG

ISO121BG

ISO121BG

ISO121BG-BI

ISO121G

ISO121G

ISO121G

ISO121G-BI

ISO122