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ISO5451

SLLSEO1B –JUNE 2015–REVISED DECEMBER 2015

ISO5451 High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver

with Active Safety Features

1 Features

3 Description

The ISO5451 is a 5.7-kV_RMS, reinforced isolated gate

1

•

50-kV/μs Minimum and 100-kV/μs Typical

Common-Mode Transient Immunity (CMTI)

at V_CM= 1500 V

driver for IGBTs and MOSFETs with 2.5-A source

and 5-A sink current. The input side operates from a

single 3-V to 5.5-V supply. The output side allows for

a supply range from minimum 15-V to maximum

30-V. Two complementary CMOS inputs control the

output state of the gate driver. The short propagation

time of 76 ns assures accurate control of the output

stage.

•

2.5-A Peak Source and 5-A Peak Sink Currents

Short Propagation Delay: 76 ns (Typ),

110 ns (Max)

•

2-A Active Miller Clamp

Output Short-Circuit Clamp

An internal desaturation (DESAT) fault detection

recognizes when the IGBT is in an overload

condition. Upon a DESAT detect the gate driver

output is driven low to V_EE2potential turning the IGBT

immediately off.

Fault Alarm upon Desaturation Detection is

Signaled on FLT and Reset Through RST

•

Input and Output Under Voltage Lock-Out (UVLO)

with Ready (RDY) Pin Indication

Active Output Pull-down and Default Low Outputs

with Low Supply or Floating Inputs

When desaturation is active, a fault signal is sent

across the isolation barrier pulling the FLT output at

the input side low and blocking the isolator input. The

FLT output condition is latched and can be reset

through a low-active pulse at the RST input.

•

3-V to 5.5-V Input Supply Voltage

15-V to 30-V Output Driver Supply Voltage

CMOS Compatible Inputs

When the IGBT is turned off during normal operation

with bipolar output supply, the output is hard clamp to

V_EE2. If the output supply is unipolar, an active Miller

clamp can be used, allowing Miller current to sink

across a low impedance path preventing IGBT to be

dynamically turned on during high voltage transient

conditions.

Rejects Input Pulses and Noise Transients

Shorter Than 20 ns

•

Operating Temperature: –40°C to 125°C Ambient

Isolation Surge Withstand Voltage 10000-V_PK

Safety and Regulatory Certifications:

–

8000-V_PKV_IOTMand 1420-V_PKV_IORM

Reinforced Isolation per DIN V VDE V 0884-10

(VDE V 0884-10):2006-12

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

–

5700-V_RMSIsolation for 1 Minute per UL 1577

ISO5451

SOIC (16)

10.30 mm × 7.50 mm

CSA Component Acceptance Notice 5A, IEC

60950-1, IEC 60601-1 and IEC 61010-1 End

Equipment Standards

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Functional Block Diagram

–

CQC Certification per GB4943.1-2011

All Certifications are Planned

2 Applications

•

Isolated IGBT and MOSFET Drives in

–

Industrial Motor Control Drives

Industrial Power Supplies

Solar Inverters

L{h5451

OUT

HEV and EV Power Modules

Induction Heating

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ISO5451

SLLSEO1B –JUNE 2015–REVISED DECEMBER 2015

www.ti.com

Table of Contents

9.2 Functional Block Diagram ....................................... 15

9.3 Feature Description................................................. 16

9.4 Device Functional Modes........................................ 20

10 Application and Implementation........................ 21

10.1 Application Information.......................................... 21

10.2 Typical Applications .............................................. 21

11 Power Supply Recommendations ..................... 29

12 Layout................................................................... 29

12.1 Layout Guidelines ................................................. 29

12.2 PCB Material......................................................... 29

12.3 Layout Example .................................................... 29

13 Device and Documentation Support ................. 30

13.1 Documentation Support ........................................ 30

13.2 Community Resources.......................................... 30

13.3 Trademarks........................................................... 30

13.4 Electrostatic Discharge Caution............................ 30

13.5 Glossary................................................................ 30

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 3

Pin Configuration and Function........................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 5

7.5 Power Rating............................................................. 5

7.6 Electrical Characteristics........................................... 5

7.7 Switching Characteristics.......................................... 6

7.8 Typical Characteristics.............................................. 7

Parameter Measurement Information ................ 13

Detailed Description ............................................ 15

9.1 Overview ................................................................. 15

8

9

14 Mechanical, Packaging, and Orderable

Information ........................................................... 30

4 Revision History

Changes from Revision A (June 2015) to Revision B

Page

•

Changed Features, Safety and Regulatory Approvals From: 6000 V_PKTo: 8000 V_PK.......................................................... 1

Changed Features, Safety and Regulatory Approvals From: 4250 V_RMSTo: 5700 V_RMS..................................................... 1

Added the Power Rating table ............................................................................................................................................... 5

Added Note 1 to I_IHin the Electrical Characteristics table ..................................................................................................... 5

Added Note 2 to I_ILin the Electrical Characteristics table ..................................................................................................... 5

Added Figure 13 to Figure 34................................................................................................................................................. 8

Changed the Regulatory Information table........................................................................................................................... 18

Changed Figure 39 and Added Figure 40 ........................................................................................................................... 19

Changed Figure 51 and Figure 52 ...................................................................................................................................... 28

Changes from Original (June 2015) to Revision A

Page

•

Changed from a 1-page Product Preview to the full datasheet. ........................................................................................... 1

Changed Features, Safety and Regulatory Approvals From: 8000 V_PKV_IOTMand 2121 V_PKTo: 6000 V_PKV_IOTMand

1420 V_PK................................................................................................................................................................................ 1

•

Changed Features, Safety and Regulatory Approvals From: 5.7 kV_RMSTo: 4250 V_RMS....................................................... 1

Changed the Applications list ................................................................................................................................................ 1

2

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SLLSEO1B –JUNE 2015–REVISED DECEMBER 2015

5 Description (continued)

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits

monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low,

otherwise this output is high.

The ISO5451 is available in a 16-pin SOIC package. Device operation is specified over a temperature range from

–40°C to 125°C ambient.

6 Pin Configuration and Function

DW Package

16-Pin SOIC

Top View

V_EE2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND1

V_CC1

DESAT

GND2

NC

RST

FLT

RDY

IN-

V_CC2

OUT

CLAMP

V_EE2

IN+

GND1

Pin Functions

I/O

DESCRIPTION

NAME

V_EE2

DESAT

GND2

NC

NO.

1, 8

2

-

I

Output negative supply. Connect to GND2 for Unipolar supply application.

Desaturation voltage input

3

-

Gate drive common. Connect to IGBT emitter.

Not connected

4

-

V_CC2

OUT

CLAMP

GND1

IN+

5

-

Most positive output supply potential.

Gate drive voltage output

6

O

-

7

Miller clamp output

9, 16

10

11

12

13

14

15

Input ground

I

Non-inverting gate drive voltage control input

Inverting gate drive voltage control input

Power-good output, active high when both supplies are good.

Fault output, low-active during DESAT condition

Reset input, apply a low pulse to reset fault latch.

Positive input supply (3 V to 5.5 V)

IN-

I

RDY

FLT

O

I

RST

V_CC1

-

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SLLSEO1B –JUNE 2015–REVISED DECEMBER 2015

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7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

GND1 - 0.3

–0.3

MAX

UNIT

V

V_CC1

Supply voltage input side

6

35

V_CC2

Positive supply voltage output side

Negative supply voltage output side

Total supply output voltage

(V_CC2– GND2)

(V_EE2– GND2)

V

V_EE2

–17.5

0.3

V

V_(SUP2)

V_OUT

I_(OUTH)

(V_CC2- V_EE2

)

–0.3

35

V

Gate driver output voltage

V_EE2- 0.3

V_CC2+ 0.3

2.7

V

Gate driver high output current

(max pulse width = 10 μs, max duty

cycle = 0.2%)

A

I_(OUTL)

Gate driver low output current

5.5

A

V_(LIP)

I_(LOP)

Voltage at IN+, IN-, FLT, RDY, RST

Output current of FLT, RDY

GND1 - 0.3

V_CC1+ 0.3

10

V

mA

V

V_(DESAT)Voltage at DESAT

V_(CLAMP)Clamp voltage

GND2 - 0.3

V_EE2- 0.3

–40

V_CC2+ 0.3

150

V

T_J

Junction temperature

Storage temperature

°C

T_STG

-65

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V

V_CC1

V_CC2

V_EE2

V_(SUP2)

V_IH

Supply voltage input side

3

5.5

Positive supply voltage output side (V_CC2– GND2)

Negative supply voltage output side (V_EE2– GND2)

15

30

V

–15

0

30

V

Total supply voltage output side (V_CC2– V_EE2

High-level input voltage (IN+, IN-, RST)

Low-level input voltage (IN+, IN-, RST)

)

15

V

0.7 x V_CC1

V_CC1

V

V_IL

0

40

0.3 x V_CC1

V

t_UI

Pulse width at IN+, IN- for full output (C_LOAD= 1nF)

Pulse width at RST for resetting fault latch

Ambient temperature

ns

°C

t_RST

T_A

800

-40

25

125

4

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SLLSEO1B –JUNE 2015–REVISED DECEMBER 2015

7.4 Thermal Information

DW (SOIC)

UNIT

THERMAL METRIC⁽¹⁾

16 PINS

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

99.6

48.5

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

56.5

29.2

56.5

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Power Rating

VALUE

1255

175

UNIT

P_D

Maximum power dissipation⁽¹⁾

Maximum input power dissipation

Maximum output power dissipation

P_ID

P_OD

mW

1080

(1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of

251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,

while ensuring that Junction temperature does not exceed 150°C.

7.6 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V,

V_CC2– GND2 = 15 V, GND2 – V_EE2= 8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE SUPPLY

Positive-going UVLO1 threshold voltage

input side (V_CC1– GND1)

V_IT+(UVLO1)

V_IT-(UVLO1)

V_HYS(UVLO1)

V_IT+(UVLO2)

V_IT-(UVLO2)

V_HYS(UVLO2)

2.25

V

Negative-going UVLO1 threshold voltage

input side (V_CC1– GND1)

1.7

UVLO1 Hysteresis voltage (V_IT+– V_IT–

input side

)

0.24

12

11

1

Positive-going UVLO2 threshold voltage

output side (V_CC2– GND2)

13

Negative-going UVLO2 threshold voltage

output side (V_CC2– GND2)

9.5

UVLO2 Hysteresis voltage (V_IT+– V_IT–

output side

)

I_Q1

Input supply quiescent current

Output supply quiescent current

2.8

3.6

4.5

6

mA

I_Q2

LOGIC I/O

Positive-going input threshold voltage (IN+,

IN-, RST)

V_IT+(IN,RST)

V_IT-(IN,RST)

0.7 x V_CC1

V

Negative-going input threshold voltage

(IN+, IN-, RST)

0.3 x V_CC1

V_HYS(IN,RST)

Input hysteresis voltage (IN+, IN-, RST)

0.15 x V_CC1

100

V

(1)

I_IH

High-level input leakage at (IN+)

IN+ = V_CC1

µA

V

(2)

I_IL

Low-level input leakage at (IN-, RST)

IN- = GND1, RST = GND1

V_(RDY)= GND1, V_(FLT)= GND1

I_(FLT)= 5 mA

-100

I_PU

V_OL

Pull-up current of FLT, RDY

100

Low-level output voltage at FLT, RDY

0.2

2

GATE DRIVER STAGE

V_(OUTPD)

V_(OUTH)

V_(OUTL)

Active output pull-down voltage

I_OUT= 200 mA, V_CC2= open

I_OUT= –20 mA

V

High-level output voltage

Low-level output voltage

V_CC2- 0.5

V_CC2- 0.24

V_EE2+ 13

I_OUT= 20 mA

V_EE2+ 50

mV

IN+ = high, IN- = low,

V_OUT= V_CC2- 15 V

I_(OUTH)

High-level output peak current

1.5

2.5

A

(1) I_IHfor IN-, RST pin is zero as they are pulled high internally.

(2) I_ILfor IN+ is zero, as it is pulled low internally.

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Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V,

V_CC2– GND2 = 15 V, GND2 – V_EE2= 8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IN+ = low, IN- = high,

V_OUT= V_EE2+ 15 V

I_(OUTL)

Low-level output peak current

3.4

5

A

ACTIVE MILLER CLAMP

V_(CLP)Low-level clamp voltage

I_(CLP)

I_(CLP)= 20 mA

V_EE2+ 0.015

V_EE2+ 0.08

2.5

V

A

V

Low-level clamp current

Clamp threshold voltage

V_(CLAMP)= V_EE2+ 2.5 V

1.6

2.5

2.1

V_(CLTH)

SHORT CIRCUIT CLAMPING

Clamping voltage

V_{(CLP_OUT)}

IN+ = high, IN- = low, t_CLP=10 µs,

I_(OUTH)= 500 mA

0.8

1.3

V

(V_OUT- V_CC2

)

Clamping voltage

(V_CLP- V_CC2

IN+ = high, IN- = low, t_CLP=10 µs,

I_(CLP)= 500 mA

V_{(CLP_CLAMP)}

1.3

0.7

V

)

V_{(CLP_CLAMP)}

Clamping voltage at CLAMP

IN+ = High, IN- = Low, I_(CLP)= 20 mA

1.1

DESAT PROTECTION

I_(CHG)

Blanking capacitor charge current

V_(DESAT)- GND2 = 2 V

V_(DESAT)- GND2 = 6 V

0.42

9

0.5

14

0.58

mA

I_(DCHG)

Blanking capacitor discharge current

DESAT threshold voltage with respect to

GND2

V_(DSTH)

V_(DSL)

8.3

0.4

9

9.5

1

V

DESAT voltage with respect to GND2,

when OUT is driven low

7.7 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V,

V_CC2– GND2 = 15 V, GND2 – V_EE2= 8 V

PARAMETER

Output signal rise time

Output signal fall time

Propagation Delay

TEST CONDITIONS

MIN

12

TYP

20

MAX UNIT

t_r

35

37

ns

t_f

12

20

t_PLH, t_PHL

t_sk-p

76

110

C_LOAD= 1 nF, see Figure 35,

Figure 36 and Figure 37

Pulse Skew |t_PHL– t_PLH

|

20

t_sk-pp

Part-to-part skew

30⁽¹⁾

40

t_GF

Glitch filter on IN+, IN-, RST

DESAT sense to 10% OUT delay

DESAT glitch filter delay

20

30

415

t_{DESAT (10%)}

t_{DESAT (GF)}

t_{DESAT (FLT)}

t_LEB

300

500

330

DESAT sense to FLT-low delay

Leading edge blanking time

Glitch filter on RST for resetting FLT

see Figure 37

2000

400

2420

500

see Figure 35 and Figure 36

330

300

t_GF(RSTFLT)

800

V_I= V_CC1/2 + 0.4 x sin (2πft),

f = 1 MHz, V_CC1= 5 V

C_I

Input capacitance⁽²⁾

2

pF

CMTI

Common-mode transient immunity

V_CM= 1500 V, see Figure 38

50

100

kV/μs

(1) Measured at same supply voltage and temperature condition

(2) Measured from input pin to ground.

6

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7.8 Typical Characteristics

0.5

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

V_CC2- V_OUT= 2.5 V

V_CC2- V_OUT= 5 V

V_CC2- V_OUT= 10 V

V_CC2- V_OUT= 15 V

V_CC2- V_OUT= 20 V

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

V_OUT- V_EE2= 2.5 V

V_OUT- V_EE2= 5 V

V_OUT- V_EE2= 10 V

V_OUT- V_EE2= 15 V

V_OUT- V_EE2= 20 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D001

D002

V_CC2= 30 V

Figure 1. Output High Drive Current vs Temperature

Figure 2. Output Low Drive Current vs Temperature

7

6

5

4

3

2

1

0

0.0

T_A= -40èC

T_A= 25èC

T_A= 125èC

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

T_A= -40èC

T_A= 25èC

T_A= 125èC

0

5

10

15

20

25

30

0

5

10

15

20

25

30

(V_CC2- V_OUT) Voltage (V)

(V_OUT- V_EE2) Voltage (V)

D003

D004

Figure 3. Output High Drive Current vs Output Voltage

Figure 4. Output Low Drive Current vs Output Voltage

9.5

9.4

9.3

9.2

9.1

9

15 V Unipolar

30 V Unipolar

8.9

8.8

8.7

8.6

8.5

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D005

Unipolar: V_CC2- V_EE2= V_CC2- GND2

Figure 5. DESAT Threshold Voltage vs Temperature

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Typical Characteristics (continued)

CH1: OUT

CH2: DESAT

CH3: /FLT

Time - 50 ns/div

C_L= 1 nF

R_G= 10 Ω

C_L= 1 nF

R_G= 0 Ω

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Figure 7. Output Transient Waveform

Figure 6. Output Transient Waveform

Time - 500 ns/div

C_L= 10 nF

R_G= 0 Ω

C_L= 10 nF

R_G= 10 Ω

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Figure 8. Output Transient Waveform

Figure 9. Output Transient Waveform

Time - 2 ms/div

Time - 1 ms/div

C_L= 100 nF

R_G= 10 Ω

C_L= 100 nF

R_G= 0 Ω

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Figure 11. Output Transient Waveform

Figure 10. Output Transient Waveform

8

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Typical Characteristics (continued)

3.5

3

CH1: OUT

2.5

2

CH2: DESAT

CH3: FLT

1.5

1

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

V_CC1= 5.5 V

0.5

0

Time - 1 ms/div

C_L= 100 nF

R_G= 10 Ω

-40

-20

0

20

40

60

80

100 120 140

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Ambient Temperature (èC)

D006

IN+ = High

IN- = Low

Figure 12. Output Transient Waveform DESAT and FLT

Figure 13. I_CC1Supply Current vs Temperature

2

5

4.5

4

1.8

1.6

1.4

1.2

1

3.5

3

2.5

2

0.8

0.6

0.4

0.2

0

1.5

1

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

V_CC1= 5.5 V

V_CC2= 15 V

V_CC2= 20 V

V_CC2= 30 V

0.5

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D007

D008

IN+ = Low

IN- = Low

Input Frequency = 1 kHz

Figure 14. I_CC1Supply Current vs Temperature

Figure 15. I_CC2Supply Current vs Temperature

3

2.5

2

5

4.5

4

V_CC1= 3 V

V_CC1= 5.5 V

3.5

3

1.5

1

2.5

2

1.5

1

V_CC2= 15 V

V_CC2= 20 V

V_CC2= 30 V

0.5

0

0.5

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Input Frequency (kHz)

D009

D010

No C_L

Figure 16. I_CC1Supply Current vs. Input Frequency

Figure 17. I_CC2Supply Current vs Input Frequency

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Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

10

0

70

V_CC2= 15 V

V_CC2= 30 V

60

50

40

30

20

10

0

tpLH at V_CC2= 15 V

tpHL at V_CC2= 15 V

tpLH at V_CC2= 30 V

tpHL at V_CC2= 30 V

0

10

20

30

40

50

60

70

80

90 100

-40

-20

0

20

40

60

80

100 120 140

Load Capacitance (nF)

Ambient Temperature (èC)

D025

D012

R_G= 10 Ω, 20kHz

C_L= 1nF

R_G= 0 Ω

V_CC1= 5 V

Figure 18. I_CC2Supply Current vs Load Capacitance

Figure 19. V_CC1Propagation Delay vs Temperature

100

90

80

70

60

50

40

30

20

10

0

1200

1000

800

600

400

200

0

tpLH at V_CC2= 15 V

tpLH at V_CC2= 30 V

tpHL at V_CC2= 15 V

tpHL at V_CC2= 30 V

tpLH at V_CC1= 3.3 V

tpHL at V_CC1= 3.3 V

tpLH at V_CC1= 5 V

tpHL at V_CC1= 5 V

-40

-20

0

20

40

60

80

100 120 140

0

10

20

30

40

50

60

70

80

90 100

Ambient Temperature (èC)

Load Capacitance (nF)

D013

D024

C_L= 1nF

R_G= 0 Ω

V_CC2= 15 V

R_G= 10 Ω

V_CC1= 5 V

Figure 20. V_CC2Propagation Delay vs Temperature

Figure 21. Propagation Delay vs Load Capacitance

800

700

600

500

400

300

200

100

0

500

450

400

350

300

250

200

150

100

50

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load Capacitance (nF)

D022

D026

R_G= 0 Ω

V_CC1= 5 V

R_G= 0 Ω

V_CC1= 5 V

Figure 22. t_rRise Time vs Load Capacitance

Figure 23. t_fFall Time v. Load Capacitance

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Typical Characteristics (continued)

4000

3500

3000

2500

2000

1500

1000

500

2500

2000

1500

1000

500

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load Capacitance (nF)

D023

D027

R_G= 10 Ω

V_CC1= 5 V

R_G= 10 Ω

V_CC1= 5 V

Figure 24. t_rRise Time vs Load Capacitance

Figure 25. t_fFall Time vs Load Capacitance

500

480

460

440

420

400

380

360

340

320

300

450

445

440

435

430

425

420

415

410

405

400

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D015

D014

C_L= 10 nF

Figure 27. DESAT Sense to V_OUT10% Delay vs Temperature

Figure 26. Leading Edge Blanking Time With Temperature

120

2.1

V_CC2= 15 V

V_CC2= 30 V

100

80

2.05

2

1.95

1.9

60

40

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

1.85

20

V_CC1= 5.5 V

1.8

-40

0

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D016

D017

C_L= 1 nF

Figure 28. DESAT Sense to FLT Low Delay vs Temperature

Figure 29. Reset to Fault Delay Across Temperature

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Typical Characteristics (continued)

5

2

1.8

1.6

1.4

1.2

1

V_(CLAMP)= 2 V

V_(CLAMP)= 4 V

V_(CLAMP)= 6 V

4.5

4

3.5

3

2.5

2

0.8

0.6

0.4

0.2

0

1.5

1

I_OUT= 100 mA

I_OUT= 200 mA

0.5

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D018

D019

Figure 30. Miller Clamp Current vs Temperature

Figure 31. Active Pull Down Voltage vs Temperature

1400

1200

1000

800

600

400

200

0

1200

1000

800

600

400

200

0

20 mA at V_CC2= 15 V

20 mA at V_CC2= 30 V

250 mA at V_CC2= 15 V

250 mA at V_CC2= 30 V

500 mA at V_CC2= 15 V

500 mA at V_CC2= 30 V

20 mA at V_CC2= 15 V

20 mA at V_CC2= 30 V

250 mA at V_CC2= 15 V

250 mA at V_CC2= 30 V

500 mA at V_CC2= 15 V

500 mA at V_CC2= 30 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D021

D020

Figure 32. Short Circuit Clamp Voltage on Clamp Across

Temperature

Figure 33. Short Circuit Clamp Voltage on OUT Across

Temperature

-400

-420

-440

-460

-480

-500

-520

-540

-560

-580

-600

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D011

V_CC2= 15 V

DESAT = 6 V

Figure 34. Blanking Capacitor Charging Current vs Temperature

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8 Parameter Measurement Information

IN-

0V

V

CC1

50 %

IN+

0V

t

f

r

90%

50%

10%

OUT

t_PLH

t

PHL

DESAT

t

LEB

Figure 35. OUT Propagation Delay, Non-Inverting Configuration

V

IN-

CC1

0V

50 %

V

IN+

CC1

t

f

r

90%

50%

10%

OUT

t

PLH

PHL

DESAT

t

LEB

Figure 36. OUT Propagation Delay, Inverting Configuration

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Parameter Measurement Information (continued)

t_{DESAT (10%)}

t_{DESAT (FLT)}

9V

t_RST

V_DESAT

OUT

10%

FLT

50 %

RST

Figure 37. DESAT, OUT, FLT, RST Delay

ISO5451

15

5

3

V_CC2

V_CC1

15V

0.1ꢀF

1ꢀF

3 V...5.5 V

9, 16

14

GND1

GND2

V_EE2

1, 8

6

RST

IN+

+

10

OUT

+

S1

Pass-Fail Criterion:

-

11

13

OUT must remain stable

C_L

1nF

IN-

2

FLT

DESAT

-

12

7

4

CLAMP

NC

RDY

-

+

V_CM

Figure 38. Common-Mode Transient Immunity Test Circuit

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9 Detailed Description

9.1 Overview

The ISO5451 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage are

separated by a capacitive, silicon dioxide (SiO₂), isolation barrier.

The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET

(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to

supply 2.5-A pull-up and 5-A pull-down currents to drive the capacitive load of the external power transistors, as

well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The

capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and

receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5451 also contains under

voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pull-down

feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The ISO5451

also has an active Miller clamp which can be used to prevent parasitic turn-on of the external power transistor,

due to Miller effect, for unipolar supply operation.

9.2 Functional Block Diagram

L{h5451

OUT

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9.3 Feature Description

9.3.1 Supply and active Miller clamp

The ISO5451 supports both bipolar and unipolar power supply with active Miller clamp.

For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its

emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its

gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the

IGBT gate. Typical values of V_CC2and V_EE2for bipolar operation are 15 V and -8 V with respect to GND2.

For operation with unipolar supply, typically, V_CC2is connected to 15 V with respect to GND2, and V_EE2is

connected to GND2. In this use case, the IGBT can turn-on due to additional charge from IGBT Miller

capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the

CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.

Miller CLAMP is designed for miller current up to 2 A. When the IGBT is turned-off and the gate voltage

transitions below 2 V the CLAMP current output is activated.

9.3.2 Active Output Pull-down

The Active output pull-down feature ensures that the IGBT gate OUT is clamped to V_EE2to ensure safe IGBT off-

state when the output side is not connected to the power supply.

9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output

Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply V_CC1

drops below V_IT-(UVLO1), irrespective of IN+, IN- and RST input till V_CC1goes above V_IT+(UVLO1)

.

In similar manner, the IGBT is turned-off, if the supply V_CC2drops below V_IT-(UVLO2), irrespective of IN+, IN- and

RST input till V_CC2goes above V_IT+(UVLO2)

.

Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection

feature. If either side of device have insufficient supply (V_CC1or V_CC2), the RDY pin output goes low; otherwise,

RDY pin also serves as an indication to the micro-controller that the device is ready for operation.

9.3.4 Fault (FLT) and Reset (RST)

During IGBT overload condition, to report desaturation error FLT goes low. If RST is held low for the specified

duration, FLT is cleared at rising edge of RST. RST has an internal filter to reject noise and glitches. By asserting

RST for at-least the specified minimum duration, device input logic can be enabled or disabled.

9.3.5 Short Circuit Clamp

Under short circuit events it is possible that currents are induced back into the gate-driver OUT and CLAMP pins

due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on

OUT and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher

than the output side supply.

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Feature Description (continued)

9.3.6 High Voltage Feature Description

9.3.6.1 Package Insulation and Safety-Related Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

L(I01)

Minimum air gap (clearance)

Shortest terminal-to-terminal distance through air

8

mm

Shortest terminal-to-terminal distance across the package

surface

L(I02)⁽¹⁾

Minimum external tracking (creepage)

8

mm

DIN EN 60112 (VDE 0303-11);

IEC 60112;

Material Group I according to IEC 60664-1;

UL 746A

Tracking resistance (comparative

tracking index)

CTI

600

V

(1) Per JEDEC package dimensions.

NOTE

Creepage and clearance requirements should be applied according to the specific

equipment isolation standards of an application. Care should be taken to maintain the

creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to

help increase these specifications.

9.3.6.2 Insulation Characteristics

PARAMETER

Distance through the insulation

TEST CONDITIONS

SPECIFICATION

UNIT

μm

DTI

Minimum internal gap (internal clearance)

21

1000

1420

V_RMS

V_DC

V_IOWM

Maximum isolation working voltage

Time dependent dielectric breakdown (TDDB) Test

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

V_IORM

Maximum repetitive peak isolation voltage

1420

1704

Method A, After Input/Output safety test subgroup 2/3,

V_PR= 1.2 x V_IORM, t = 10 sec,

Partial discharge < 5 pC

Method A, After environmental tests subgroup 1,

V_PR= 1.6 × V_IORM, t = 10 sec (qualification)

Partial discharge < 5 pC

V_PR

Input to output test voltage

2272

2662

V_PK

Method B1, 100% Production test,

V_PR= 1.875 × V_IORM, t = 1 sec

Partial discharge < 5 pC

V_TEST= V_IOTM, t = 60 sec (qualification), t = 1 sec (100%

production)

V_IOTM

V_IOSM

Maximum Transient isolation voltage

Maximum surge isolation voltage

8000

6250

Test method per IEC 60065, 1.2/50 μs waveform,

V_TEST= 1.6 x V_IOSM= 10000 V_PK(qualification)⁽¹⁾

> 10¹²

> 10¹¹

> 10⁹

1

V_IO= 500 V, T_A= 25°C

Ω

R_IO

C_IO

Isolation resistance, input to output⁽²⁾

V_IO= 500 V, 100°C ≤ T_A≤ max

V_IO= 500 V at T_S

Ω

Barrier capacitance, input to output⁽²⁾

Pollution degree

V_IO= 0.4 x sin (2πft), f = 1 MHz

pF

2

UL 1577

V_TEST= V_ISO, t = 60 sec (qualification),

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 sec (100%

production)

V_ISO

Withstanding Isolation voltage

5700

V_RMS

(1) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(2) All pins on each side of the barrier tied together creating a two-terminal device

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9.3.6.3 Regulatory Information

VDE

CSA

UL

CQC

Plan to certify to DIN V VDE V 0884-

Plan to certify under CSA Component Plan to certify under 1577 Component Plan to certify according to GB

10 (VDE V 0884-10):2006-12 and DIN Acceptance Notice 5A, IEC 60950-1,

Recognition Program

4943.1-2011

EN 60950-1 (VDE 0805 Teil 1):2011- IEC 61010-1, and IEC 60601-1

01

Isolation Rating of 5700 V_RMS

;

Reinforced insulation per CSA 61010-

1-12 and IEC 61010-1 (3rd Ed.), 300

VRMS max working voltage;

Reinforced Insulation Maximum

Transient isolation voltage, 8000 V_PK

Maximum surge isolation voltage,

;

Reinforced insulation per CSA 60950-

1- 07+A1+A2 and IEC 60950-1 (2nd

Ed.), 800 VRMS max working voltage

(pollution degree 2, material group I) ;

2 MOPP (Means of Patient Protection)

per CSA 60601-1:14 and IEC 60601-1

Ed. 3.1, 250 VRMS (354 VPK) max

working voltage

Reinforced Insulation, Altitude ≤

5000m, Tropical climate, 250 V_RMS

maximum working voltage

(1)

Single Protection, 5700 V_RMS

6250 V_PK

,

Maximum repetitive peak isolation

voltage, 1420 V_PK

Certification planned

(1) Production tested ≥ 6840 V_RMSfor 1 second in accordance with UL 1577.

9.3.6.4 IEC 60664-1 Rating Table

PARAMETER

Basic Isolation Group

TEST CONDITIONS

SPECIFICATION

Material Group

I

Rated Mains Voltage ≤ 300 V_RMS

Rated Mains Voltage ≤ 600 V_RMS

Rated Mains Voltage ≤ 1000 V_RMS

I-IV

I-III

I-II

Installation Classification

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9.3.6.5 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.

A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate

sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system

failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

θ_JA= 99.6°C/W, V_I= 3.6 V, T_J= 150°C,

349

T_A= 25°C

θ_JA= 99.6°C/W, V_I= 5.5 V, T_J= 150°C,

T_A= 25°C

228

84

I_S

Safety input, output or supply current

Safety input, output, or total power

mA

θ_JA= 99.6°C/W, V_I= 15 V, T_J= 150°C,

T_A= 25°C

θ_JA= 99.6°C/W, V_I= 30 V, T_J= 150°C,

T_A= 25°C

42

P_S

T_S

θ_JA= 99.6°C/W, T_J= 150°C, T_A= 25°C

1255⁽¹⁾

150

Maximum ambient safety

temperature

°C

(1) Input, output, or the sum of input and output power should not exceed this value

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum

Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the

application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the

Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount

Packages. The power is the recommended maximum input voltage times the current. The junction temperature is

then the ambient temperature plus the power times the junction-to-air thermal resistance.

400

350

300

250

200

150

100

50

1400

1200

1000

800

600

400

200

0

V_CC1= 3.6 V

V_CC1= 5.5 V

V_CC2= 15 V

V_CC2= 30 V

Power

0

50

100

150

200

0

50

100

150

200

Ambient Temperature (èC)

Figure 39. Thermal Derating Curve for Safety Limiting

Current per VDE

Figure 40. Thermal Derating Curve for Safety Limiting

Power per VDE

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9.4 Device Functional Modes

In ISO5451 OUT to follow IN+ in normal functional mode, RST and RDY needs to be in high state.

Table 1. Function Table⁽¹⁾

V_CC1

PU

PD

PU

V_CC2

PD

IN+

X

IN-

X

RST

X

RDY

Low

High

Low

High

OUT

Low

High

PU

X

PU

X

Low

X

Open

PU

X

Low

X

PU

High

Low

X

PU

High

(1) PU: Power Up (V_CC1≥ 2.25-V, V_CC2≥ 13-V), PD: Power Down (V_CC1≤ 1.7-V, V_CC2≤ 9.5-V), X: Irrelevant

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ISO5451 is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is

intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In

these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at

the system level eventually may determine, for example, the speed, position, and torque of the motor or the

output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a micro

controller, and are at low voltage levels such as 3.3-V or 5-V. The gate controls required by the MOSFETs and

IGBTs, on the other hand, are in the range of 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output

Supply), and need high current capability to be able to drive the large capacitive loads offered by those power

transistors. Not only that, the gate drive needs to be applied with reference to the Emitter of the IGBT (Source for

MOSFET), and by construction, the Emitter node in a gate drive system swings between 0 to the DC bus

voltage, that can be several 100s of volts in magnitude.

The ISO5451 is thus used to level shift the incoming 3.3-V and 5-V control signals from the microcontroller to the

30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output Supply) drive required by the power

transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.

10.2 Typical Applications

Figure 41 shows the typical application of a three-phase inverter using six ISO5451 isolated gate drivers. Three-

phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high

power applications such as High-Voltage DC (HVDC) power transmission.

The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5451

devices that are connected to one of the three load terminals. The operation of the three switches is coordinated

so that one switch operates at each 60 degree point of the fundamental output waveform, thus creating a six-

step line-to-line output waveform. In this type of applications, carrier-based PWM techniques are applied to retain

waveform envelope and cancel harmonics.

Figure 41. Typical Motor Drive Application

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Typical Applications (continued)

10.2.1 Design Requirements

Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the

input control signals, the input control to the ISO5451 is CMOS and can be directly driven by the microcontroller.

Other design requirements include decoupling capacitors on the input and output supplies, a pullup resistor on

the common drain FLT output signal, and a high-voltage protection diode between the IGBT collector and the

DESAT input. Further details are explained in the subsequent sections. Table 2 shows the allowed range for

Input and Output supply voltage, and the typical current output available from the gate-driver.

Table 2. Design Parameters

PARAMETER

Input supply voltage

VALUE

3-V to 5.5-V

15-V to 30-V

0-V to 15-V

2.5-A

Unipolar output supply voltage (V_CC2- GND2 = V_CC2- V_EE2

)

Bipolar output supply voltage (V_CC2- V_EE2

)

Bipolar output supply voltage (GND2 - V_EE2

Output current

)

10.2.2 Detailed Design Procedure

10.2.2.1 Recommended ISO5451 Application Circuit

The ISO5451 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open

drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 42 illustrates

a typical gate driver implementation with Unipolar Output Supply and Figure 43 illustrates a typical gate driver

implementation with Bipolar Output Supply using the ISO5451.

A 0.1-μF bypass capacitor, recommended at input supply pin V_CC1and 1-μF bypass capacitor, recommended at

output supply pin V_CC2, provide the large transient currents necessary during a switching transition to ensure

reliable operation. The 220 pF blanking capacitor disables DESAT detection during the off-to-on transition of the

power device. The DESAT diode (D_DST) and its 1-kΩ series resistor are external protection components. The R_G

gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times.

The open-drain FLT output and RDY output has a passive 10-kΩ pull-up resistor. In this application, the IGBT

gate driver is disabled when a fault is detected and will not resume switching until the micro-controller applies a

reset signal.

10R

15

9,16

10

5

15

9,16

10

5

V_CC1

GND1

IN+

V_CC2

GND2

V_EE2

V_CC1

GND1

IN+

V_CC2

GND2

V_EE2

ISO5451

1ꢀF

0.1ꢀF

3V - 5.5V

3V-5.5V

15V

0.1ꢀF

15V

3

1,8

D_DST

1kΩ

10k

11

12

13

14

2

7

6

4

11

12

13

14

2

7

6

4

IN-

DESAT

CLAMP

OUT

IN-

DESAT

CLAMP

OUT

RDY

FLT

RST

RDY

R_G

FLT

NC

RST

220

pF

220

pF

Figure 42. Unipolar Output Supply

Figure 43. Bipolar Output Supply

22

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10.2.2.2 FLT and RDY Pin Circuitry

There is 50k pull-up resistor internally on FLT and RDY pins. The FLT and RDY pin is an open-drain output. A

10-kΩ pull-up resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive,

as shown in Figure 44.

Fast common mode transients can inject noise and glitches on FLT and RDY pins due to parasitic coupling. This

is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT

and RDY pins.

10R

ISO5451

15

V_CC1

0.1ꢀF

3V - 5V

9, 16

GND1

10k

12

13

RDY

FLT

ꢀC

14

10

RST

IN+

11

IN-

Figure 44. FLT and RDY Pin Circuitry for High CMTI

10.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the

high-voltage output circuit to the low-voltage input side of the ISO5451. For maximum CMTI performance, the

digital control inputs, IN+ and IN-, must be actively driven by standard CMOS, push-pull drive circuits. This type

of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5451

output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain

configurations using pull-up resistors, must be avoided. There is a 20 ns glitch filter which can filter a glitch up to

20 ns on IN+ or IN-.

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10.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the

individual reset lines are asserted low independently to reset the motor controller after a fault condition.

10R

ISO5451

V_CC1

15

10R

15

ISO5451

V_CC1

0.1ꢀF

3V - 5V

0.1ꢀF

3V - 5V

9,16

GND1

10k

12

13

12

13

RDY

FLT

RDY

FLT

ꢀC

14

10

14

10

RST

IN+

RST

IN+

11

IN-

11

IN-

Figure 45. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5451 can be configured to shutdown automatically in the event

of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of

multiple ISO5451 devices can be wired together forming a single, common fault bus for interfacing directly to the

micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FLT

output disables all six gate drivers simultaneously.

10R

15

ISO5451

V_CC1

0.1ꢀF

3V - 5V

9,16

GND1

10k

12

13

RDY

FLT

ꢀC

14

10

RST

IN+

11

IN-

to other

s

FLT

RST

Figure 46. Global Shutdown with Inverting Input Configuration

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10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching

cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault

state until the gate control signal changes to the 'gate low' state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high

again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next

'on' cycle.

ISO5451

V_CC1

10R

ISO5451

V_CC1

10R

15

0.1ꢀF

3V - 5V

0.1ꢀF

3V - 5V

9, 16

GND1

RDY

10k

12

13

12

13

RDY

FLT

RST

IN+

ꢀC

14

10

14

10

RST

IN+

11

IN-

Figure 47. Auto Reset for Non-inverting and Inverting Input Configuration

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes

of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial

current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in

series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of

the DESAT input to GND2 potential at low voltage levels.

ISO5451

5

V_CC2

GND2

V_EE2

1ꢀF

15V

3

1,8

D_DST

R_S

2

7

6

4

DESAT

CLAMP

OUT

R_G

V_FW-Inst

NC

220 pF

V_FW

Figure 48. DESAT Pin Protection with Series Resistor and Schottky Diode

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10.2.2.8 DESAT Diode and DESAT Threshold

The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-to-

emitter voltage, V_(CESAT), (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the

short transition time when the IGBT is switching, there is commonly a high dV_CE/dt voltage ramp rate across the

IGBT. This results in a charging current I_(CHARGE)= C_(D-DESAT)x d_VCE/dt, charging the blanking capacitor. C_(D-DESAT)

is the diode capacitance at DESAT.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are

recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector

voltage transients appear at DESAT attenuated by the ratio of 1+ C_(BLANK)/ C_(D-DESAT)

.

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the

voltage at the DESAT-pin, V_F+ V_CE= V_(DESAT), the V_CElevel, which triggers a fault condition, can be modified by

adding multiple DESAT diodes in series: V_CE-FAULT(TH)= 9 V – n x VF (where n is the number of DESAT diodes).

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be

chosen.

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, P_OD-max

The ISO5451 maximum allowed total power consumption of P_D= 251 mW consists of the total input power, P_ID,

the total output power, P_OD, and the output power under load, P_OL

:

P_D= P_ID+ P_OD+ P_OL

(1)

(2)

(3)

(4)

With:

P_ID= V_CC1-max× I_CC1-max= 5.5 V × 4.5 mA = 24.75 mW

and:

P_OD= (V_CC2– V_EE2) x I_CC2-max= (15V – ( –8V)) × 6 mA = 138 mW

then:

P_OL= P_D– P_ID– P_OD= 251 mW – 24.75 mW – 138 mW = 88.25 mW

In comparison to P_OL, the actual dynamic output power under worst case condition, P_OL-WC, depends on a variety

of parameters:

æ

ç

è

ö

÷

ø

r_on-max

r_off-max

P_OL-WC= 0.5 ´ f

´ Q_G

´

V

- V_EE2

´

+

(

)

INP

CC2

r_on-max+ R_G

r_off-max+ R_G

where

•

f_INP= signal frequency at the control input IN+

Q_G= power device gate charge

V_CC2= positive output supply with respect to GND2

V_EE2= negative output supply with respect to GND2

r_on-max= worst case output resistance in the on-state: 4Ω

r_off-max= worst case output resistance in the off-state: 2.5Ω

R_G= gate resistor

(5)

Once R_Gis determined, Equation 5 is to be used to verify whether P_OL-WC< P_OL. Figure 49 shows a simplified

output stage model for calculating P_OL-WC

.

26

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ISO5451

V_CC2

15V

R_G

r_on-max

OUT

Q_G

r_off-max

8V

V_EE2

Figure 49. Simplified Output Model for Calculating P_OL-WC

10.2.2.10 Example

This examples considers an IGBT drive with the following parameters:

I_ON-PK= 2 A, Q_G= 650 nC, f_INP= 20 kHz, V_CC2= 15V, V_EE2= –8 V

(6)

Apply the value of the gate resistor R_G= 10 Ω.

Then, calculating the worst-case output power consumption as a function of R_G, using Equation 5 r_on-max= worst

case output resistance in the on-state: 4Ω, r_off-max= worst case output resistance in the off-state: 2.5Ω, R_G= gate

resistor yields

4 Ω

2.5 Ω

æ

ç

è

ö

÷

ø

P_OL-WC= 0.5´20 kHz´650 nC´ 15 V -( -8 V) ´

( )

+

4 Ω + 10 Ω 2.5 Ω + 10 Ω

= 72.61 mW

(7)

Because P_OL-WC= 72.61 mW is below the calculated maximum of P_OL= 88.25 mW, the resistor value of R_G= 10

Ω is suitable for this application.

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10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in

Figure 50) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and

must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10

pair for up to 15 A maximum.

5

V_CC2

ISO5451

1ꢀF

15V

3

GND2

V_EE2

1, 8

D_DST

1kΩ

2

7

6

4

DESAT

CLAMP

OUT

r_G

10Ω

NC

220

pF

Figure 50. Current Buffer for Increased Drive Current

10.2.3 Application Curve

C_L= 1 nF

R_G= 10 Ω

C_L= 1 nF

R_G= 10 Ω

GND2 - V_EE2= 8 V

V_CC2- V_EE2= V_CC2- GND2 = 20 V

V_CC2- GND2 = 15 V

(V_CC2- V_EE2= 23 V)

Figure 52. Normal Operation - Unipolar Supply

Figure 51. Normal Operation - Bipolar Supply

28

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11 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at

input supply pin V_CC1and 1-μF bypass capacitor is recommended at output supply pin V_CC2. The capacitors

should be placed as close to the supply pins as possible. Recommended placement of capacitors needs to be

2-mm maximum from input and output power supply pin (V_CC1and V_CC2).

12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 53). Layer stacking should

be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and

low-frequency signal layer.

•

Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of

their inductances) and allows for clean interconnects between the gate driver and the microcontroller and

power transistors. Gate driver control input, Gate driver output OUT and DESAT should be routed in the top

layer.

•

Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for

the return current flow. On the driver side, use GND2 as the ground plane.

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/inch². On the gate-driver V_EE2and V_CC2can be used as power planes. They can share

the same layer on the PCB as long as they are not connected together.

•

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,

routing etc. see Application Note SLLA284, Digital Isolator Design Guide.

12.2 PCB Material

Standard FR-4 epoxy-glass is recommended as PCB material. FR-4 (Flame Retardant 4) meets the

requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower

dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-

extinguishing flammability-characteristics.

12.3 Layout Example

High-speed traces

10 mils

Ground plane

Yeep this

FR-4

0 ~ 4.5

space free

from planes,

traces, pads,

and vias

40 mils

10 mils

r

Power plane

Low-speed traces

Figure 53. Recommended Layer Stack

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following:

•

ISO5851 Evaluation Module (EVM) User’s Guide, SLLU218

Digital Isolator Design Guide, SLLA284

Isolation Glossary (SLLA353)

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30

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PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.38

0.25

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/A 08/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MO-013, variation AA.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

9

8

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/A 08/2013

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/A 08/2013

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jul-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ISO5451DWR

SOIC

DW

16

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jul-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

ISO5451DWR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ISO5451
厂家：	TEXAS INSTRUMENTS
描述：	High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver with Active Safety Features 栅双极性晶体管
文件：	总38页 (文件大小：1592K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO5451 [TI]

相关型号：

ISO5451-Q1

ISO5451DW

ISO5451DWR

ISO5451QDWQ1

ISO5451QDWRQ1

ISO5452

ISO5452-Q1

ISO5452DW

ISO5452DWR

ISO5452QDWQ1

ISO5452QDWRQ1

ISO5500