ISO7041QDBQRQ1 [TI]
汽车类 120µA 超低功耗四通道数字隔离器 | DBQ | 16 | -40 to 125;
| 型号： | ISO7041QDBQRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 120µA 超低功耗四通道数字隔离器 | DBQ | 16 | -40 to 125 |
| 文件： | 总32页 (文件大小：1752K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7041-Q1
ZHCSNP7 –JUNE 2022
ISO7041-Q1 汽车类超低功耗四通道数字隔离器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性：
ISO7041-Q1 器件是一款可用于隔离 CMOS 或
LVCMOS 数字 I/O 的超低功耗多通道数字隔离器。每
条隔离通道的逻辑输入和输出缓冲器均由双电容二氧化
硅 (SiO2) 绝缘栅相隔离。基于边缘的创新架构与开关
键控调制方案相结合，使这些隔离器具有非常低的功
耗，同时符合 UL1577 规定的 3000VRMS 隔离额定
值。ISO7041-Q1 器件在 3.3V 时的每通道动态电流消
耗低于 120μA/Mbps ， 每通道静态电流消耗为
3.5μA，因此可用于对功耗和热性能有要求的系统设
计中。
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
• 提供功能安全
– 可提供用于功能安全系统设计的文档：
ISO7041-Q1
• 满足VDA320 隔离要求
• 超低功耗
– 每通道静态电流为3.5μA (3.3V)
– 100kbps 时的每通道电流为15μA (3.3V)
– 1Mbps 时的每通道电流为116μA (3.3V)
• 稳健可靠的隔离栅
该器件可在低至 3.0V 和高达 5.5V 的电压下工作，并
可在隔离层的每一侧采用不同电源电压的情况下完全正
常运行。四通道隔离器采用16-QSOP 封装，具有三个
正向通道和一个反向通道。该器件具有默认输出高电平
和低电平选项。如果输入功率或信号出现损失，则不具
有 F 后缀的 ISO7041-Q1 器件默认输出高电平，具有
F 后缀的 ISO7041F-Q1 器件默认输出低电平。请参阅
器件功能模式部分以了解详情。
– 预计寿命超过100 年
– 隔离额定值为3000VRMS
– CMTI 典型值为±100kV/μs
• 宽电源电压范围：3.0V 至5.5V
• 宽温度范围：–40°C 至125°C
• 小型16-QSOP 封装(16-DBQ)
• 信令速率：高达4Mbps
• 默认输出高电平(ISO7041-Q1) 和低电平
(ISO7041F-Q1) 选项
• 优异的电磁兼容性(EMC)
器件信息
器件型号(1)
ISO7041-Q1
封装尺寸（标称值）
封装
QSOP (16)
4.90mm × 3.90mm
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
FUSE
Relay
– 超低干扰(EMI)
IN
12 V
Fuse/relay sense
• 安全相关认证（计划）：
PMIC
OUT
VCC
BAT
CVDD
VCC1
VCC2
– DIN V VDE 0884-11:2017-01
– UL 1577 组件认证计划
GPIOx
ISO7041-Q1
BQ75614-Q1
Battery
– IEC 60950-1、IEC 62368-1、IEC 61010-1、
IEC60601-1 和GB 4943.1-2011 认证
MCU
UART
GND1
GND2
Current sense
2 应用
Rs
• 混合动力、电动和动力总成系统(EV/HEV)
简化版应用原理图
– 电池管理系统(BMS)
– 车载充电器
– 牵引逆变器
– 直流/直流转换器
– 逆变器和电机控制
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFN3
ISO7041-Q1
ZHCSNP7 –JUNE 2022
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Table of Contents
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................17
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 20
10 Power Supply Recommendations..............................24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 Receiving Notification of Documentation Updates..26
12.3 支持资源..................................................................26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
12.6 术语表..................................................................... 26
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 绝对最大额定值...........................................................4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
Insulation Specifications................................................... 7
6.6 Safety-Related Certifications...................................... 8
6.7 Safety Limiting Values.................................................8
6.8 Electrical Characteristics 5V Supply........................... 9
6.9 Supply Current Characteristics 5V Supply..................9
6.10 Electrical Characteristics 3.3V Supply.................... 11
6.11 Supply Current Characteristics 3.3V Supply........... 11
6.12 Switching Characteristics........................................12
6.13 Insulation Characteristics Curves........................... 12
6.14 Typical Characteristics............................................13
7 Parameter Measurement Information..........................14
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
June 2022
*
Initial Release
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Device Comparison Table
表5-1. Device Features
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PART NUMBER
CHANNEL DIRECTION
PACKAGE
DBQ-16
RATED ISOLATION
3000 VRMS / 4242 VPK
3000 VRMS / 4242 VPK
3 Forward,
1 Reverse
ISO7041-Q1
4 Mbps
4 Mbps
High
ISO7041-Q1 with F
suffix
3 Forward,
1 Reverse
Low
DBQ-16
5 Pin Configuration and Functions
1
2
3
4
5
6
7
8
VCC2
16
VCC1
GND1
GND2 15
OUTA 14
OUTB 13
OUTC 12
IND 11
INA
INB
INC
OUTD
GND1
GND1
GND2 10
GND2
9
Not to scale
图5-1. ISO7041-Q1 DBQ Package 16-Pin QSOP Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
2
GND1
7
Ground connection for VCC1
Ground connection for VCC2
—
8
9
GND2
10
15
3
—
INA
I
I
Input, channel A. 300-Ω series resistor recommended
Input, channel B. 300-Ω series resistor recommended
Input, channel C. 300-Ω series resistor recommended
Input, channel D. 300-Ω series resistor recommended
Output, channel A. 300-Ω series resistor recommended
Output, channel B. 300-Ω series resistor recommended
Output, channel C. 300-Ω series resistor recommended
Output, channel D. 300-Ω series resistor recommended
Power supply, side 1
INB
4
INC
5
I
IND
11
14
13
12
6
I
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
O
O
O
O
1
—
—
16
Power supply, side 2
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6 Specifications
6.1 绝对最大额定值
在自然通风条件下的工作温度范围内（除非另有说明）(1) (2) (3)
最小值
最大值
单位
-0.5
6
V
V
CC1 至GND1
CC2 至GND2
V
电源电压
-0.5
-0.5
-0.5
-0.5
-15
6
VCCX + 0.5
VCCX + 0.5
VCCX + 0.5
15
INx 至GNDx
OUTx 至GNDx
ENx 至GNDx
输入通道，Ii
Io
V
输入/输出电压
mA
mA
°C
输入电流
输出电流
-15
15
150
运行结温，TJ
贮存温度，Tstg
温度
-65
150
°C
(1) 超出这些列出的绝对最大额定值的压力可能会对器件造成永久损坏。这些仅仅是压力额定值，并不表示器件在这些条件下以及在“建议
运行条件”以外的任何其他条件下能够正常运行。在绝对最大额定值条件下长时间运行可影响器件可靠性。
(2) 除差分I/O 总线电压以外的所有电压值都是以本地接地端子（GND1 或GND2）为基准的峰值电压值。
(3) 最大电压不得超过6V。
6.2 ESD Ratings
(1) (2)
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±5000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
V(ESD)
Electrostatic discharge
±1500
±8000
V
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
(1)
VCC1
VCC2
VIH
Supply Voltage Side 1
Supply Voltage Side 2
High level Input voltage
Low level Input voltage
3.0
5.5
5.5
(1)
3.0
V
0.7 x VCCI
VCCI
V
VIL
0
-4
-2
0.3 x VCCI
V
(2)
VCCO
= 5 V
mA
mA
mA
mA
Mbps
°C
IOH
High level output current
Low level output current
VCCO = 3.3 V
VCCO = 5 V
4
2
IOL
VCCO = 3.3 V
DR
TA
Data Rate
0
4
Ambient temperature
-40
125
(1) VCC1 and VCC2 can be set independent of one another
(2) VCCI = Input-side VCC; VCCO = Output-side VCC
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UNIT
6.4 Thermal Information
ISO7041-Q1
DBQ (SOIC)
16 PINS
87.0
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
33.3
49.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.4
ψJT
48.5
ψJB
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.82
4.46
3.36
UNIT
mW
mW
mW
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 1-MHz 50% duty cycle square
wave
PD1
PD2
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Insulation Specifications
PARAMETER
SPECIFICATIONS
QSOP-16
TEST CONDITIONS
UNIT
IEC 60664-1
CLR
CPG
External clearance(1)
Side 1 to side 2 distance through air
>3.7
>3.7
mm
mm
Side 1 to side 2 distance across package
surface
External Creepage(1)
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
IEC 60112; UL 746A
17
µm
V
>600
I
According to IEC 60664-1
Overvoltage category per IEC 60664-1
I-III
Rated mains voltage ≤300 VRMS
DIN V VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
566
400
566
4242
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test; See TBD
VIOWM
Maximum isolation working voltage
DC voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 6400 VPK
(qualification)
VIOSM
4000
≤5
≤5
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM
tm = 10 s
,
Method a: After environmental tests
subgroup 1, Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM
tini = 1 s;
,
≤5
Vpd(m) = 1.875 × VIORM , tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
~1.5
> 1012
> 1011
> 109
2
pF
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤150°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST
1.2 × VISO , t = 1 s (100% production)
=
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
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6.6 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950- 1:2006/
A2:2013 and EN
Certified according to UL
1577 Component
Recognition Program
Certified according to DIN Certified according to IEC
VDE V 0884-11:2017- 01 60950-1 and IEC 62368-1
Certified according to
GB4943.1-2011
62368-1:2014
3000 VRMS insulation per
Maximum transient
isolation voltage,
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2, CSA
EN 61010- 1:2010/
A1:2019, 300 VRMS basic
isolation
EN 60950- 1:2006/
A2:2013 and EN
62368-1:2014, 400 VRMS
basic isolation
Basic insulation, Altitude
≤5000 m, Tropical
Climate,
400 VRMS maximum
working voltage
4242 VPK
;
Maximum repetitive peak 62368-1- 14 and IEC
isolation voltage, 566 VPK 62368-1:2014 370 VRMS
Maximum surge isolation (DBQ-16) maximum
voltage,
4000 VPK
Single protection,
3000 VRMS
;
working voltage (pollution
degree 2, material group I)
Certification Planned
Certification Planned
Certification Planned
Certification Planned
Certification Planned
6.7 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16-QSOP PACKAGE
R
θJA = 87°C/W, VI = 5.5 V, TJ = 150°C,
261
399
mA
mA
TA = 25°C
θJA = 87°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
θJA = 87°C/W, TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
R
1435
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.8 Electrical Characteristics 5V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1)
VIT+(IN)
VIT-(IN)
VOH
Rising input switching threshold
Falling input switching threshold
High-level output voltage
Low-level output voltage
0.7 x VCCI
V
V
V
V
0.3 x VCCI
VCCO - 0.4
IOH = -4 mA
VOL
IOL = 4 mA
0.4
Input threshold voltage
hysteresis
VI(HYS)
0.1 x VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
1
µA
µA
-1
Common mode transient
immunity
CMTI
Ci
VI = VCC or 0 V, VCM = 1200 V
50
100
2
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
1 MHz, VCC = 5 V
Input Capacitance (2)
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.9 Supply Current Characteristics 5V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ISO7041-Q1
ICC1
ICC2
ICC1
6.2
10.1
8.2
14.3
18.5
16.7
µA
µA
µA
Refresh disable
Refresh enable
VI = VCCI (1) (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
Supply current - DC
signal
ICC2
ICC1
ICC2
10.8
9.5
18.5
19.9
19.5
µA
µA
µA
Refresh enable
VI = 0 V (ISO7041-Q1);
VI = VCCI (ISO7041-Q1 with F suffix)
11.3
ICC1
6.7
11.8
19.7
20.6
57.4
37.7
436.1
211.1
20.8
20.4
57.4
37.7
436.1
211.1
7.4
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Refresh disable
10 kbps, No Load
ICC2
ICC1
37.1
25.8
340.5
167.0
10.6
11.9
Refresh disable
100 kbps, No Load
ICC2
ICC1
Refresh disable
1 Mbps, No Load
ICC2
Supply current - AC
signal
ICC1
Refresh enable
10 kbps, No Load
ICC2
ICC1
37.1
25.8
338.3
166.0
4.1
Refresh enable
100 kbps, No Load
ICC2
ICC1
Refresh enable
1 Mbps, No Load
ICC2
DC Signal
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
Total Supply Current
Per Channel,
Refresh Disabled
10 kbps, No Load
100 kbps, No Load
1 Mbps, No Load
5.9
10.7
23.4
164.5
17.4
137.0
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
VI = VCCI (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
ICC1(ch) + ICC2(ch)
4.8
8.5
µA
VI = 0 V (ISO7041-Q1);
VI = VCCI (ISO7041-Q1 with F suffix)
Total Supply Current
Per Channel,
ICC1(ch) + ICC2(ch)
5.3
9.6
µA
Refresh Enabled
10 kbps, No Load
100 kbps, No Load
1 Mbps, No Load
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
5.7
16.4
10.4
22.3
µA
µA
µA
125.9
154.0
(1) VCCI = Input-side VCC
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6.10 Electrical Characteristics 3.3V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1)
VIT+(IN)
VIT-(IN)
VOH
Rising input switching threshold
Falling input switching threshold
High-level output voltage
Low-level output voltage
0.7 x VCCI
V
V
V
V
0.3 x VCCI
VCCO - 0.3
IOH = -2mA
VOL
IOL = 2mA
0.3
Input threshold voltage
hysteresis
VI(HYS)
0.1 x VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI (1) at INx
VIL = 0 V at INx
1
µA
µA
-1
Common mode transient
immunity
CMTI
Ci
VI = VCC or 0 V, VCM = 1200 V
50
100
2
kV/us
pF
VI = VCC/ 2 + 0.4×sin(2πft), f =
1 MHz, VCC = 3.6 V
Input Capacitance(2)
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
(2) Measured from input pin to same side ground.
6.11 Supply Current Characteristics 3.3V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ISO7041-Q1
ICC1
ICC2
ICC1
5.1
8.9
6.8
8.8
14.0
12.2
µA
µA
µA
Refresh disable
Refresh enable
VI = VCCI (1) (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
Supply current - DC
signal
ICC2
ICC1
ICC2
9.6
8.1
14.0
14.8
15.6
µA
µA
µA
Refresh enable
VI = 0 V (ISO7041-Q1);
VI = VCCI (ISO7041-Q1 with F suffix)
10.0
ICC1
7.9
10.4
35.9
22.7
316.4
147.2
9.8
13.7
15.9
48.3
31.4
395.7
188.2
16.4
16.2
48.3
31.4
395.7
188.2
5.7
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Refresh disable
10 kbps, No Load
ICC2
ICC1
Refresh disable
100 kbps, No Load
ICC2
ICC1
Refresh disable
1 Mbps, No Load
ICC2
Supply current - AC
signal
ICC1
Refresh enable
10 kbps, No Load
ICC2
10.5
35.9
22.7
315.3
146.2
3.5
ICC1
Refresh enable
100 kbps, No Load
ICC2
ICC1
Refresh enable
1 Mbps, No Load
ICC2
DC Signal
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
Total Supply Current
Per Channel,
Refresh Disabled
10 kbps, No Load
100 kbps, No Load
1 Mbps, No Load
5.2
8.2
14.8
115.7
19.2
138.7
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
VI = VCCI (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
ICC1(ch) + ICC2(ch)
4.2
6.8
µA
VI = 0 V (ISO7041-Q1);
VI = VCCI (ISO7041-Q1 with F suffix)
Total Supply Current
Per Channel,
ICC1(ch) + ICC2(ch)
4.6
7.7
µA
Refresh Enabled
10 kbps, No Load
100 kbps, No Load
1 Mbps, No Load
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
ICC1(ch) + ICC2(ch)
5.2
14.8
8.2
19.2
µA
µA
µA
115.7
138.7
(1) VCCI = Input-side VCC
6.12 Switching Characteristics
VCC1, VCC2 = 3.0 V to 5.5 V (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
tP(dft)
Propagation delay time
Propagation delay drift
Minimum pulse width
Pulse width distortion
148
15
165
ns
See 图7-1
ps/℃
ns
tUI
250
See 图7-1
PWD
10
10
10
70
16
16
ns
Same-direction channels
ns
tsk(o)
Channel to channel output skew time
Opposite-direction channels
ns
tsk(p-p)
Part to part skew time
Output signal rise time
Output signal fall time
ns
tr
tf
ns
See 图7-1
See 图7-1
ns
Default output delay time from input
power loss
tDO
400
10
750
5
us
See 图7-2
tPU
FR
Time from UVLO to valid output data
Refresh rate
1
5
ms
kbps
6.13 Insulation Characteristics Curves
500
1600
VCC = 3.6 V
VCC = 5.5 V
400
300
200
100
0
1200
800
400
0
0
40
80
120
160
200
0
20
40
60
80
100
120
140
160
Ambient Temperature (èC)
Ambient Temperature (C)
SLLS
图6-2. Thermal Derating Curve for Limiting Power
图6-1. Thermal Derating Curve for Limiting Current
per VDE
per VDE
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6.14 Typical Characteristics
500
500
100
100
10
2
10
2
1
10
100
1000
4000
0.2
1
10
100
1000
4000
Data Rate (kbps)
Data Rate (kbps)
TA = 25°C
CL = 0 pF
TA = 25°C
CL = 15 pF
图6-3. ISO7041-Q1 Supply Current vs Data Rate at 图6-4. ISO7041-Q1 Supply Current vs Data Rate at
3.3 V
3.3 V
(With No Load)
(With 15-pF Load)
500
100
500
100
10
2
10
2
0.2
1
10
100
1000
4000
0.2
1
10
100
1000
4000
Data Rate (kbps)
Data Rate (kbps)
TA = 25°C
CL = 0 pF
TA = 25°C
CL = 15 pF
图6-5. ISO7041-Q1 Supply Current vs Data Rate at 图6-6. ISO7041-Q1 Supply Current vs Data Rate at
5 V
5 V
(With No Load)
(With 15-pF Load)
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7 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input
Generator
(See Note A)
C
L
V
I
V
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3ns, ZO
= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图7-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
V
CC
V
CC
V
I
1.7 V
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
图7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
V
OH
or V
OL
C
L
œ
See Note A
GNDI
GNDO
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图7-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7041-Q1 device uses edge encoding of data with an ON-OFF keying (OOK) modulation scheme to
transmit the digital data across a silicon dioxide isolation barrier. The transmitter uses a high frequency carrier
signal to pass data across the barrier representing a signal edge transition. Using this method achieves very low
power consumption and high immunity. The receiver demodulates the carrier signal after advanced signal
conditioning and produces the output through a buffer stage. For low data rates, a refresh logic option is
available to make sure the output state matches the input state. Advanced circuit techniques are used to
maximize the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO
buffer switching. The conceptual block diagram of a digital capacitive isolator, Conceptual Block Diagram of a
Digital Capacitive Isolator, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
TX IN
Edge
Encoding
Capacitive
Isolation
Barrier
Refresh
Logic
Watch Dog
Timer
Oscillator
图8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
8.3 Feature Description
8.3.1 Refresh
The ISO7041 uses an edge based encoding scheme to transfer an input signal change across the isolation
barrier versus sending across the DC state. The built in refresh function consistently validates that the DC output
state of each isolator channel matches the DC input state. An internal watchdog timer monitors for activity on the
individual inputs and transmits the logic state when there is no input signal transition for more than 100 µs. This
ensures that the input and output state of the isolator always match.
8.3.2 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO70xx
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
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• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
The device has no issue being able to meet either CISPR 22 Class A and CISPR22 Class B standards in an
unshielded environment.
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8.4 Device Functional Modes
表8-1 shows the functional modes for the device.
表8-1. Function Table
REFRESH
ENABLE
(ENx)
INPUT
(INx)
OUTPUT
(OUTx)
(1)
VCCI
VCCO
COMMENTS
H
L
L
L
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
PU
The device needs an input signal transition to validate the output
X
X
H
Undetermined tracks the input state. Without a signal edge transition, the output will
be in an undetermined state.
When VCCI is unpowered, a channel output assumes the logic state
based on the selected default option. Default is High for the device
without the F suffix and Low for device with the F suffix.
L
Default
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
PD
PU
When VCCI transitions from powered-up to unpowered, channel
output assumes the selected default state.
When VCCI is unpowered, a channel output assumes the logic state
based on the previous state of the output before VCCI powered down.
H
L
Undetermined
When VCCO is unpowered, a channel output is undetermined.(2)
Undetermined When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
X
X
PD
X
X
X
When VCCO is unpowered, a channel output is undetermined.(2)
Undetermined When VCCO transitions from unpowered to powered-up, a channel
output assumes the selected default option.
H
When ENx is unconnected or open, the device output will be in an
Undetermined undetermined and unknown state. ENx must be connected high or
low for the device to behave correctly.
Open
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥1.54 V); PD = Powered down (VCC ≤1.54); X = Irrelevant;
H = High level; L = Low level ; Z = High Impedance.
(2) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
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8.4.1 Device I/O Schematics
Refresh Enable
Input
V
V
V
CCI
CCI
CCI
V
V
V
CCI
CCI
CCI
985 ꢀ
1970 ꢀ
INx
ENx
Output
V
CCO
~20 ꢀ
OUTx
图8-2. Device I/O Schematics
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO7041-Q1 device is an ultra-low power digital isolator. The device uses single-ended CMOS-logic
switching technology. The voltage range is from 3.0 V to 5.5 V for both supplies, VCC1 and VCC2, and can be set
irrespective of one another. When designing with digital isolators, keep in mind that because of the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard. See Isolated power and data interface for low-power applications reference design TI Design for
detailed information on designing the ISO70xx in low-power applications.
9.1.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; see 图 9-1 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm) and a minimum insulation lifetime of 20 years. VDE standard also requires additional safety margin of
20% for working voltage and 87.5% for insulation lifetime which translates into minimum required life time of 37.5
years.
图 9-2 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of these devices is 400 VRMS with a lifetime of >100 years.
Other factors, such as package size, pollution degree, material group, and so forth can further limit the working
voltage of the component. The working voltage of the DBQ-16 package specified up to 400 VRMS. At the lower
working voltages, the corresponding insulation barrier life time is much longer.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND
1
GND 2
V
S
Oven at 150 °C
图9-1. Test Setup for Insulation Lifetime Measurement
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图9-2. Insulation Lifetime Projection Data
9.2 Typical Application
Isolated UART for an Automotive Battery Management System shows the isolated UART and GPIO (NFAULT)
interface.
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CVDD
CVSS
N
N
N
1
DVDD
DVSS
10 kꢀ
10 kꢀ
TSREF
GPIO1
N
1
1
REFHP
REFHM
N
N
N
GPIO2
GPIO3
AVDD
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
NEG5V
AVSS
N
N
LDOIN
NPNB
BAT
200 ꢀ
100 ꢀ
MCU
ISO7041-Q1
To CVDD
30 ꢀ
BQ75614-Q1
VCC1
VCC2
VCC
100 kꢀ
100 kꢀ
100 kꢀ
10 nF
INA
OUTA
NFAULT
TX
INB
OUTB
OUTC
IND
INT
100 ꢀ
INC
RX
TX
VC14
VC13
0.47 uF
100 ꢀ
RX
OUTD
+
CELL 14
0.47 uF
GND1
GND2
GND
+
CELL 13
100 ꢀ
100 ꢀ
VC1
VC0
0.47 uF
+
0.47 uF
CELL 1
CB14
CB13
CELL 14
100 ꢀ
0.47 uF
CELL 13
100 ꢀ
SRP
CB1
CB0
CELL 1
CELL 0
100 ꢀ
100 ꢀ
0.47 uF
0.47 uF
Rsense
SRN
图9-3. Isolated UART for an Automotive Battery Management System
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETER
VALUE
3.0 V to 5.5 V
0.1 µF
Supply voltage, VCC1 and VCC2
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the device only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
VCC2
VCC1
1
16
0.1 µF
0.1 µF
GND1
GND2
2
3
15
14
INA
INB
INC
OUTA
OUTB
OUTC
13
4
12
11
10
9
5
6
7
8
IND
OUTD
GND2
GND2
GND1
GND1
图9-4. Typical ISO7041-Q1 Circuit Hook-up
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9.2.3 Application Curves
The following typical eye diagrams of the device indicates wide open eye at the maximum data rate of 4 Mbps.
图9-5. Eye Diagram at 4 Mbps PRBS 216 –1, 3.3 V and 25°C
图9-6. Eye Diagram at 4 Mbps PRBS 216 –1, 5 V and 25°C
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10 Power Supply Recommendations
Put a 0.1-μF bypass capacitor at the input and output supply pins (VCC1 and VCC2) to make sure that operation
is reliable at data rates and supply voltage. Put the capacitors as near to the supply pins as possible. If only one
primary-side power supply is available in an application, use a transformer driver to help generate the isolated
power for the secondary-side. Texas Instruments recommends the SN6501 device or SN6505A device. Refer to
the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies data sheet for detailed power supply design and transformer selection
recommendations.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 11-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations,.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图11-1. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments,BQ75614-Q1, 14-S automotive precision battery monitor, balancer and integrated
protector with ASIL-D compliance
• Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power
Applications TI Design
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Instruments, Isolated power and data interface for low-power applications reference design TI Design
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
26
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Product Folder Links: ISO7041-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7041FQDBQRQ1
ISO7041QDBQRQ1
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
16
16
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
7041F
7041
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2022
OTHER QUALIFIED VERSIONS OF ISO7041-Q1 :
Catalog : ISO7041
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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