ISO7220BDG4 [TI]
双通道、2/0、5Mbps 数字隔离器 | D | 8 | -40 to 125;
| 型号： | ISO7220BDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、2/0、5Mbps 数字隔离器 | D | 8 | -40 to 125 驱动 光电二极管 接口集成电路 驱动程序和接口 |
| 文件： | 总26页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com ................................................................................................................................................................ SLLS755H–JULY 2006–REVISED MAY 2008
DUAL DIGITAL ISOLATORS
1
FEATURES
•
•
•
4 kV ESD Protection
2
•
1, 5, 25, and 150-Mbps Signaling Rate Options
High Electromagnetic Immunity
–
–
–
Low Channel-to-Channel Output Skew;
1 ns max
–40°C to 125°C Operating Range
APPLICATIONS
•
Industrial Fieldbus
Low Pulse-Width Distortion (PWD);
1 ns max
–
–
–
Modbus
Profibus™
DeviceNet™ Data Buses
Low Jitter Content; 1 ns Typ at 150 Mbps
•
•
Typical 25-Year Life at Rated Voltage
(see app. note SLLA197 and Figure 20)
•
•
•
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
4000-Vpeak Isolation, 560 V peak VIORM
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1
–
50 kV/µs Typical Transient Immunity
•
Operates with 3.3-V or 5-V Supplies
DESCRIPTION
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented
in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input
and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to
4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and
prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or
damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received every 4 µs, the input is assumed to be
unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The small capacitance and resulting time constant provide fast operation with signaling rates available from 0
Mbps (dc) to 150 Mbps.(1)The A-, B- and C-option devices have TTL input thresholds and a noise filter at the
input that prevents transient pulses from being passed to the output of the device. The M-option devices have
CMOS VCC/2 input thresholds and do not have the input noise-filter and the additional propagation delay.
These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
ISO7221xD
ISO7220xD
1
2
3
4
8
7
6
5
VCC1
OUTA
INB
VCC2
1
2
3
4
8
7
6
5
VCC1
INA
INB
VCC2
INA
OUTA
OUTB
GND2
OUTB
GND2
GND1
GND1
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
DeviceNet is a trademark of Open DeviceNet Vendors Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755H–JULY 2006–REVISED MAY 2008 ................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SINGLE-CHANNEL FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
Data MUX
AC Detect
Input
+
Filter
Vref
IN
OUT
Output Buffer
AC Channel
AVAILABLE OPTIONS
PRODUCT
SIGNALING
RATE
PACKAGE
INPUT
THRESHOLD
CHANNEL
DIRECTION
MARKED
ORDERING
NUMBER
AS
ISO7220AD (rail)
ISO7220ADR (reel)
ISO7220BD (rail)
ISO7220BDR (reel)
ISO7220CD (rail)
ISO7220CDR (reel)
ISO7220MD (rail)
ISO7220MDR (reel)
ISO7221AD (rail)
ISO7221ADR (reel)
ISO7221BD (rail)
ISO7221ABR (reel)
ISO7221CD (rail)
ISO7221CDR (reel)
ISO7221MD (rail)
ISO7221MDR (reel)
≈ 1.5 V (TTL)
(CMOS compatible)
ISO7220A
ISO7220B
ISO7220C
ISO7220M
ISO7221A
ISO7221B
ISO7221C
ISO7221M
1 Mbps
5 Mbps
SOIC-8
I7220A
≈ 1.5 V (TTL)
(CMOS compatible
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
I7220B
I7220C
I7220M
I7221A
I7221B
TI7221C
I7221M
Same direction
≈ 1.5 V (TTL)
(CMOS compatible)
25 Mbps
150 Mbps
1 Mbps
VCC/2 (CMOS)
≈ 1.5 V (TTL)
(CMOS compatible)
≈ 1.5 V (TTL)
(CMOS compatible)
5 Mbps
Opposite directions
≈ 1.5 V (TTL)
(CMOS compatible)
25 Mbps
150 Mbps
VCC/2 (CMOS)
REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Acceptance Notice
Recognized under 1577 Component
Recognition Program(1)
Certified according to IEC 60747-5-2
File Number: 40016131
File Number: 1698195
File Number: E181974
(1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
2
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com ................................................................................................................................................................ SLLS755H–JULY 2006–REVISED MAY 2008
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.5 to 6
–0.5 to 6
±15
UNIT
V
VCC
VI
Supply voltage(2), VCC1, VCC2
Voltage at IN, OUT
Output current
V
IO
mA
Electrostatic discharge JEDEC Standard
22, Test Method A114-C.01
Human Body Model
±4
±1
kV
Electrostatic
discharge
ESD
Field-Induced-Charged Device
Model
All pins
JEDEC Standard 22, Test Method C101
ANSI/ESDS5.2-1996
Machine Model
±200
170
V
TJ
Maximum junction temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
5.5
4
UNIT
V
VCC
IOH
IOL
Supply voltage(1), VCC1, VCC2
High-level output current
Low-level output current
3
mA
mA
µs
–4
ISO722xA
ISO722xB
ISO722xC
ISO722xM
ISO722xA
ISO722xB
ISO722xC
ISO722xM
1
0.67
100
33
200
tui
Input pulse width
Signaling rate
40
ns
6.67
5
0
1500
10
1000
5
kbps
0
Mbps
1/tui
0
30
200(2)
25
Mbps
0
150
VIH
VIL
VIH
VIL
TJ
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
Junction temperature
2
VCC
0.8
V
V
ISO722xA, ISO722xC
ISO722xM
0
0.7 VCC
0
VCC
0.3 VCC
150
V
V
–40
°C
A/m
H
External magnetic field-strength immunity per IEC 61000-4-8 & IEC 61000-4-9
certification
1000
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
(2) Typical sigalling rate under ideal conditions at 25°C.
Copyright © 2006–2008, Texas Instruments Incorporated
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Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755H–JULY 2006–REVISED MAY 2008 ................................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT
ISO7220x
1
8.5
2
2
17
3
Quiescent VI = VCC or 0 V, no load
ISO7221
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ICC1
1 Mbps
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
10
4
18
9
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
25 Mbps
12
16
8.5
17
10
20
12
4.6
5
22
mA
31
Quiescent VI = VCC or 0 V, no load
ISO7221x
17
32
18
34
22
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ICC2
1 Mbps
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
25 Mbps
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
V
0.2
0
0.4
V
VOL
0.1
VI(HYS) Input voltage hysteresis
150
mV
IIH
IIL
CI
High-level input current
Low-level input current
Input capacitance to ground
10
IN from 0 V to VCC
µA
–10
25
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 3
50
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tpLH
tpHL
,
Propagation delay
280
405
1
475
14
70
3
ISO722xA
ISO722xB
ISO722xC
ISO722xM
(1)
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
|
|
|
|
,
Propagation delay
42
22
6
55
1
tpHL
PWD
tpLH
(1)
(1)
(1)
Pulse-width distortion |tpHL – tpLH
Propagation delay
See Figure 1
ns
,
32
1
42
2
tpHL
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
Propagation delay
,
10
0.5
16
tpHL
PWD
Pulse-width distortion |tpHL – tpLH
1
180
17
ISO722xA
ISO722xB
ISO722xC
ISO722xM
(2)
tsk(pp)
Part-to-part skew
ns
10
3
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com ................................................................................................................................................................ SLLS755H–JULY 2006–REVISED MAY 2008
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ISO722xA
ISO722xB
ISO722xC/M
3
0.6
0.2
1
15
3
ns
(3)
tsk(o)
Channel-to-channel output skew
1
tr
Output signal rise time
See Figure 1
ns
tf
Output signal fall time
1
tfs
Failsafe output delay time from input power loss
See Figure 2
3
µs
150 Mbps PRBS NRZ data, 5-bit max
same polarity input, both channels, See
Figure 4, Figure 17
1
2
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO722xM
ns
150 Mbps unrestricted bit run length
data input, both channels, See Figure 4
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
V
SUPPLY CURRENT
ISO7220x
1
8.5
2
2
17
3
Quiescent
1 Mbps
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
ISO7221x
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ICC1
10
4
18
9
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
25 Mbps
Quiescent
1 Mbps
12
8
22
18
9.5
19
11
20
12
ISO7221x
4.3
9
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ICC2
5
10
6
25 Mbps
VI = VCC or 0 V, no load
ISO7220x
IOH = –4 mA, See Figure 1
VCC – 0.4
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
ISO7221x (5-V side)
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
0.4
0.1
VOL
V
VI(HYS)
IIH
Input voltage hysteresis
150
mV
µA
High-level input current
10
IN from 0 V to VCC
IIL
Low-level input current
–10
15
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
VI = VCC or 0 V, See Figure 3
40
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright © 2006–2008, Texas Instruments Incorporated
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Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755H–JULY 2006–REVISED MAY 2008 ................................................................................................................................................................ www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tpLH
tpHL
,
Propagation delay
285
410
1
480
14
75
3
ISO722xA
ISO722xB
ISO722xC
ISO722xM
(1)
PWD Pulse-width distortion |tpHL – tpLH
|
|
|
|
tpLH
,
Propagation delay
45
25
7
58
1
tpHL
PWD Pulse-width distortion |tpHL – tpLH
tpLH
(1)
(1)
(1)
See Figure 1
ns
,
Propagation delay
36
1
48
2
tpHL
PWD Pulse-width distortion |tpHL – tpLH
tpLH
,
Propagation delay
12
0.5
20
tpHL
PWD Pulse-width distortion |tpHL – tpLH
1
180
17
10
5
ISO722xA
ISO722xB
ISO722xC
ISO722xM
ISO722xA
ISO722xB
ISO722xC/M
(2)
tsk(pp) Part-to-part skew
ns
3
0.6
0.2
2
15
3
(3)
tsk(o)
Channel-to-channel output skew
1
tr
Output signal rise time
Output signal fall time
See Figure 1
See Figure 2
ns
tf
2
tfs
Failsafe output delay time from input power loss
3
µs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 4,
Figure 17
1
2
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO722xM
ns
150 Mbps unrestricted bit run length data
input, both channels, See Figure 4
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com ................................................................................................................................................................ SLLS755H–JULY 2006–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7220x
0.6
4.3
1
1
9.5
2
Quiescent
1 Mbps
VI = VCC or 0 V, no load
ISO7221x
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ICC1
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
5
11
4
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
2
25 Mbps
Quiescent
1 Mbps
6
12
31
17
32
18
34
22
mA
16
8.5
18
10
20
12
ISO7221x
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ICC2
25 Mbps
ISO7220x
VCC – 0.8
VCC – 0.4
VCC – 0.1
IOH = –4 mA, See Figure 1
ISO7221x
(3.3-V side)
VOH
High-level output voltage
V
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
0.4
0.1
VOL
Low-level output voltage
0
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
150
mV
10
IN from 0 V or VCC
µA
IIL
Low-level input current
–10
15
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
VI = VCC or 0 V, See Figure 3
40
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright © 2006–2008, Texas Instruments Incorporated
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Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755H–JULY 2006–REVISED MAY 2008 ................................................................................................................................................................ www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tpLH
tpHL
,
Propagation delay
285
395
1
480
18
75
4
ISO722xA
ISO722xB
ISO722xC
ISO722xM
(1)
(1)
(1)
(1)
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
|
|
|
|
,
Propagation delay
45
25
7
58
1
tpHL
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
Propagation delay
See Figure 1
,
36
1
48
3
tpHL
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
Propagation delay
,
12
0.5
21
tpHL
ns
PWD
Pulse-width distortion |tpHL – tpLH
1
190
17
10
5
ISO722xA
ISO722xB
ISO722xC
ISO722xM
ISO722xA
ISO722xB
ISO7220C/M
(2)
tsk(pp)
Part-to-part skew
3
0.6
0.2
1
15
3
(3)
tsk(o)
Channel-to-channel output skew
1
tr
Output signal rise time
Output signal fall time
See Figure 1
See Figure 2
tf
1
tfs
Failsafe output delay time from input power loss
3
µs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 4,
Figure 17
1
2
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO722xM
ns
150 Mbps unrestricted bit run length data input,
both channels, See Figure 4
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
8
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7220A ISO7220B ISO7220C ISO7220M ISO7221A ISO7221B ISO7221C ISO7221M
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com ................................................................................................................................................................ SLLS755H–JULY 2006–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7220x
0.6
4.3
1
1
9.5
2
Quiescent
1 Mbps
VI = VCC or 0 V, no load
ISO7221x
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ICC1
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
VI = VCC or 0 V, no load
5
11
4
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ISO7220x
2
25 Mbps
Quiescent
1 Mbps
6
12
18
9.5
19
11
20
12
mA
8
ISO7221x
4.3
9
ISO7220A, ISO7220B
ISO7221A, ISO7221B
ISO7220C, ISO7220M
ISO7221C, ISO7221M
ICC2
5
10
6
25 Mbps
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.4
VCC – 0.1
3
VOH
High-level output voltage
Low-level output voltage
3.3
0.2
0
V
0.4
0.1
VOL
VI(HYS)
IIH
Input voltage hysteresis
150
mV
High-level input current
10
IN from 0 V or VCC
µA
IIL
Low-level input current
–10
15
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
VI = VCC or 0 V, See Figure 3
40
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
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SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tpLH
tpHL
,
Propagation delay
290
400
1
485
18
78
4
ISO722xA
ISO722xB
ISO722xC
ISO722xM
(1)
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
|
|
|
|
,
Propagation delay
46
26
8
62
1
tpHL
PWD
tpLH
(1)
(1)
(1)
Pulse-width distortion |tpHL – tpLH
Propagation delay
See Figure 1
,
40
1
52
3
tpHL
PWD
tpLH
Pulse-width distortion |tpHL – tpLH
Propagation delay
,
16
0.5
25
tpHL
ns
PWD
Pulse-width distortion |tpHL – tpLH
1
190
17
10
5
ISO722xA
ISO722xB
ISO722xC
ISO722xM
ISO722xA
ISO722xB
ISO722xC/M
tsk(pp)
Part-to-part skew(2)
3
0.6
0.2
2
15
3
(3)
tsk(o)
Channel-to-channel output skew
1
tr
Output signal rise time
Output signal fall time
See Figure 1
See Figure 2
tf
2
tfs
Failsafe output delay time from input power loss
3
µs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 4,
Figure 17
1
2
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO722xM
ns
150 Mbps unrestricted bit run length data
input, both channels, See Figure 4
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
CC
V
1/2
I
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
V
I
V
1
CC
V
1
CC
V
I
0 V
or
2.7 V
OUT
IN
V
0 V
V
O
V
1
t
CC
fs
OH
C
V
L
FAILSAFE HIGH
50%
O
NOTE A
V
OL
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE A
V
or V
OL
OH
GND1
GND2
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
V
1
CC
DUT
Tektronix
HFS9009
IN
0 V
V
Tektronix
OUT
784D
PATTERN
/2
GENERATOR
CC
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps.
Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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DEVICE INFORMATION
IEC PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
L(I01) Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
4.8
mm
SOIC-8
L(I02) Minimum external tracking
(Creepage)
Shortest terminal-to-terminal distance across the
package surface
4.3
≥175
0.008
mm
V
CTI
Tracking resistance (Comparative
Tracking Index)
DIN IEC 60112 / VDE 0303 Part 1
Distance through the insulation
Minimum Internal Gap (Internal
Clearance)
mm
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V, 100°C ≤ TA ≤ max
VI = 0.4 sin (4E6πt)
>1011
Ω
CIO
CI
Barrier capacitance Input to output
Input capacitance to ground
1
1
pF
pF
VI = 0.4 sin (4E6πt)
NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation
standards of an application. Care should be taken to maintain the creepage and clearance distance of a board
design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques
shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Material group
SPECIFICATION
Basic isolation group
IIIa
I-IV
I-III
I-II
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Rated mains voltage ≤400 VRMS
Installation classification
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
V
VIORM Maximum working insulation
voltage
560
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s, Partial discharge <5 pC
VPR
Input to output test voltage
1050
VIOTM Transient overvoltage
t = 60 s
4000
>109
2
RS
Insulation resistance
Pollution degree
VIO = 500 V at TS
Ω
(1) Climatic Classification 40/125/21
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DEVICE I/O SCHEMATICS
Input
Output
CC2
V
V
V
V
CC1
CC1
CC1
750 kW
8 W
500 W
IN
OUT
13 W
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
124
190
150
UNIT
θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
Safety input, output, or
supply current
IS
SOIC-8
mA
TS
Maximum case temperature SOIC-8
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
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SOIC-8 PACKAGE THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance(1)
High-K Thermal Resistance
MIN
TYP
212
122
37
MAX
UNIT
°C/W
mW
θJA
Junction-to-air
θJB
θJC
PD
Junction-to-Board Thermal Resistance
Junction-to-Case Thermal Resistance
69.1
Device Power Dissipation ISO722xM VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
390
Input a 150 Mbps 50% duty cycle square wave
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
250
225
V
at 3.6 V
CC1,2
200
175
150
125
100
75
V
at 5.5 V
CC1,2
50
25
0
0
50
100
- Case Temperature - °C
150
200
T
C
Figure 5. SOIC-8 θJC THERMAL DERATING CURVE per IEC 60747-5-2
DEVICE FUNCTION TABLE
Table 1. ISO7220x or ISO7221x(1)
INPUT SIDE VCC
OUTPUT SIDE VCC
INPUT IN
OUTPUT OUT
H
L
H
L
PU
PD
PU
PU
Open
X
H
H
(1) PU = Powered Up(Vcc ≥ 3.0V); PD = Powered Down (Vcc ≤ 2.5V); X = Irrelevant; H = High Level;
L = Low Level
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TYPICAL CHARACTERISTIC CURVES
3.3-V RMS SUPPLY CURRENT
vs
SIGNALING RATE (Mbps)
5-V RMS SUPPLY CURRENT
vs
SIGNALING RATE (Mbps)
20
18
16
14
30
28
26
24
22
T
= 25°C,
T
= 25°C,
A
15 pF Load
A
15 pF Load
ISO7220x I
CC2
ISO7220x I
CC2
20
18
16
ISO7221x I
CC1&2
12
10
14
12
10
ISO7221x I
CC1&2
8
6
ISO7220x I
CC1
8
6
4
4
2
0
ISO7220x I
CC1
2
0
0
25
50
75
100
0
25
50
75
100
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 6.
Figure 7.
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, ISO722xA
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, ISO722xB
450
70
65
60
T
= 25°C,
15 pF Load
A
15 pF Load
440
430
420
410
400
390
380
370
360
350
t
& t
PHL
PLH
V
V
= 3.3 V
CC
VCC = 3.3 V
tpLH & tpHL
VCC = 5 V
tpLH & tpHL
= 5 V
t
& t
55
50
45
CC
PLH PHL
-40
-15
10
35
60
85
110 125
-40
25
Temperature - °C
125
Temperature - °C
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTIC CURVES (continued)
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, ISO722xC
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, ISO722xM
30
25
20
15
10
5
20
15
10
5
VCC = 3.3 V
VCC = 3.3 V
tpLH & tpHL
tpLH & tpHL
VCC = 5 V
VCC = 5 V
tpLH & tpHL
tpLH & tpHL
15 pF Load
15 pF Load
0
0
-40
-15
10
35
60
85
110
-40
-15
10
35
60
85
110
125
125
Temperature - °C
Temperature - °C
Figure 10.
Figure 11.
ISO722xA, ISO722xB AND ISO722xC INPUT VOLTAGE
LOW-TO-HIGH SWITCHING THRESHOLD
vs
ISO722xM INPUT VOLTAGE HIGH-TO-LOW
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.5
2.4
2.3
2.2
2.1
2
1.4
5-V Vth+
5-V Vth+
5-V Vth-
1.35
1.3
1.25
1.2
3.3-V Vth+
15 pF Load
15 pF Load
1.9
1.8
1.7
1.6
1.5
1.4
1.15
1.1
5-V Vth-
3.3-V Vth+
3.3-V Vth-
1.05
3.3-V Vth-
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature - °C
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature - °C
Figure 12.
Figure 13.
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ISO7221A, ISO7221B, ISO7221C, ISO7221M
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TYPICAL CHARACTERISTIC CURVES (continued)
VCC FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
2.92
2.9
-80
-70
-60
-50
-40
-30
-20
-10
0
15 pF Load
VCC = 3.3 V or 5 V
15 pF Load
TA = 25°C
VFS
2.88
2.86
2.84
2.82
2.8
VCC = 5 V
VCC = 3.3 V
VFS-
2.78
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
2
4
6
Temperature - °C
VOUT - V
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
ISO722xM JITTER
vs
SIGNALING RATE
70
60
50
40
30
20
10
0
2000
1800
1600
1400
1200
1000
800
15 pF Load
TA = 25°C
15 pF Load
TA = 25°C
VCC = 5 V
VCC = 3.3 V
VCC1 = VCC2 = 5 V
600
VCC1 = VCC2 = 3.3 V
400
200
0
0
1
2
3
4
5
0
50
100
150
200
VOUT - V
Figure 16.
Signaling Rate - Mbps
Figure 17.
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ISO7220A, ISO7220B, ISO7220C, ISO7220M
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APPLICATION INFORMATION
Typical Applications
VCC 1
VCC2
20 mm
max .
from
20 mm
max .
from
m
0.1 F
m
0.1 F
Vcc 1
Vcc 2
1
2
8
7
6
5
INA
INB
OUTA
OUTB
OUTPUT
OUTPUT
INPUT
INPUT
3
4
ISO7220
GND 1
GND 2
Figure 18. Typical ISO7220 Application Circuit
VCC 1
VCC2
20 mm
max .
from
20 mm
max .
from
m
0.1 F
m
0.1 F
Vcc 1
Vcc 2
1
2
8
7
OUTA
INB
INA
OUTPUT
INPUT
INPUT
OUTB
OUTPUT
3
4
6
5
ISO 7221
GND 1
GND 2
Figure 19. Typical ISO7221 Application Circuit
100
VIORM at 560 V
28
10
0
250
500
750
1000
120
880
WORKING VOLTAGE (VIORM) -- V
Figure 20. Time Dependent Dielectric Breakdown Test Results
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ISOLATION GLOSSARY
Creepage Distance — The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance — The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to Output Barrier Capacitance — The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to Output Barrier Resistance — The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit — An internal circuit directly connected to an external supply mains or other equivalent source
which supplies the primary circuit electric power.
Secondary Circuit — A circuit with no direct connection to primary power, and derives its power from a separate
isolated source.
Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials which is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher
CTI value of the insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
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Insulation:
Operational insulation — Insulation needed for the correct operation of the equipment.
Basic insulation — Insulation to provide basic protection against electric shock.
Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation — Insulation comprising both basic and supplementary insulation.
Reinforced insulation — A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category — This section is directed at insulation co-ordination by identifying the transient
overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664.
I: Signal Level — Special equipment or parts of equipment.
II: Local Level — Portable equipment etc.
III: Distribution Level — Fixed installation
IV: Primary Supply Level — Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
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PACKAGE OPTION ADDENDUM
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1-May-2008
PACKAGING INFORMATION
Orderable Device
ISO7220AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7220ADG4
ISO7220ADR
ISO7220ADRG4
ISO7220BD
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7220BDR
ISO7220CD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7220CDG4
ISO7220CDR
ISO7220CDRG4
ISO7220MD
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7220MDG4
ISO7220MDR
ISO7220MDRG4
ISO7221AD
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7221ADG4
ISO7221ADR
ISO7221ADRG4
ISO7221BD
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7221BDR
ISO7221CD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7221CDG4
ISO7221CDR
ISO7221CDRG4
ISO7221MD
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2008
Orderable Device
ISO7221MDG4
ISO7221MDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ISO7221MDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ISO7220ADR
ISO7220BDR
ISO7220CDR
ISO7220MDR
ISO7221ADR
ISO7221BDR
ISO7221CDR
ISO7221MDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
13.0
12.4
12.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7220ADR
ISO7220BDR
ISO7220CDR
ISO7220MDR
ISO7221ADR
ISO7221BDR
ISO7221CDR
ISO7221MDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
358.0
358.0
358.0
358.0
358.0
358.0
358.0
358.0
335.0
335.0
335.0
335.0
335.0
335.0
335.0
335.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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