ISO722QDRQ1 [TI]
具有使能功能的汽车类单通道 100Mbps 数字隔离器 | D | 8 | -40 to 125;
| 型号： | ISO722QDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类单通道 100Mbps 数字隔离器 | D | 8 | -40 to 125 |
| 文件： | 总28页 (文件大小：1115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO721-Q1, ISO722-Q1
www.ti.com
SLLS918C –JULY 2008–REVISED JUNE 2013
3.3-V AND/OR 5-V HIGH-SPEED DIGITAL ISOLATORS
Check for Samples: ISO721-Q1, ISO722-Q1
1
FEATURES
•
Qualified for Automotive Applications
•
•
•
•
•
Low-Power Sleep Mode
•
AEC-Q100 Qualified With the Following
Results:
High Electromagnetic Immunity
Low Input Current Requirement
Failsafe Output
–
Device Temperature Grade 1: –40ºC to
125ºC Ambient Operating Temperature
Range
Drop-In Replacement for Most Optical and
Magnetic Isolators
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C5
•
•
4000-V(peak) Isolation
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1
–
50-kV/s Transient Immunity (Typ)
Signaling Rate 0 Mbps to 100 Mbps
–
–
Low Propagation Delay
Low Pulse Skew
(Pulse-Width Distortion)
DESCRIPTION
The ISO72x-Q1 is a digital isolator with a logic input and output buffer separated by a silicon oxide (SiO2)
insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in conjunction with isolated
power supplies, this device prevents noise currents on a data bus or other circuits from entering the local ground
and interfering with or damaging sensitive circuitry.
The capacitive isolation barrier conditions, translates to a balanced signal, then differentiates a binary input
signal. Across the isolation barrier, a differential comparator receives the logic-transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse sent across the barrier ensures the
proper dc level of the output. On failure to receive this dc refresh pulse for more than 4 μs, the response of the
device is as if the input is or not actively driven, and the failsafe circuit drives the output to a logic-high state.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO721-Q1, ISO722-Q1
SLLS918C –JULY 2008–REVISED JUNE 2013
www.ti.com
FUNCTION DIAGRAM
Isolation Barrier
DC Channel
+
_
Filter
Pulse Width
Demodulation
OSC
+
PWM
V
ref
_
+
Carrier Detect
POR
POR
BIAS
+
_
Data MUX
AC Detect
3-State
Input
+
Filter
IN
V
ref
_
+
OUT
Output Buffer
AC Channel
2
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Product Folder Links: ISO721-Q1 ISO722-Q1
ISO721-Q1, ISO722-Q1
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SLLS918C –JULY 2008–REVISED JUNE 2013
DESCRIPTION (CONTINUED)
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching
and allows fast transient voltage changes between the input and output grounds without corrupting the output.
The small capacitance and resulting time constant provide for fast operation with signaling rates(1) from 0 Mbps
(dc) to 100 Mbps.
The device requires two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply, and all outputs are 4-mA CMOS. The device has a TTL input threshold and a noise
filter at the input that prevents transient pulses of up to 2 ns in duration from being passed to the output of the
device.
The ISO722-Q1 device includes an active-low output enable that, when driven to a high logic level, places the
output in a high-impedance state and turns off internal bias circuitry to conserve power.
The ISO72x-Q1 is characterized for operation over the ambient temperature range of –40°C to 125°C.
(1) The signaling rate of a line is the number of voltage transitions that occur per second, expressed in the
units bps (bits per second).
ISO721-Q1
D PACKAGE
(TOP VIEW)
VCC1
VCC2
8
7
6
5
1
2
3
4
IN
VCC1
GND2
OUT
GND1
GND2
ISO722-Q1
D PACKAGE
(TOP VIEW)
VCC1
VCC2
8
7
6
5
1
2
3
4
IN
VCC1
EN
OUT
GND2
GND1
ORDERING AND PACKAGING INFORMATION
For the most-current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Acceptance Notice: CA-5A
Recognized under 1577
Certified according to IEC 60747-5-2
File Number: 40016131
Component Recognition Program(1)
File Number: 1698195
File Number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
Copyright © 2008–2013, Texas Instruments Incorporated
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ISO721-Q1, ISO722-Q1
SLLS918C –JULY 2008–REVISED JUNE 2013
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ABSOLUTE MAXIMUM RATINGS(1)
VCC
Supply voltage(2), VCC1, VCC2
Voltage at IN or OUT terminal
Output current
–0.5 V to 6 V
VI
–0.5 V to 6 V
±15 mA
170°C
IO
TJ
Maximum virtual-junction temperature
Human-Body Model(3)
Charged-Device Model(4)
±2 kV
ESD
Electrostatic discharge rating
±1 kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
(3) JEDEC Standard 22, Test Method A114-C.01
(4) JEDEC Standard 22, Test Method C101
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
VCC
IOH
IOL
tui
Supply voltage(1), VCC1, VCC2
High-level output current
3
5.5
4
V
mA
mA
ns
V
Low-level output current
–4
10
2
Input pulse duration
VIH
VIL
TA
TJ
High-level input voltage (IN)
Low-level input voltage (IN)
Operating free-air temperature
Operating virtual-junction temperature
VCC
0.8
0
V
–40
125
150
°C
°C
See the Thermal Characteristics table
H
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9 certification
1000 A/m
(1) For 5-V operation, VCC1 or VCC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 specification is from 3 V to 3.6 V.
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
UNIT
VIORM
Maximum working insulation voltage
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
896
V
V
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
VPR
Input-to-output test voltage
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
VIOTM
RS
Transient overvoltage
Insulation resistance
Pollution degree
t = 60 s
4000
>109
2
V
VIO = 500 V at TS
Ω
(1) Climatic Classification 40/125/21
4
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ISO721-Q1, ISO722-Q1
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SLLS918C –JULY 2008–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Quiescent
25 Mbps
0.5
2
1
4
ICC1
VCC1 supply current
VI = VCC or 0 V, No load
mA
ISO722-Q1 Sleep
Mode
EN at VCC
200
μA
VI = VCC or 0 V, No load
ICC2
VCC2 supply current
EN at 0 V or
ISO721-Q1
Quiescent
25 Mbps
8
10
12
14
mA
V
VI = VCC or 0 V, No load
IOH = -4 mA, See Figure 1
VCC
0.8
–
4.6
VOH
High-level output voltage
VCC
0.1
–
IOH = –20 μA, See Figure 1
5
IOL = 4 mA, See Figure 1
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
IOL = 20 μA, See Figure 1
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
150
mV
μA
IN at 2 V
10
1
IIL
IN at 0.8 V
–10
15
High-impedance
output current
IOZ
ISO722-Q1
EN, IN at VCC
μA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
50
kV/μs
(1) For 5-V operation, VCC1 or VCC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 specification is from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN
TYP MAX UNIT
tPLH
tPHL
tsk(p)
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
17
17
24 ns
24 ns
See Figure 1
See Figure 1
Pulse skew |tPHL – tPLH
|
0.5
2
ns
tsk(pp)
Part-to-part skew
0
3
ns
(1)
tr
tf
Output-signal rise time
Output-signal fall time
See Figure 1
See Figure 1
1
1
ns
ns
Sleep-mode propagation delay,
high-level-to-high-impedance output
tpHZ
tpZH
tpLZ
6
3.5
5.5
4
8
4
8
15 ns
μs
15 ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
8
ISO722-Q1
Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
5
3
2
8
μs
μs
Failsafe output delay time from input power loss
100-Mbps NRZ data input,
See Figure 6
tjit(PP)
Peak-to-peak eye-pattern jitter
ns
100-Mbps unrestricted bit run
length data input, See Figure 6
3
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISO721-Q1, ISO722-Q1
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ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Quiescent
25 Mbps
0.5
2
1
4
ICC1
VCC1 supply current
VI = VCC or 0 V, No load
mA
μA
ISO722-Q1
Quiescent
25 Mbps
EN at VCC
150
6.5
7.5
ICC2
VCC2 supply current
VI = VCC or 0 V, No load
4
5
EN at 0 V or
ISO721-Q1
mA
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
VCC – 0.4
VCC – 0.1
3
VOH
High-level output voltage
Low-level output voltage
V
V
3.3
0.2
0
0.4
0.1
VOL
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
150
mV
μA
μA
IN at 2 V
10
1
IIL
IN at 0.8 V
–10
15
High-impedance output
current
IOZ
ISO722-Q1
EN, IN at VCC
μA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/μs
(1) For 5-V operation, VCC1 or VCC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 specification is from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN TYP MAX UNIT
tPLH
tPHL
tsk(p)
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
19
19
30 ns
30 ns
See Figure 1
See Figure 1
Pulse skew |tPHL – tPLH
|
0.5
3
ns
tsk(pp)
Part-to-part skew
0
5
ns
(1)
tr
tf
Output signal rise time
Output signal fall time
See Figure 1
See Figure 1
2
2
ns
ns
Sleep-mode propagation delay,
high-level-to-high-impedance output
tpHZ
tpZH
tpLZ
7
5
7
5
13
6
25 ns
μs
25 ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
8
ISO722-Q1
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
6
3
2
8
μs
μs
Failsafe output delay time from input power loss
100-Mbps NRZ data input,
See Figure 6
tjit(PP)
Peak-to-peak eye-pattern jitter
ns
100-Mbps unrestricted bit run length
data input, See Figure 6
3
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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ISO721-Q1, ISO722-Q1
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SLLS918C –JULY 2008–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Quiescent
25 Mbps
0.3
1
0.5
2
ICC1
VCC1 supply current
VI = VCC or 0 V, No load
mA
ISO722-Q1
Sleep Mode
EN at VCC
200
μA
VI = VCC or 0 V, No load
ICC2
VCC2 supply current
EN at 0 V or ISO721-
Q1
Quiescent
25 Mbps
8
12
14
mA
VI = VCC or 0 V, No load
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
10
4.6
5
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
V
V
0.2
0
0.4
0.1
VOL
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
150
mV
μA
μA
IN at 2 V
10
1
IIL
IN at 0.8 V
–10
15
High-impedance output
current
IOZ
ISO722-Q1
EN, IN at VCC
μA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/μs
(1) For 5-V operation, VCC1 or VCC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 specification is from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
TEST CONDITIONS
See Figure 1
MIN TYP MAX UNIT
tPLH
tPHL
tsk(p)
17
17
30 ns
30 ns
See Figure 1
See Figure 1
Pulse skew |tPHL – tPLH
|
0.5
3
ns
tsk(pp)
Part-to-part skew
0
5
ns
(1)
tr
tf
Output signal rise time
Output signal fall time
See Figure 1
See Figure 1
2
2
ns
ns
Sleep-mode propagation delay,
high-level-to-high-impedance output
tpHZ
tpZH
tpLZ
7
4.5
7
9
5
9
15 ns
μs
15 ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
8
ISO722-Q1
Sleep-mode propagation delay,
low-level-to-high-impedance output
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
4.5
5
3
2
8
μs
μs
Failsafe output delay time from input power loss
100-Mbps NRZ data input,
See Figure 6
tjit(PP)
Peak-to-peak eye-pattern jitter
ns
100-Mbps unrestricted bit
run length data input, See
Figure 6
3
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Quiescent
25 Mbps
0.3
1
0.5
2
ICC1
VCC1 supply current
VI = VCC or 0 V, No load
mA
ISO722-Q1
Sleep Mode
EN at VCC
150
μA
VI = VCC or 0 V, No load
ICC2
VCC2 supply current
EN at 0 V or ISO721-
Q1
Quiescent
25 Mbps
4
6.5
7.5
mA
VI = VCC or 0 V, No load
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
5
3
VCC – 0.4
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
V
V
3.3
0.2
0
0.4
0.1
VOL
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
150
mV
μA
μA
IN at 2 V
10
1
IIL
IN at 0.8 V
–10
15
High-impedance output
current
IOZ
ISO722-Q1
EN, IN at VCC
μA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/μs
(1) For 5-V operation, VCC1 or VCC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 or VCC2 specification is from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN TYP MAX UNIT
tPLH
tPHL
tsk(p)
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
20
20
34 ns
34 ns
See Figure 1
See Figure 1
Pulse skew |tPHL – tPLH
|
0.5
3
ns
tsk(pp)
Part-to-part skew
0
5
ns
(1)
tr
tf
Output signal rise time
Output signal fall time
See Figure 1
See Figure 1
2
2
ns
ns
Sleep-mode propagation delay,
high-level-to-high-impedance output
tpHZ
tpZH
tpLZ
7
5
7
5
13
6
25 ns
μs
25 ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
8
ISO722-Q1
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
6
3
2
8
μs
μs
Failsafe output delay time from input power loss
100-Mbps NRZ data input,
See Figure 6
tjit(PP)
Peak-to-peak eye-pattern jitter
ns
100-Mbps unrestricted bit run
length data input, See
Figure 6
3
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
8
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SLLS918C –JULY 2008–REVISED JUNE 2013
PARAMETER MEASUREMENT INFORMATION
V
CC1
V
V
V
/2
V
/2
CC1
I
I
OUT
CC1
O
IN
0 V
t
t
PHL
V
PLH
Input
Generator
(see Note A)
V
O
OH
OL
C
90%
10%
V
L
I
50 W
50%
50%
O
(see Note B)
V
t
t
f
r
A. A generator having the following characteristics supplies the input pulse:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
V
O
V
CC2
IN
V
OUT
C
I
V
/2
3 V
V
/2
CC2
CC2
0 V
V
EN
t
R
= 1 kW ±1 %
PZH
L
L
OH
NOTE B
+
50%
Input
Generator
NOTE A
0.5 V
V
O
V
I
50 W
0 V
t
PHZ
-
Figure 2. ISO722-Q1 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
V
CC2
R
= 1 kW ±1%
L
V
CC2
0 V
V
I
V
/2
V
/2
CC2
CC2
IN
OUT
V
0 V
O
t
t
PZL
PLZ
V
CC2
EN
0.5 V
V
C
L
O
50%
NOTE B
+
V
Input
Generator
NOTE A
OL
50 W
V
I
-
Figure 3. ISO722-Q1 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
NOTE
A: A generator having the following characteristics Supplies the input pulse:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B: CL = 15 pF ± 20% and includes instrumentation and fixture capacitance.
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PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
CC1
V
CC1
V
2.7 V
I
IN
0 V
V
OUT
V
0 V
t
fs
O
OH
50%
V
O
C
L
V
OL
15 pF
±20%
NOTE: VI transition time is 100 ns.
Figure 4. Failsafe Delay-Time Test Circuit and Voltage Waveforms
V
V
CC2
CC1
OUT
C
IN
V
L
CC
V
15 pF
±20%
O
or
0 V
C = 0.1 mF,
I
GND1
GND2
±1%
V
CM
NOTE: Pass or fail criterion is no change in VO.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
Tektronix
HFS9009
Tektronix
784D
PATTERN
GENERATOR
V
CC1
In p u t
0 V
O u tp u t
V
CC2/2
J itte r
NOTE: Bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive
1s or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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DEVICE INFORMATION
PACKAGE CHARACTERISTICS
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
(1)
L(101)
L(102)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4.8
mm
Shortest terminal-to-terminal distance across the
package surface
Minimum external tracking (creepage)
4.3
≥ 175
0.008
mm
V
Tracking resistance (comparative
tracking index)
CTI
DIN IEC 60112/VDE 0303 Part 1
Distance through insulation
Minimum internal gap
(internal clearance)
mm
Input to output, VIO = 500 V, all pins on each side of
the barrier tied together creating a two-terminal
device, TA < 100°C
>1012
>1011
Ω
Ω
RIO
Isolation resistance
Input-to-output, VIO = 500 V,
100°C ≤ TA< TA max.
CIO
CI
Barrier capacitance, input to output
Input capacitance to ground
VI = 0.4 sin (4E6πt)
VI = 0.4 sin (4E6πt)
1
1
pF
pF
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to
maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit
board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Use techniques such as inserting grooves and/or ribs on a printed circuit board to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
TEST CONDITIONS
SPECIFICATION
Material group
IIIa
I-IV
I-III
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Installation classification
DEVICE I/O SCHEMATIC
Figure 7. Equivalent Input and Output Schematic Diagrams
Input
Output
V
CC2
V
V
CC1
CC1
V
CC1
8 W
1 MW
OUT
500 W
IN
13 W
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IEC SAFETY LIMITING VALUES
Safety limiting is designed to prevent potential damage to the isolation barrier on failure of input or output
circuitry. A failure of the IO can allow low resistance to ground or the supply, and without current limiting,
dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary
system failures.
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
100
mA
153
IS
Safety input, output, or supply current
Maximum case temperature
TS
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board
for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
Table 2. THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
263
125
44
MAX UNIT
Low-K(1)
High-K(1)
θJA
Junction-to-air thermal resistance
°C/W
θJB
θJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
°C/W
°C/W
75
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 100-Mbps 50% duty cycle square wave
PD
Device power dissipation
159 mW
(1) Tested in accordance with the low-K or high-K thermal metric definition of EIA/JESD51-3 for leaded surface-mount packages.
200
175
V
, V
= 3.6 V
CC1 CC2
150
125
100
75
50
25
0
V
, V
= 5.5 V
CC1 CC2
0
50
100
Case Temperature
150
200
−
oC
Figure 8. θJC Thermal Derating Curve Per IEC 60747-5-2
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Table 3. FUNCTION TABLE(1)
INPUT
(IN)
OUTPUT
(OUT)
VCC1
VCC2
H
H
L
PU
PD
PU
PU
L
Open
X
H
H
(1) PU = powered up (VCC ≥ 3 V), PD = powered down (VCC ≤ 2.5 V), X = irrelevant, H = high level,
L = low level
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TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT versus
RMS SUPPLY CURRENT versus
SIGNALING RATE
SIGNALING RATE
10
9
15
14
13
12
V
V
T
= 3.3 V,
= 3.3 V,
= 25oC,
V
V
T
= 5 V,
CC1
CC2
CC1
CC2
= 5 V,
= 25oC,
8
7
6
5
A
A
I
CC2
C
= 15 pF
C
= 15 pF
L
L
11
10
9
8
7
6
I
CC2
I
4
3
2
CC1
5
4
3
2
1
0
I
CC1
1
0
0
25
50
75
100
0
25
50
75
100
Signaling Rate (Mbps)
Figure 9.
Signaling Rate (Mbps)
Figure 10.
PROPAGATION DELAY versus
FREE-AIR TEMPERATURE
PROPAGATION DELAY versus
FREE-AIR TEMPERATURE
30
25
20
18
t
PLH
t
PLH
16
t
PHL
t
PHL
14
12
10
20
15
8
6
4
10
V
V
= 3.3 V,
CC1
CC2
V
V
= 5 V,
= 5 V,
CC1
CC2
= 3.3 V,
= 15 pF,
5
0
C
L
C
= 15 pF,
L
Air Flow at 7 cf/m
2
0
Air Flow at 7 cf/m
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
T
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
A
A
Figure 11.
Figure 12.
INPUT THRESHOLD VOLTAGE versus
FREE-AIR TEMPERATURE
VCC1 FAILSAFE THRESHOLD VOLTAGE versus
FREE-AIR TEMPERATURE
1.4
1.35
1.3
2.92
2.9
5-V (V
)
IT+
3.3-V (V
)
V
2.88
2.86
IT+
fs+
1.25
1.2
V
= 5 V or 3.3 V,
= 15 pF,
CC
C
L
Air Flow at 7 cf/m
Air Flow at 7 cf/m
2.84
2.82
1.15
1.1
1.05
1
5-V (V
)
IT-
V
fs-
2.8
3.3-V (V
)
IT-
2.78
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
T
A
A
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT CURRENT versus
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT versus
HIGH-LEVEL OUTPUT VOLTAGE
-80
-70
-60
-50
-40
-30
-20
70
60
T
= 25oC
= 25oC
A
T
A
V
= 5 V
CC
V
= 5 V
CC
50
40
30
20
V
= 3.3 V
V
= 3.3 V
CC
CC
10
0
-10
0
0
1
2
3
4
5
6
0
1
2
3
4
5
V
− High-Level Output Voltage − V
V
− Low-Level Output Voltage − V
OL
OH
Figure 15.
Figure 16.
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APPLICATION INFORMATION
MANUFACTURER CROSS-REFERENCE DATA
The ISO72x-Q1 isolator has the same functional pinout as most other vendors, and it is often a pin-for-pin drop-
in replacement. The notable differences in the product are propagation delay, signaling rate, power consumption,
and transient protection rating. Use(1) as a guide for replacing other isolators with the ISO72x-Q1 single-channel
isolators.
HCPL-xxxx
IL710
ISO722
ISO721
ADuM1100
V
V
V
V
V
V
V
DD2
1
2
3
4
1
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
DD1
V
V
V
V
V
V
CC2
DD1
DD2
DD2
DD1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC1
CC2
CC1
V
I
V
V
2
3
4
NC
GND2
V
I
V
I
OE
GND2
OUT
GND2
OUT
IN
IN
V
O
V
O
NC
DD1
O
CC1
CC1
*
GND1
GND2
GND1
GND1
GND2
GND2
GND1
GND2
GND1
GND2
Figure 17. Pinout Cross-Reference
Table 4. Competitive Cross-Reference
PIN 7
ISOLATOR
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 8
ISO721
ISO722
ISO721(1) (2)
VCC1
VDD1
IN
VI
VCC1
VDD1
GND1
GND1
GND2
GND2
OUT
VO
GND2
EN
VCC2
VDD2
ADuM1100(1) (2)
HCPL-xxxx
IL710
GND2
NC(4)
V OE
Leave
VDD1
VDD1
VI
VI
GND1
GND1
GND2
GND2
VO
VO
VDD2
VDD2
open(3)
NC(5)
(1) An HCPL device pin 7 must be floating (open) or grounded to use an ISO722 device as a drop-in replacement. Placing pin 7 of the
ISO722 device in a high logic state disables the output of the device.
(1) The ISO721 pin 1 and pin 3 connect together internally. One may use either or both as VCC1
.
(2) The ISO721 pin 5 and pin 7 connect together internally. One may use either or both as GND2.
(3) Pin 3 of the HCPL devices must be open. This is not a problem when substituting an ISO721, because the extra VCC1 on pin 3 may be
open-circuit as well.
(4) An HCPL device pin 7 must be floating (open) or grounded to use an ISO722 device as a drop-in replacement. Placing pin 7 of the
ISO722 device in a high logic state disables the output of the device.
(5) Pin 3 of the IL710 must not tie to ground on the circuit board, because this shorts the ISO721 VCC1 to ground. The IL710 pin 3 may only
tie to VCC or be open to drop in an ISO721.
20 mm (max)
from VCC1
20 mm (max)
from VCC2
VCC1
VCC2
0.1 µF
0.1 µF
ISO721
1
2
3
4
8
7
6
5
Input
IN
Output
GND2
OUT
GND1
Figure 18. Basic Application Circuit
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ISOLATION GLOSSARY
Creepage Distance—The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest-distance path is around the end of the package body.
Clearance—The shortest distance between two conductive input to output leads measured through air (line of
sight)
Input-to-Output Barrier Capacitance—The total capacitance between all input terminals connected together,
and all output terminals connected together
Input-to-Output Barrier Resistance—The total resistance between all input terminals connected together, and
all output terminals connected together
Primary Circuit—An internal circuit directly connected to an external supply main or other equivalent source
which supplies the primary-circuit electric power
Secondary Circuit—A circuit with no direct connection to primary power, and deriving its power from a separate
isolated source
Comparative Tracking Index (CTI)—CTI is an index used for electrical insulating materials and defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, generating an electric spark.
These sparks often cause carbonization on insulation material and lead to a carbon track between points of
different potential. The name of this process is tracking.
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Insulation
Operational insulation—Insulation needed for the correct operation of the equipment
Basic insulation—Insulation to provide basic protection against electric shock
Supplementary insulation-—Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation
Double insulation—Insulation comprising both basic and supplementary insulation
Reinforced insulation—A single insulation system that provides a degree of protection against electric shock
equivalent to double insulation
Pollution Degree
Pollution Degree 1—No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2—Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3—Conductive pollution occurs or dry nonconductive pollution occurs that becomes conductive
due to condensation, which is to be expected.
Pollution Degree 4–Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category
Overvoltage Category—This section addresses insulation coordination by identifying the transient overvoltages
that may occur and by assigning four different levels as indicated in IEC 60664.
I: Signal Level-—Special equipment or parts of equipment
II: Local Level—Portable equipment, etc.
III: Distribution Level-—Fixed installation
IV: Primary Supply Level-—Overhead lines, cable systems
Each successive category should be subject to smaller transients than any higher-numbered category following
it.
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REVISION HISTORY
Changes from Revision B (June 2013) to Revision C
Page
•
Changed temperature grade from 3 to 1 .............................................................................................................................. 1
Changes from Revision A (September 2011) to Revision B
Page
•
•
•
•
Added AEC-Q100 qualifications ........................................................................................................................................... 1
Changed signaling-rate limit to 100 Mbps ............................................................................................................................ 1
Deleted Ordering Information table ....................................................................................................................................... 3
Changed last sentence in the Installation Category section ............................................................................................... 19
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO721QDRQ1
ISO722QDRQ1
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
IS721Q
IS722Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
OTHER QUALIFIED VERSIONS OF ISO721-Q1, ISO722-Q1 :
Catalog: ISO721, ISO722
•
Military: ISO721M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO721QDRQ1
ISO722QDRQ1
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO721QDRQ1
ISO722QDRQ1
SOIC
SOIC
D
D
8
8
2500
2500
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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