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ISO7240ADWG4 [TI]

QUAD DIGITAL ISOLATORS; 4通道数字隔离器
ISO7240ADWG4
型号： ISO7240ADWG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

QUAD DIGITAL ISOLATORS
4通道数字隔离器

驱动程序和接口 接口集成电路 光电二极管
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ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
QUAD DIGITAL ISOLATORS  
1
FEATURES  
•
1, 25, and 150-Mbps Signaling Rate Options  
•
•
High Electromagnetic Immunity  
(see application report SLLA181)  
–
–
–
Low Channel-to-Channel Output Skew;  
1 ns Max  
–40°C to 125°C Operating Range  
Low Pulse-Width Distortion (PWD);  
2 ns Max  
APPLICATIONS  
•
•
•
•
Industrial Fieldbus  
Low Jitter Content; 1 ns Typ at 150 Mbps  
Computer Peripheral Interface  
Servo Control Interface  
Data Acquisition  
•
Typical 25-Year Life at Rated Working Voltage  
(see application note SLLA197 and Figure 15)  
•
•
•
•
4000-Vpeak Isolation, 560-Vpeak Working Voltage  
UL 1577 Certified  
4 kV ESD Protection  
Operate With 3.3-V or 5-V Supplies  
DESCRIPTION  
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and  
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide  
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,  
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging  
sensitive circuitry.  
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same  
direction and one channel in opposition. The ISO7242 has two channels in each direction.  
The A and C option devices have TTL input thresholds and a noise-filter at the input that prevents transient  
pulses from being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds  
and do not have the input noise-filter or the additional propagation delay.  
A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh  
pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit  
drives the output to a logic high state. (Contact TI for a logic low failsafe option).  
These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V,  
5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage  
supply level being used.  
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.  
ISO7240  
ISO7241  
ISO7242  
V
V
V
V
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
1
2
3
4
5
6
7
8
16  
15  
1
2
3
4
5
6
7
8
16  
15  
CC1  
CC2  
CC1  
CC2  
CC1  
GND1  
GND2  
GND1  
GND2  
GND1  
GND2  
IN  
A
IN  
B
IN  
C
14  
13  
12  
11  
10  
9
OUT  
A
IN  
IN  
IN  
14  
13  
12  
11  
10  
9
OUT  
A
IN  
IN  
14  
13  
12  
11  
10  
9
OUT  
A
A
B
C
A
OUT  
B
OUT  
B
OUT  
B
B
OUT  
C
OUT  
C
OUT  
OUT  
IN  
C
C
OUT  
D
OUT  
IN  
D
IN  
D
IN  
D
D
D
EN  
EN  
1
EN  
NC  
EN  
2
EN  
2
1
GND1  
GND2  
GND1  
GND2  
GND1  
GND2  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
FUNCTION DIAGRAM  
Galvanic Isolation  
Barrier  
DC Channel  
Filter  
OSC  
+
PWM  
Pulse Width  
Demodulation  
Vref  
Carrier Detect  
EN  
Data MUX  
AC Detect  
Input  
+
Filter  
Vref  
IN  
OUT  
Output Buffer  
AC Channel  
(1)  
Table 1. Device Function Table ISO724x  
INPUT  
(IN)  
OUTPUT ENABLE  
OUTPUT  
(OUT)  
VCC1  
VCC2  
(EN)  
H or Open  
H or Open  
L
H
L
H
L
PU  
PU  
X
Z
H
H
Z
Open  
X
H or Open  
H or Open  
L
PD  
PD  
PU  
PU  
X
(1) PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level  
2
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Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
AVAILABLE OPTIONS  
SIGNALING  
RATE  
INPUT  
THRESHOLD  
CHANNEL  
CONFIGURATION  
MARKED  
AS  
ORDERING  
NUMBER(1)  
PRODUCT  
ISO7240ADW (rail)  
ISO7240ADWR (reel)  
ISO7240CDW (rail)  
ISO7240CDWR (reel)  
ISO7240MDW (rail)  
ISO7240MDWR (reel)  
ISO7241ADW (rail)  
ISO7241ADWR (reel)  
ISO7241CDW (rail)  
ISO7241CDWR (reel)  
ISO7241MDW (rail)  
ISO7241MDWR (reel)  
ISO7242ADW (rail)  
ISO7242ADWR (reel)  
ISO7242CDW (rail)  
ISO7242CDWR (reel)  
ISO7242MDW (rail)  
ISO7242MDWR (reel)  
~1.5 V (TTL)  
(CMOS compatible)  
ISO7240ADW  
1 Mbps  
25 Mbps  
150 Mbps  
1 Mbps  
ISO7240A  
ISO7240C  
ISO7240M  
ISO7241A  
ISO7241C  
ISO7241M  
ISO7242A  
ISO7242C  
ISO7242M  
~1.5 V (TTL)  
(CMOS compatible)  
ISO7240CDW  
ISO7240MDW  
ISO7241ADW  
ISO7241CDW  
ISO7241MDW  
ISO7242ADW  
ISO7242CDW  
ISO7242MDW  
4/0  
Vcc/2 (CMOS)  
~1.5 V (TTL)  
(CMOS compatible)  
~1.5 V (TTL)  
(CMOS compatible)  
25 Mbps  
150 Mbps  
1 Mbps  
3/1  
2/2  
Vcc/2 (CMOS)  
~1.5 V (TTL)  
(CMOS compatible)  
~1.5 V (TTL)  
(CMOS compatible)  
25 Mbps  
150 Mbps  
Vcc/2 (CMOS)  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
Copyright © 2007, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
ABSOLUTE MAXIMUM RATINGS(1)  
VALUE  
UNIT  
VCC Supply voltage(2), VCC1, VCC2  
–0.5 to 6  
–0.5 to 6  
±15  
V
V
VI  
IO  
Voltage at IN, OUT, EN  
Output current  
mA  
Human Body Model  
JEDEC Standard 22, Test Method A114-C.01  
JEDEC Standard 22, Test Method C101  
ANSI/ESDS5.2-1996  
±4  
kV  
Electrostatic Field-Induced-Charged Device  
ESD  
All pins  
±1  
discharge  
Model  
Machine Model  
±200  
170  
V
TJ  
Maximum junction temperature  
°C  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to network ground terminal and are peak voltage values.  
RECOMMENDED OPERATING CONDITIONS  
MIN  
4.5  
TYP  
MAX UNIT  
5.5  
V
VCC Supply voltage, VCC1, VCC2  
3.15  
3.45  
IOH  
IOL  
High-level output current  
Low-level output current  
4
mA  
mA  
µs  
–4  
ISO724xA  
ISO724xC  
ISO724xM  
ISO724xA  
ISO724xC  
ISO724xM  
1
tui  
Input pulse width  
40  
ns  
6.67  
5
1500(1)  
30(1)  
0
1000  
25  
kbps  
Mbps  
1/tui Signaling rate  
0
0
200(1)  
150  
VIH  
VIL  
VIH  
VIL  
TJ  
High-level input voltage (IN)  
0.7 VCC  
VCC  
V
V
ISO724xM  
Low-level input voltage (IN)  
0
2
0
0.3 VCC  
VCC  
High-level input voltage (IN) (EN on all devices)  
Low-level input voltage (IN) (EN on all devices)  
Junction temperature  
V
ISO724xA, ISO724xC  
0.8  
V
150  
°C  
A/m  
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9  
certification  
1000  
(1) Typical value at room temperature and well-regulated power supply.  
4
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Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
ELECTRICAL CHARACTERISTICS  
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
SUPPLY CURRENT  
ISO7240A/C/M  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
mA  
mA  
mA  
mA  
mA  
mA  
Quiescent  
1 Mbps  
1
1
3
3
VI = VCC or 0 V, All channels, no load,  
EN2 at 3 V  
ISO7240A  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
7
10.5  
10  
10  
18  
16  
16  
24  
22  
22  
25  
20  
20  
28  
16  
16  
24  
6.5  
6.5  
12  
10  
10  
15  
15  
16  
17  
13  
13  
18  
10  
10  
15  
VI = VCC or 0 V, All channels, no load,  
EN1 at 3 V, EN2 at 3 V  
ICC1  
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load,  
EN1 at 3 V, EN2 at 3 V  
ISO7242C/M  
ISO7240A/C/M  
ISO7240A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load,  
EN2 at 3 V  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load,  
EN1 at 3 V, EN2 at 3 V  
ICC2  
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load,  
EN1 at 3 V, EN2 at 3 V  
ISO7242C/M  
25 Mbps  
ELECTRICAL CHARACTERISTICS  
IOFF  
Sleep mode output current  
EN at VCC, Single channel  
IOH = –4 mA, See Figure 1  
IOH = –20 µA, See Figure 1  
IOL = 4 mA, See Figure 1  
IOL = 20 µA, See Figure 1  
0
µA  
VCC – 0.8  
VCC – 0.1  
VOH  
High-level output voltage  
V
0.4  
0.1  
VOL  
Low-level output voltage  
V
VI(HYS)  
IIH  
Input voltage hysteresis  
High-level input current  
Low-level input current  
Input capacitance to ground  
150  
mV  
µA  
10  
IN from 0 V to VCC  
IIL  
–10  
25  
CI  
IN at VCC, VI = 0.4 sin (4E6πt)  
2
pF  
CMTI  
Common-mode transient immunity  
VI = VCC or 0 V, See Figure 4  
50  
kV/µs  
Copyright © 2007, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
SWITCHING CHARACTERISTICS  
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
Propagation delay  
Pulse-width distortion(1) |tPHL – tPLH  
TEST CONDITIONS  
MIN TYP  
MAX UNIT  
tPLH, tPHL  
PWD  
40  
95  
ISO724xA  
ISO724xC  
ISO724xM  
|
|
|
10  
ns  
42  
tPLH, tPHL  
PWD  
Propagation delay  
18  
See Figure 1  
Pulse-width distortion(1) |tPHL – tPLH  
Propagation delay  
Pulse-width distortion(1) |tPHL – tPLH  
2.5  
tPLH, tPHL  
PWD  
10  
23  
ns  
2
1
ISO724xA/C  
ISO724xM  
2
1
ns  
(2)  
tsk(o)  
Channel-to-channel output skew  
0
2
tr  
Output signal rise time  
Output signal fall time  
See Figure 1  
ns  
tf  
2
tPHZ  
tPZH  
tPLZ  
tPZL  
tfs  
Propagation delay, high-level-to-high-impedance output  
Propagation delay, high-impedance-to-high-level output  
Propagation delay, low-level-to-high-impedance output  
Propagation delay, high-impedance-to-low-level output  
Failsafe output delay time from input power loss  
15  
15  
15  
15  
12  
20  
20  
20  
20  
See Figure 2  
See Figure 3  
ns  
µs  
150 Mbps NRZ data input, Same  
polarity input on all channels, See  
Figure 5  
tjit(pp)  
Peak-to-peak eye-pattern jitter  
ISO724xM  
1
ns  
(1) Also referred to as pulse skew.  
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the  
same direction while driving identical specified loads.  
6
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Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
ELECTRICAL CHARACTERISTICS  
VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
SUPPLY CURRENT  
ISO7240A/C/M  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
mA  
mA  
mA  
mA  
mA  
mA  
Quiescent  
1 Mbps  
1
1
3
3
ISO7240A  
VI = VCC or 0 V, All channels, no load, EN2 at 3 V  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
7
10.5  
10  
10  
18  
16  
16  
24  
15  
15  
17  
13  
13  
18  
10  
10  
14  
6.5  
6.5  
12  
10  
10  
15  
9.5  
10  
10.5  
8
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
ICC1  
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
ISO7242C/M  
ISO7240A/C/M  
ISO7240A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load, EN2 at 3 V  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
ICC2  
8
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
11.5  
6
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
6
ISO7242C/M  
25 Mbps  
9
ELECTRICAL CHARACTERISTICS  
IOFF  
Sleep mode output current  
High-level output voltage  
EN at VCC, Single channel  
ISO7240  
0
µA  
VCC – 0.4  
VCC – 0.8  
VCC – 0.1  
IOH = –4 mA, See Figure 1  
ISO724x  
VOH  
V
(5-V side)  
IOH = –20 µA, See Figure 1  
IOL = 4 mA, See Figure 1  
IOL = 20 µA, See Figure 1  
0.4  
0.1  
VOL  
Low-level output voltage  
V
VI(HYS) Input voltage hysteresis  
150  
mV  
µA  
IIH  
High-level input current  
Low-level input current  
Input capacitance to ground  
10  
IN from 0 V to VCC  
IIL  
–10  
25  
CI  
IN at VCC, VI = 0.4 sin (4E6πt)  
2
pF  
CMTI  
Common-mode transient immunity VI = VCC or 0 V, See Figure 4  
50  
kV/µs  
Copyright © 2007, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
SWITCHING CHARACTERISTICS  
VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
tPLH, tPHL Propagation delay  
PWD  
Pulse-width distortion(1) |tPHL – tPLH  
tPLH, tPHL Propagation delay  
TEST CONDITIONS  
MIN  
TYP MAX  
UNIT  
40  
100  
11  
50  
3
ISO724xA  
|
|
ns  
20  
12  
ISO724xC  
ISO724xM  
See Figure 1  
PWD  
Pulse-width distortion(1) |tPHL – tPLH  
tPLH, tPHL Propagation delay  
29  
2
ns  
ns  
PWD  
Pulse-width distortion(1) |tPHL – tPLH  
|
1
ISO724xA/C  
ISO724xM  
3
(2)  
tsk(o)  
Channel-to-channel output skew  
0
2
1
tr  
Output signal rise time  
Output signal fall time  
See Figure 1  
ns  
ns  
tf  
2
tPHZ  
tPZH  
tPLZ  
tPZL  
tfs  
Propagation delay, high-level-to-high-impedance output  
Propagation delay, high-impedance-to-high-level output  
Propagation delay, low-level-to-high-impedance output  
Propagation delay, high-impedance-to-low-level output  
Failsafe output delay time from input power loss  
15  
15  
15  
15  
18  
20  
20  
20  
20  
See Figure 2  
See Figure 3  
µs  
150 Mbps PRBS NRZ data input,  
Same polarity input on all  
channels, See Figure 5  
tjit(pp)  
Peak-to-peak eye-pattern jitter  
ISO724xM  
1
ns  
(1) Also known as pulse skew  
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the  
same direction while driving identical specified loads.  
8
Submit Documentation Feedback  
Copyright © 2007, Texas Instruments Incorporated  
Product Folder Link(s): ISO7240 ISO7241 ISO7242  
ISO7240  
ISO7241  
ISO7242  
www.ti.com  
SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
ELECTRICAL CHARACTERISTICS  
VCC1 at 3.3-V, VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
SUPPLY CURRENT  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
mA  
mA  
mA  
mA  
mA  
mA  
ISO7240A/C/M  
ISO7240A  
Quiescent  
1 Mbps  
0.5  
1
1
2
VI = VCC or 0 V, All channels, no load, EN2 at 3 V  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
3
5
4
7
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
ICC1  
4
7
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
6.5  
6
11  
10  
10  
14  
22  
22  
25  
20  
20  
28  
16  
16  
24  
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
6
ISO7242C/M  
ISO7240A/C/M  
ISO7240A  
25 Mbps  
Quiescent  
1 Mbps  
9
15  
16  
17  
13  
13  
18  
10  
10  
15  
VI = VCC or 0 V, All channels, no load, EN2 at 3 V  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
ICC2  
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,  
EN2 at 3 V  
ISO7242C/M  
25 Mbps  
ELECTRICAL CHARACTERISTICS  
IOFF  
Sleep mode output current  
High-level output voltage  
EN at VCC, Single channel  
ISO7240  
0
µA  
VCC – 0.4  
VCC – 0.8  
IOH = –4 mA, See Figure 1  
ISO724x  
VOH  
V
(5-V side)  
IOH = –20 µA, See Figure 1  
IOL = 4 mA, See Figure 1  
IOL = 20 µA, See Figure 1  
VCC – 0.1  
0.4  
0.1  
VOL  
Low-level output voltage  
V
VI(HYS)  
IIH  
Input voltage hysteresis  
High-level input current  
Low-level input current  
Input capacitance to ground  
150  
mV  
µA  
10  
IN from 0 V to VCC  
IIL  
–10  
25  
CI  
IN at VCC, VI = 0.4 sin (4E6πt)  
2
pF  
Common-mode transient  
immunity  
VI = VCC or 0 V, See Figure 4  
CMTI  
50  
kV/µs  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
SWITCHING CHARACTERISTICS  
VCC1 at 3.3-V and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP MAX  
UNIT  
tPLH, tPHL  
PWD  
Propagation delay  
40  
100  
11  
51  
3
ISO724xA  
ISO724xC  
ISO724xM  
Pulse-width distortion(1) |tPHL – tPLH  
Propagation delay  
Pulse-width distortion(1) |tPHL – tPLH  
|
ns  
tPLH, tPHL  
PWD  
22  
12  
See Figure 1  
|
tPLH, tPHL  
PWD  
Propagation delay  
30  
2
ns  
ns  
ns  
Pulse-width distortion(1) |tPHL – tPLH  
|
1
ISO724xA/C  
ISO724xM  
2.5  
1
(2)  
tsk(o)  
Channel-to-channel output skew  
0
2
tr  
Output signal rise time  
Output signal fall time  
See Figure 1  
tf  
2
tPHZ  
tPZH  
tPLZ  
tPZL  
tfs  
Propagation delay, high-level-to-high-impedance output  
Propagation delay, high-impedance-to-high-level output  
Propagation delay, low-level-to-high-impedance output  
Propagation delay, high-impedance-to-low-level output  
Failsafe output delay time from input power loss  
15  
15  
15  
15  
12  
20  
20  
20  
20  
See Figure 2  
See Figure 3  
ns  
µs  
150 Mbps NRZ data input, Same polarity  
input on all channels, See Figure 5  
tjit(pp)  
Peak-to-peak eye-pattern jitter  
ISO724xM  
1
ns  
(1) Also known as pulse skew  
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the  
same direction while driving identical specified loads.  
10  
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ISO7240  
ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
ELECTRICAL CHARACTERISTICS  
VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP MAX  
UNIT  
SUPPLY CURRENT  
ISO7240A/C/M  
Quiescent  
1 Mbps  
0.5  
1
1
2
VI = VCC or 0 V, all channels, no load,  
EN2 at 3 V  
ISO7240A  
mA  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
3
5
4
7
VI = VCC or 0 V, all channels, no load,  
EN1 at 3 V, EN2 at 3 V  
ICC1  
4
7
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
6.5  
6
11  
10  
10  
14  
15  
15  
17  
13  
13  
18  
10  
10  
14  
mA  
mA  
mA  
VI = VCC or 0 V, all channels, no load,  
EN1 at 3 V, EN2 at 3 V  
6
ISO7242C/M  
ISO7240A/C/M  
ISO7240A  
25 Mbps  
Quiescent  
1 Mbps  
9
9.5  
10  
10.5  
8
VI = VCC or 0 V, all channels, no load,  
EN2 at 3 V  
ISO7240C/M  
ISO7241A/C/M  
ISO7241A  
25 Mbps  
Quiescent  
1 Mbps  
VI = VCC or 0 V, all channels, no load,  
EN1 at 3 V, EN2 at 3 V  
ICC2  
8
ISO7241C/M  
ISO7242A/C/M  
ISO7242A  
25 Mbps  
Quiescent  
1 Mbps  
11.5  
6
VI = VCC or 0 V, all channels, no load,  
EN1 at 3 V, EN2 at 3 V  
6
ISO7242C/M  
25 Mbps  
9
ELECTRICAL CHARACTERISTICS  
IOFF  
Sleep mode output current  
EN at VCC, single channel  
IOH = –4 mA, See Figure 1  
IOH = –20 µA, See Figure 1  
IOL = 4 mA, See Figure 1  
IOL = 20 µA, See Figure 1  
0
µA  
VCC – 0.4  
VCC – 0.1  
VOH  
High-level output voltage  
V
0.4  
0.1  
VOL  
Low-level output voltage  
V
VI(HYS)  
IIH  
Input voltage hysteresis  
150  
mV  
µA  
High-level input current  
10  
IN from 0 V or VCC  
IIL  
Low-level input current  
–10  
25  
CI  
Input capacitance to ground  
Common-mode transient immunity  
IN at VCC, VI = 0.4 sin (4E6πt)  
2
pF  
CMTI  
VI = VCC or 0 V, See Figure 4  
50  
kV/µs  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
SWITCHING CHARACTERISTICS  
VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)  
PARAMETER  
Propagation delay  
TEST CONDITIONS  
MIN  
TYP MAX  
UNIT  
tPLH, tPHL  
PWD  
45  
110  
12  
56  
4
ISO724xA  
ISO724xC  
ISO724xM  
(1)  
(1)  
(1)  
Pulse-width distortion |tPHL – tPLH  
|
|
|
ns  
tPLH, tPHL  
PWD  
Propagation delay  
25  
12  
See Figure 1  
Pulse-width distortion |tPHL – tPLH  
Propagation delay  
tPLH, tPHL  
PWD  
34  
2
ns  
ns  
Pulse-width distortion |tPHL – tPLH  
1
ISO724xA/C  
ISO724xM  
3.5  
1
(2)  
tsk(o)  
Channel-to-channel output skew  
0
2
tr  
Output signal rise time  
Output signal fall time  
See Figure 1  
tf  
2
tPHZ  
tPZH  
tPLZ  
tPZL  
tfs  
Propagation delay, high-level-to-high-impedance output  
Propagation delay, high-impedance-to-high-level output  
Propagation delay, low-level-to-high-impedance output  
Propagation delay, high-impedance-to-low-level output  
Failsafe output delay time from input power loss  
15  
15  
15  
15  
18  
20  
20  
20  
20  
See Figure 2  
See Figure 3  
ns  
µs  
150 Mbps PRBS NRZ data input, same  
polarity input on all channels, See Figure 5  
tjit(pp)  
Peak-to-peak eye-pattern jitter  
ISO724xM  
1
ns  
(1) Also referred to as pulse skew.  
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the  
same direction while driving identical specified loads.  
12  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
PARAMETER MEASUREMENT INFORMATION  
V
1
CC  
V
V
1/2  
CC  
V
1/2  
I
CC  
IN  
OUT  
0 V  
t
t
PHL  
PLH  
Input  
Generator  
V
C
V
V
O
50 W  
OH  
OL  
L
NOTE B  
I
90%  
10%  
V
O
50%  
50%  
NOTE A  
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3  
ns, tf ≤ 3 ns, ZO = 50Ω.  
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.  
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms  
Vcc  
Vcc  
RL = 1 kW 1ꢀ  
Vcc/2  
50ꢀ  
Vcc/2  
V
I
IN  
0 V  
OUT  
VO  
tPZL  
0V  
tPLZ  
Vcc  
0.5 V  
EN  
CL  
V
O
NOTE  
B
Input  
VOL  
VI  
Generator  
50 W  
NOTE A  
Vcc  
V
O
IN  
Vcc/2  
Vcc/2  
OUT  
V
3V  
I
0 V  
VOH  
t
PZH  
EN  
CL  
RL = 1 kW 1ꢀ  
50ꢀ  
0.5 V  
NOTE  
B
V
Input  
O
0 V  
VI  
Generator  
tPHZ  
50 W  
NOTE A  
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3  
ns, tf ≤ 3 ns, ZO = 50Ω.  
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.  
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
PARAMETER MEASUREMENT INFORMATION (continued)  
V
I
V
1
CC  
V
1
CC  
V
I
0 V  
or  
2.7 V  
OUT  
IN  
V
0 V  
V
O
V
1
t
CC  
fs  
OH  
C
V
L
50%  
O
NOTE B  
V
OL  
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.  
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3  
ns, tf ≤ 3 ns, ZO = 50Ω.  
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms  
V
1
V
2
CC  
CC  
C = 0.1 mF 1ꢀ  
C = 0.1 mF 1ꢀ  
Pass-fail criteria:  
Output must  
remain stable  
OUT  
IN  
S1  
NOTE B  
V
or V  
OL  
OH  
GND1  
GND2  
V
CM  
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.  
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3  
ns, tf ≤ 3 ns, ZO = 50Ω.  
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform  
V
1
CC  
DUT  
Tektronix  
HFS9009  
IN  
0 V  
V
Tektronix  
784D  
OUT  
PATTERN  
/2  
GENERATOR  
CC  
Jitter  
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s  
or 0s.  
Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
DEVICE INFORMATION  
PACKAGE CHARACTERISTICS  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP MAX UNIT  
L(I01) Minimum air gap (Clearance)  
Shortest terminal-to-terminal distance through air  
7.7  
mm  
L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the  
package surface  
8.1  
mm  
mm  
Minimum Internal Gap (Internal  
Distance through the insulation  
Clearance)  
0.008  
Input to output, VIO = 500 V, all pins on each side of the  
barrier tied together creating a two-terminal device  
RIO  
Isolation resistance  
>1012  
Ω
CIO  
CI  
Barrier capacitance Input to output  
Input capacitance to ground  
VI = 0.4 sin (4E6πt)  
2
2
pF  
pF  
VI = 0.4 sin (4E6πt)  
DEVICE I/O SCHEMATICS  
Enable  
Output  
Input  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
1 MW  
500 W  
8 W  
500 W  
IN  
EN  
OUT  
13 W  
1 MW  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
REGULATORY INFORMATION  
VDE  
CSA  
UL  
Recognized under 1577  
Component Recognition  
Program(1)  
Certified according to IEC  
60747-5-2  
Approved under CSA Component  
Acceptance Notice  
File Number: Pending  
File Number: Pending  
File Number: E181974  
(1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.  
THERMAL CHARACTERISTICS  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP MAX UNIT  
Low-K Thermal Resistance(1)  
168  
°C/W  
96.1  
θJA  
Junction-to-air  
High-K Thermal Resistance  
θJB  
θJC  
Junction-to-Board Thermal Resistance  
Junction-to-Case Thermal Resistance  
61  
48  
°C/W  
°C/W  
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,  
Input a 50% duty cycle square wave  
PD  
Device Power Dissipation  
220  
mW  
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.  
TYPICAL CHARACTERISTIC CURVES  
ISO7240C/M RMS SUPPLY CURRENT  
ISO7241C/M RMS SUPPLY CURRENT  
vs  
vs  
SIGNALING RATE  
SIGNALING RATE  
45  
40  
35  
45  
40  
T
= 25°C,  
T = 25°C,  
A
A
Load = 15 pF,  
All Channels  
Load = 15 pF,  
All Channels  
35  
30  
5-V ICC2  
5-V ICC2  
30  
5-V ICC1  
3.3-V ICC2  
25  
20  
25  
20  
3.3-V ICC2  
3.3-V ICC1  
5-V ICC1  
15  
15  
10  
10  
5
5
0
3.3-V ICC1  
0
0
25  
50  
75  
100  
125  
150  
0
25  
50  
75  
100  
125  
150  
Signaling Rate - Mbps  
Signaling Rate - Mbps  
Figure 6.  
Figure 7.  
16  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
TYPICAL CHARACTERISTIC CURVES (continued)  
ISO7242C/M RMS SUPPLY CURRENT  
PROPAGATION DELAY  
vs  
FREE-AIR TEMPERATURE  
vs  
SIGNALING RATE  
45  
40  
35  
45  
T
= 25°C,  
A
40  
35  
Load = 15 pF,  
All Channels  
C 3.3-V tpLH, tpHL  
C 5-V tpLH, tpHL  
30  
25  
20  
30  
5-V ICC1,ICC2  
25  
20  
M 3.3-V tpLH, tpHL  
15  
10  
15  
3.3-V ICC1,ICC2  
M 5-V tpLH, tpHL  
10  
5
T
= 25°C,  
A
5
0
Load = 15 pF,  
All Channels  
0
110 125  
0
25  
50  
75  
100  
125  
150  
80  
-40  
65  
95  
-25  
-10  
5
35  
20  
50  
Signaling Rate - Mbps  
TA - Free-Air Temperature - °C  
Figure 8.  
Figure 9.  
INPUT VOLTAGE THRESHOLD  
vs  
FREE-AIR TEMPERATURE  
VCC1 FAILSAFE THRESHOLD  
vs  
FREE-AIR TEMPERATURE  
1.4  
1.35  
1.3  
3
VCC at 5 V or 3.3 V,  
5 V Vth+  
2.9  
Load = 15 pF,  
Air Flow at 7/cf/m,  
Low-K Board  
2.8  
3.3 V Vth+  
2.7  
2.6  
2.5  
2.4  
2.3  
Vfs+  
1.25  
1.2  
Air Flow at 7 cf/m,  
Low_K Board  
Vfs-  
1.15  
1.1  
5 V Vth-  
2.2  
1.05  
1
3.3 V Vth-  
2.1  
2
-40 -25  
-10  
5
20  
35  
50  
65  
80  
95  
110 125  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110 125  
TA - Free-Air Temperature - °C  
TA - Free-Air Temperature - °C  
Figure 10.  
Figure 11.  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
TYPICAL CHARACTERISTIC CURVES (continued)  
HIGH-LEVEL OUTPUT CURRENT  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
LOW-LEVEL OUTPUT CURRENT  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
50  
45  
50  
40  
30  
20  
Load = 15 pF,  
TA = 25°C  
Load = 15 pF,  
TA = 25°C  
VCC = 5 V  
40  
35  
VCC = 3.3 V  
VCC = 3.3 V  
30  
25  
20  
VCC = 5 V  
15  
10  
10  
0
5
0
1
0
2
3
4
5
0
4
6
2
VO - Output Voltage - V  
VO - Output Voltage - V  
Figure 12.  
Figure 13.  
18  
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ISO7241  
ISO7242  
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SLLS868A–SEPTEMBER 2007–REVISED DECEMBER 2007  
APPLICATION INFORMATION  
20 mm  
20 mm  
V
V
CC1  
Max From  
CC2  
Max From  
V
V
CC1  
CC2  
0.1 mF  
0.1 mF  
1
2
16  
GND1  
15  
GND2  
IN  
IN  
IN  
OUT  
OUT  
3
4
5
6
14  
13  
12  
11  
10  
A
B
C
A
B
OUT  
C
IN  
D
OUT  
D
EN  
NC  
7
8
9
GND2  
GND1  
ISO7240x  
Figure 14. Typical ISO724x Application Circuit  
LIFE EXPECTANCY vs. WORKING VOLTAGE  
100  
V
at 560-V  
IORM  
28 Years  
10  
0
120  
250  
500  
750  
1000  
880  
WORKING VOLTAGE (VIORM) -- V  
Figure 15. Time-Dependant Dielectric Breakdown Testing Results  
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PACKAGE OPTION ADDENDUM  
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21-Dec-2007  
PACKAGING INFORMATION  
Orderable Device  
ISO7240ADW  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
DW  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7240ADWG4  
ISO7240ADWR  
ISO7240ADWRG4  
ISO7240CDW  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7240CDWG4  
ISO7240CDWR  
ISO7240CDWRG4  
ISO7240MDW  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7240MDWG4  
ISO7240MDWR  
ISO7240MDWRG4  
ISO7241ADW  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7241ADWR  
ISO7241CDW  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7241CDWR  
ISO7241MDW  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7241MDWR  
ISO7242ADW  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7242ADWR  
ISO7242CDW  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7242CDWR  
ISO7242MDW  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
49 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
ISO7242MDWR  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
21-Dec-2007  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Dec-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
330  
330  
330  
330  
330  
330  
330  
330  
(mm)  
16  
ISO7240ADWR  
ISO7240CDWR  
ISO7240MDWR  
ISO7241ADWR  
ISO7241CDWR  
ISO7241MDWR  
ISO7242ADWR  
ISO7242CDWR  
ISO7242MDWR  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
16  
16  
16  
16  
16  
16  
16  
16  
16  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
10.9  
10.9  
10.9  
10.9  
10.9  
10.9  
10.9  
10.9  
10.9  
10.78  
10.78  
10.78  
10.78  
10.78  
10.78  
10.78  
10.78  
10.78  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
3.0  
12  
12  
12  
12  
12  
12  
12  
12  
12  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
16  
16  
16  
16  
16  
16  
16  
16  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Dec-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
ISO7240ADWR  
ISO7240CDWR  
ISO7240MDWR  
ISO7241ADWR  
ISO7241CDWR  
ISO7241MDWR  
ISO7242ADWR  
ISO7242CDWR  
ISO7242MDWR  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
DW  
16  
16  
16  
16  
16  
16  
16  
16  
16  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
SITE 35  
406.0  
406.0  
406.0  
406.0  
406.0  
406.0  
406.0  
406.0  
406.0  
348.0  
348.0  
348.0  
348.0  
348.0  
348.0  
348.0  
348.0  
348.0  
63.0  
63.0  
63.0  
63.0  
63.0  
63.0  
63.0  
63.0  
63.0  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this  
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily  
performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should  
provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask  
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services  
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such  
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under  
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is  
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an  
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties  
may be subject to additional restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service  
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business  
practice. TI is not responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would  
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement  
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications  
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related  
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any  
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its  
representatives against any damages arising out of the use of TI products in such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is  
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in  
connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products  
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any  
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Amplifiers  
Data Converters  
DSP  
Applications  
Audio  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/audio  
Automotive  
Broadband  
Digital Control  
Military  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
interface.ti.com  
logic.ti.com  
Logic  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/lpw  
Telephony  
Low Power  
Wireless  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2007, Texas Instruments Incorporated  

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