ISO7240CF_15 [TI]
High-Speed, Quad-Channel Digital Isolators;
| 型号： | ISO7240CF_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed, Quad-Channel Digital Isolators |
| 文件： | 总16页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7240CF
www.ti.com ................................................................................................................................................ SLLS869B–SEPTEMBER 2007–REVISED APRIL 2008
QUAD DIGITAL ISOLATOR WITH SELECTABLE FAILSAFE OUTPUT
1
FEATURES
•
0-Mbps (DC) to 25 Mbps Signaling Rate
•
•
Operates with 3.3-V or 5-V Supplies
–
Low Channel-to-Channel Output Skew;
2 ns Max
High Electromagnetic Immunity
(see application note SLLA181)
–
Low Pulse-Width Distortion (PWD);
2.5 ns Max
•
–40°C to 125°C Operating Range
APPLICATIONS
•
•
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 11)
•
•
•
•
•
Flat Plasma Display Panels
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
4000-Vpeak Isolation, 560 Vpeak VIORM
–
UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1 and CSA Approved
•
4 kV ESD Protection
DESCRIPTION
The ISO7240CF is a quad-channel digital isolator with an input disable function and a selectable high or low
failsafe-output function with the CTRL pin (pin 10). The device has logic input and output buffers separated by
TI’s silicon dioxide (SiO2) isolation barrier. When used in conjunction with isolated power supplies, the device
blocks high voltage, isolates grounds, and prevents noise currents from entering the local ground and interfering
with or damaging sensitive circuitry.
A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh
pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven, and
the failsafe circuit drives the output to the logic state selected by the user.
The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left unconnected. If a
logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output state.
The ISO7240CF also includes an input disable function that prevents data from being passed across the isolation
barrier to the output. When the inputs are disabled, the outputs are set by the CTRL pin.
This device may be powered from either 3.3-V or 5-V supplies on either side in any combination. Note that the
signal input pins are 5-V tolerant regardless of the voltage supply level being used.
The device is characterized for operation over the ambient temperature range of –40°C to 125°C.
ISO7240CF
V
V
CC2
1
2
3
4
5
6
7
8
16
15
CC1
GND1
GND2
IN
A
14
13
12
11
10
OUT
A
IN
B
OUT
B
IN
C
OUT
C
OUT
D
IN
D
CTRL
GND2
DISABLE
GND1
9
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ISO7240CF
SLLS869B–SEPTEMBER 2007–REVISED APRIL 2008 ................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE FUNCTION TABLE(1)
DATA INPUT
(IN)
DISABLE INPUT
(DISABLE)
FAILSAFE CONTROL
INPUT (CTRL)
DATA OUTPUT
(OUT)
VCC1
VCC2
PU
PU
X
PU
PU
PU
PU
PU
PU
H
L
L or Open
X
H
L
L or Open
X
X
X
X
X
H
H
X
X
H or Open
H
L
X
L
H or Open
L
PD
PD
H
L
(1) PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.5 to 6
–0.5 to 6
±15
UNIT
V
VCC Supply voltage(2), VCC1, VCC2
VI
IO
Voltage at IN, OUT, EN
Output current
V
mA
Electrostatic discharge JEDEC Standard
22, Test Method A114-C.01
Human Body Model
±4
kV
Electrostatic
discharge
ESD
TJ
All pins
Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101
±1
Machine Model
Maximum junction temperature
ANSI/ESDS5.2-1996
±200
170
V
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
3
TYP
MAX
5.5
3.6
4
UNIT
VCC
Supply voltage, VCC1, VCC2
V
IOH
IOL
tui
High-level output current
mA
mA
ns
Low-level output current
–4
40
0
Input pulse width
1/tui
VIH
VIL
TJ
Signaling rate
30(1)
25
VCC
0.8
Mbps
V
High-level input voltage (IN, DISABLE, CTRL)
Low-level input voltage (IN, DISABLE, CTRL)
Junction temperature
2
0
V
150
°C
External magnetic field-strength immunity per IEC 61000-4-8 and IEC
61000-4-9 certification
H
1000
A/m
(1) Typical signaling rate under ideal conditions at 25°C.
2
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ISO7240CF
www.ti.com ................................................................................................................................................ SLLS869B–SEPTEMBER 2007–REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
3
UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
ICC1
Supply current
VI = VCC or 0 V, all channels, no load
mA
7
10.5
22
15
17
0
ICC2
IOFF
VOH
Supply current
VI = VCC or 0 V, all channels, no load
mA
µA
V
25
Sleep mode output current
High-level output voltage
DISABLE at VCC, single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.4
VCC – 0.1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
200
mV
µA
10
IN, DISABLE, CTRL from 0 V to VCC
IIL
–10
35
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
50
kV/µs
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD
tsk(pp)
tsk(o)
tr
Propagation delay, low-to-high-level output
18
42
2.5
8
See Figure 1
ns
(1)
Pulse-width distortion |tPHL – tPLH
|
(2)
Part-to-part skew
ns
ns
(3)
Channel-to-channel output skew
Output signal rise time
0
2
2
See Figure 1
ns
tf
Output signal fall time
2
twake
tfs
(1) Also referred to as pulse skew.
Wake time from input disable
See Figure 2
See Figure 3
15
12
µs
µs
Failsafe output delay time from input power loss
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ELECTRICAL CHARACTERISTICS
VCC1 at 5 V and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
3
UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
ICC1
Supply current
VI = VCC or 0 V, all channels, no load
mA
7
10.5
15
9.5
10.5
0
ICC2
IOFF
VOH
Supply current
VI = VCC or 0 V, all channels, no load
mA
µA
V
17
Sleep mode output current
High-level output voltage
DISABLE at Vcc, single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.4
VCC – 0.1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
200
mV
µA
10
IN, DISABLE, CTRL from 0 V to VCC
IIL
–10
25
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
50
kV/µs
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD
tsk(pp)
tsk(o)
tr
Propagation delay, low-to-high-level output
20
46
3
See Figure 1
ns
(1)
Pulse-width distortion |tPHL – tPLH
|
(2)
Part-to-part skew
10
2.5
ns
ns
(3)
Channel-to-channel output skew
Output signal rise time
0
2
See Figure 1
ns
tf
Output signal fall time
2
twake
tfs
(1) Also referred to as pulse skew.
Wake time from input disable
See Figure 2
See Figure 3
15
18
µs
µs
Failsafe output delay time from input power loss
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
4
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ISO7240CF
www.ti.com ................................................................................................................................................ SLLS869B–SEPTEMBER 2007–REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS
VCC1 at 3.3-V, VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
3
MAX
1
UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
ICC1
Supply current
VI = VCC or 0 V, all channels, no load
mA
5
15
17
0
22
25
ICC2
IOFF
VOH
Supply current
VI = VCC or 0 V, all channels, no load
mA
µA
V
Sleep mode output current
High-level output voltage
DISABLE at VCC, single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.4
VCC – 0.1
0.4
0.1
VOL
Low-level output voltage
V
0
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
200
mV
µA
10
IN, DISABLE, CTRL from 0 V to VCC
IIL
–10
25
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
50
kV/µs
SWITCHING CHARACTERISTICS
VCC1 at 3.3-V and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD
tsk(pp)
tsk(o)
tr
Propagation delay, low-to-high-level output
22
51
3
See Figure 1
ns
(1)
Pulse-width distortion |tPHL – tPLH
|
(2)
Part-to-part skew
10
2.5
ns
ns
(3)
Channel-to-channel output skew
Output signal rise time
0
2
See Figure 1
ns
tf
Output signal fall time
2
twake
tfs
(1) Also referred to as pulse skew.
Wake time from input disable
See Figure 2
See Figure 3
15
12
µs
µs
Failsafe output delay time from input power loss
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
3
MAX
1
UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
ICC1
Supply current
VI = VCC or 0 V, all channels, no load
mA
5
9.5
10.5
0
15
17
ICC2
IOFF
VOH
Supply current
VI = VCC or 0 V, all channels, no load
mA
µA
V
Sleep mode output current
High-level output voltage
DISABLE at VCC, single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.4
VCC – 0.1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
200
mV
µA
10
IN, DISABLE, CTRL from 0 V to VCC
IIL
–10
25
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
1
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
50
kV/µs
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD
tsk(pp)
tsk(o)
tr
Propagation delay, low-to-high-level output
25
56
4
See Figure 1
ns
(1)
Pulse-width distortion |tPHL – tPLH
|
(2)
Part-to-part skew
10
3
ns
ns
(3)
Channel-to-channel output skew
Output signal rise time
0
2
See Figure 1
ns
tf
Output signal fall time
2
twake
tfs
(1) Also referred to as pulse skew.
Wake time from input disable
See Figure 2
See Figure 3
15
18
µs
µs
Failsafe output delay time from input power loss
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6
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PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
CC
V
1/2
I
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
VCC2
VO
IN
OUT
VI
VCC2 /2
3 V
0 V
CTRL
0 V
DISABLE
t wake
VCC2
CL
Input
Generator
50%
(Note B)
VI
50 W
VO
0 V
(Note A)
VCC2
IN
OUT
VO
0 V
VI
VCC2 /2
0 V
DISABLE
CTRL
3 V
t wake
CL
VCC2
Input
(Note B)
50%
VI
50 W
Generator
(Note A)
VO
0 V
NOTE: Which ever test yields the longest time is used in this data sheet.
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Wake Time From Input Disable
V
I
V
1
CC
V
1
CC
V
I
0 V
or
2.7 V
OUT
IN
V
0 V
V
O
V
1
t
CC
fs
OH
C
V
L
FAILSAFE HIGH
50%
O
NOTE B
V
OL
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE B
V
or V
OL
OH
GND1
GND2
V
CM
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
L(I01) Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
7.7
mm
Minimum external tracking
(Creepage)
Shortest terminal-to-terminal distance across the
package surface
L(I02)
8.1
mm
mm
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
>1011
Ω
CIO
CI
Barrier capacitance Input to output VI = 0.4 sin (4E6πt)
1
1
pF
pF
Input capacitance to ground
VI = 0.4 sin (4E6πt)
DEVICE I/O SCHEMATICS
INPUT
DISABLE
CTRL
OUTPUT
VCC2
VCC1
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
1MW
500 W
8W
500 W
500 W
IN
OUT
EN
EN
13W
1MW
1 MW
8
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ISO7240CF
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THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance(1)
MIN
TYP MAX
UNIT
168
96.1
61
θJA
Junction-to-air
°C/W
High-K Thermal Resistance
θJB
θJC
Junction-to-Board Thermal Resistance
Junction-to-Case Thermal Resistance
°C/W
°C/W
48
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 12.5 MHz 50% duty cycle square wave
PD
Device Power Dissipation
220
mW
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
REGULATORY INFORMATION
UL
Recognized under 1577 Component Recognition Program(1)
File Number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL
1577.
TYPICAL CHARACTERISTIC CURVES
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
1.4
45
40
5 V, Vth+
t
1.35
PLH
3.3 V, Vth+
3.3 V
5 V
35
30
25
20
15
10
t
PHL
1.3
1.25
1.2
t
PLH
t
PHL
Air Flow at 7 cf/m,
Low-K Board
1.15
1.1
5 V, Vth-
3.3 V, Vth-
Load = 15 pF,
Air Flow at 7 cf/m,
Low-K Board
1.05
1
5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
T
- Free-Air Temperature - °C
T
- Free-Air Temperature - °C
A
A
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTIC CURVES (continued)
HIGH-LEVEL OUTPUT VOLTAGE
VCC1 FAILSAFE THRESHOLD
vs
vs
HIGH-LEVEL OUTPUT CURRENT
vs SUPPLY VOLTAGE
Vout (Vout vs VCC1 ACROSS TEMPERATURE)
3
2.9
2.8
50
40
V
at 5 V or 3.3 V,
CC
T
= 25°C,
A
Load = 15 pF
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
V
= 5 V
CC
2.7
2.6
2.5
2.4
V
fs+
30
20
V
fs-
V
= 3.3 V
CC
2.3
2.2
10
0
2.1
2
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
1
2
3
4
5
6
T
- Free-Air Temperature - °C
A
V
- Output Voltage - V
O
Figure 7.
Figure 8.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
50
T
= 25°C,
A
Load = 15 pF
45
40
35
30
V
= 3.3 V
CC
V
= 5 V
25
20
CC
15
10
5
0
0
1
2
3
4
5
V
- Output Voltage - V
O
Figure 9.
10
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ISO7240CF
www.ti.com ................................................................................................................................................ SLLS869B–SEPTEMBER 2007–REVISED APRIL 2008
APPLICATION INFORMATION
20 mm
20 mm
max. from
max. from
V
V
CC2
CC1
V
V
CC1
CC2
0.1 mF
0.1 mF
1
16
15
GND2
GND1
2
IN
IN
IN
OUT
OUT
OUT
OUT
A
B
C
A
B
C
D
14
13
12
11
10
3
4
5
6
7
8
IN
D
DISABLE
GND 1
CTRL
GND 2
9
ISO7240CF
NOTE: It is recommended that the DISABLE pin not be left floating if unused in an application.
Figure 10. Typical ISO7240CF Failsafe-Low Application Circuit
100
VIORM at 560 V
28 Years
10
0
250
500
750
1000
120
880
WORKING VOLTAGE (VIORM) -- V
Figure 11. Time Dependent Dielectric Breakdown Test Results
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Product Folder Link(s) :ISO7240CF
PACKAGE OPTION ADDENDUM
www.ti.com
22-Apr-2008
PACKAGING INFORMATION
Orderable Device
ISO7240CFDW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ISO7240CFDWG4
ISO7240CFDWR
ISO7240CFDWRG4
SOIC
SOIC
SOIC
DW
DW
DW
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ISO7240CFDWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
406.0 348.0 63.0
ISO7240CFDWR
2000
Pack Materials-Page 2
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