ISO7241C-Q1 [TI]
汽车类四通道、3/1、25Mbps 数字隔离器;
| 型号： | ISO7241C-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类四通道、3/1、25Mbps 数字隔离器 驱动 接口集成电路 驱动程序和接口 |
| 文件： | 总27页 (文件大小：826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
HIGH-SPEED QUAD DIGITAL ISOLATORS
Check for Samples: ISO7240CF-Q1, ISO7241C-Q1
1
FEATURES
•
•
•
Qualified for Automotive Applications
•
•
•
4 kV ESD Protection
Selectable Failsafe Output (ISO7240CF)
25 and 150-Mbps Signaling Rate Options
Operate With 3.3-V or 5-V Supplies
High Electromagnetic Immunity
(see application report SLLA181)
–
–
–
Low Channel-to-Channel Output Skew;
1 ns Max
•
–40°C to 125°C Operating Range
Low Pulse-Width Distortion (PWD);
2 ns Max
Low Jitter Content; 1 ns Typ at 150 Mbps
•
•
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 17)
4000-Vpeak Isolation, 560-Vpeak VIORM
–
UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1, IEC 60950-1 and CSA
Approved
DESCRIPTION
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging
sensitive circuitry.
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same
direction and one channel in opposition. The ISO7242 has two channels in each direction.
The C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from
being passed to the output of the device. The M option devices have CMOS VCC/2 input thresholds and do not
have the input noise-filter or the additional propagation delay.
The ISO7240CF has an input disable function on pin 7, and a selectable high or low failsafe-output function with
the CTRL pin (pin 10). The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left
unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output
state. The ISO7240CF input disable function prevents data from being passed across the isolation barrier to the
output. When the inputs are disabled, the outputs are set by the CTRL pin.
These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V,
5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage
supply level being used.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
ISO7240CFQDWRQ1
ISO7240CQDWRQ1
TOP-SIDE MARKING
ISO7240CFQ
Product Preview
ISO7241CQ
–40°C to 125°C
SOIC – DW
Reel of 2000
ISO7241CQDWRQ1
ISO7242CQDWRQ1
ISO7242CQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ISO7240
ISO7241
ISO7242
ISO7240CF
V
1
2
3
4
5
6
7
8
V
V
V
V
V
V
V
CC2
16
1
2
3
4
5
6
7
8
16
15
1
2
3
4
5
6
7
8
16
15
1
2
3
4
5
6
7
8
16
15
CC2
CC1
CC1
CC2
CC1
CC2
CC1
15
GND2
GND1
GND1
GND2 GND1
GND2 GND1
GND2
14
13
12
11
10
9
OUT
A
IN
A
IN
B
IN
C
IN
A
IN
B
IN
C
14
13
12
11
10
9
OUT
OUT
OUT
IN
IN
IN
14
13
12
11
10
9
OUT
OUT
OUT
IN
IN
14
13
12
11
10
9
OUT
A
A
B
C
A
A
B
C
A
B
C
OUT
B
OUT
B
B
OUT
C
OUT
OUT
IN
C
C
OUT
D
OUT
EN
OUT
IN
D
IN
D
IN
D
IN
D
D
D
D
CTRL
GND2
EN
EN
1
DISABLE
GND1
NC
EN
2
EN
2
1
GND1
GND2 GND1
GND2 GND1
GND2
Table 1. ISO724xC Function Table(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
INPUT VCC
OUTPUT VCC
H
L
H or Open
H or Open
L
H
L
PU
PU
X
Z
H
H
Z
Open
X
H or Open
H or Open
L
PD
PD
PU
PU
X
(1) PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
Table 2. ISO7240CF Function Table
VCC1
VCC2
DATA INPUT
(IN)
DISABLE INPUT
(DISABLE)
FAILSAFE CONTROL INPUT
(CTRL)
DATA OUTPUT
(OUT)
PU
PU
X
PU
PU
PU
PU
PU
PU
H
L
L or Open
X
H
L
L or Open
X
X
X
X
X
H
H
X
X
H or Open
H
L
X
L
H or Open
L
PD
PD
H
L
2
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Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.5 to 6
–0.5 to 6
±15
UNIT
V
VCC Supply voltage(2), VCC1, VCC2
VI
IO
Voltage at IN, OUT, EN, DISABLE, CTRL
Output current
V
mA
Human-Body Model
Electrostatic
±4
kV
ESD
TJ
Field-Induced-Charged Device Model
All pins
±1
discharge
Machine Model
±200
150
V
Maximum junction temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
VCC Supply voltage(1), VCC1, VCC2
3.15
5.5
4
V
IOH
IOL
tui
High-level output current
Low-level output current
Input pulse width
mA
mA
ns
–4
40
0
1/tui Signaling rate
30(2)
25 Mbps
VIH
VIL
TA
High-level input voltage (IN, DISABLE, CTRL, EN)
2
VCC
V
V
Low-level input voltage (IN, DISABLE, CTRL, EN)
Operating free-air temperature
0
0.8
-40
125
°C
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
H
1000
A/m
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
(2) Typical value at room temperature and well-regulated power supply.
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
UNIT
VIORM
Maximum working insulation voltage
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
896
V
V
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
VPR
Input to output test voltage
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
VIOTM
RS
Transient overvoltage
Insulation resistance
Pollution degree
t = 60 s
4000
>109
2
V
VIO = 500 V at TS
Ω
(1) Climatic Classification 40/125/21
Copyright © 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V(1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
1
7
3
10.5
11
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
ISO7240C
ISO7241C
ISO7242C
ISO7240C
ISO7241C
ISO7242C
mA
mA
mA
mA
mA
mA
6.5
12
10
15
15
17
13
18
10
15
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC1
18
16
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
24
22
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
25
20
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC2
28
16
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
24
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0
μA
V
CC – 0.8
CC – 0.1
VOH
High-level output voltage
V
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
μA
10
IN from 0 V to VCC
IIL
–10
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
25
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
4
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN TYP
MAX UNIT
tPLH, tPHL
PWD
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
18
45
ns
5
|
(2)
tsk(pp)
Part-to-part skew
8
3
4
ns
ISO7240C, ISO7241C
ISO7242C
(3)
tsk(o)
Channel-to-channel output skew
ns
tr
Output signal rise time
Output signal fall time
2
2
See Figure 1
ns
ns
tf
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
Wake time from input disable
15
15
15
15
12
15
25
25
25
25
See Figure 2
See Figure 3
See Figure 4
μs
μs
twake
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP MAX
UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
1
7
3
10.5
11
ISO7240C
ISO7241C
ISO7242C
ISO7240C
ISO7241C
ISO7242C
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
mA
mA
mA
mA
mA
mA
6.5
12
10
15
9.5
10.5
8
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC1
18
16
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
24
15
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
17
13
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC2
11.5
6
18
10
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
9
14
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
ISO7240
0
μA
VCC – 0.4
VCC – 0.8
VCC – 0.1
IOH = –4 mA, See Figure 1
ISO724x (5-V
side)
VOH
High-level output voltage
V
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
IIL
CI
High-level input current
Low-level input current
Input capacitance to ground
10
IN from 0 V to VCC
–10
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
CMTI
25
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
6
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN
TYP
MAX
50
3
UNIT
tPLH, tPHL
PWD
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
20
|
ISO7240C, ISO7241C
ISO7242C
ns
4
(2)
tsk(pp)
Part-to-part skew
10
3
ns
ns
ISO7240C, ISO7241C
ISO7242C
(3)
tsk(o)
Channel-to-channel output skew
4
tr
Output signal rise time
Output signal fall time
2
2
See Figure 1
ns
ns
tf
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
Wake time from input disable
15
15
15
15
18
15
25
25
25
25
See Figure 2
See Figure 3
See Figure 4
μs
μs
twake
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2010–2011, Texas Instruments Incorporated
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Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
0.5
3
1
5
ISO7240C
mA
mA
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
Quiescent
25 Mbps
4
6.5
6
7
11
10
ISO7241C
ICC1
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
Quiescent
ISO7242C
ISO7240C
ISO7241C
mA
mA
mA
25 Mbps
Quiescent
25 Mbps
9
15
17
14
22
25
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
Quiescent
25 Mbps
Quiescent
25 Mbps
13
18
10
15
20
28
16
24
ICC2
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7242C
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
High-level output voltage
EN at 0 V, Single channel
0
μA
ISO7240
IOH = –4 mA, See Figure 1
ISO724x (5-V side)
VCC – 0.4
VCC – 0.8
VCC – 0.1
VOH
V
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
μA
10
IN from 0 V to VCC
IIL
–10
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
CMTI
25
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
8
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Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MA UNIT
X
tPLH
tPHL
,
Propagation delay
See Figure 1
See Figure 1
20
51
3
Pulse-width distortion(1) |tPHL – tPLH
|
ISO7240C,
ISO7241C
ns
PWD
ISO7242C
4
10
3
(2)
tsk(pp)
tsk(o)
Part-to-part skew
ns
ns
ISO7240C, ISO7241C
ISO7242C
(3)
Channel-to-channel output skew
4
tr
Output signal rise time
Output signal fall time
Propagation delay,
2
2
See Figure 1
ns
tf
tPHZ
15 25
15 25
15 25
15 25
high-level-to-high-impedance output
tPZH
tPLZ
tPZL
Propagation delay,
high-impedance-to-high-level output
See Figure 2
ns
Propagation delay, low-level-to-high-impedance
output
Propagation delay, high-impedance-to-low-level
output
tfs
Failsafe output delay time from input power loss See Figure 3
Wake time from input disable See Figure 4
12
15
μs
μs
twake
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2010–2011, Texas Instruments Incorporated
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9
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN TYP MAX UNIT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
0.5
3
1
5
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
ISO7240C
ISO7241C
mA
mA
mA
mA
4
7
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC1
6.5
6
11
10
14
15
17
13
18
10
14
ISO7242C
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
9
9.5
10.5
8
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
ISO7240C
ISO7241C
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ICC2
11.5
6
ISO7242C
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
9
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0
μA
V
CC – 0.4
CC – 0.1
VOH
High-level output voltage
V
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
μA
10
IN from 0 V or VCC
IIL
–10
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
25
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MI TY MAX UNIT
N
P
tPLH
tPHL
,
Propagation delay
25
56
See Figure 1
ns
(1)
PWD
tsk(pp)
Pulse-width distortion |tPHL – tPLH
|
4
10
3.5
4
(2)
Part-to-part skew
ns
ns
ISO7240C, ISO7241C
ISO7242C
(3)
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
Output signal fall time
Propagation delay,
2
2
ns
ns
See Figure 1
tf
tPHZ
ISO7240C,
ISO7241C
15
15
15
15
15
15
15
15
18
15
20
25
20
25
20
25
20
25
high-level-to-high-impedance output
ISO7242C
tPZH
tPLZ
tPZL
Propagation delay,
high-impedance-to-high-level output
ISO7240C,
ISO7241C
ISO7242C
See Figure 2
ns
Propagation delay, low-level-to-high-impedance
output
ISO7240C,
ISO7241C
ISO7242C
Propagation delay, high-impedance-to-low-level
output
ISO7240C,
ISO7241C
ISO7242C
Failsafe output delay time from input power
loss
See Figure 3
See Figure 4
μs
μs
tfs
twake
Wake time from input disable
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
V
1/2
I
CC
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
VCC
RL = 1 kW 1ꢀ
VCC/2
VCC/2
V
I
IN
0 V
OUT
VO
tPZL
0V
tPLZ
VCC
0.5 V
EN
CL
V
50ꢀ
O
NOTE
B
Input
VOL
VI
Generator
50 W
NOTE A
VCC
V
O
VCC/2
VCC/2
IN
OUT
V
3V
I
0 V
t
PZH
EN
VOH
CL
RL = 1 kW 1ꢀ
50ꢀ
0.5 V
NOTE
B
V
Input
O
0 V
VI
Generator
tPHZ
50 W
NOTE A
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
V
CC
CC
2.7 V
V
I
0 V
or
OUT
0 V
V
IN
V
O
t
V
1
fs
CC
OH
C
L
V
50%
O
NOTE A
fs low
V
OL
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
CC
V
O
IN
OUT
V
V
/2
3 V
I
CC2
0 V
V
CTRL
DISABLE
twake
CC
C
Input
L
0 V
50 %
(Note B)
V
Generator
(Note A)
I
V
50 W
O
0 V
V
CC2
IN
OUT
V
0V
O
V
V
/2
CC2
I
0 V
DISABLE
t
CTRL
wake
V
C
CC2
L
Input
3 V
(Note B )
50 %
V
Generator
(Note A )
50 W
I
V
O
0 V
NOTE: Which ever test yields the longest time is used in this data sheet
A. Whichever test yields the longest time is used in this data sheet.
Figure 4. Wake Time From Input Disable Test Circuit and Voltage Waveforms
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE B
V
or V
OL
OH
GND1
GND2
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
V
1
CC
DUT
Tektronix
HFS9009
IN
0 V
V
Tektronix
784D
OUT
PATTERN
/2
GENERATOR
CC
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
L(I01) Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
Shortest terminal-to-terminal distance across the
package surface
L(I02) Minimum external tracking (Creepage)
8.1
≥ 175
0.008
mm
V
Tracking resistance (comparative
tracking index)
CTI
DIN IEC 60112/VDE 0303 Part 1
Distance through the insulation
Minimum Internal Gap (Internal
Clearance)
mm
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
RIO
Isolation resistance
>1012
Ω
CIO
CI
Barrier capacitance Input to output
Input capacitance to ground
VI = 0.4 sin (4E6πt)
VI = 0.4 sin (4E6πt)
2
2
pF
pF
IEC 60664-1 RATINGS TABLE
TEST CONDITIONS
PARAMETER
SPECIFICATION
Basic isolation group
Material group
IIIa
I-IV
I-III
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Installation classification
REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Acceptance Notice
Recognized under 1577 Component Recognition
Program(1)
Certified according to IEC 60747-5-2
File Number: 40016131
File Number: 1698195
File Number: E181974
(1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
DEVICE I/O SCHEMATICS
Enable
Output
Input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1 MW
1 MW
500 W
8 W
500 W
IN
EN
OUT
13 W
ISO7240CF
Input
VCC
VCC
500 W
IN
1 MW
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Junction-to-air
TEST CONDITIONS
Low-K Thermal Resistance(1)
High-K Thermal Resistance
MIN
TYP MAX UNIT
168
°C/W
96.1
θJA
θJB
θJC
Junction-to-Board Thermal Resistance
Junction-to-Case Thermal Resistance
61
48
°C/W
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
PD
Device Power Dissipation
220
mW
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
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ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
TYPICAL CHARACTERISTIC CURVES
ISO7240C RMS SUPPLY CURRENT
ISO7241C RMS SUPPLY CURRENT
vs
vs
SIGNALING RATE
SIGNALING RATE
45
40
35
45
40
T
= 25°C,
T = 25°C,
A
A
Load = 15 pF,
All Channels
Load = 15 pF,
All Channels
35
30
5-V ICC2
5-V ICC2
30
5-V ICC1
3.3-V ICC2
25
20
25
20
3.3-V ICC2
3.3-V ICC1
5-V ICC1
15
15
10
10
5
5
0
3.3-V ICC1
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 7.
Figure 8.
ISO7242C RMS SUPPLY CURRENT
PROPAGATION DELAY
vs
vs
SIGNALING RATE
FREE-AIR TEMPERATURE
45
45
40
35
T
= 25°C,
A
40
35
Load = 15 pF,
All Channels
C 3.3-V tpLH, tpHL
C 5-V tpLH, tpHL
30
25
20
30
5-V ICC1,ICC2
25
20
M 3.3-V tpLH, tpHL
15
10
15
3.3-V ICC1,ICC2
M 5-V tpLH, tpHL
10
5
T
= 25°C,
A
5
0
Load = 15 pF,
All Channels
0
110 125
0
25
50
75
100
125
150
80
-40
65
95
-25
-10
5
35
20
50
Signaling Rate - Mbps
TA - Free-Air Temperature - °C
Figure 9.
Figure 10.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
INPUT VOLTAGE THRESHOLD
VCC1 FAILSAFE THRESHOLD
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.4
1.35
1.3
3
2.9
2.8
VCC at 5 V or 3.3 V,
5 V Vth+
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
3.3 V Vth+
2.7
2.6
2.5
2.4
2.3
Vfs+
1.25
1.2
Air Flow at 7 cf/m,
Low_K Board
Vfs-
1.15
1.1
5 V Vth-
2.2
1.05
1
3.3 V Vth-
2.1
2
-40 -25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 11.
Figure 12.
HIGH-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
50
45
50
40
30
20
Load = 15 pF,
TA = 25°C
Load = 15 pF,
TA = 25°C
VCC = 5 V
40
35
VCC = 3.3 V
VCC = 3.3 V
30
25
20
VCC = 5 V
15
10
10
0
5
0
1
0
2
3
4
5
0
4
6
2
VO - Output Voltage - V
VO - Output Voltage - V
Figure 13.
Figure 14.
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ISO7241C-Q1, ISO7242C-Q1
www.ti.com
SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
APPLICATION INFORMATION
2 mm
2 mm
max. from
V
V
max. from
CC1
CC2
V
CC1
V
CC2
0.1 mF
0.1 mF
1
16
GND1
2
15
14
13
12
11
10
9
GND2
IN
IN
IN
3
4
5
6
7
8
OUT
OUT
OUT
OUT
A
B
C
A
B
C
D
IN
D
EN
NC
GND2
GND1
ISO7240x
Figure 15. Typical ISO7240x Application Circuit
2 mm
2 mm
max. from
V
V
max. from
CC1
CC2
V
CC1
V
CC2
0.1 mF
0.1 mF
1
2
16
15
14
13
12
11
10
9
GND1
GND2
IN
IN
IN
OUT
OUT
OUT
OUT
A
B
C
A
B
C
D
3
4
5
6
7
8
IN
D
DISABLE
GND1
CTRL
GND2
ISO7240CF
Figure 16. Typical ISO7240CF Failsafe-Low Application Circuit
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SLLSE40A –SEPTEMBER 2010–REVISED SEPTEMBER 2011
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LIFE EXPECTANCY vs WORKING VOLTAGE
100
V
at 560-V
IORM
28 Years
10
0
120
250
500
750
1000
880
WORKING VOLTAGE (VIORM) -- V
Figure 17. Time-Dependant Dielectric Breakdown Testing Results
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO7240CFQDWRQ1
ISO7241CQDWRQ1
ISO7242CQDWRQ1
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7240CF-Q1, ISO7241C-Q1, ISO7242C-Q1 :
Catalog: ISO7240CF, ISO7241C, ISO7242C
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2012
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7240CFQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
ISO7240CFQDWRQ1
2000
Pack Materials-Page 2
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