ISO7421-EP [TI]
低功耗双通道数字隔离器;
| 型号： | ISO7421-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗双通道数字隔离器 |
| 文件： | 总24页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7421-EP
ZHCSEG4 –DECEMBER 2015
ISO7421-EP 低功耗双路数字隔离器
1 特性
2 应用
1
•
•
最高信号传输速率：1Mbps
•
是下列应用中光耦合器的替代产品：
低功耗，每通道 ICC 典型值（3.3V 工作电
压）：1.5mA
–
工业现场总线
–
–
–
Profibus 现场总线
•
•
•
•
•
•
•
•
•
低传播延迟 - 9ns 典型值
Modbus 协议
低偏移 - 300ps 典型值
DeviceNet™数据总线
宽 TA 温度范围：-55℃ 至 136℃
50kV/μs 瞬态抗扰度，典型值
在额定电压上超过 25 年的隔离装置完好性
可由 3.3V 和 5V 电源及逻辑电平供电
3.3V 和 5V 电平转换
–
–
–
–
伺服控制接口
电机控制
电源
电池组
3 说明
窄体小尺寸集成电路 (SOIC)-8 封装
安全及管理批准:
ISO7421-EP 器件可提供符合 UL 标准的长达 1 分钟且
高达 2500 VRMS 的电流隔离。ISO7421-EP 器件有两
个隔离通道。每个隔离通道的逻辑输入和输出缓冲器均
由二氧化硅 (SiO2) 绝缘隔栅分离开来。与隔离式电源
一起使用时，此器件可防止数据总线或者其他电路上的
噪声电流进入本地接地端并干扰或损坏敏感电路。
–
–
–
–
符合 DIN V VDE V 0884-10 和 DIN EN 61010-
1 标准的 4242 VPK 隔离
符合 UL 1577 标准且长达 1 分钟的 2500 VRMS
隔离
CSA 组件接受通知 5A，IEC 60950-1 和 IEC
61010-1 标准
此器件具有晶体管-晶体管逻辑电路 (TTL) 输入阈值，
并且需要两个电源电压，3.3 或 5V，或者任意组合。
当由一个 3.3V 电源供电时，所有输入均为 5V 耐压。
通过 GB4943.1-2011 CQC 认证
ISO7421-EP 器件的额定信号传输速率高达 1Mbps。
由于其响应时间短，在大多数情况下，此器件还将发送
脉宽更短的数据。如果需要，设计人员应添加外部滤波
来去除输入脉冲持续时间 < 20ns 的寄生信号。
器件信息(1)
部件号
封装
SOIC (8)
封装尺寸（标称值）
ISO7421-EP
4.90mm x 3.91mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
数字电容隔离器的概念框图
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEN3
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
目录
6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V
±10%.......................................................................... 7
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.14 Typical Characteristics............................................ 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
7
8
9
6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V
±10%.......................................................................... 5
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 器件和文档支持 ..................................................... 17
12.1 文档支持................................................................ 17
12.2 社区资源................................................................ 17
12.3 商标....................................................................... 17
12.4 静电放电警告......................................................... 17
12.5 Glossary................................................................ 17
13 机械、封装和可订购信息....................................... 17
6.6 Electrical Characteristics: VCC1 at 5 V ±10%, VCC2 at
3.3 V ±10% ................................................................ 5
6.7 Electrical Characteristics: VCC1 at 3.3 V ±10%, VCC2
at 5 V ±10% ............................................................... 6
6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V
±10%.......................................................................... 6
6.9 Power Dissipation ..................................................... 6
6.10 Switching Characteristics: VCC1 and VCC2 at 5 V
±10%.......................................................................... 7
6.11 Switching Characteristics: VCC1 at 5 V ±10%, VCC2
at 3.3 V ±10% ............................................................ 7
6.12 Switching Characteristics: VCC1 at 3.3 V ±10%,
VCC2 at 5 V ±10% ...................................................... 7
4 修订历史记录
日期
修订版本
注释
2015 年 12 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
VCC1
VCC2
8
1
2
3
4
7
6
5
OUTA
INB
INA
OUTB
GND2
GND1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND1
GND2
INA
NO.
4
—
—
I
Ground connection for VCC1
Ground connection for VCC2
Input, channel A
5
7
INB
3
I
Input, channel B
OUTA
OUTB
VCC1
2
O
O
—
—
Output, channel A
6
Output, channel B
1
Power supply, VCC1
Power supply, VCC2
VCC2
8
Copyright © 2015, Texas Instruments Incorporated
3
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1)
see
MIN
–0.5
–0.5
–15
MAX
UNIT
V
VCC
VI
Supply voltage(2), VCC1, VCC2
Voltage at IN, OUT
6
VCC + 0.5(3)
15
V
IO
Output current
mA
°C
TJ(max)
Tstg
Maximum junction temperature
Storage temperature
150
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Field-induced charged-device model, JEDEC Standard 22, Test Method
C101
V(ESD)
Electrostatic discharge
V
Machine model, ANSI/ESDS5.2-1996
±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM
MAX
3.6
UNIT
Supply voltage - 3.3-V operation
Supply voltage - 5-V operation
High-level output current
Low-level output current
High-level input voltage
Low-level input voltage
Signaling rate
3
4.5
–4
3.3
5
VCC1, VCC2
V
5.5
IOH
IOL
VIH
VIL
1/tui
tui
mA
mA
V
4
5.25
0.8
1
2
0
V
0
Mbps
us
Input pulse duration
1
(1)
TJ
Junction temperature
–55
136
°C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.4 Thermal Information
ISO7421-EP
D (SOIC)
8 PINS
212
THERMAL METRIC(1)
UNIT
Low-K Board
RθJA
Junction-to-ambient thermal resistance
°C/W
High-K Board
116.6
RθJC(top)
RθJB
ψJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
71.6
°C/W
°C/W
°C/W
°C/W
57.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
28.3
ψJB
56.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ±10%
TJ = –55°C to 136°C
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 6.
MIN
VCCO(1) – 0.8
VCCO – 0.1
TYP
4.6
5
MAX
UNIT
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 6.
IOL = 4 mA; see Figure 6.
IOL = 20 μA; see Figure 6.
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input threshold voltage hysteresis
400
mV
μA
IIH
IIL
High-level input current
Low-level input current
10
(1)
INx at 0 V or VCCI
–10
25
μA
CMTI Common-mode transient immunity
VI = VCCI or 0 V; see Figure 8.
50
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT)
ICC1
ICC2
Supply current for VCC1
Supply current for VCC2
2
2
4
4
DC to 1 Mbps VI = VCCI or 0 V, 15 pF load
mA
(1) VCCI = Input-side power supply, VCCO = Output-side power supply
6.6 Electrical Characteristics: VCC1 at 5 V ±10%, VCC2 at 3.3 V ±10%
TJ = –55°C to 136°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1)
IOH = –4 mA; see
Figure 6.
5-V side
VCCO
–
4.6
0.8
VOH
High-level output voltage
V
3.3-V side
VCCO – 0.4
VCCO – 0.1
3
VCC
0.2
0
IOH = –20 μA; see Figure 6,
IOL = 4 mA; see Figure 6.
IOL = 20 μA; see Figure 6.
0.4
V
VOL
Low-level output voltage
0.1
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
400
mV
10
μA
μA
(1)
INx at 0 V or VCCI
IIL
Low-level input current
–10
25
CMTI
Common-mode transient immunity
VI = VCCI or 0 V; seeFigure 8 .
40
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT)
ICC1
ICC2
Supply current for VCC1
Supply current for VCC2
2
4
mA
mA
VI = VCCI or 0 V,
15 pF load
DC to 1 Mbps
1.5
3.5
(1) VCCI = Input-side power supply, VCCO = Output-side power supply
Copyright © 2015, Texas Instruments Incorporated
5
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
6.7 Electrical Characteristics: VCC1 at 3.3 V ±10%, VCC2 at 5 V ±10%
TJ = –55°C to 136°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(1)
VCCO
–
5-V side
3.3-V side
4.6
0.8
IOH = –4 mA; see Figure 6.
VOH
High-level output voltage
V
VCCO – 0.4
VCCO – 0.1
3
VCC
0.2
0
IOH = –20 μA; see Figure 6
IOL = 4 mA; see Figure 6.
IOL = 20 μA; see Figure 6.
0.4
V
VOL
Low-level output voltage
0.1
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
400
mV
10
μA
μA
(1)
INx at 0 V or VCCI
IIL
Low-level input current
–10
25
CMTI
Common-mode transient immunity
VI = VCCI or 0 V; see Figure 8.
40
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT)
ICC1
ICC2
Supply current for VCC1
Supply current for VCC2
1.5
2
3.5
4
VI = VCCI or 0
V, 15 pF load
DC to 1 Mbps
mA
(1) VCCI = Input-side power supply, VCCO = Output-side power supply
6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±10%
TJ = –55°C to 136°C
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 6.
MIN
VCCO(1) – 0.4
VCCO – 0.1
TYP
3
MAX UNIT
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 6.
IOL = 4 mA; see Figure 6.
IOL = 20 μA; see Figure 6.
3.3
0.2
0
0.4
V
VOL
Low-level output voltage
0.1
VI(HYS) Input threshold voltage hysteresis
400
mV
IIH
IIL
High-level input current
Low-level input current
10
μA
μA
(1)
INx at 0 V or VCCI
–10
25
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V; seeFigure 8 .
40
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT)
ICC1
ICC2
Supply current for VCC1
Supply current for VCC2
1.5
1.5
3.5
3.5
DC to 1 Mbps VI = VCCI or 0 V, 15 pF load
mA
(1) VCCI = Input-side power supply, VCCO = Output-side power supply
6.9 Power Dissipation
ISO7421-EP
D (SOIC)
8 PINS
THERMAL METRIC
UNIT
VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF
Input a 1-Mbps 50% duty-cycle square wave
PD
Device power dissipation
55
mW
6
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
6.10 Switching Characteristics: VCC1 and VCC2 at 5 V ±10%
TJ = –55°C to 136°C
PARAMETER
Propagation delay time
TEST CONDITIONS
MIN
MIN
MIN
MIN
TYP
9
MAX
14
UNIT
ns
tPLH, tPHL
PWD(1)
See Figure 6.
Pulse width distortion |tPHL – tPLH
|
0.3
4
ns
tsk(pp)
tsk(o)
tr
Part-to-part skew time
4.9
3.6
ns
Channel-to-channel output skew time
Output signal rise time
ns
See Figure 6.
See Figure 7.
1
1
6
ns
tf
Output signal fall time
ns
tfs
Fail-safe output delay time from input power loss
μs
(1) Also known as pulse skew.
6.11 Switching Characteristics: VCC1 at 5 V ±10%, VCC2 at 3.3 V ±10%
TJ = –55°C to 136°C
PARAMETER
Propagation delay time
TEST CONDITIONS
See Figure 6.
TYP
10
MAX
18.5
6
UNIT
ns
tPLH, tPHL
PWD(1)
Pulse width distortion |tPHL – tPLH
|
0.5
ns
tsk(pp)
tsk(o)
tr
Part-to-part skew time
6.3
7
ns
Channel-to-channel output skew time
Output signal rise time
ns
See Figure 6.
See Figure 7.
2
2
6
ns
tf
Output signal fall time
ns
tfs
Fail-safe output delay time from input power loss
μs
(1) Also known as pulse skew.
6.12 Switching Characteristics: VCC1 at 3.3 V ±10%, VCC2 at 5 V ±10%
TJ = –55°C to 136°C
PARAMETER
Propagation delay time
TEST CONDITIONS
See Figure 6.
TYP
10
MAX
21
UNIT
ns
tPLH, tPHL
PWD(1)
Pulse width distortion |tPHL – tPLH
|
0.5
4.5
ns
tsk(pp)
tsk(o)
tr
Part-to-part skew time
8.5
ns
Channel-to-channel output skew time
Output signal rise time
10.8
ns
See Figure 6.
See Figure 7.
2
2
6
ns
tf
Output signal fall time
ns
tfs
Fail-safe output delay time from input power loss
μs
(1) Also known as pulse skew.
6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%
TJ = –55°C to 136°C
PARAMETER
Propagation delay time
TEST CONDITIONS
TYP
12
1
MAX
UNIT
ns
tPLH, tPHL
PWD(1)
22.5
5.2
Pulse width distortion |tPHL – tPLH
|
See Figure 6.
ns
tsk(pp)
tsk(o)
tr
Part-to-part skew time
6.8
ns
Channel-to-channel output skew time
Output signal rise time
7.8
ns
2
2
6
ns
See Figure 6.
See Figure 7.
tf
Output signal fall time
ns
tfs
Fail-safe output delay time from input power loss
μs
(1) Also known as pulse skew.
Copyright © 2015, Texas Instruments Incorporated
7
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
6.14 Typical Characteristics
14
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VIT+, 5 V
12
10
8
V , V
CC1 CC2
at 3.3 V
VIT+, 3.3 V
V , V
CC1 CC2
at 5 V
6
VIT−, 5 V
4
VIT−, 3.3 V
2
0
−55 −35 −15
5
25
45
65
85
105 125
−55 −35 −15
5
25
T − Free-Air Temperature − °C
A
45
65
85
105 125
T
− Free-Air Temperature − °C
A
G004
G005
Figure 1. Propagation Delay Time vs Free-Air Temperature
Figure 2. Input Voltage Switching Threshold vs Free-Air
Temperature
2.62
2.61
0
T
A
= 25°C
−10
−20
−30
−40
−50
−60
−70
−80
−90
FS+
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
V , V
CC1 CC2
at 3.3 V
FS−
25
V , V
CC1 CC2
at 5 V
−55 −35 −15
5
45
65
85
105 125
0
1
2
3
4
5
6
T
A
− Free-Air Temperature − °C
V
OH
− High-Level Output Voltage − V
G006
G007
Figure 3. Fail-Safe Voltage Threshold vs Free-Air
Temperature
Figure 4. High-Level Output Current vs High-Level Output
Voltage
80
T
A
= 25°C
70
60
50
40
30
20
10
0
V
, V
CC1 CC2
at 5 V
V
, V
CC1 CC2
at 3.3 V
0
1
2
3
4
5
6
V
OL
− Low-Level Output Voltage − V
G008
Figure 5. Low-Level Output Current vs Low-Level Output Voltage
8
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
7 Parameter Measurement Information
VCCI
VI
1.4 V
1.4 V
IN
OUT
VO
0 V
tPLH
tPHL
Input
Generator(1)
(2)
50 W
VI
CL
VOH
VOL
90%
10%
50%
50%
VO
tr
tf
(1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCCI
VCCI
VI
2.7 V
0 V
OUT
IN = 0 V
tfs
VO
VOH
(1)
50%
VO
Fail-Safe HIGH
VOL
CL
(1) CL = 15 pF ± 20% includes instrumentation and fixture capacitance.
Figure 7. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 μF 1ꢀ
C = 0.1 μF 1ꢀ
Pass-fail criteria –
output must remain
stable.
IN
OUT
S1
+
CL
(1)
VOH or VOL
–
GNDI
GNDO
–
+
VCM
(1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Common-Mode Transient Immunity Test Circuit
Copyright © 2015, Texas Instruments Incorporated
9
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
The ISO7421 digital isolator has two isolated channels. The ISO7421 provides galvanic isolation up to
2500VRMS for one minute per UL. The isolator in Figure 9 is based on a capacitive isolation barrier technique.
The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a
bandwidth from 100 kbps up to 1 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps
down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal via
the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients,
which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate
flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop
measures the durations between signal transients. If the duration between two consecutive transients exceeds a
certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from
the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Figure 9. Conceptual Block Diagram of a Digital Capacitive Isolator
10
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
8.3 Feature Description
8.3.1 Insulation Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
SPECIFICATION
UNIT
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
VPR
Maximum working insulation voltage
Input-to-output test voltage
566
VPK
VPK
t = 1 s (100% production), partial discharge 5 pC
t = 60 s (qualification)
1062
VIOTM
RS
Transient overvoltage
4242
VPK
t = 1 s (100% production)
Insulation resistance
Pollution degree
VIO = 500 V at TS
>109
2
Ω
UL 1577
VTEST = VISO = 2500 VRMS, t = 60 s (qualification)
VTEST = 1.2 x VISO = 3000 VRMS, t = 1 s (100%
production)
VISO
Isolation voltage per UL
2500
VRMS
(1) Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Installation classification
8.3.2 Package Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
L(I02)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
V
Tracking resistance (comparative
tracking index)
CTI
DTI
DIN EN 60112 (VDE 0303-11); IEC 60112
>400
Distance through the insulation
Minimum internal gap (internal clearance)
VIO = 500 V, TA = 25°C
0.014
mm
Ω
>1012
>1011
Isolation resistance, input to
output(1)
RIO
VIO = 500 V, 100°C ≤ TA ≤ max
Ω
Barrier capacitance, input to
output(1)
Input capacitance(2)
CIO
CI
VIO = 0.4 sin (2πft), f = 1 MHz
1
1
pF
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
Copyright © 2015, Texas Instruments Incorporated
11
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
SPACER
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
8.3.3 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
112
171
150
UNIT
mA
R
θJA = 212°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C
θJA = 212°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C
Safety input, output, or supply
current
IS
R
TS
Maximum safety temperature
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test
Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
180
V , V
CC1 CC2
at 3.45 V
160
140
120
100
80
V , V
CC1 CC2
at 5.25 V
60
40
20
0
0
50
100
Case Temperature − °C
150
200
G002
Figure 10. RθJC Thermal Derating Curve per VDE
12
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
8.3.4 Regulatory Information
VDE
CSA
UL
CQC
Certified according to
DIN V VDE V 0884-10 (VDE V
Recognized under UL1577
Component Recognition
Program(1)
Approved under CSA Component
Acceptance Notice #5A
Certified according to
GB4943.1-2011
0884-10):2006-12 and
DIN EN 61010-1 (VDE 0411-1):
2011-07
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK
Maximum Working Voltage, 566
VPK
Basic insulation per CSA 60950-1-
07 and IEC 60950-1 (2nd Ed),
390 VRMS maximum working
voltage
Basic Insulation, Altitude ≤
5000 m, Tropical Climate, 250
VRMS maximum working
voltage
Single Protection, 2500 VRMS
File number: E181974
Certificate number:
CQC14001109540
Certificate number: 40016131
Master contract number: 220991
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
8.4 Device Functional Modes
Table 2 shows the device functions.
Table 2. Function Table(1)
INPUT
INA, INB
OUTPUT
OUTA, OUTB
VCCI
VCCO
H
L
H
PU
PU
L
H(2)
H(2)
Open
X
PD
X
PU
PD
X
Undetermined
(1) VCCI = Input-side power supply; VCCO = Output-side power supply;
PU = Powered up (VCC ≥ 3.15 V); PD = Powered down (VCC ≤ 2.1
V); X = Irrelevant; H = High level; L = Low level
(2) In fail-safe condition, output defaults to high level.
Input
V
Output
V
CC2
V
V
CC1
CC1
CC1
1 MW
8 W
500 W
IN
OUT
13 W
Figure 11. Device I/O Schematics
Copyright © 2015, Texas Instruments Incorporated
13
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7421-EP device uses a single-ended TTL-logic switching technology. Its supply voltage range is from
3.15 V to 5.25 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in
mind that due to the single-ended design structure, digital isolators do not conform to any specific interface
standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is
typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver,
regardless of the interface type or standard.
9.2 Typical Application
ISO7421-EP can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,
transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3VISO
10 ꢀF
3
1
1
3
5
2
V
CC
D2
D1
IN
OUT
GND
TPS76333
SN6501
10 ꢀF 0.1 ꢀF
EN
GND
4, 5
10 ꢀF
MBR0520L
0.1 ꢀF
0.1 ꢀF
20 ꢁ
ISO-BARRIER
0.1 ꢀF
LOOP+
15
3
0.1 ꢀF
0.1 ꢀF
VA
VD
10
8
16
LOW
BASE
OUT
1
8
0.1 ꢀF 1 ꢀF
2
ERRLVL
V
V
CC2
CC1
DAC161P997
DV
CC
7
5
4
5
22 ꢁ
OUTA
INB
INA
DBACK
DIN
11
12
2
3
XOUT
P3.0
P3.1
ISO7421
9
MSP430
G2132
6
OUTB
6
LOOPœ
C1 C2 C3 COMA COMD
XIN
GND1
GND2
5
14 13 12
1
2
DV
SS
3 þ 22 nF
4
4
Figure 12. Isolated 4- to 20-mA Current Loop
9.2.1 Design Requirements
For applications that require isolation in place of using x-fmr to provide isolation, ISO7421-EP meets the system
needs with small size. Unlike optocouplers, which require external components to improve performance, provide
bias, or limit current, the ISO7421-EP device only requires two external bypass capacitors to operate.
14
Copyright © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
Typical Application (continued)
9.2.2 Detailed Design Procedure
ISO7421 digital isolator containing two channels has logic input and output buffer isolated by silicon dioxide
(SiO2) isolation barrier. When using ISO7421 in conjunction with isolated power supplies, these devices prevent
noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging
sensitive circuitry. ISO7421 are specified for signaling rate up to 1Mbps. These devices also transmit data with
much shorter pulse widths, in most cases, because of their fast response time. Designer must add external
filtering to remove spurious signals with input pulse duration < 20 ns.
VCC1
1
8
VCC2
0.1 µF
0.1 µF
OUTA
INB
7
6
INA
2
3
OUTB
GND2
GND1
5
4
Figure 13. Typical ISO7421-EP Circuit Hookup
9.2.3 Application Curve
100
28 Years
VIORM at 566 V
10
0
120
250
500
VIORM – Working Voltage – V
750
880
1000
G001
Figure 14. Life Expectancy vs Working Voltage
Copyright © 2015, Texas Instruments Incorporated
15
ISO7421-EP
ZHCSEG4 –DECEMBER 2015
www.ti.com.cn
10 Power Supply Recommendations
Install high quality X7R capacitors typically 0.1 µF close to the device. To ensure reliable operation at all data
rates and supply voltages, a 0.1 µF bypass capacitor is recommended at input and output supply pins (VCC1 and
VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side
power supply is available in an application, isolated power can be generated for the secondary-side with the help
of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design
and transformer selection recommendations are available in SN6501 datasheet (SLLSEA0).
11 Layout
11.1 Layout Guidelines
There are several signals that conduct fast charging current or voltages that can interact with stray inductance or
parasitic capacitors to generate noise. Thus to eliminate these problems Vin ins of ISO7421 should be bypass to
gnd with low esr ceramic bypass capacitor with X7R dielectric. A minimum of four layers is required to
accomplish a low EMI PCB design (see Figure 15). Layer stacking should be in the following order (top-to-
bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
0 ~ 4.5
space free
from planes,
traces , pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 15. Recommended Layer Stack
16
版权 © 2015, Texas Instruments Incorporated
ISO7421-EP
www.ti.com.cn
ZHCSEG4 –DECEMBER 2015
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
《SN6501 用于隔离电源的变压器驱动器》，SLLSEA0
《隔离相关术语》，SLLA353
《数字隔离器设计指南》，SLLA284
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
17
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7421MDREP
V62/16605-01XE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
7421EP
7421EP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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