ISO7710D [TI]
EMC 性能优异的单通道、增强型数字隔离器 | D | 8 | -55 to 125;
| 型号： | ISO7710D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EMC 性能优异的单通道、增强型数字隔离器 | D | 8 | -55 to 125 |
| 文件： | 总42页 (文件大小：1677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7710
ZHCSFQ7D –NOVEMBER 2016 –REVISED MARCH 2023
EMC 性能优异的ISO7710 高速单通道增强型数字隔离器
1 特性
3 说明
• 100 Mbps 数据速率
• 稳健可靠的隔离栅：
ISO7710 器件是一款高性能单通道数字隔离器，可提
供符合 UL 1577 的 5000VRMS （ DW 封装） 和
3000VRMS（D 封装）隔离额定值。此器件还通过了
VDE、TUV、CSA 和CQC 认证。
– 在1500VRMS 工作电压下预计寿命超过100 年
– 隔离等级高达5000 VRMS
– 浪涌能力高达12.8 kV
在隔离互补金属氧化物半导体 (CMOS) 或者低电压互
补金属氧化物半导体 (LVCMOS) 数字 I/O 的同时，
ISO7710 器件还可提供高电磁抗扰度和低辐射，同时
具备低功耗特性。隔离通道的逻辑输入和输出缓冲器由
双电容二氧化硅 (SiO2) 绝缘栅相隔离。如果输入功率
或信号出现损失，不带后缀 F 的器件默认输出高电
平，带后缀 F 的器件默认输出低电平。更多详细信
息，请参阅器件功能模式部分。
– CMTI 典型值为±100kV/μs
• 宽电源电压范围：2.25V 至5.5V
• 2.25V 至5.5V 电平转换
• 默认输出高电平(ISO7710) 和低电平(ISO7710F)
选项
• 宽温度范围：-55°C 至125°C
• 低功耗，1Mbps 时的
电流典型值为1.7mA
该器件与隔离式电源搭配使用，有助于防止数据总线
（例如，RS-485、RS-232 和 CAN ）或其他电路上的
噪声电流进入本地接地以及干扰或损坏敏感电路。凭借
创新型芯片设计和布线技术，ISO7710 器件的电磁兼
容性得到了显著增强，可缓解系统级 ESD、EFT 和浪
涌问题并符合辐射标准。ISO7710 器件可提供 16 引脚
SOIC 宽体(DW) 和8 引脚SOIC 窄体(D) 封装。
• 低传播延迟：典型值为11ns
（5V 电源）
• 优异的电磁兼容性(EMC)
– 系统级ESD、EFT 和浪涌抗扰性
– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放
电保护
– 低辐射
• 宽体SOIC (DW-16) 和窄体SOIC (D-8) 封装选项
• 提供汽车版本：ISO7710-Q1
• 安全相关认证
器件信息
封装尺寸（标称值）
器件型号
封装
SOIC (D)
4.90mm x 3.91mm
10.30mm x 7.50mm
ISO7710
– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标
准的VDE 增强型绝缘
SOIC (DW)
V
V
CC2
CC1
Series Isolation
Capacitors
– UL 1577 组件认证计划
– IEC 62368-1、IEC 61010-1、IEC 60601-1 和
GB 4943.1 认证
OUT
IN
2 应用
• 工业自动化
• 电机控制
• 电源
GND2
GND1
Copyright © 2019, Texas Instruments Incorporated
• 光伏逆变器
• 医疗设备
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSER9
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Table of Contents
6.18 Insulation Characteristics Curves........................... 17
6.19 Typical Characteristics............................................18
7 Parameter Measurement Information..........................19
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................27
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Documentation Support.......................................... 29
12.2 Receiving Notification of Documentation Updates..29
12.3 支持资源..................................................................29
12.4 Trademarks.............................................................29
12.5 静电放电警告.......................................................... 29
12.6 术语表..................................................................... 29
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 5
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................8
6.5 Power Ratings.............................................................8
6.6 Insulation Specifications............................................. 9
6.7 Safety-Related Certifications.....................................11
6.8 Safety Limiting Values...............................................11
6.9 Electrical Characteristics—5-V Supply..................... 13
6.10 Supply Current Characteristics—5-V Supply..........13
6.11 Electrical Characteristics—3.3-V Supply.................14
6.12 Supply Current Characteristics—3.3-V Supply.......14
6.13 Electrical Characteristics—2.5-V Supply ............... 15
6.14 Supply Current Characteristics—2.5-V Supply.......15
6.15 Switching Characteristics—5-V Supply...................16
6.16 Switching Characteristics—3.3-V Supply................16
6.17 Switching Characteristics—2.5-V Supply................17
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (April 2020) to Revision D (March 2023)
Page
• 将整个文档中的标准名称从“DIN V VDE V 0884-11:2017-01”更改为“DIN EN IEC 60747-17 (VDE
0884-17)”..........................................................................................................................................................1
• 通篇删除了对标准IEC/EN/CSA 60950-1 的引用............................................................................................... 1
• 通篇删除了所有标准名称中的标准版本和年份参考............................................................................................ 1
• Added Maximum impulse voltage (VIMP) specification per DIN EN IEC 60747-17 (VDE 0884-17)....................9
• Changed test conditions and values of Maximum surge isolation voltage (VIOSM) specification per DIN EN IEC
60747-17 (VDE 0884-17)....................................................................................................................................9
• Clarified method b test conditions of Apparent charge (qPD)..............................................................................9
• Changed working voltage lifetime margin from: 87.5% to: 50%, minimum required insulation lifetime from:
37.5 years to: 30 years and insulation lifetime per TDDB from: 135 years to: 169 years in per DIN EN IEC
60747-17 (VDE 0884-17)..................................................................................................................................25
• Changed 图9-5 per DIN EN IEC 60747-17 (VDE 0884-17).............................................................................25
Changes from Revision B (March 2017) to Revision C (April 2020)
Page
• 通篇进行了编辑性和修饰性更改.........................................................................................................................1
• 将“隔离栅寿命：超过40 年”更改为“在1500VRMS 工作电压下预计寿命超过 100 年”（位于节1）..........1
• 在节1 中添加了“隔离等级高达 5000VRMS”....................................................................................................1
• 在节1 中添加了“浪涌能力高达 12.8kV”.........................................................................................................1
• 在节1 中添加了“在整个隔离栅具有 ±8kV IEC 61000-4-2 接触放电保护”......................................................1
• 添加了“提供汽车版本：ISO7710-Q1”（位于节1）....................................................................................... 1
• 将“符合DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 标准的VDE 增强型绝缘”更改为“符合DIN VDE
V 0884-11:2017-01 标准的VDE 增强型绝缘”（位于节1）............................................................................. 1
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• 使用节1 中的标准名称，将CSA、CQC 和TUV 要点合并为一个要点..............................................................1
• 删除了节1 中的“完成DW-16 封装的VDE、UL、CSA 和TUV 认证；已规划其他所有认证”要点................1
• 更新了图3-1，以便显示两个串联的隔离电容器，而不是单个隔离电容器......................................................... 1
•
Added "Contact discarge per IEC 61000-4-2" specification of 8000V ............................................................. 6
• Changed "Signaling rate" to "Data rate" and added table note...........................................................................7
• Updated DW-16 package VIORM and VIOWM values............................................................................................9
• Added TDDB figure reference to VIOWM ............................................................................................................ 9
• Updated VIOSM, VIOTM, qpd test conditions..........................................................................................................9
• Corrected ground symbols for "Input (Devices with F suffix)" in 节8.4.1 ........................................................ 22
• Fixed 图9-2 INPUT wire connection................................................................................................................ 24
• Added 节9.2.3.1 sub-section under 节9.2.3 section....................................................................................... 25
• Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' to 节12.1
section.............................................................................................................................................................. 29
Changes from Revision A (December 2016) to Revision B (March 2017)
Page
• Added D-8 values for TUV................................................................................................................................11
• Changed the Electrostatic Discharge Caution statement ................................................................................ 29
Changes from Revision * (November 2016) to Revision A (December 2016)
Page
• 将特性从IEC 60950-1、IEC 60601-1 和IEC 61010-1 终端设备标准更改为IEC 60950-1 和IEC 60601-1 终
端设备标准..........................................................................................................................................................1
• Added Climatic category.....................................................................................................................................9
• Updated CSA column and changed DW package to (DW-16)..........................................................................11
• Changed tie TYP value from 1.5 to 1 in Switching Characteristics tables throughout the document................16
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5 Pin Configuration and Functions
GND1
NC
1
2
3
4
5
6
7
8
16 GND2
15 NC
14
V
V
CC2
CC1
IN
13 OUT
12 NC
11 NC
10 NC
9 GND2
NC
NC
GND1
NC
图5-1. DW Package 16-Pin SOIC Top View
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1
2
3
4
8
7
6
V
V
CC2
CC1
IN
NC
OUT
V
CC1
GND1
5 GND2
图5-2. D Package 8-Pin SOIC Top View
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DW
D
1, 3
8
VCC1
VCC2
GND1
GND2
IN
3
Power supply, VCC1
Power supply, VCC2
Ground connection for VCC1
Ground connection for VCC2
Input channel
—
—
—
—
I
14
1, 7
9, 16
4
4
5
2
OUT
13
6
O
Output channel
2, 5, 6, 8, 10 ,11, 12,
15
NC
7
Not connect pin; it has no internal connection
—
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6 Specifications
6.1 Absolute Maximum Ratings
See(1)
MIN
-0.5
-0.5
-15
MAX
UNIT
V
VCC1, VCC2
Supply Voltage (2)
Voltage at INx, OUTx
Output current
6
V
VCCX + 0.5 (3)
V
IO
15
150
150
mA
°C
TJ
Tstg
Junction temperature
Storage temperature
-65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
VESD
Electrostatic discharge
±1500
±8000
V
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
V
VCC1, VCC2 Supply voltage
2.25
VCC(UVLO+) UVLO threshold when supply voltage is rising
VCC(UVLO-) UVLO threshold when supply voltage is falling
VHYS(UVLO) Supply voltage UVLO hysteresis
VCC2 = 5 V
2
1.8
2.25
V
1.7
100
-4
V
200
mV
IOH
High level output current
VCC2 = 3.3 V
VCC2 = 2.5 V
VCC2 = 5 V
-2
mA
mA
-1
4
IOL
Low level output current
VCC2 = 3.3 V
VCC2 = 2.5 V
2
1
VIH
High level Input voltage
Low level Input voltage
Data Rate
0.7 x VCC1
VCC1
V
V
VIL
0
0
0.3 x VCC1
100
DR((1))
Mbps
°C
TA
Ambient temperature
-55
25
125
(1) 100 Mbps is the maximum specified data rate, although higher data rates are possible.
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UNIT
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6.4 Thermal Information
ISO7710
THERMAL METRIC ((1))
DW (SOIC)
(16-Pin)
D(SOIC)
(8-Pin)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
94.4
57.3
57.1
40.0
56.8
146.1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
63.1
80.0
9.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
79.0
ψJB
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7710
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
50
12.5
37.5
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 50-MHz 50% duty cycle
square wave
PD1
PD2
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6.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
UNIT
DW-16
D-8
IEC 60664-1
CLR
CPG
DTI
External clearance(1)
Shortest terminal-to-terminal distance through air
Shortest terminal-to-terminal distance across the package surface
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
According to IEC 60664-1
8
4
4
mm
mm
µm
V
External creepage(1)
8
Distance through the insulation
Comparative tracking index
Material Group
21
21
CTI
>600
I
>600
I
I-IV
I-III
n/a
n/a
Rated mains voltage ≤150 VRMS
I–IV
I–IV
I–IV
I-III
Rated mains voltage ≤300 VRMS
Overvoltage category per IEC
60664-1
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak
VIORM
AC voltage (bipolar)
2121
637
VPK
isolation voltage
AC voltage; time-dependent dielectric breakdown (TDDB) test,
see 图9-5
1500
2121
8000
8000
450
VRMS
VDC
VPK
VPK
VPK
Maximum working isolation
voltage
VIOWM
DC voltage
637
Maximum transient isolation
voltage
VTEST = VIOTM , t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
4242
5000
VIMP
Maximum impulse voltage((3))
Tested in air, 1.2/50-μs waveform per IEC 62368-1
Maximum surge isolation
voltage((4))
V
IOSM ≥1.3 x VIMP; Tested in oil (qualification test),
VIOSM
12800 10000
1.2/50-µs waveform per IEC 62368-1
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM , tm = 10 s
≤5
≤5
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
qpd
Apparent charge((5))
Vpd(m) = 1.6 × VIORM , tm = 10 s
pC
Method b: At routine test (100% production) and preconditioning
(type test);
Vini = 1.2 x VIOTM, tini = 1 s;
≤5
≤5
Vpd(m) = 1.875 x VIORM (ISO7710), tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)
Barrier capacitance, input to
output(6)
CIO
RIO
~0.4
~0.4
pF
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
> 1012 > 1012
> 1011 > 1011
Insulation resistance((6))
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
> 109
2
> 109
2
Pollution degree
Climatic category
55/125/ 55/125/
21
21
UL 1577
VTEST = VISO , t = 60 s (qualification);
VTEST = 1.2 × VISO , t = 1 s (100% production)
VISO
Withstand isolation voltage
5000
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
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(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to DIN
EN IEC 60747-17 (VDE
0884-17)
Certified according to UL
1577 Component
Recognition Program
Certified according to IEC
62368-1 and IEC 60601-1
Certified according to
GB4943.1
Certified according to EN
61010-1 and EN 62368-1
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Maximum transient
Reinforced insulation per
DW-16: Reinforced
Insulation, Altitude ≤
5000 m, Tropical Climate,
700 VRMS maximum
working voltage;
D-8: Basic Insulation,
Altitude ≤5000 m,
Tropical Climate, 400
VRMS maximum working
voltage
isolation voltage, 8000 VPK CSA 62368-1 and IEC
(DW-16, Reinforced) and 62368-1, 800 VRMS
4242 VPK (D-8); Maximum (DW-16) and 400 VRMS
Reinforced insulation per
EN 61010-1 up to working
voltage of 600 VRMS
(DW-16) and 300 VRMS
(D-8) 5000 VRMS (DW-16)
and 3000 VRMS (D-8)
Reinforced insulation per
EN 62368-1 up to working
voltage of 800 VRMS
(DW-16) and 400 VRMS
(D-8)
repetitive peak isolation
(D-8) max working voltage DW-16: Single
(pollution degree 2, protection, 5000 VRMS
D-8: Single protection,
637 VPK (D-8); Maximum 2 MOPP (Means of Patient 3000 VRMS
voltage, 2121 VPK
;
(DW-16, Reinforced) and material group I);
surge isolation voltage,
12800 VPK (DW-16,
Reinforced) and 10000
VPK (D-8)
Protection) per CSA
60601-1 and IEC 60601-1,
250 VRMS (DW-16) max
working voltage
Certificate numbers:
CQC21001304083
(DW-16)
File number:
E181974
Certificate number:
40040142
Master contract number:
220991
Client ID number: 77311
CQC15001121656 (D-8)
6.8 Safety Limiting Values
Safety limiting((1)) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-16 PACKAGE
R
θJA =94.4°C/W, VI = 5.5 V, TJ = 150°C, TA
241
368
482
= 25°C, see 图6-1
θJA = 94.4°C/W, VI = 3.6 V, TJ = 150°C, TA
= 25°C, see 图6-1
θJA = 94.4°C/W, VI = 2.75 V, TJ = 150°C, TA
= 25°C, see 图6-1
θJA = 94.4°C/W, TJ = 150°C, TA = 25°C,
see 图6-2
R
Safety input, output, or supply
current
IS
mA
R
R
Safety input, output, or total
power
PS
TS
1324
150
mW
°C
Maximum safety temperature
D-8 PACKAGE
R
θJA =146.1°C/W, VI = 5.5 V, TJ = 150°C, TA
156
238
311
= 25°C, see 图6-3
RθJA = 146.1°C/W, VI = 3.6 V, TJ = 150°C, TA
Safety input, output, or supply
IS
mA
current (1)
= 25°C, see 图6-3
RθJA = 146.1°C/W, VI = 2.75 V, TJ = 150°C,
TA = 25°C, see 图6-3
R
θJA = 146.1°C/W, TJ = 150°C, TA = 25°C,
Safety input, output, or total
power (1)
PS
TS
856
150
mW
°C
see 图6-4
Maximum safety temperature (1)
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
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PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -4 mA; see 图7-1
IOL = 4 mA; see 图7-1
MIN
TYP
4.8
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input threshold voltage
Falling input threshold voltage
Input threshold voltage hysteresis
High-level input current
VCC2 - 0.4
V
VOL
0.2
0.4
V
V
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.6 x VCC1
0.4 x VCC1
0.2 x VCC1
0.7 x VCC1
0.3 x VCC1
0.1 x VCC1
V
V
VIH = VCC1 at INx
VIL = 0 V at INx
10
µA
µA
IIL
Low-level input current
-10
85
VI = VCC1 or 0 V, VCM = 1200 V;
see 图7-3
CMTI
CI
Common mode transient immunity
Input Capacitance ((1))
100
2
kV/μs
VI = VCC/ 2 + 0.4×sin(2πft), f =
1 MHz, VCC = 5 V;
pF
(1) Measured from input pin to same side ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7710
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.5
0.6
1.6
0.6
1.1
0.6
1.1
1.1
1.4
5.9
0.8
1
VI = VCC1(ISO7710), VI = 0 V (ISO7710 with F suffix)
VI = 0V (ISO7710), VI = VCC1 (ISO7710 with F suffix)
1 Mbps
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
2.5
1
1.5
mA
1.1
1.6
1.6
2
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -2mA ; see 图7-1
IOL = 2mA ; see 图7-1
MIN
TYP
3.2
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input threshold voltage
Falling input threshold voltage
VCC2 - 0.3
V
VOL
0.1
0.3
V
V
V
VIT+(IN)
VIT-(IN)
0.6 x VCC1
0.4 x VCC1
0.7 x VCC1
0.3 x VCC1
0.1 x VCC1
Input threshold voltage
hysteresis
VI(HYS)
0.2 x VCC1
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCC1 at INx
VIL = 0 V at INx
10
µA
µA
-10
85
VI = VCC1 or 0 V, VCM = 1200 V;
see 图7-3
Common mode transient
immunity
CMTI
100
kV/µs
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7710
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.5
0.6
1.6
0.6
1.1
0.6
1
0.8
1
VI = VCC1 (ISO7710), VI = 0 V (ISO7710 with F suffix)
VI = 0V (ISO7710), VI = VCC1 (ISO7710 with F suffix)
1 Mbps
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
2.5
1
1.5
mA
1
1.6
1.4
1.8
5.3
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
1.1
1.3
4.3
100 Mbps
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -1mA ; see 图7-1
IOL = 1mA ; see 图7-1
MIN
TYP
2.45
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Rising input threshold voltage
Falling input threshold voltage
VCC2 - 0.2
V
VOL
0.05
0.2
V
V
V
VIT+(IN)
VIT-(IN)
0.6 x VCC1
0.4 x VCC1
0.7 x VCC1
0.3 x VCC1
0.1 x VCC1
Input threshold voltage
hysteresis
VI(HYS)
0.2 x VCC1
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCC1 at INx
VIL = 0 V at INx
10
µA
µA
-10
85
VI = VCC1 or 0 V, VCM = 1200 V;
see 图7-3
Common mode transient
immunity
CMTI
100
kV/µs
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
CURRENT
PARAMETER
ISO7710
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
0.5
0.6
1.6
0.6
1.1
0.6
1.1
0.9
1.2
3.4
0.8
1
VI = VCC1 (ISO7710), VI = 0 V (ISO7710 with F suffix)
VI = 0V (ISO7710), VI = VCC1 (ISO7710 with F suffix)
1 Mbps
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Supply current - DC signal
Supply current - AC signal
2.5
1
1.5
mA
1
1.5
1.4
1.6
4.4
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
MAX
16
UNIT
ns
tPLH, tPHL
Propagation delay time
Pulse width distortion((1)) |tPHL –tPLH
Part-to-part skew time ((2))
Output signal rise time
6
See 图7-1
PWD
tsk(pp)
tr
0.6
4.9
4.5
3.9
3.9
ns
|
ns
1.8
1.9
ns
See 图7-1
tf
Output signal fall time
ns
Measured from the time VCC1 goes
below 1.7V. See 图7-2
Default output delay time from input
power loss
tDO
tie
0.1
1
0.3
μs
216 –1 PRBS data at 100 Mbps
Time interval error
ns
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
11
MAX
16
5
UNIT
ns
tPLH, tPHL
Propagation delay time
Pulse width distortion((1)) |tPHL –tPLH
Part-to-part skew time ((2))
Output signal rise time
6
See 图7-1
PWD
tsk(pp)
tr
0.1
ns
|
4.5
3
ns
0.7
0.7
ns
See 图7-1
tf
Output signal fall time
3
ns
Measured from the time VCC1 goes
below 1.7V. See 图7-2
Default output delay time from input
power loss
tDO
tie
0.1
1
0.3
μs
216 –1 PRBS data at 100 Mbps
Time interval error
ns
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX
18.5
5.1
UNIT
ns
tPLH, tPHL
Propagation delay time
Pulse width distortion(1) |tPHL –tPLH
Part-to-part skew time((2))
Output signal rise time
Output signal fall time
7.5
See 图7-1
PWD
tsk(pp)
tr
0.2
ns
|
4.6
ns
1
1
3.5
ns
See 图7-1
tf
3.5
ns
Measured from the time VCC1 goes
below 1.7V. See 图7-2
Default output delay time from input
power loss
tDO
tie
0.1
1
0.3
μs
216 –1 PRBS data at 100 Mbps
Time interval error
ns
(1) Also known as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.18 Insulation Characteristics Curves
600
500
400
300
200
100
0
1400
1200
1000
800
600
400
200
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D002
D001
图6-2. Thermal Derating Curve for Limiting Power
图6-1. Thermal Derating Curve for Limiting Current
per VDE for DW-16 Package
per VDE for DW-16 Package
350
900
800
700
600
500
400
300
200
100
0
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
0
50
100
Ambient Temperature (èC)
150
200
Ambient Temperature (èC)
D003
D004
图6-3. Thermal Derating Curve for Limiting Current 图6-4. Thermal Derating Curve for Limiting Power
per VDE for D-8 Package
per VDE for D-8 Package
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6.19 Typical Characteristics
7
2.5
2
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
6
5
4
3
2
1
0
1.5
1
0.5
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D006
D005
TA = 25°C
CL = No Load
TA = 25°C
CL = 15 pF
图6-6. ISO7710 Supply Current vs Data Rate (With
图6-5. ISO7710 Supply Current vs Data Rate (With
No Load)
15 pF Load)
6
5
4
3
2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0.1
0
0
0
5
10
Low-Level Output Current (mA)
15
-15
-10 -5
High-Level Output Current (mA)
0
D012
D011
TA = 25°C
TA = 25°C
图6-8. Low-Level Output Voltage vs Low-Level
图6-7. High-Level Output Voltage vs High-level
Output Current
Output Current
2.10
2.05
2.00
1.95
1.90
1.85
1.80
14
13
12
11
10
1.75
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
1.70
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
9
8
1.65
1.60
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
-55
-25
5
35
65
95
125
Free-Air Temperature (èC)
D009
Free Air Temperature (èC)
D010
图6-9. Power Supply Undervoltage Threshold vs
图6-10. Propagation Delay Time vs Free-Air
Free-Air Temperature
Temperature
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7 Parameter Measurement Information
V
CC1
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
O
50 ꢀ
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr ≤3 ns, tf ≤3ns, ZO
= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图7-1. Switching Characteristics Test Circuit and Voltage Waveforms
V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
图7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CC1
CC1
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
EN
V
or V
OH
OL
C
L
œ
See Note A
GND1
GND2
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图7-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7710 device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. The device also
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, 图8-1, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
图8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
图8-2 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图8-2. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
The ISO7710 device is available in two default output state options to enable a variety of application uses. 表8-1
lists the device features.
表8-1. Device Features
MAXIMUM DATA
RATE
CHANNEL
DIRECTION
DEFAULT OUTPUT
STATE
PART NUMBER
PACKAGE
RATED ISOLATION(1)
DW-16
D-8
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
ISO7710
100 Mbps
100 Mbps
1 Forward, 0 Reverse
1 Forward, 0 Reverse
High
Low
DW-16
D-8
ISO7710F
(1) See the Safety-Related Certifications section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7710
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
表8-2 lists the functional modes of ISO7710 device.
表8-2. Function Table
INPUT
(IN)(3)
OUTPUT
(OUT)
VCC1
VCC2
COMMENTS
H
L
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU(1)
PU
Default mode: When IN is open, the corresponding channel output goes to its
default logic state. Default is High for ISO7710 and Low for ISO7710F.
Open
Default
Default mode: When VCC1 is unpowered, a channel output assumes the logic
state based on the selected default option. Default is High for ISO7710 and
Low for ISO7710F.
PD
X
PU
PD
X
Default
When VCC1 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCC1 transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCC2 is unpowered, a channel output is undetermined (2)
.
X
Undetermined
When VCC2 transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
(1) PU = Powered up (VCC ≥2.25 V); PD = Powered down (VCC ≤1.7 V); X = Irrelevant; H = High level; L = Low level
(2) The outputs are in undetermined state when 1.7 V < VCC1, VCC2 < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
Input (Devices with F suffix)
V
V
V
V
CCI
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
Output
V
CCO
~20 ꢀ
OUTx
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图8-3. Device I/O Schematics
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO7710 device is a high-performance, single-channel digital isolator. The device uses single-ended CMOS-
logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2
.
When designing with digital isolators, keep in mind that because of the single-ended design structure, digital
isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7710 device can be used with Texas Instruments' mixed signal microcontroller, CAN transceiver,
transformer driver, and low-dropout voltage regulator to create an Isolated CAN Interface as shown below.
VS
10 ꢀF
3.3 V
2
MBR0520L
Vcc
1:1.33
ISO 3.3V
3
1
1
5
2
D2
D1
IN
OUT
GND
TPS76333
SN6501
10 ꢀF
0.1 ꢀF
10 ꢀF
3
EN
MBR0520L
GND
GND
4
5
ISO Barrier
0.1 ꢀF
5
4
GND2
GND1
IN
3
0.1 ꢀF
6
8
2
ISO7710
OUT
VCC
RS
8
10 ꢁ (optional)
10 ꢁ (optional)
1,3
4
1
VCC2
VCC1
R
CANH
29,57
7
6
0.1 ꢀF
0.1 ꢀF
SN65HVD231
V
DDIO
26
25
D
CANL
Vref
CANRXA
TMS320F28035PAG
CANTXA
0.1 ꢀF
GND
5
0.1 ꢀF
SM712
2
VCC1
VCC2
OUT
1,3
2
8
6
V
SS
IN
ISO7710
6,28
GND1
GND2
4
5
4.7 nF /
2 kV
Copyright © 2016, Texas Instruments Incorporated
图9-1. Isolated CAN Interface
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9.2.1 Design Requirements
To design with this device, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETER
VALUE
2.25 V to 5.5 V
0.1 µF
Supply voltage, VCC1 and VCC2
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require components to improve performance, provide bias, or limit current, the
ISO7710 device only requires two external bypass capacitors to operate.
VCC1
VCC2
2 mm
2 mm
maximum
from VCC1
maximum
from VCC2
0.1 …F
0.1 …F
1
2
8
7
INPUT
IN
3
4
OUT 6
5
OUTPUT
GND2
GND1
图9-2. Typical ISO7710 Circuit Hook-up
9.2.3 Application Curve
The following typical eye diagram of the ISO7710 device indicates low jitter and wide open eye at the maximum
data rate of 100 Mbps.
Time = 3.5 ns / div
图9-3. ISO7710 Eye Diagram at 100 Mbps PRBS, 5-V Supplies and 25°C
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9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 9-4 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 50% for
lifetime which translates into minimum required insulation lifetime of 30 years at a working voltage that's 20%
higher than the specified value.
图 9-5 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 169 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified up to 1500 VRMS and D-8 package up to 450
VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 169 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图9-4. Test Setup for Insulation Lifetime Measurement
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图9-5. Insulation Lifetime Projection Data
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505A. For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501 Transformer Driver for Isolated Power Supplies or SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 11-1). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Digital Isolator Design Guide
• Isolation Glossary
• How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
• SN6501 Transformer Driver for Isolated Power Supplies
• SN65HVD23x 3.3-V CAN Bus Transceivers
• TMS320F28035 Piccolo™ Microcontrollers
• TPS76333 Low-Power 150-mA Low-Dropout Linear Regulators
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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ZHCSFQ7D –NOVEMBER 2016 –REVISED MARCH 2023
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSDE
METAL
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
5
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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ZHCSFQ7D –NOVEMBER 2016 –REVISED MARCH 2023
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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ZHCSFQ7D –NOVEMBER 2016 –REVISED MARCH 2023
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
R0.05 TYP
14X (1.27)
R0.05 TYP
9
9
8
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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ZHCSFQ7D –NOVEMBER 2016 –REVISED MARCH 2023
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (0.6)
16X (2)
1
1
16
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7710D
ISO7710DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
7710
7710
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7710DW
ISO7710DWR
ISO7710FD
DW
DW
D
16
16
8
ISO7710
ISO7710
7710F
ISO7710FDR
ISO7710FDW
ISO7710FDWR
D
8
7710F
DW
DW
16
16
ISO7710F
ISO7710F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7710 :
Automotive : ISO7710-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7710DR
ISO7710DWR
ISO7710DWR
ISO7710FDR
ISO7710FDWR
ISO7710FDWR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
2500
2000
2000
2500
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
16.4
12.4
16.4
16.4
6.4
5.2
2.1
2.7
2.7
2.1
2.7
2.7
8.0
12.0
12.0
8.0
12.0
16.0
16.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
DW
DW
D
16
16
8
10.75 10.7
10.75 10.7
6.4
5.2
DW
DW
16
16
10.75 10.7
10.75 10.7
12.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7710DR
ISO7710DWR
ISO7710DWR
ISO7710FDR
ISO7710FDWR
ISO7710FDWR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
2500
2000
2000
2500
2000
2000
350.0
356.0
350.0
350.0
350.0
356.0
350.0
356.0
350.0
350.0
350.0
356.0
43.0
35.0
43.0
43.0
43.0
35.0
DW
DW
D
16
16
8
DW
DW
16
16
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Mar-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7710D
ISO7710DW
ISO7710DW
ISO7710FD
ISO7710FDW
ISO7710FDW
D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
75
40
40
75
40
40
505.46
506.98
507
6.76
12.7
3810
4826
5080
3810
4826
5080
4
DW
DW
D
16
16
8
6.6
6.6
4
12.83
6.76
505.46
506.98
507
DW
DW
16
16
12.7
6.6
6.6
12.83
Pack Materials-Page 3
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