ISO7740_V02 [TI]
ISO774x High-Speed, Robust-EMC Reinforced and Basic Quad-Channel Digital Isolators;
| 型号： | ISO7740_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ISO774x High-Speed, Robust-EMC Reinforced and Basic Quad-Channel Digital Isolators |
| 文件： | 总52页 (文件大小：2920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7740, ISO7741, ISO7742
SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
ISO774x High-Speed, Robust-EMC Reinforced and Basic Quad-Channel Digital Isolators
1 Features
3 Description
The ISO774x devices are high-performance, quad-
channel digital isolators with 5000 VRMS (DW
package) and 3000 VRMS (DBQ package) isolation
ratings per UL 1577. This family includes devices with
reinforced insulation ratings according to VDE, CSA,
TUV and CQC. The ISO7741B device is designed for
applications that require basic insulation ratings only.
1
•
•
100 Mbps data rate
Robust isolation barrier:
–
>100-year projected lifetime at 1500 VRMS
working voltage
–
–
–
Up to 5000 VRMS isolation rating
Up to 12.8 kV surge capability
±100 kV/μs typical CMTI
The ISO774x devices provide high electromagnetic
immunity and low emissions at low power
consumption, while isolating CMOS or LVCMOS
digital I/Os. Each isolation channel has a logic input
and output buffer separated by a double capacitive
silicon dioxide (SiO2) insulation barrier. These
devices come with enable pins which can be used to
put the respective outputs in high impedance for
multi-master driving applications and to reduce power
consumption. The ISO7740 device has all four
channels in the same direction, the ISO7741 device
has three forward and one reverse-direction
channels, and the ISO7742 device has two forward
and two reverse-direction channels. If the input power
or signal is lost, default output is high for devices
without suffix F and low for devices with suffix F. See
the Device Functional Modes section for further
details.
•
•
•
Wide supply range: 2.25 V to 5.5 V
2.25-V to 5.5-V level translation
Default output high (ISO774x) and low
(ISO774xF) options
•
•
Wide temperature range: –55°C to 125°C
Low power consumption, typical 1.5 mA per
channel at 1 Mbps
•
•
Low propagation delay: 10.7 ns typical
(5-V Supplies)
Robust electromagnetic compatibility (EMC)
–
–
System-level ESD, EFT, and surge immunity
±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
–
Low emissions
Device Information(1)
•
Wide-SOIC (DW-16) and QSOP (DBQ-16)
package options
PART NUMBER
ISO7740
ISO7741
ISO7742
PACKAGE
BODY SIZE (NOM)
SOIC (DW)
10.30 mm × 7.50 mm
•
•
Automotive version available: ISO774x-Q1
SSOP (DBQ)
SOIC (DW)
4.90 mm × 3.90 mm
10.30 mm × 7.50 mm
Safety-related certifications:
ISO7741B
–
–
–
DIN VDE V 0884-11:2017-01
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
UL 1577 component recognition program
CSA, CQC, and TUV certifications
Simplified Schematic
2 Applications
•
•
•
•
•
Industrial automation
Motor control
VCCO
VCCI
Power supplies
Solar inverters
Series Isolation
Capacitors
INx
OUTx
ENx
Medical equipment
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7740, ISO7741, ISO7742
SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
www.ti.com
Table of Contents
7.18 Insulation Characteristics Curves ......................... 20
7.19 Typical Characteristics.......................................... 21
Parameter Measurement Information ................ 23
Detailed Description ............................................ 25
9.1 Overview ................................................................. 25
9.2 Functional Block Diagram ....................................... 25
9.3 Feature Description................................................. 26
9.4 Device Functional Modes........................................ 27
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description Continued .......................................... 5
Pin Configuration and Functions......................... 6
Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 9
7.5 Power Rating............................................................. 9
7.6 Insulation Specifications.......................................... 10
7.7 Safety-Related Certifications................................... 11
7.8 Safety Limiting Values ............................................ 11
7.9 Electrical Characteristics—5-V Supply ................... 12
7.10 Supply Current Characteristics—5-V Supply........ 13
7.11 Electrical Characteristics—3.3-V Supply .............. 14
7.12 Supply Current Characteristics—3.3-V Supply..... 15
7.13 Electrical Characteristics—2.5-V Supply .............. 16
7.14 Supply Current Characteristics—2.5-V Supply..... 17
7.15 Switching Characteristics—5-V Supply................. 18
7.16 Switching Characteristics—3.3-V Supply.............. 18
7.17 Switching Characteristics—2.5-V Supply.............. 19
8
9
10 Application and Implementation........................ 29
10.1 Application Information.......................................... 29
10.2 Typical Application ................................................ 29
11 Power Supply Recommendations ..................... 32
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
12.2 Layout Example .................................................... 33
13 Device and Documentation Support ................. 34
13.1 Documentation Support ........................................ 34
13.2 Related Links ........................................................ 34
13.3 Receiving Notification of Documentation Updates 34
13.4 Community Resources.......................................... 34
13.5 Trademarks........................................................... 34
13.6 Electrostatic Discharge Caution............................ 34
13.7 Glossary................................................................ 35
14 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (May 2019) to Revision G
Page
•
•
•
Added ISO7741B device to the data sheet for applications that require basic insulation only.............................................. 1
Combined CSA, CQC, and TUV Features bullets into a single bullet ................................................................................... 1
Deleted "All certifications complete" bullet in Features .......................................................................................................... 1
Changes from Revision E (January 2018) to Revision F
Page
•
•
Made editorial and cosmetic changes throughout the document .......................................................................................... 1
Changed From: "Isolation Barrier Life: >40 Years" To: " >100-year projected lifetime at 1500 VRMS working voltage"
in Features.............................................................................................................................................................................. 1
•
•
•
•
•
Added "Up to 5000 VRMS isolation rating" in Features............................................................................................................ 1
Added "Up to 12.8 kV surge capability" in Features .............................................................................................................. 1
Added "±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier" in Features ......................................... 1
Added "Automotive version available: ISO774x-Q1" in Features........................................................................................... 1
Changed From: "All Certifications Complete except CQC Approval of DBQ-16 Package Devices" To: "All
certifications complete" in Features ....................................................................................................................................... 1
•
Updated Simplified Schematic to show two isolation capacitors in series per channel instead of a single isolation
capacitor ................................................................................................................................................................................. 1
•
•
Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in ESD Ratings..................................................... 8
Added the following table note to Data rate specification: "100 Mbps is the maximum specified data rate, although
higher data rates are possible." ............................................................................................................................................. 8
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SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
•
•
Changed VIORM value for DW-16 package From: "1414 VPK" To: "2121 VPK" in Insulation Specifications table.................. 10
Changed VIOWM values for DW-16 package From: "1000 VRMS" and "1414 VDC" To: "1500 VRMS" and "2121 VDC" in
Insulation Specifications table ............................................................................................................................................. 10
•
•
Added 'see Figure 28' to TEST CONDITIONS of VIOWM specification in Insulation Specifications...................................... 10
Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1" in
Insulation Specifications table .............................................................................................................................................. 10
•
•
•
•
Updated certification information in Safety-Related Certifications table .............................................................................. 11
Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in Figure 12 .............................................................................. 21
Added Insulation Lifetime sub-section under Application Curve section.............................................................................. 31
Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' application report to
Documentation Support section ........................................................................................................................................... 34
Changes from Revision D (May 2017) to Revision E
Page
•
•
•
Changed the DIN certification number and certification status throughout the document ..................................................... 1
Changed the isolation rating of the DBQ package from 2500 VRMS to 3000 VRMS ................................................................. 1
Added VTEST to the conditions for the maximum transient isolation voltage parameter in the Insulation Specifications
table...................................................................................................................................................................................... 10
•
•
•
Changed the value for the DBQ package from 3600 VPK to 4242 VPK throughout the document...................................... 10
Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table ...................................... 10
Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage Threshold vs
Free-Air Temperature ........................................................................................................................................................... 21
Changes from Revision C (December 2016) to Revision D
Page
•
•
Updated the Safety-Related Certifications table................................................................................................................... 11
Changed the minimum CMTI from 40 to 85 in all Electrical Characteristics tables ............................................................ 12
Changes from Revision B (October 2016) to Revision C
Page
•
•
Changed the Regulatory Information table to Safety-Related Certifications and updated content...................................... 11
Changed the certifications from planned to certified in the Safety-Related Certifications table........................................... 11
Changes from Revision A (June 2016) to Revision B
Page
•
•
Changed Feature From: High CMTI: ±75 kV/μs Typical To: High CMTI: ±100 kV/μs Typical ............................................... 1
Changed Feature From: All Certifications are Planned To: 'VDE, UL, and TUV Certifications for DW Package
Complete; All Other Certifications are Planned...................................................................................................................... 1
•
•
•
•
•
•
Changed the unit value of CLR and CPG From: μm To: mm in Insulation Specifications................................................... 10
Changed From: "Plan to certify" To: "Certified" in column VDE of Safety-Related Certifications ........................................ 11
Added a conditions statement to Safety-Related Certifications .......................................................................................... 11
Changed From: "Plan to certify" To: "Certified" in column UL of Safety-Related Certifications........................................... 11
Changed From: "Plan to certify" To: "Certified" in column TUV of Safety-Related Certifications ........................................ 11
Changed From: "Certification Planned" To: 'Certificate number: 40040142" in column VDE of Safety-Related
Certifications......................................................................................................................................................................... 11
•
•
•
•
•
Changed From: "Certification Planned" To: "File number: E181974" in column VDE of Safety-Related Certifications....... 11
Changed From: "Certification Planned" To: "Client ID number: 77311" in column TUV of Safety-Related Certifications ... 11
Changed the CMTI TYP value From: 75 kV/μs To: 100 kV/μs in the Electrical Characteristics—5-V Supply..................... 12
Changed the CMTI TYP value From: 75 kV/μs To: 100 kV/μs in the Electrical Characteristics—3.3-V Supply.................. 14
Changed the CMTI TYP value From: 75 kV/μs To: 100 kV/μs in the Electrical Characteristics—2.5-V Supply.................. 16
Copyright © 2016–2020, Texas Instruments Incorporated
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SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
www.ti.com
•
•
•
Changed the tDO TYP value From: 6 μs To: 0.1 μs and the MAX value From: 9 µs To: 0.3 µs in the Switching
Characteristics—5-V Supply................................................................................................................................................. 18
Changed the tDO TYP value From: 6 μs To: 0.1 μs and the MAX value From: 9 µs To: 0.3 µs in the Switching
Characteristics—3.3-V Supply.............................................................................................................................................. 18
Changed the tDO TYP value From: 6 μs To: 0.1 μs and the MAX value From: 9 µs To: 0.3 µs in the Switching
Characteristics—2.5-V Supply.............................................................................................................................................. 19
•
•
•
Added Note B to Figure 17................................................................................................................................................... 24
Changed the Design Requirements paragraph ................................................................................................................... 30
Replaced the Power Supply Recommendations section ..................................................................................................... 32
Changes from Original (March 2016) to Revision A
Page
•
Changed the device status From: Preview To: Production. ................................................................................................... 1
4
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SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
5 Description Continued
Used in conjunction with isolated power supplies, these devices help prevent noise currents on data buses, such
as RS-485, RS-232, and CAN, or other circuits from entering the local ground and interfering with or damaging
sensitive circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility of the
ISO774x devices have been significantly enhanced to ease system-level ESD, EFT, surge, and emissions
compliance. The ISO774x devices are available in 16-pin SOIC and QSOP packages.
Copyright © 2016–2020, Texas Instruments Incorporated
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6 Pin Configuration and Functions
ISO7740 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
ISO7741 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
1
2
3
4
5
6
7
8
16
V
V
1
2
3
4
5
6
7
8
16
V
CC1
CC2
V
CC1
CC2
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 OUTC
11 OUTD
10 EN2
9 GND2
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 OUTC
11 IND
10 EN2
9 GND2
INB
INB
INC
INC
IND
OUTD
EN1
NC
GND1
GND1
ISO7742 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
GND1
INA
15 GND2
14 OUTA
13 OUTB
12 INC
11 IND
10 EN2
9 GND2
INB
OUTC
OUTD
EN1
GND1
6
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SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
Pin Functions
PIN
ISO7741
I/O
DESCRIPTION
NAME
ISO7740
ISO7742
Output enable 1. Output pins on side 1 are enabled when EN1 is high
or open and in high-impedance state when EN1 is low.
EN1
—
7
7
I
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high
or open and in high-impedance state when EN2 is low.
EN2
10
10
10
2
8
2
8
2
8
GND1
—
—
Ground connection for VCC1
Ground connection for VCC2
9
9
9
GND2
15
3
15
3
15
3
INA
I
I
Input, channel A
Input, channel B
Input, channel C
Input, channel D
Not connected
INB
4
4
4
INC
5
5
12
11
—
14
13
5
I
IND
6
11
—
14
13
12
6
I
NC
7
—
O
O
O
O
—
—
OUTA
OUTB
OUTC
OUTD
VCC1
VCC2
14
13
12
11
1
Output, channel A
Output, channel B
Output, channel C
Output, channel D
Power supply, side 1
Power supply, side 2
6
1
1
16
16
16
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
–0.5
–0.5
–15
MAX
UNIT
V
VCC1, VCC2
Supply voltage(2)
6
VCCX + 0.5(3)
15
V
Voltage at INx, OUTx, ENx
Output current
V
IO
mA
°C
TJ
Tstg
Junction temperature
Storage temperature
150
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(3)(4)
V(ESD)
Electrostatic discharge
±1500
±8000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
V
VCC1, VCC2
VCC(UVLO+)
VCC(UVLO-)
VHYS(UVLO)
Supply voltage
2.25
UVLO threshold when supply voltage is rising
UVLO threshold when supply voltage is falling
Supply voltage UVLO hysteresis
2
1.8
2.25
V
1.7
100
–4
V
200
mV
VCCO(1) = 5 V
IOH
High-level output current
Low-level output current
VCCO = 3.3 V
VCCO = 2.5 V
VCCO = 5 V
–2
mA
mA
–1
4
IOL
VCCO = 3.3 V
VCCO = 2.5 V
2
1
(1)
VIH
VIL
DR
TA
High-level input voltage
Low-level input voltage
Data rate(2)
0.7 × VCCI
VCCI
V
V
0
0
0.3 × VCCI
100
Mbps
°C
Ambient temperature
–55
25
125
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) 100 Mbps is the maximum specified data rate, although higher data rates are possible.
8
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7.4 Thermal Information
ISO774x
DBQ
THERMAL METRIC(1)
DWW (SOIC) DW (SOIC)
UNIT
(QSOP)
16 Pins
109
16 Pins
58.3
21.4
30.5
7.1
16 Pins
83.4
46
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.4
48
51.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
19.1
47.5
—
14.2
ψJB
29.8
—
51.4
RθJC(bottom)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Rating
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7740
PD
Maximum power dissipation
200
40
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
160
ISO7741
PD
Maximum power dissipation
200
75
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
125
ISO7742
PD
Maximum power dissipation
200
100
100
mW
mW
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
PD1
PD2
Maximum power dissipation by side-1
Maximum power dissipation by side-2
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7.6 Insulation Specifications
VALUE
PARAMETER
TEST CONDITIONS
UNIT
DW-16 DBQ-
16
CLR
CPG External creepage(1)
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
>8
>3.7
>3.7
>21
>600
I
mm
mm
μm
V
Shortest terminal-to-terminal distance across the package surface
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
DTI
CTI
Distance through the insulation
>21
>600
I
Comparative tracking index
Material group
Rated mains voltage ≤ 300 VRMS
I-IV
I-IV
I-III
I-III
n/a
Overvoltage category per IEC
60664-1
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
n/a
DIN VDE V 0884-11:2017-01(2)
ISO774x
2121
1414
1500
1000
2121
1414
566
n/a
Maximum repetitive peak
VIORM
AC voltage (bipolar)
VPK
isolation voltage
ISO7741B
ISO774x
400
n/a
AC voltage; Time dependent dielectric breakdown (TDDB)
Test; see Figure 28
VRMS
ISO7741B
ISO774x
Maximum working isolation
voltage
VIOWM
566
n/a
DC voltage
VDC
VPK
ISO7741B
VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t= 1 s (100% production)
Maximum transient isolation
voltage
VIOTM
8000
8000
6000
4242
4000
n/a
VTEST = 1.6 × VIOSM
(ISO774x)
Maximum surge isolation
VIOSM
Test method per IEC 62368-1, 1.2/50 µs waveform
VPK
voltage(3)
VTEST = 1.3 × VIOSM
(ISO7741B)
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
≤5
≤5
Vpd(m) = 1.6 × VIORM
tm = 10 s (ISO774x)
,
,
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
qpd
Apparent charge(4)
Vpd(m) = 1.2 × VIORM
pC
tm = 10 s (ISO7741B)
Vpd(m) = 1.875 × VIORM
tm = 1 s (ISO774x)
,
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
≤5
≤5
Vpd(m) = 1.5 × VIORM
,
tm = 1 s (ISO7741B)
Barrier capacitance, input to
output(5)
CIO
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
~1
~1
pF
>1012
>1011
>109
2
>1012
>1011
>109
2
VIO = 500 V, TA = 25°C
Isolation resistance(5)
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/ 55/125/
21
21
UL 1577
Maximum withstanding isolation
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
VISO
5000
3000
VRMS
voltage
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation (ISO774x) and basic electrical insulation (ISO7741B) only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
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7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019, EN
60950-1:2006/A2:2013 and
EN 62368-1:2014
Certified according to IEC
60950-1, IEC 62368-1 and IEC
60601-1
Certified according to UL 1577
Component Recognition
Program
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to GB
4943.1-2011
5000 VRMS (DW-16) and
3000 VRMS (DBQ-16)
Maximum transient
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC 60950-
1 2nd Ed.+A1+A2, CSA 62368-
1-14 and IEC 62368-1 2nd Ed.
800 VRMS (DW-16) and 370 VRMS
(DBQ-16) max working voltage
(pollution degree 2, material
group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3.1, 250
VRMS (DW-16) max working
voltage
isolation voltage, 8000 VPK
(DW-16) and 4242 VPK
(DBQ-16);
Reinforced insulation per
EN 61010-1:2010/A1:2019
up to working voltage of 600
VRMS (DW-16) and 300
VRMS (DBQ-16)
DW-16: Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
DW-16: Single protection, 5000 Climate, 700 VRMS maximum
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW-16, Reinforced),
1414 VPK (DW-16, Basic)
and 566 VPK (DBQ-16);
Maximum surge isolation
voltage, 8000 VPK (DW-16,
Reinforced), 6000 VPK
(DW-16, Basic) and 4000
VPK (DBQ-16)
VRMS
;
working voltage;
5000 VRMS (DW-16) and
3000 VRMS (DBQ-16)
DBQ-16: Single protection,
3000 VRMS
DBQ-16: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 400 VRMS maximum
working voltage
Reinforced insulation per
EN 60950-1:2006/A2:2013
and EN 62368-1:2014 up to
working voltage of 800 VRMS
(DW-16) and 370 VRMS
(DBQ-16)
Reinforced certificate:
40040142
Basic certificate:
40047657
Certificate numbers:
CQC15001121716 (DW-16)
CQC18001199097 (DBQ-16)
Master contract number: 220991 File number: E181974
Client ID number: 77311
7.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
DW-16 PACKAGE
TEST CONDITIONS
MIN TYP MAX UNIT
R
R
R
θJA = 83.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
θJA = 83.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
θJA = 83.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
273
Safety input, output, or supply
current
416
mA
IS
545
Figure 1
PS
TS
Safety input, output, or total power
Maximum safety temperature
RθJA = 83.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 3
1499 mW
150
°C
DBQ-16 PACKAGE
R
R
R
θJA = 109 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2
θJA = 109 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2
θJA = 109 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
209
319
Safety input, output, or supply
current
IS
mA
417
Figure 2
PS
TS
Safety input, output, or total power
Maximum safety temperature
RθJA = 109 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
1147 mW
150 °C
(1) The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-
air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-
air thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded Surface Mount Packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature
plus the power times the junction-to-air thermal resistance
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7.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 15
IOL = 4 mA; see Figure 15
MIN
VCCO(1) – 0.4
TYP
4.8
MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
V
0.2
0.4
V
V
V
VIT+(IN) Rising input voltage threshold
VIT-(IN) Falling input voltage threshold
0.6 × VCCI
0.4 × VCCI
0.7 × VCCI
0.3 × VCCI
0.1 × VCCI
Input threshold voltage
hysteresis
VI(HYS)
0.2 × VCCI
V
IIH
IIL
High-level input current
Low-level input current
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
–10
85
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see
Figure 18
CMTI
CI
100
2
kV/μs
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz,
VCC = 5 V
Input Capacitance(2)
pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
(2) Measured from input pin to ground.
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7.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
CURRENT
PARAMETER
ISO7740
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.2
0.3
5.5
0.3
1.2
2
1.6
0.5
7.8
0.5
1.6
3.2
EN2 = 0 V; VI = VCC1 (ISO7740);
VI = 0 V (ISO7740 with F suffix)
Supply current - Disable
Supply current - DC signal
EN2 = 0 V; VI = 0 V (ISO7740);
VI = VCC1 (ISO7740 with F suffix)
EN2 = VCC2; VI = VCC1 (ISO7740);
VI = 0 V (ISO7740 with F suffix)
5.5
2.2
3.3
2.3
3.4
4.2
3.8
22.7
7.8
mA
3.6
EN2 = VCC2; VI = 0 V (ISO7740);
VI = VCC1 (ISO7740 with F suffix)
4.7
3.6
4.8
5.8
5.7
28
1 Mbps
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
ISO7741
EN1 = EN2 = 0 V; VI = VCCI(1) (ISO7741);
VI = 0 V (ISO7741 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1
0.8
4.3
1.8
1.5
2
1.5
1.1
6.3
2.7
2.3
3
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7741);
VI = VCCI (ISO7741 with F suffix)
EN1 = EN2 = VCCI; VI = VCCI (ISO7741);
VI = 0 V (ISO7741 with F suffix)
Supply current - DC signal
Supply current - AC signal
4.8
3.2
3.2
2.8
3.7
4.2
8.6
18
6.8
mA
4.9
EN1 = EN2 = VCCI; VI = 0 V (ISO7741);
VI = VCCI (ISO7741 with F suffix)
4.6
4.1
1 Mbps
5.2
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
5.7
11.3
22
100 Mbps
ISO7742
EN1 = EN2 = 0 V; VI = VCCI (ISO7742);
VI = 0 V (ISO7742 with F suffix)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
0.9
3
1.3
4.6
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7742);
VI = VCCI (ISO7742 with F suffix)
EN1 = EN2 = VCCI; VI = VCCI (ISO7742);
VI = 0 V (ISO7742 with F suffix)
1.7
4
2.7
mA
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7742);
VI = VCCI (ISO7742 with F suffix)
5.9
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
3
4
4.4
5.5
17
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
(1) VCCI = Input-side VCC
10 Mbps
100 Mbps
13.4
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1) – 0.3
TYP
3.2
MAX
UNIT
V
VOH
High-level output voltage
Low-level output voltage
Rising input voltage threshold
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
IOH = –2 mA; see Figure 15
VOL
IOL = 2 mA; see Figure 15
0.1
0.3
V
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.6 × VCCI
0.4 × VCCI
0.2 × VCCI
0.7 × VCCI
V
0.3 × VCCI
0.1 × VCCI
V
V
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
IIL
Low-level input current
–10
85
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V, VCM = 1200 V; see Figure 18
100
kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
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7.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
CURRENT
PARAMETER
ISO7740
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.2
0.3
5.5
0.3
1.2
1.9
5.5
2.2
3.3
2.2
3.4
3.6
3.3
17
1.6
0.5
7.8
0.5
1.6
3.2
EN2 = 0 V; VI = VCC1 (ISO7740);
VI = 0 V (ISO7740 with F suffix)
Supply current - Disable
Supply current - DC signal
EN2 = 0 V; VI = 0 V (ISO7740);
VI = VCC1 (ISO7740 with F suffix)
EN2 = VCC2; VI = VCC1 (ISO7740);
VI = 0 V (ISO7740 with F suffix)
7.8
mA
3.6
EN2 = VCC2; VI = 0 V (ISO7740);
VI = VCC1 (ISO7740 with F suffix)
4.7
3.6
4.8
5
1 Mbps
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
5.5
20
ISO7741
EN1 = EN2 = 0 V; VI = VCCI(1) (ISO7741);
VI = 0 V (ISO7741 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1
0.8
4.3
1.9
1.5
2
1.5
1.1
6.3
2.7
2.3
3
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7741);
VI = VCCI (ISO7741 with F suffix)
EN1 = EN2 = VCCI; VI = VCCI (ISO7741);
VI = 0 V (ISO7741 with F suffix)
Supply current - DC signal
Supply current - AC signal
4.8
3.2
3.2
2.7
3.5
3.7
6.8
13.7
6.8
mA
4.9
EN1 = EN2 = VCCI; VI = 0 V (ISO7741);
VI = VCCI (ISO7741 with F suffix)
4.6
4.1
5
1 Mbps
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
5.2
9.3
16.4
100 Mbps
ISO7742
EN1 = EN2 = 0 V; VI = VCCI (ISO7742);
VI = 0 V (ISO7742 with F suffix)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
0.9
3
1.3
4.6
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7742);
VI = VCCI (ISO7742 with F suffix)
EN1 = EN2 = VCCI; VI = VCCI (ISO7742);
VI = 0 V (ISO7742 with F suffix)
1.7
4
2.7
mA
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7742);
VI = VCCI (ISO7742 with F suffix)
5.9
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
2.9
3.6
4.3
5.1
13
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
(1) VCCI = Input-side VCC
10 Mbps
100 Mbps
10.3
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7.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCO(1) – 0.2
TYP
2.45
MAX
UNIT
V
VOH
High-level output voltage
Low-level output voltage
Rising input voltage threshold
Falling input voltage threshold
Input threshold voltage hysteresis
High-level input current
IOH = –1 mA; see Figure 15
VOL
IOL = 1 mA; see Figure 15
0.05
0.2
V
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
0.6 × VCCI
0.4 × VCCI
0.2 × VCCI
0.7 × VCCI
V
0.3 × VCCI
0.1 × VCCI
V
V
VIH = VCCI(1) at INx or ENx
VIL = 0 V at INx or ENx
10
μA
μA
IIL
Low-level input current
–10
85
Common-mode transient
immunity
CMTI
VI = VCCI or 0 V, VCM = 1200 V; see Figure 18
100
kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC
.
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7.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
CURRENT
PARAMETER
ISO7740
TEST CONDITIONS
MIN
TYP
MAX UNIT
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.2
0.3
5.5
0.3
1.2
1.9
5.4
2.2
3.3
2.2
3.4
3.2
3.2
13
1.6
0.5
7.8
0.5
1.6
3.2
EN2 = 0 V; VI = VCC1 (ISO7740);
VI = 0 V (ISO7740 with F suffix)
Supply current - Disable
Supply current - DC signal
EN2 = 0 V; VI = 0 V (ISO7740);
VI = VCC1 (ISO7740 with F suffix)
EN2 = VCC2; VI = VCC1 (ISO7740);
VI = 0 V (ISO7740 with F suffix)
7.8
mA
3.6
EN2 = VCC2; VI = 0 V (ISO7740);
VI = VCC1 (ISO7740 with F suffix)
4.7
3.5
4.8
4.7
5.4
17
1 Mbps
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
10 Mbps
100 Mbps
ISO7741
EN1 = EN2 = 0 V; VI = VCCI(1) (ISO7741);
VI = 0 V (ISO7741 with F suffix)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1
0.8
4.3
1.8
1.4
2
1.5
1.1
6.3
2.7
2.3
3
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7741);
VI = VCCI (ISO7741 with F suffix)
EN1 = EN2 = VCCI; VI = VCCI (ISO7741);
VI = 0 V (ISO7741 with F suffix)
Supply current - DC signal
Supply current - AC signal
4.7
3.2
3.1
2.7
3.4
3.5
5.6
10.8
6.8
mA
4.9
EN1 = EN2 = VCCI; VI = 0 V (ISO7741);
VI = VCCI (ISO7741 with F suffix)
4.6
4
1 Mbps
4.9
4.9
8.3
13.8
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
ISO7742
EN1 = EN2 = 0 V; VI = VCCI (ISO7742);
VI = 0 V (ISO7742 with F suffix)
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
0.9
3
1.3
4.6
Supply current - Disable
EN1 = EN2 = 0 V; VI = 0 V (ISO7742);
VI = VCCI (ISO7742 with F suffix)
EN1 = EN2 = VCCI; VI = VCCI (ISO7742);
VI = 0 V (ISO7742 with F suffix)
1.7
4
2.7
mA
Supply current - DC signal
EN1 = EN2 = VCCI; VI = 0 V (ISO7742);
VI = VCCI (ISO7742 with F suffix)
5.9
1 Mbps
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
2.9
3.4
8.3
4.3
4.9
All channels switching with square
wave clock input; CL = 15 pF
Supply current - AC signal
(1) VCCI = Input-side VCC
10 Mbps
100 Mbps
11.5
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MAX UNIT
7.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
TEST CONDITIONS
MIN
TYP
10.7
0
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
16
4.9
4
ns
ns
ns
ns
ns
ns
ns
ns
See Figure 15
|
Same-direction channels
See Figure 15
4.4
3.9
3.9
20
20
Output signal rise time
2.4
2.4
9
tf
Output signal fall time
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
9
Enable propagation delay, high impedance-to-high output
for ISO774x
7
3
3
7
20
8.5
8.5
20
ns
μs
μs
ns
tPZH
Enable propagation delay, high impedance-to-high output
for ISO774x with F suffix
See Figure 16
Enable propagation delay, high impedance-to-low output for
ISO774x
tPZL
Enable propagation delay, high impedance-to-low output for
ISO774x with F suffix
Measured from the time VCC goes
below 1.7 V. See Figure 18
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.8
0.3
μs
216 – 1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
TEST CONDITIONS
MIN
TYP
11
MAX
16
5
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
See Figure 15
|
0.1
ns
Same-direction channels
See Figure 15
4.1
4.5
3
ns
ns
Output signal rise time
1.3
1.3
17
ns
tf
Output signal fall time
3
ns
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
30
30
ns
17
ns
Enable propagation delay, high impedance-to-high output
for ISO774x
17
3.2
3.2
17
30
8.5
8.5
30
ns
μs
μs
ns
tPZH
Enable propagation delay, high impedance-to-high output
for ISO774x with F suffix
See Figure 16
Enable propagation delay, high impedance-to-low output
for ISO774x
tPZL
Enable propagation delay, high impedance-to-low output
for ISO774x with F suffix
Measured from the time VCC goes
below 1.7 V. See Figure 18
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.9
0.3
μs
216 – 1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
TEST CONDITIONS
MIN
7.5
TYP
12
MAX
18.5
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
See Figure 15
|
0.2
5.1
4.1
4.6
3.5
3.5
40
ns
Same-direction Channels
See Figure 15
ns
ns
Output signal rise time
1
1
ns
tf
Output signal fall time
ns
tPHZ
tPLZ
Disable propagation delay, high-to-high impedance output
Disable propagation delay, low-to-high impedance output
22
22
ns
40
ns
Enable propagation delay, high impedance-to-high output
for ISO774x
18
3.3
3.3
18
40
8.5
8.5
40
ns
μs
μs
ns
tPZH
Enable propagation delay, high impedance-to-high output
for ISO774x with F suffix
See Figure 16
Enable propagation delay, high impedance-to-low output
for ISO774x
tPZL
Enable propagation delay, high impedance-to-low output
for ISO774x with F suffix
Measured from the time VCC goes
below 1.7 V. See Figure 18
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
216 – 1 PRBS data at 100 Mbps
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.18 Insulation Characteristics Curves
600
450
400
350
300
250
200
150
100
50
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
0
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D001
D002
Figure 1. Thermal Derating Curve for Safety Limiting
Current for DW-16 Package
Figure 2. Thermal Derating Curve for Safety Limiting
Current for DBQ-16 Package
1600
1400
1400
1200
1000
800
600
400
200
0
1200
1000
800
600
400
200
0
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
D003
D004
Figure 3. Thermal Derating Curve for Safety Limiting Power
for DW-16 Package
Figure 4. Thermal Derating Curve for Safety Limiting Power
for DBQ-16 Package
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7.19 Typical Characteristics
25
9
8
7
6
5
4
3
2
1
0
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
20
ICC2 at 5 V
15
ICC2 at 5 V
10
5
0
0
0
0
25
50
Data Rate (Mbps)
75
100
0
0
0
25
50
Data Rate (Mbps)
75
100
D005
D006
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 5. ISO7740 Supply Current vs Data Rate
(With 15-pF Load)
Figure 6. ISO7740 Supply Current vs Data Rate
(With No Load)
20
18
16
14
12
10
8
9
8
7
6
5
4
3
2
1
0
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC2 at 5 V
6
4
2
0
25
50
Data Rate (Mbps)
75
100
25
50
Data Rate (Mbps)
75
100
D007
D008
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 7. ISO7741 Supply Current vs Data Rate
(With 15-pF Load)
Figure 8. ISO7741 Supply Current vs Data Rate
(With No Load)
16
14
12
10
8
8
7
6
5
4
3
2
1
0
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC2 at 5 V
6
4
2
0
25
50
Data Rate (Mbps)
75
100
25
50
Data Rate (Mbps)
75
100
D009
D010
TA = 25°C
CL = 15 pF
TA = 25°C
CL = No Load
Figure 9. ISO7742 Supply Current vs Data Rate
(With 15-pF Load)
Figure 10. ISO7742 Supply Current vs Data Rate
(With No Load)
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Typical Characteristics (continued)
6
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
3
2
1
0
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
-15
-10
High-Level Output Current (mA)
-5
0
0
5 10
Low-Level Output Current (mA)
15
D011
D012
TA = 25°C
TA = 25°C
Figure 11. High-Level Output Voltage vs High-level Output
Current
Figure 12. Low-Level Output Voltage vs Low-Level Output
Current
2.10
2.05
2.00
1.95
1.90
1.85
1.80
14
13
12
11
10
VCC1 Rising
VCC2 Rising
VCC1 Falling
VCC2 Falling
1.75
1.70
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5 V
9
8
1.65
-55
-5
45
95
125
-55
-25
5
35
65
95
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D013
D014
Figure 13. Power Supply Undervoltage Threshold vs Free-
Air Temperature
Figure 14. Propagation Delay Time vs Free-Air Temperature
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8 Parameter Measurement Information
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input
Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCO
V
CC
R
L
= 1 kꢀ 1%
V
/ 2
CC
V
/ 2
CC
V
I
IN
OUT
0 V
V
0 V
O
t
t
PLZ
PZL
V
OH
EN
0.5 V
V
V
O
50%
C
L
OL
See Note B
Input
Generator
(See Note A)
V
I
50 ꢀ
V
CC
V
O
IN
OUT
3 V
V / 2
CC
V
/ 2
CC
V
I
0 V
t
PZH
EN
See Note B
R
L
= 1 kꢀ 1%
V
OH
C
L
50%
Input
Generator
(See Note A)
0.5 V
V
O
V
I
0 V
t
50 ꢀ
PHZ
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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Parameter Measurement Information (continued)
V
I
See Note B
V
CC
V
CC
V
1.7 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 17. Default Output Delay Time Test Circuit and Voltage Waveforms
V
V
CCO
CCI
C = 0.1 µF 1%
C = 0.1 µF 1%
Pass-fail criteria:
The output must
remain stable.
IN
OUT
S1
+
C
L
V
or V
OL
OH
See Note A
œ
GNDO
GNDI
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 18. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISO774x family of devices an ON-OFF keying (OOK) modulation scheme to transmit the digital data across
a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is low
then the output goes to high impedance. The ISO774x devices also incorporate advanced circuit techniques to
maximize the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO
buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 19, shows a functional
block diagram of a typical channel.
9.2 Functional Block Diagram
Transmitter
Receiver
EN
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 20 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 20. On-Off Keying (OOK) Based Modulation Scheme
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9.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PART NUMBER
CHANNEL DIRECTION
PACKAGE
RATED ISOLATION(1)
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
DW-16
DBQ-16
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
4 Forward,
0 Reverse
ISO7740
100 Mbps
100 Mbps
100 Mbps
100 Mbps
High
Low
High
Low
ISO7740 with F
suffix
4 Forward,
0 Reverse
3 Forward,
1 Reverse
ISO7741
ISO7741 with F
suffix
3 Forward,
1 Reverse
3 Forward,
1 Reverse
ISO7741B
100 Mbps
100 Mbps
High
Low
DW-16
DW-16
5000 VRMS / 8000 VPK
5000 VRMS / 8000 VPK
ISO7741B with F
suffix
3 Forward,
1 Reverse
DW-16
DBQ-16
DW-16
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
5000 VRMS / 8000 VPK
3000 VRMS / 4242 VPK
2 Forward,
2 Reverse
ISO7742
100 Mbps
100 Mbps
High
Low
ISO7742 with F
suffix
2 Forward,
2 Reverse
DBQ-16
(1) See Safety-Related Certifications for detailed isolation ratings.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO774x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
Table 2 lists the functional modes for the ISO774x devices.
Table 2. Function Table(1)
OUTPUT
ENABLE
(ENx)
INPUT
(INx)(2)
OUTPUT
(OUTx)
VCCI
VCCO
COMMENTS
H
L
H or open
H or open
H
L
Normal Operation:
A channel output assumes the logic state of its input.
PU
X
PU
PU
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is High for ISO774x and Low for
ISO774x with F suffix.
Open
X
H or open
L
Default
Z
A low value of output enable causes the outputs to be high-
impedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO774x and Low for ISO774x with F suffix.
PD
X
PU
PD
X
X
H or open
Default
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(3)
.
X
Undetermined When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
(2) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
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9.4.1 Device I/O Schematics
Input (ISO774x)
Input (ISO774xF)
V
V
V
V
V
V
V
CCI
CCI
CCI
CCI
CCI
CCI
CCI
1.5 MW
985 W
985 W
INx
INx
1.5 MW
Output
Enable
V
CCO
V
V
V
V
CCO
CCO
CCO
CCO
2 MW
~20 W
1970 W
OUTx
ENx
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Device I/O Schematics
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO774x devices are high-performance, quad-channel digital isolators. These devices come with enable pins
on each side which can be used to put the respective outputs in high impedance for multi master driving
applications and reduce power consumption. The ISO774x devices use single-ended CMOS-logic switching
technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with
digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform
to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal
lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a
line transceiver, regardless of the interface type or standard.
10.2 Typical Application
Figure 22 shows the isolated serial peripheral interface (SPI).
VS
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3 VISO
3
1
4
3
1
2
Vcc
D2
SN6501
IN
OUT
TLV70733
EN GND
10 ꢀF 0.1 ꢀF
10 ꢀF
2
4
6
D1
GND
VIN VOUT
REF5025
GND
10 ꢀF
MBR0520L
4,5
1 ꢀF
22 ꢀF
ISO-BARRIER
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
0.1 ꢀF
1
16
4.7 kꢁ
4.7 kꢁ
Vcc1
EN1
INA
Vcc2
2
3
2
28 32 31
7
3
4
5
6
10
EN2
AINP MXO VBD VA REFP
DVcc
6
14
23
24
25
26
20
OUTA
CS
CH0
P1.4
5
6
ISO7741
7
13
12
11
16
Analog
Inputs
MSP430
G2132
(14-PW)
XOUT
INB
INC
OUTB
SCLK
SDI
SCLK
ADS7953
8
OUTC
SDO
XIN
9
5
OUTD
GND1
2,8
IND
SDO
CH15
SDI
DVss
4
BDGND AGND REFM
GND2
27 1,22 30
9,15
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Figure 22. Isolated SPI for an Analog Input Module With 16 Input
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Typical Application (continued)
10.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
Supply voltage, VCC1 and VCC2
VALUE
2.25 to 5.5 V
0.1 µF
Decoupling capacitor between VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
10.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO774x family of devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC1
2 mm maximum
from VCC2
0.1 µF
0.1 µF
VCC2
VCC1
1
16
GND1
GND2
2
3
15
14
INA
INB
INC
OUTA
OUTB
OUTC
13
4
12
11
10
9
5
6
7
8
IND
OUTD
EN2
EN1
GND2
GND1
Figure 23. Typical ISO774x Circuit Hook-up
The DWW package provides wider creepage and clearance without the need for two isolators in series or an
extra isolated power supply, saving design cost and board space. For more details, please refer to the technical
document How to Meet the Higher Isolation Creepage & Clearance Needs in Automotive Applications.
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10.2.3 Application Curve
The following typical eye diagrams of the ISO774x family of devices indicates low jitter and wide open eye at the
maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
Figure 24. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and
25°C
Figure 25. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
and 25°C
Time = 2.5 ns / div
Figure 26. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 27 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 28 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the insulation withstand capability of DW-16 package is 1500 VRMS with a lifetime of
135 years as illustrated in Figure 28. Similarly, the insulation withstand capability of DWW-16 package is 2000
VRMS with a corresponding lifetime of 34 years. DBQ-16 package at 400 VRMS working voltage has a much longer
lifetime than both DW-16 and DWW-16 packages. Factors, such as package size, pollution degree, and material
group can limit the working voltage of a component.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 27. Test Setup for Insulation Lifetime Measurement
Figure 28. Insulation Lifetime Projection Data
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505A. For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505A Low-Noise 1-A
Transformer Drivers for Isolated Power Supplies data sheet.
32
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Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: ISO7740 ISO7741 ISO7742
ISO7740, ISO7741, ISO7742
www.ti.com
SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 29). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this
FR-4
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
0 ~ 4.5
r
Power plane
Low-speed traces
Figure 29. Layout Example Schematic
Copyright © 2016–2020, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: ISO7740 ISO7741 ISO7742
ISO7740, ISO7741, ISO7742
SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, ADS79xx 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial
Interface ADCs data sheet
•
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, Isolation Glossary
Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
•
•
•
•
•
Texas Instruments, MSP430G2132 Mixed Signal Microcontroller data sheet
Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
Texas Instruments, TLV707, TLV707P 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable
Devices data sheet
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
ISO7740
ISO7741
ISO7742
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
34
Submit Documentation Feedback
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: ISO7740 ISO7741 ISO7742
ISO7740, ISO7741, ISO7742
www.ti.com
SLLSEP4G –MARCH 2016–REVISED FEBRUARY 2020
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2020, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Links: ISO7740 ISO7741 ISO7742
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7740DBQ
ISO7740DBQR
ISO7740DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
SOIC
DBQ
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
7740
7740
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7740
ISO7740
7740F
ISO7740DWR
ISO7740FDBQ
ISO7740FDBQR
ISO7740FDW
ISO7740FDWR
ISO7741BDW
ISO7741BDWR
ISO7741DBQ
ISO7741DBQR
ISO7741DW
DW
DBQ
DBQ
DW
7740F
ISO7740F
ISO7740F
ISO7741B
ISO7741B
7741
DW
DW
DW
DBQ
DBQ
DW
7741
ISO7741
ISO7741
ISO7741DWR
ISO7741FBDW
DW
DW
(ISO7731FB, ISO774
1FB)
ISO7741FBDWR
ISO7741FDBQ
ISO7741FDBQR
ISO7741FDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SSOP
SSOP
SOIC
SOIC
DW
DBQ
DBQ
DW
16
16
16
16
16
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
ISO7741FB
7741F
7741F
ISO7741F
ISO7741F
ISO7741FDWR
DW
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7742DBQ
ISO7742DBQR
ISO7742DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SOIC
SOIC
DBQ
DBQ
DW
16
16
16
16
16
16
16
16
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
7742
7742
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ISO7742
ISO7742
7742F
ISO7742DWR
ISO7742FDBQ
ISO7742FDBQR
ISO7742FDW
ISO7742FDWR
DW
DBQ
DBQ
DW
7742F
ISO7742F
ISO7742F
DW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7740, ISO7741, ISO7742 :
Automotive : ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7740DBQR
ISO7740DWR
ISO7740DWR
ISO7740FDBQR
ISO7740FDWR
ISO7740FDWR
ISO7741BDWR
ISO7741BDWR
ISO7741DBQR
ISO7741DWR
ISO7741DWR
ISO7741FBDWR
ISO7741FBDWR
ISO7741FDBQR
ISO7741FDWR
ISO7741FDWR
ISO7742DBQR
ISO7742DWR
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SSOP
SOIC
DBQ
DW
DW
DBQ
DW
DW
DW
DW
DBQ
DW
DW
DW
DW
DBQ
DW
DW
DBQ
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
2000
2000
2500
2000
2000
2000
2000
2500
2000
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
16.4
12.4
16.4
16.4
16.4
16.4
12.4
16.4
16.4
16.4
16.4
12.4
16.4
16.4
12.4
16.4
6.4
5.2
2.1
2.7
2.7
2.1
2.7
2.7
2.7
2.7
2.1
2.7
2.7
2.7
2.7
2.1
2.7
2.7
2.1
2.7
8.0
12.0
12.0
8.0
12.0
16.0
16.0
12.0
16.0
16.0
16.0
16.0
12.0
16.0
16.0
16.0
16.0
12.0
16.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
10.75 10.7
10.75 10.7
6.4
5.2
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
12.0
12.0
12.0
12.0
8.0
6.4
5.2
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
12.0
12.0
12.0
12.0
8.0
6.4
5.2
10.75 10.7
10.75 10.7
12.0
12.0
8.0
6.4
5.2
10.75 10.7
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jun-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7742DWR
ISO7742FDBQR
ISO7742FDWR
ISO7742FDWR
SOIC
SSOP
SOIC
SOIC
DW
DBQ
DW
16
16
16
16
2000
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
12.4
16.4
16.4
10.75 10.7
6.4 5.2
2.7
2.1
2.7
2.7
12.0
8.0
16.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
10.75 10.7
10.75 10.7
12.0
12.0
DW
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7740DBQR
ISO7740DWR
ISO7740DWR
ISO7740FDBQR
ISO7740FDWR
ISO7740FDWR
ISO7741BDWR
ISO7741BDWR
ISO7741DBQR
ISO7741DWR
ISO7741DWR
ISO7741FBDWR
ISO7741FBDWR
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SOIC
SSOP
SOIC
SOIC
SOIC
SOIC
DBQ
DW
DW
DBQ
DW
DW
DW
DW
DBQ
DW
DW
DW
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
2000
2000
2500
2000
2000
2000
2000
350.0
350.0
853.0
350.0
853.0
350.0
367.0
350.0
350.0
350.0
853.0
853.0
350.0
350.0
350.0
449.0
350.0
449.0
350.0
367.0
350.0
350.0
350.0
449.0
449.0
350.0
43.0
43.0
35.0
43.0
35.0
43.0
38.0
43.0
43.0
43.0
35.0
35.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jun-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7741FDBQR
ISO7741FDWR
ISO7741FDWR
ISO7742DBQR
ISO7742DWR
ISO7742DWR
ISO7742FDBQR
ISO7742FDWR
ISO7742FDWR
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
DBQ
DW
16
16
16
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
2500
2000
2000
350.0
853.0
350.0
350.0
350.0
853.0
350.0
367.0
350.0
350.0
449.0
350.0
350.0
350.0
449.0
350.0
367.0
350.0
43.0
35.0
43.0
43.0
43.0
35.0
43.0
38.0
43.0
DW
DBQ
DW
DW
DBQ
DW
DW
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
9
8
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
8
9
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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