ISO7821LLSDWR [TI]
双通道、2/0、150Mbps、高性能、增强型隔离式 LVDS 缓冲器 | DW | 16 | -55 to 125;
| 型号： | ISO7821LLSDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、2/0、150Mbps、高性能、增强型隔离式 LVDS 缓冲器 | DW | 16 | -55 to 125 |
| 文件： | 总38页 (文件大小：2431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO7821LLS
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
ISO7821LLS 高性能 8000 VPK 增强型隔离式双 LVDS 缓冲器
1 特性
2 应用
1
•
•
•
•
•
•
符合 TIA/EIA-644-A LVDS 标准
•
•
•
•
•
电机控制
测试和测量
工业自动化
医疗设备
通信系统
信号传输速率：50Mbps 至 150Mbps
针对直流均衡数据进行了优化
宽电源电压范围：3V 至 5.5V
宽温度范围：-55°C 至 125°C
低功耗：电流典型值为 10.3mA/通道（150Mbps
时）
3 说明
ISO7821LLS 器件是一款高性能、隔离式双 LVDS 缓
冲器，隔离电压为 8000 VPK。在隔离 LVDS 总线信号
时，该器件可提供高电磁抗扰度，辐射较低，并且具有
低功耗特性。各隔离通道具有一个 LVDS 接收和传输
缓冲器。ISO7821LLS 器件的定时性能针对与通信系
统结合使用进行了优化。通信采用通过内部失真校正方
案实现的直流均衡数据流。
•
•
•
•
低传播延迟：17ns（典型值）
行业领先的 CMTI（最小值）：±100kV/μs
优异的电磁兼容性 (EMC)
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪
涌保护
•
•
•
•
•
低辐射
隔离栅寿命：> 40 年
SOIC-16 宽体 (DW) 和超宽体 (DWW) 封装选项
可承受的隔离浪涌电压高达 12800 VPK
安全相关认证：
ISO7821LLS 器件有一条正向通道和一条反向通道。
凭借创新的芯片设计和布线技术，ISO7821LLS 器件
的电磁兼容性得到了显著增强，从而可确保提供系统级
ESD、EFT 和浪涌保护并符合辐射标准。
–
–
–
–
符合 DIN V VDE V 0884–10 (VDE V 0884–10):
2006–12 标准的 8000 VPK 增强型隔离
符合 UL 1577 标准且长达 1 分钟的 5700 VRMS
隔离
ISO7821LLS 器件采用 16 引脚小外形尺寸集成电路
(SOIC) 宽体 (DW) 和超宽体 (DWW) 封装。
CSA 组件验收通知 5A，IEC 60950-1 和 IEC
60601-1 终端设备标准
器件信息(1)
符合 EN 61010-1 和 EN 60950-1 标准的 TUV
认证
器件型号
封装
DW (16)
DWW (16)
封装尺寸（标称值）
10.30mm x 7.50mm
10.30mm x 14.00mm
ISO7821LLS
–
–
符合 GB4943.1–2011 标准的 CQC 认证
已通过所有认证
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
简化电路原理图
V
V
CCI
CCO
Isolation
Capacitor
INx+
OUTx+
LVDS RX
LVDS TX
INxœ
OUTxœ
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
V
CCI 和 GNDI 分别是输入通道的电源和接地连接。
CCO 和 GNDO 分别是输出通道的电源和接地连接。
V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSET5
ISO7821LLS
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Ratings........................................................... 5
6.6 Insulation Specifications............................................ 6
6.7 Safety-Related Certifications..................................... 7
6.8 Safety Limiting Values .............................................. 7
6.9 DC Electrical Characteristics .................................... 8
6.10 DC Supply Current Characteristics......................... 9
7
8
Parameter Measurement Information ................ 14
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 20
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 文档支持................................................................ 25
12.2 接收文档更新通知 ................................................. 25
12.3 社区资源................................................................ 25
12.4 商标....................................................................... 25
12.5 静电放电警告......................................................... 25
12.6 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
6.11 Timing Requirements for Distortion Correction
Scheme...................................................................... 9
6.12 Switching Characteristics...................................... 10
6.13 Insulation Characteristics Curves ......................... 11
6.14 Typical Characteristics.......................................... 12
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (March 2016) to Revision A
Page
•
已更改 器件状态“产品预览”至“量产数据”并且已发布完整版本数据表 ..................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
ISO7821LLS
www.ti.com.cn
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
DW and DWW Packages
16-Pin SOIC
Top View
1
2
3
4
5
6
7
8
16
V
V
CC1
CC2
GND1
INA+
15 GND2
14 OUTA+
13 OUTAœ
12 INBœ
11 INB+
10 EN2
INAœ
OUTBœ
OUTB+
EN1
GND1
9 GND2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high
impedance state when EN1 is low.
EN1
7
I
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high
impedance state when EN2 is low.
EN2
10
2
8
GND1
—
—
Ground connection for VCC1
Ground connection for VCC2
9
GND2
15
3
INA+
I
I
Positive differential input, channel A
Negative differential input, channel A
Positive differential input, channel B
Negative differential input, channel B
Positive differential output, channel A
Negative differential output, channel A
Positive differential output, channel B
Negative differential output, channel B
Power supply, side 1, VCC1
INA–
4
INB+
11
12
14
13
6
I
INB–
I
OUTA+
OUTA–
OUTB+
OUTB–
VCC1
O
O
O
O
—
—
5
1
VCC2
16
Power supply, side 2, VCC2
Copyright © 2016, Texas Instruments Incorporated
3
ISO7821LLS
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCCx
V
Supply voltage(2)
VCC1, VCC2
–0.5
6
V
Voltage on input, output, and
enable pins
OUTx, INx, ENx
–0.5
VCCx + 0.5(3)
V
IO
Maximum current through OUTx pins
Junction temperature
–20
–55
–65
20
mA
°C
TJ
150
150
Tstg
Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2) and are peak voltage
values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
±4500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC1, VCC2 Supply voltage
3
3.3
5.5
V
Magnitude of RX input
differential voltage
|VID
|
Driven with voltage sources on RX pins
100
600
mV
V
RX input common-
mode voltage
VIC
VCC1, VCC2 ≥ 3 V
0.5 |VID
|
2.4 – 0.5 |VID|
RL
DR
TA
TX far-end differential termination
Signaling rate
100
25
Ω
Mbps
°C
50
150
125
Ambient temperature
–55
4
Copyright © 2016, Texas Instruments Incorporated
ISO7821LLS
www.ti.com.cn
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
6.4 Thermal Information
ISO7821LLS
THERMAL METRIC(1)
DW (SOIC)
16 PINS
82
DWW (SOIC)
16 PINS
84.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.6
46.4
46.6
55.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
17.8
18.7
ψJB
46.1
54.5
RθJC(bottom)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 5 pF, RL = 100-Ω differential, input a 75-MHz 50% duty-cycle square wave,
EN1 = EN2 = 5.5 V
PARAMETER
TEST CONDITIONS
MAX
TYP
MAX
180
90
UNIT
mW
mW
mW
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side 1)
Maximum power dissipation (side 2)
PD1
PD2
90
Copyright © 2016, Texas Instruments Incorporated
5
ISO7821LLS
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
6.6 Insulation Specifications
over operating free-air temperature range (unless otherwise noted)
SPECIFICATION
PARAMETER
TEST CONDITIONS
UNIT
DW
DWW
GENERAL
CLR
CPG
DTI
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
>8
>14.5
>14.5
>21
mm
mm
μm
V
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>600
Tracking resistance (comparative
tracking index)
CTI
DIN EN 60112 (VDE 0303–11); IEC 60112; UL 746A
>600
Material group
According to IEC 60664-1
I
I
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–III
I–IV
I–IV
Overvoltage category per IEC 60664-1
DIN V VDE V 0884–10 (VDE V 0884–10):2006–12(2)
Maximum repetitive peak isolation
voltage
VIORM
AC voltage (bipolar)
2121
2828
VPK
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test; see Figure 1 and Figure 2
1500
2121
8000
2000
2828
8000
VRMS
VDC
VPK
VIOWM Maximum isolation working voltage
DC voltage
VTEST = VIOTM, t = 60 s (qualification)
t = 1 s (100% production)
VIOTM Maximum transient isolation voltage
VIOSM Maximum surge isolation voltage(3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and
3394 VPK (DWW), tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and
4525 VPK (DWW), tm = 10 s
≤5
≤5
≤5
≤5
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIORM, tini = 1 s;
Vpd(m) = 1.875 × VIORM= 3977 VPK (DW) and
5303 VPK (DWW), tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~0.7
>1012
>1011
>109
2
~0.7
>1012
>1011
>109
2
pF
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/21 55/125/21
UL 1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VISO
Withstanding isolation voltage
VTEST = 1.2 × VISO = 6840 VRMS
,
5700
5700
VRMS
t = 1 s (100% production)
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
6
Copyright © 2016, Texas Instruments Incorporated
ISO7821LLS
www.ti.com.cn
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Plan to certify according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
and DIN EN 60950-1 (VDE
0805 Teil 1):2011-01
Plan to certify under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Plan to certify according to
Plan to certify according to EN 61010-1:2010 (3rd Ed) and
Plan to certify according
to UL 1577 Component
Recognition Program
GB 4943.1-2011
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
(DW package) and 1450 VRMS
(DWW package) max working
voltage (pollution degree 2,
material group I);
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
Reinforced insulation
Maximum transient
isolation voltage, 8000 VPK
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW), 2828 VPK (DWW);
Maximum surge isolation
voltage, 8000 VPK
;
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
Single protection,
5700 VRMS
maximum working voltage
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
working voltage (DW package)
Certification planned
Certification planned
Certification planned
Certification planned
Certification planned
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW PACKAGE
R
θJA = 82°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
277
423
see Figure 3
θJA = 82°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 3
θJA = 82°C/W, TJ = 150°C, TA = 25°C,
see Figure 5
Safety input, output, or supply
current
IS
mA
R
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
1524
150
mW
°C
DWW PACKAGE
R
θJA = 84.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 4
θJA = 84.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 4
θJA = 84.6°C/W, TJ = 150°C, TA = 25°C,
see Figure 6
269
410
Safety input, output, or supply
current
IS
mA
R
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
1478
150
mW
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a High-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
Copyright © 2016, Texas Instruments Incorporated
7
ISO7821LLS
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
MAX UNIT
6.9 DC Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
GENERAL
Leakage Current on ENx
pins
IIN(EN)
Internal pullup on ENx pins
13
40
µA
V
Positive-going undervoltage-
lockout (UVLO) threshold
VCC+(UVLO)
VCC–(UVLO)
2.25
Negative-going UVLO
threshold
1.7
V
VHYS(UVLO) UVLO threshold hysteresis
0.2
V
V
V
V
VEN(ON)
VEN(OFF)
VEN(HYS)
EN pin turn-on threshold
EN pin turn-off threshold
EN pin threshold hysteresis
0.7 VCCx
0.3 VCCx
100
0.1 VCCx
120
Common-mode transient
immunity
VI = VCCI(1) or 0 V;
VCM = 1000 V, see Figure 22
CMTI
kV/μs
LVDS TX
TX DC output differential
voltage
|VOD
|
RL = 100 Ω, see Figure 23
RL = 100 Ω, see Figure 23
250
–10
350
0
450 mV
Change in TX DC output
differential between logic 1
and 0 states
∆VOD
10
mV
TX DC output common-
mode voltage
VOC
RL = 100 Ω, see Figure 23
RL = 100 Ω, see Figure 23
1.125
–25
1.2
0
1.375
25
V
TX DC common-mode
voltage difference
∆VOC
mV
OUTx = 0
10
10
TX output short circuit
current through OUTx
IOS
IOZ
mA
µA
OUTxP = OUTxM
TX output current when in
high impedance
ENx = 0, OUTx from 0 to VCCx
–5
5
DW package: ENx = 0, DC offset = VCC / 2,
Swing = 200 mV, Frequency (f) = 1 MHz
10
10
TX output pad capacitance
on OUTx at 1 MHz
COUT
pF
DWW package: ENx = 0,
DC offset = VCC / 2, Swing = 200 mV,
Frequency (f) = 1 MHz
LVDS RX
RX input common mode
voltage
VIC
VCCx ≥ 3 V
0.5 |VID
|
1.2 2.4 – 0.5 |VID
|
V
Positive going RX input
differential threshold
VIT1
Across VIC
Across VIC
50
mV
mV
Negative going RX input
differential threshold
VIT2
IINx
–50
–6
Input current on INx
From 0 to VCC (each input independently)
From 0 to VCC
10
20
6
µA
µA
IINxP – IINxM Input current balance
DW package: DC offset = 1.2 V,
Swing = 200 mV, f = 1 MHz
6.6
7.5
RX input pad capacitance on
INx at 1 MHz
CIN
pF
DWW package: DC offset = 1.2 V,
Swing = 200 mV, f = 1 MHz
(1) VCCI = Input-side VCCx; VCCO = Output-side VCCx
.
8
Copyright © 2016, Texas Instruments Incorporated
ISO7821LLS
www.ti.com.cn
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
6.10 DC Supply Current Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
2.3
3.5
6.2
7.5
3.6
5.6
9.9
12
3 V < VCC1
VCC2 < 3.6 V
,
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
7.6 12.1
8.5 13.6
8.9 14.2
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
125 Mbps
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
150 Mbps
Supply current
side 1 and
side 2
ICC1
ICC2
mA
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.3
3.6
3.6
5.7
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
6.6 10.5
7.9 12.6
4.5 V < VCC1
VCC2 < 5.5 V
,
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
8.3 13.2
9.7 15.5
10.3 16.4
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
125 Mbps
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
150 Mbps
6.11 Timing Requirements for Distortion Correction Scheme
Valid data = 8b10b like data with DC balance and bounded disparity. See Figure 25.
MIN
NOM
MAX
UNIT
Time to complete internal calibration, after exiting idle state. LVDS TX
tCALIB
output is held high during this time. During this time valid data must be
presented at the receiver.
250
750
µs
The minimum duration of any idle state that must be maintained between
valid data transmissions.
tIDLE
10
µs
ns
After a channel enters idle state, the internal calibration loses lock after this
time, and the LVDS outputs are gated high.
tIDLE_OUT
200
600
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6.12 Switching Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVDS CHANNEL
tPLH
tPHL
Propagation delay time
Channel-to-channel output skew time
Part-part skew
17
25
4.5
4.5
20
ns
ns
ns
µs
Opposite directional channels, same
voltage and temperature
tsk(o)
Same directional channels, same
voltage and temperature
tsk(pp)
tCMset
Common-mode setting time after
EN = 0 to EN = 1 transition
Common-mode capacitive
load = 100 pF to 0.5 nF
DC balanced data with maximum run
length of 6 at 125 Mbps,
RX VID = 350 mVPP, 1 ns trf 10%-90%,
30%
–40 < TA < 125°C, 3 V < VCC1
,
VCC2 < 5 V
Total eye closure
DC balanced data with maximum run
length of 6 at 150 Mbps,
RX VID = 350 mVPP, 1 ns trf 10%-90%,
40%
9
–40 < TA < 125°C, 3 V < VCC1
,
VCC2 < 5 V
Default output delay time from input
power loss
Measured from the time VCC goes
below 1.7 V, see Figure 21
tfs
0.2
µs
ps
LVDS TX AND RX
TX differential rise and fall times
(20% to 80%)
trf
See Figure 19
300
780
1380
TX common-mode voltage peak-to-
peak at 100 Mbps
∆VOC(pp)
0
10
10
150
20
mVPP
ns
tPLZ, tPHZ TX disable time—valid output to HiZ See Figure 20
TX enable time—HiZ to valid high
tPZH
See Figure 20
20
ns
output(1)
Driven with voltage sources on RX pins,
see figures in the Parameter
Measurement Information section
Magnitude of RX input differential
voltage for valid operation
|VID
|
100
600
mV
ns
Allowed RX input differential rise and
fall times (20% to 80%)
trf(RX)
See Figure 24
1
0.3 × UI(2)
(1) The tPZL parameter is not defined because of the distortion-correction scheme. See the Distortion-Correction Scheme section for more
information.
(2) UI is the unit interval.
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6.13 Insulation Characteristics Curves
1.E+11
1.E+11
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+2
1.E+1
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
87.5%
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
87.5%
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
20%
1.E+1
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
400 1400 2400 3400 4400 5400 6400 7400 8400 9400
Stress Voltage (VRMS
)
Stress Voltage (VRMS
)
TA upto 150°C
Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
TA upto 150°C
Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 1. Reinforced Isolation Capacitor Lifetime Projection
for Devices in DW Package
Figure 2. Reinforced Isolation Capacitor Lifetime Projection
for Devices in DWW Package
500
500
VCCx = 3.6 V
VCCx = 5.5 V
VCCx = 3.6 V
VCCx = 5.5 V
400
300
200
100
0
400
300
200
100
0
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (èC)
Ambient Temperature (èC)
D006
D008
Figure 3. Thermal Derating Curve for Limiting Current for
DW Package
Figure 4. Thermal Derating Curve for Limiting Current for
DWW Package
1800
1600
Power
1400
Power
1600
1400
1200
1000
800
600
400
200
0
1200
1000
800
600
400
200
0
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (èC)
Ambient Temperature (èC)
D007
D010109
Figure 5. Thermal Derating Curve for Limiting Power for DW
Package
Figure 6. Thermal Derating Curve for Limiting Power for
DWW Package
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6.14 Typical Characteristics
10
10
8
8
6
4
2
0
6
4
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
ICC1 at 3.3 V
2
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
0
50
75
100
125
150
50
75
100
125
150
Data Rate (Mbps)
Data Rate (Mbps)
D001
D002
TA = 25°C
CH-A toggle
TA = 25°C
CH-B toggle
Figure 7. Supply Current vs Data Rate (CH-A)
Figure 8. Supply Current vs Data Rate (CH-B)
10
8
14
12
10
8
6
6
4
4
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
2
2
ICC1, ICC2 at 50 Mbps
ICC1, ICC2 at 150 Mbps
0
0
3
3.5
4
4.5
5
5.5
-55
-35
-15
5
25
45
65
85
105 125
VCCx Output Supply Voltage (V)
Temperature (èC)
D003
D004
TA = 25°C
Data rate = 150 Mbps
CH-A toggle
Figure 9. Supply Current vs VCCx Output Supply Voltage
Figure 10. Supply Current vs Temperature (CH-A)
10
16
15
14
13
12
11
10
9
8
6
4
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
2
ICC2 at 5 V
0
-55
8
-55
-35
-15
5
25
45
65
85 105 125
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D005
D010
Data rate = 150 Mbps
CH-B toggle
Figure 11. Supply Current vs Temperature (CH-B)
Figure 12. Propagation Delay Time vs Temperature
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Typical Characteristics (continued)
17
16
15
14
13
12
11
10
9
3
2
1
0
tPLH
tPHL
VOUT+
VOC
VOUT-
8
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
VCCx Output Supply Voltage (V)
VCCx Output Supply Voltage (V)
D011
D012
TA = 25°C
TA = 25°C
Figure 13. Propagation Delay Time vs VCCx Output Supply
Voltage
Figure 14. Output Voltage vs VCCx Output Supply Voltage
15
15
Input to LVDS RX
Input to LVDS RX
Output from
LVDS TX
Output from
LVDS TX
D023
D023
Figure 15. Distortion Correction Scheme Calibration Time
Figure 16. Transition From Valid Data to Idle (tIDLE_OUT)
(tCALIB
)
15
15
VI
VI
VOD
VOD
D023
D023
Figure 17. Disable to Enable Time (tPZH
)
Figure 18. Disable Time (tPLZ, tPHZ)
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7 Parameter Measurement Information
V
C
P
CCI
V
V
V
ID(H)
ID(L)
CCO
50%
50%
OUTx+
LVDS TX
INx+
V
ID
100 ꢀ
ID
R
L
Signal
Generator
LVDS RX
V
V
t
t
PHL
OD
PLH
V
V
OD(H)
OD(L)
INxœ
OUTxœ
C
80%
20%
P
50%
50%
V
OD
GNDI
GNDO
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CP = 5 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 19. Switching Characteristics Test Circuit and Voltage Waveforms
V
CCI
V
CCO
OUTx+
LVDS TX
INx+
LVDS RX
100 ꢀ
V
V
R
C
V
CCO
OD
ID
L
L
V
I
V
/ 2
CCO
INxœ
V
≤ œ50 mV
OUTxœ
ID
0 V
0V
t
EN
PLZ
GNDI
GNDO
50%
V
V
OD
OD(L)
Signal
Generator
V
50 ꢀ
I
V
CCI
V
CCO
OUTx+
INx+
V
CCO
LVDS RX
LVDS TX
100 ꢀ
V
C
L
V
R
OD
ID
L
V / 2
CCO
V
CCO
/ 2
V
I
INxœ
V
≥ 50 mV
OUTxœ
EN
ID
0 V
t
PZH
V
OD(H)
GNDI
GNDO
50%
50%
V
OD
0 V
t
PHZ
Signal
Generator
V
50 ꢀ
I
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 5 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 20. Enable and Disable Propagation Delay Time Test Circuit and Waveform
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Parameter Measurement Information (continued)
V
I
V
CCI
V
CCO
V
CCI
1.7 V
V
I
OUTx+
LVDS TX
INx+
0 V
LVDS RX
100 ꢀ
V
C
L
V
ID
R
L
OD
t
fs
V
OD(H)
V
≤ œ50 mV
INxœ
ID
OUTxœ
V
50%
OD
V
OD(L)
GNDI
GNDO
A. CL = 5 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 21. Default Output Delay Time Test Circuit and Voltage Waveforms
V
CCI
V
CCO
OUTx+
LVDS TX
INx+
S1
S2
LVDS RX
100 ꢀ
V
C
L
V
R
OD
ID
L
INxœ
OUTxœ
GNDO
GNDI
œ
+
V
CM
A. CL = 5 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 22. Common-Mode Transient Immunity Test Circuit
V
CCI
V
CCO
R
L
/ 2
INx+
100 ꢀ
OUTx+
LVDS RX
LVDS TX
V
V
OUTxœ
INxœ
V
V
OD
R
L
/ 2
OC
GNDI
GNDO
= Measured Parameter
Figure 23. Driver Test Circuit
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Parameter Measurement Information (continued)
V
CCI
V
CCO
INx+
OUTx+
LVDS RX
LVDS TX
V
V
OD
ID
INxœ
OUTxœ
V
OUT+
V
IN+
V
V
OUTœ
INœ
GNDI
GNDO
1.375 V
1.025 V
V
V
IN+
INœ
U
I
V
ID
V
0.35 V
ID(H),
0 V
V
œ0.35 V
ID(L),
t
t
PLH
PHL
V
OD(H)
V
OD
80%
20%
50%
V
OD(L)
t
t
f
r
Figure 24. Voltage Definitions and Waveforms
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8 Detailed Description
8.1 Overview
The ISO7821LLS device is an isolated LVDS buffer. The differential signal received on the LVDS input pins is
first converted to CMOS logic levels. It is then transmitted across a silicon dioxide based capacitive isolation
barrier using an On-Off Keying (OOK) modulation scheme. A high frequency carrier transmitted across the
barrier represents one logic state and an absence of a carrier represents the other logic state. On the other side
of the barrier a demodulator converts the OOK signal back to logic levels, which is then converted to LVDS
outputs by a differential driver. This device incorporates advanced circuit techniques to maximize CMTI
performance and minimize radiated emissions.
The ISO7821LLS device implements an eye-diagram improvement scheme to correct for signal distortions that
are introduced in the LVDS receiver as well as the isolation channel. This enables the device to guarantee an
eye closure of less than 30% at 125 Mbps, and less than 40% at 150 Mbps. The distortion correction scheme is
optimized for operation with DC balanced data (for example 8b10b or equivalent) with a maximum run length of
6. The minimum data-rate of operation is also constrained to 50 Mbps. For general purpose data communication
from 0 to 100 Mbps, the ISO782xLL family of devices should be considered.
The ISO7821LLS device is TIA/EIA-644-A standard compliant. The LVDS transmitter drives a minimum
differential-output voltage magnitude of 250 mV into a 100-Ω load, and the LVDS receiver is capable of detecting
differential signal ≥50 mV in magnitude. The device consumes 11 mA per channel at 150 Mbps with 5-V
supplies.
The Functional Block Diagram section shows a conceptual block diagram of one channel of the ISO7821LLS
device.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
OOK
modulation
Envelope
Detector
+
Distortion
Correction
IN+
OUT+
SiO2
based
Capacitive
Isolation
Barrier
LVDS
RX
Preamplifier
LVDS
TX
INœ
OUTœ
Emissions
Reduction
Techniques
Oscillator
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8.3 Feature Description
The ISO7821LLS device is available in a two-channel configuration with a default differential-high output state.
Table 1 lists the device features.
Table 1. Device Features
PART
NUMBER
DEFAULT DIFFERENTIAL
OUTPUT
CHANNEL DIRECTION
RATED ISOLATION
MAXIMUM DATA RATE
(1)
ISO7821LLS
1 Forward, 1 Reverse
5700 VRMS / 8000 VPK
150 Mbps
High
(1) See the Safety-Related Certifications section for detailed isolation ratings.
8.3.1 Distortion-Correction Scheme
The ISO7821LLS device implements a distortion-correction scheme to correct for signal distortions that are
introduced in the LVDS receiver as well as the isolation channel. This scheme is optimized for a DC-balanced
data-stream with a maximum run length of 6. One example of such a data stream is 8b10b encoded data. The
minimum data rate supported by the ISO7821LLS device is 50 Mbps and the maximum is 150 Mbps.
Figure 25 shows the timing requirements associated with the distortion correction scheme (see the Timing
Requirements for Distortion Correction Scheme table for timing parameters). The input to the LVDS channel
should be either idle low, idle high, or should have clock or DC-balanced data transitions at 25 MHz / 50 Mbps or
higher. Low frequency or DC-unbalanced data is not allowed. The distortion-correction scheme runs an internal
calibration each time the LVDS channel transitions from an idle state to a data transmission state. The calibration
runs for a period of tCALIB during which the LVDS channel output is held at logic high. This calibration is also run
at power up. Lack of activity on the receive inputs for a period greater than tIDLE_OUT takes the channel to an
uncalibrated state. If the communication protocol requires the channel to transition to the idle state, the idle-high
or idle-low state must be held for at least duration of tIDLE
.
t
t
IDLE
CALIB
Input to LVDS RX
Output from LVDS TX
t
IDLE_OUT
A. Signals shown are differential logic states.
Logic high → VIN+ > VIN–
Logic low → VIN– > VIN+
B. The data to ISOLVDS channel should be either idle high, idle low, clock, or valid data.
Valid data = 8b10b like data with DC balance and bounded disparity.
C. When transitioning from an uncalibrated sate to a calibrated state, the ISOLVDS channel output is gated high for up
to tCALIB, during which the channel is calibrated.
D. If the channel finds no transitions in the incoming data for a period of tIDLE_OUT, the channel goes to an uncalibrated
state.
E. Power loss (which implies no data transitions) takes the channel to an uncalibrated state.
F. If, for some reason, the idle-high or idle-low state must be held on the line, this state must be held for at least tIDLE
.
Figure 25. DCD Correction Timing Diagram
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7821LLS device.
Table 2. ISO7821LLS Function Table(1)
INPUT
OUTPUT ENABLE
(ENx)
OUTPUT
VCCI
PU
X
VCCO
COMMENTS
(INx±)(2)
(OUTx±)(3)
H
L
I
H or open
H or open
H or open
H
L
Normal Operation:
A channel output assumes the logic state of the input.
PU
H or L
A low-logic state at the output enable causes the outputs to be in high
impedance.
PU
X
L
Z
Default mode: When VCCI is unpowered, a channel output assumes
the logic high state.
When VCCI transitions from unpowered to powered up, a channel
output assumes the logic state of the input.
PD
PU
X
H or open
H
When VCCI transitions from powered up to unpowered, a channel
output assumes the selected default high state.
When VCCO is unpowered, a channel output is undetermined.
X
PD
X
X
Undetermined When VCCO transitions from unpowered to powered up, a channel
output assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCCx ≥ 2.25 V); PD = Powered down (VCCx ≤ 1.7 V); X = Irrelevant
(2) Input (INx±): H = high level (VID ≥ 50 mV); L = low level (VID ≤ –50 mV); I = indeterminate (–50 mV < VID < 50 mV)
(3) Output (OUTx±): H = high level (VOD ≥ 250 mV); L = low level (VOD ≤ –250 mV); Z = high impedance.
8.4.1 Device I/O Schematics
LVDS Input
LVDS Output
V
CC
600 kꢀ
600 kꢀ
INxœ
V
CC
INx+
20 ꢀ
OUTx
20 kꢀ
Enable
VCC
275 kꢀ
1 kꢀ
ENx
Figure 26. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7821LLS device is a high-performance, reinforced isolated dual-LVDS buffer. Isolation can be used to
help achieve human and system safety, to overcome ground potential difference (GPD), or to improve noise
immunity and system performance.
The LVDS signaling can be used over most interfaces to achieve higher data rates because the LVDS is only a
physical layer. LVDS can also be used for a proprietary communication scheme implemented between a host
controller and a slave. Example use cases include connecting a high-speed I/O module to a host controller, a
subsystem connecting to a backplane, and connection between two high-speed subsystems. Many of these
systems operate under harsh environments making them susceptible to electromagnetic interferences, voltage
surges, electrical fast transients (EFT), and other disturbances. These systems must also meet strict limits on
radiated emissions. Using isolation in combination with a robust low-noise signaling standard such as LVDS,
achieves both high immunity to noise and low emissions.
Example end applications that could benefit from the ISO7821LLS device include high-voltage motor control, test
and measurement, industrial automation, and medical equipment.
9.2 Typical Application
One application for isolated LVDS buffers is for point-to-point communication between two high-speed capable,
application-specific integrated circuits (ASICs) or FPGAs. In a high-voltage motor control application, for
example, Node 1 could be a controller on a low-voltage or earth referenced board, and Node 2, could be
controller placed on the power board, biased to high voltage. Figure 27 and Figure 28 show the application
schematics.
Figure 28 provides further details of using the ISO7821LLS device to isolate the LVDS interface. The LVDS
connection to the ISO7821LLS device can be traces on a board (shown as straight lines between Node 1 and
the ISO7821LLS device), a twisted pair cable (as shown between Node 2 and the ISO7821LLS device), or any
other controlled impedance channel. Differential 100-Ω terminations are placed near each LVDS receiver. The
characteristic impedance of the channel should also be 100-Ω differential.
In the example shown in Figure 27 and Figure 28, the ISO7821LLS device provides reinforced or safety isolation
between the high-voltage elements of the motor drive and the low-voltage control circuitry. This configuration
also ensures reliable communication, regardless of the high conducted and radiated noise present in the system.
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Typical Application (continued)
Isolated IGBT
Gate Drivers
Rectifier Diodes
IGBT Module
DC+
Drive
Output
Power
Input
M
PWM
Signals
DCœ
ISO7821LLS
Communication Bus
RS-485, CAN,
Ethernet
Node 2
Node 1
Isolated Current
and Voltage Sense
Encoder
High Voltage Motor Drive
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Isolated LVDS Interface in Motor Control Application
VCC1
VCC2
0.1 ꢀF
0.1 ꢀF
3.3 V
3.3 V
1
16
Vcc2
Vcc1
7
10
14
13
12
EN1
EN2
3
4
5
6
INA+
OUTA+
Node 1
100 Ω
ISO7821LLS
100 Ω
Node 2
INAœ
OUTAœ
ASIC or FPGA
INBœ
OUTBœ
OUTB+
ASIC or FPGA
100 Ω
100 Ω
11
INB+
GND1
2, 8
GND2
9, 15
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Isolated LVDS Interface Between Two Nodes (ASIC or FPGA)
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Typical Application (continued)
9.2.1 Design Requirements
For the ISO7821LLS device, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
3 V to 5.5 V
0.5 |VID| to 2.4 – 0.5 |VID
100 Ω
Supply voltage range, VCC1 and VCC2
Receiver common-mode voltage range
External termination resistance
|
Interconnect differential characteristic impedance
Signaling rate
100 Ω
50 to 150 Mbps
0.1 µF
Decoupling capacitor from VCC1 and GND1
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
The ISO7821LLS device has minimum requirements on external components for correct operation. External
bypass capacitors (0.1 µF) are required for both supplies (VCC1 and VCC2). A termination resistor with a value of
100 Ω is required between each differential input pair (INx+ and INx–), with the resistors placed as close to the
device pins as possible. A differential termination resistor with a value of 100 Ω is required on the far end for the
LVDS transmitters. Figure 29 shows these connections.
VCC1
VCC2
1
16
0.1 ꢀF
0.1 ꢀF
GND2
OUTA+
OUTAœ
INBœ
GND1
INA+
2
3
15
14
LVDS
RX
LVDS
TX
100 ꢁ
INAœ
13
4
OUTBœ
12
11
10
9
5
6
7
8
LVDS
TX
LVDS
RX
100 ꢁ
OUTB+
EN1
INB+
EN2
GND1
GND2
Figure 29. Typical ISO7821LLS Circuit Hook-Up
22
Copyright © 2016, Texas Instruments Incorporated
ISO7821LLS
www.ti.com.cn
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISO7821LLS device incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
9.2.3 Application Curve
Figure 30 shows a typical eye diagram of the ISO7821LLS device which indicates low jitter and a wide-open eye
at the maximum data rate of 150 Mbps.
Figure 30. Eye Diagram at 150 Mbps PRBS, 3.3 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505. For such applications, detailed power supply design and transformer selection recommendations are
available in the following data sheets: SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0) and
SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies (SLLSEP9).
Copyright © 2016, Texas Instruments Incorporated
23
ISO7821LLS
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 31). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
While routing differential traces on a board, TI recommends that the distance between two differential pairs be
much higher (at least 2x) than the distance between the traces in a differential pair. This distance minimizes
crosstalk between the two differential pairs.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
The ISO7821LLS device requires no special layout considerations to mitigate electromagnetic emissions.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps (or rise and fall times higher than 1 ns) and trace
lengths of up to 10 inches, use standard FR–4 UL94V-0 epoxy-glass as PCB material. This PCB is preferred
over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption,
greater strength and stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 31. Layout Example
24
版权 © 2016, Texas Instruments Incorporated
ISO7821LLS
www.ti.com.cn
ZHCSFH5A –MARCH 2016–REVISED SEPTEMBER 2016
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
《数字隔离器设计指南》（文献编号：SLLA284）
《ISO782xLLx 隔离式双 LVDS 缓冲器评估模块》（文献编号：SLLU240）
《隔离相关术语》（文献编号：SLLA353）
《LVDS 所有者手册》（文献编号：SNLA187）
《SN6501 适用于隔离式电源的变压器驱动器》（文献编号：SLLSEA0）
《SN6505 适用于隔离式电源的低噪声 1A 变压器驱动器》（文献编号：SLLSEP9）
12.2 接收文档更新通知
要接收文档更新通知，请访问 www.ti.com.cn 您器件对应的产品文件夹。点击右上角的提醒我 (Alert me) 注册后，
即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO7821LLSDW
ISO7821LLSDWR
ISO7821LLSDWW
ISO7821LLSDWWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
ISO7821LLS
2000 RoHS & Green
45 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ISO7821LLS
ISO7821LLS
ISO7821LLS
DWW
DWW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7821LLSDWR
SOIC
SOIC
DW
16
16
2000
1000
330.0
330.0
16.4
24.4
10.75 10.7
18.0 10.0
2.7
3.0
12.0
20.0
16.0
24.0
Q1
Q1
ISO7821LLSDWWR
DWW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7821LLSDWR
SOIC
SOIC
DW
16
16
2000
1000
350.0
350.0
350.0
350.0
43.0
43.0
ISO7821LLSDWWR
DWW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO7821LLSDW
DW
SOIC
SOIC
16
16
40
45
506.98
507
12.7
20
4826
5000
6.6
9
ISO7821LLSDWW
DWW
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DWW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC SMALL OUTLINE
C
17.4
17.1
SEATING PLANE
A
0.1 C
PIN 1 ID AREA
14X 1.27
16
1
10.4
10.2
NOTE 3
2X
8.89
8
9
0.51
0.31
16X
(2.286)
14.1
13.9
NOTE 4
B
0.25
A B
C
2.65 MAX
0.28
0.22
TYP
SEE DETAIL A
(1.625)
0.25
GAGE PLANE
0.3
0.1
1.1
0.6
0 -8
DETAIL A
TYPICAL
4221501/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0,15 mm per side.
4. This dimension does not include interlead flash.
www.ti.com
EXAMPLE BOARD LAYOUT
DWW0016A
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
16X (1.875)
(14.5)
16X (2)
(14.25)
16X (0.6)
16X (0.6)
1
1
16
16
SYMM
SYMM
14X
8
14X
(1.27)
9
8
9
(1.27)
SYMM
(16.25)
SYMM
(16.375)
LAND PATTERN EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
SCALE:3X
LAND PATTERN EXAMPLE
STANDARD
SCALE:3X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221501/A 11/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWW0016A
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
8
9
(16.25)
SOLDER PASTE EXAMPLE
STANDARD
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
16X (1.875)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
8
9
(16.375)
SOLDER PASTE EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221501/A 11/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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