ISOW7741F [TI]
ISOW7741 5000-VRMS Reinforced Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-Noise DC-DC Converter;
| 型号： | ISOW7741F |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ISOW7741 5000-VRMS Reinforced Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-Noise DC-DC Converter |
| 文件： | 总41页 (文件大小：2191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISOW7741
SLLSFK1 – DECEMBER 2020
ISOW7741 5000-VRMS Reinforced Quad-Channel Digital Isolator with Integrated Low-
Emissions, Low-Noise DC-DC Converter
1 Features
2 Applications
•
•
100 Mbps data rate
Integrated DC-DC converter with low-emissions,
low-noise
•
•
•
•
•
Factory automation
Motor control
Grid infrastructure
Medical equipment
Test and measurement
– Emission optimized to meet CISPR 32 limits
– Low frequency power converter at 25 MHz
enabling low noise performance
3 Description
– Low output ripple: 24 mV
The ISOW7741 device is a galvanically-isolated quad-
channel digital isolator with an integrated high-
efficiency power converter with low emissions. The
integrated DC-DC converter provides up to 500 mW
of isolated power, eliminating the need for a separate
isolated power supply in space-constrained isolated
designs.
•
•
High efficiency output power
– Efficiency at max load: 45%
– Up to 0.5-W output power
– Visoout accuracy of 5%
– 5 V to 5 V: Available load current ≥ 110 mA
– 5 V to 3.3 V: Available load current ≥ 110 mA
– 3.3 V to 3.3 V: Available load current ≥ 60 mA
Independent power supply for channel isolator &
power converter
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
ISOW7741
ISOW7741F
DFM (20)
12.83 mm × 7.5 mm
– Logic supply (VIO): 1.71-V to 5.5-V
– Power converter supply (VDD): 3-V to 5.5-V
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
Reinforced isolation barrier:
– >100-year projected lifetime at 1 kVRMS working
voltage
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
VISOIN
VIO
EN_IO2
OUTA
Tx
Tx
Rx
Rx
INA
INB
OUTB
Rx
Tx
Tx
Rx
OUTC
IND
INC
– Up to 5000 VRMS isolation rating
– Up to 10 kVPK surge capability
– ±100 kV/µs typical CMTI
OUTD
EN_IO1
GND2
GND1
GND1
GND2
•
Safety-Related Certifications (pending):
– VDE reinforced insulation per DIN VDE V
0884-11:2017-01
VSEL
VDD
DC-DC
DC-DC
EN_DCDC
GND1
Primary
Secondary
VISOOUT
GND2
– UL 1577 component recognition program
– IEC 60950-1, IEC 62368-1, IEC 61010-1, IEC
60601-1 and GB 4943.1-2011 certifications
Extended temperature range: –40°C to +125°C
20-pin wide SOIC package
•
•
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
ISOW7741
SLLSFK1 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Power Ratings ............................................................7
7.6 Insulation Specifications ............................................ 8
7.7 Safety-Related Certifications ..................................... 9
7.8 Safety Limiting Values ................................................9
7.9 Electrical Characteristics - Power Converter ........... 10
7.10 Supply Current Characteristics - Power
Converter ....................................................................11
7.11 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 5-V .........................................................12
7.12 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 5-V ..........................................12
7.13 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 3.3-V ......................................................13
7.14 Supply Current Characteristics Channel
7.17 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 1.8-V ......................................................15
7.18 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 1.8-V .......................................15
7.19 Switching Characteristics - 5-V Supply ..................16
7.20 Switching Characteristics - 3.3-V Supply ...............17
7.21 Switching Characteristics - 2.5-V Supply ...............18
7.22 Switching Characteristics - 1.8-V Supply ...............19
8 Parameter Measurement Information..........................20
9 Detailed Description......................................................22
9.1 Overview...................................................................22
9.2 Functional Block Diagram.........................................23
9.3 Feature Description...................................................24
9.4 Device Functional Modes..........................................27
10 Application and Implementation................................29
10.1 Application Information........................................... 29
10.2 Typical Application.................................................. 29
11 Power Supply Recommendations..............................31
12 Layout...........................................................................32
12.1 Layout Guidelines................................................... 32
12.2 Layout Example...................................................... 33
13 Device and Documentation Support..........................34
13.1 Device Support....................................................... 34
13.2 Documentation Support.......................................... 34
13.3 Receiving Notification of Documentation Updates..34
13.4 Support Resources................................................. 34
13.5 Trademarks.............................................................34
13.6 Electrostatic Discharge Caution..............................34
13.7 Glossary..................................................................34
14 Mechanical, Packaging, and Orderable
Isolator - VIO, VISOIN = 3.3-V .......................................13
7.15 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 2.5-V ......................................................14
7.16 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 2.5-V .......................................14
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
December 2020
REVISION
NOTES
*
Initial Release
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5 Description (continued)
The high-efficiency of the power converter allows for operation at a wide operating ambient temperature range of
–40°C to +125°C. This device provides improved emissions performance, allowing for simplified board design
and has provisions for ferrite beads to further attenuate emissions. The ISOW7741 has been designed with
enhanced protection features in mind, including soft-start to limit inrush current, over-voltage and under-voltage
lock out, fault detection on the EN_DCDC pin, overload and short-circuit protection, and thermal shutdown.
The ISOW7741 device provides high electromagnetic immunity while isolating CMOS or LVCMOS digital I/Os.
The signal-isolation channel has a logic input and output buffer separated by a double capacitive silicon dioxide
(SiO2) insulation barrier, whereas, power isolation uses on-chip transformers separated by thin film polymer as
insulating material. This device has three channels in the forward and one channel in the reverse direction. If the
input signal is lost, the default output is high for the ISOW7741 device without the F suffix and low for the
ISOW7741F device with the F suffix. The ISOW7741 can operate from a single supply voltage of 3 V to 5.5 V by
connecting VIO and V DD together on PCB. If lower logic levels are required, these devices support 1.71 V to 5.5
V logic supply (VIO) that can be independent from the power converter supply (VDD) of 3 V to 5.5 V. VISOIN and
VISOOUT needs to be connected on board with either a ferrite bead or fed through a LDO.
This device helps prevent noise currents on data buses, such as UART, SPI, RS-485, RS-232, and CAN, or
other circuits from entering the local ground and interfering with or damaging sensitive circuitry. Through
innovative chip design and layout techniques, electromagnetic compatibility of the device has been significantly
enhanced to ease system-level ESD, EFT, surge and emissions compliance. The device is available in a 20-pin
SOIC wide-body (SOIC-WB) DFM package.
6 Pin Configuration and Functions
VIO
INA
INB
1
2
3
20
19
18
VISOIN
OUTA
OUTB
INC
4
5
6
17
16
15
OUTC
IND
OUTD
GND1
GND2
EN_IO1
7
14
EN_IO2
EN_DCDC
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
Figure 6-1. ISOW7741 DFM Package 20-Pin SOIC-WB Top View
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Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
ISOW7741
GND1
GND2
6, 10
—
—
Ground connection for VDD and VIO. Both GND1 pins needs to be shorted on board.
Ground connection for VISOIN and VISOOUT. GND2 pins can be shorted on board or connected
through a ferrite bead. See the Layout Section for more information.
11, 15
INA
2
3
I
I
Input channel A
Input channel B
Input channel C
Input channel D
Output channel A
Output channel B
Output channel C
Output channel D
INB
INC
4
I
IND
16
19
18
17
5
I
OUTA
OUTB
OUTC
OUTD
O
O
O
O
Output Enable 1: When EN_IO1 is high or open then the channel output pins on side 1 are enabled.
When EN_IO1 is low then the channel output pins on side 1 are in a high impedance state and the
transmitter of the channel input pins on side 1 are disabled.
EN_IO1
EN_IO2
7
I
I
Output Enable 2: When EN_IO2 is high or open then the channel output pins on side 2 are enabled.
When EN_IO2 is low then the channel output pins on side 2 are in a high impedance state and the
transmitter of the channel input pins on side 2 are disabled.
14
Multi-function power converter enable input pin or fault output pin. Can only be used as either an
input pin or an output pin.
Power converter enable input pin: enables and disables the integrated DC-DC power converter.
Connect directly to microcontroller or through a series current limiting resistor to use as an enable
input pin. DC-DC power converted is enabled when EN_DCDC is high and disabled when low.
Fault output pin: Alert signal if power converter is not operating properly. This pin is active low.
Connect to microcontroller through a 5 kΩ or greater pull-up resistor in order to use as a fault outpin
pin.
EN_DCDC
VSEL
8
I/O
See Section 9.3.3 for more information
VISOOUT selection pin. VISOOUT = 5 V when VSEL shorted to VISOOUT. VISOOUT = 3.3 V, when VSEL
shorted to GND2 or when left floating. For more information see the Device Functional Modes.
13
I
VIO
1
9
—
—
—
—
Side 1 logic supply.
VDD
Side 1 DC-DC converter power supply.
VISOIN
VISOOUT
20
12
Side 2 supply voltage for isolation channels. This pin and VISOOUT needs to be shorted on board.
Isolated power converter output voltage. This pin and VISOIN needs to be shorted on board.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–15
MAX
UNIT
V
VDD
Power converter supply voltage
Isolated supply voltage, input supply for secondary side isolation channels
Isolated supply voltage, Power converter output
Primary side logic supply voltage
Voltage at INx, OUTx, EN_IOx
6
VISOIN
VISOOUT
VIO
6
V
6
V
6
VIO + 0.5
VIO + 0.5
VISOOUT + 0.5
15
V
V
V
Voltage at EN_DCDC
V
Voltage at VSEL
V
IO
Maximum output current through data channels
Junction temperature
mA
°C
°C
TJ
–40
150
Tstg
Storage temperature
–65
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD, VISOIN VISOOUT, and VIO are with respect to the local ground pin (GND1 or GND2). All voltage values except differential I/O bus
voltages are peak voltage values.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±4000
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
V(ESD)
±1500
±8000
V
Contact discharge per IEC 61000-4-2(2)
Isolation barrier withstand test
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
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UNIT
SLLSFK1 – DECEMBER 2020
7.3 Recommended Operating Conditions
MIN
NOM
MAX
Power Converter
3.3 V operation
5 V operation
2.97
4.5
3.3
5
3.63
5.5
V
V
Power converter supply
voltage
VDD
VDD(UVLO Positive threshold when power Positive threshold when power converter
converter supply is rising supply is rising
2.7
2.95
V
V
V
+)
VDD(UVLO- Positive threshold when power Positive threshold when power converter
2.40
0.15
2.55
converter supply is falling
supply is falling
)
Power converter supply
voltage hysteresis
VDD(HYS)
Power converter supply voltage hysteresis
Channel Isolation
1.8 V operation
1.71
2.25
1.89
5.5
V
V
VIO
VISOIN
,
Channel logic supply voltage
2.5 V, 3.3 V, and 5 V operation
VIO(UVLO
Rising threshold of logic supply voltage
1.55
1.41
1.7
V
+)
VIO(UVLO-) Falling threshold of logic supply voltage
VIO(HYS) Logic supply voltage hysteresis
1.0
75
–4
–2
–1
–1
V
mV
mA
mA
mA
mA
mA
mA
mA
mA
V
VISOIN = 5 V
VISOIN = 3.3 V
VISOIN = 2.5 V
VISOIN = 1.8 V
VISOIN = 5 V
IOH
High level output current(1)
Low level output current(1)
4
VISOIN = 3.3 V
VISOIN = 2.5 V
VISOIN = 1.8 V
2
IOL
1
1
VIH
VIL
DR
High-level input voltage
Low-level input voltage
Data rate
0.7 × VSI
0
VSI
0.3 × VSI
100
V
Mbps
Channel isolator ready after
power up or EN_DCDC high
tPWRUP
TA
VISOIN > VIO(UVLO+)
5
ms
°C
Ambient temperature
–40
125
(1) This current is for data output channel.
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7.4 Thermal Information
ISOW7741
DFM (SOIC)
20 PINS
68.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
24.6
53.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.1
ΨJB
50.9
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VDD = VIO = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤ 80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.48
0.74
0.74
UNIT
W
PD
Maximum power dissipation (both sides) VDD = 5.5 V, VIO = 5.5 V, VISOOUT
=
VISOIN, IISOOUT = 100 mA, TJ = 150°C,
TA ≤ 80°C, CL = 15 pF, input a 50-MHz
50% duty-cycle square wave
PD1
PD2
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
W
W
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UNIT
SLLSFK1 – DECEMBER 2020
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
Minimum internal gap (internal clearance – capacitive
signal isolation)
> 17
DTI
CTI
Distance through the insulation
µm
V
Minimum internal gap (internal clearance –
transformer power isolation)
>120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
Rated mains voltage ≤ 300 VRMS
I-IV
I-IV
I-III
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
DIN V VDE 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
1500
VPK
voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
1000
1500
7071
VRMS
VDC
VPK
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)
6250
≤ 5
VPK
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s
≤ 5
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and
preconditioning (type test),
Vini = 1.2 × VIOTM, tini = 1 s;
≤ 5
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance(5)
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~3.5
> 1012
> 1011
> 109
pF
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V, TS = 150°C
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%
production)
VISO(UL) Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
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(5) All pins on each side of the barrier tied together creating a two-terminal device.
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to IEC
60950-1, IEC 62368-1, and IEC 1577 Component
60601-1
Recognized under UL
Certified according to EN
61010-1:2010 and EN
60950- 1:2006/A2:2013
Certified according to DIN
V VDE V 0884-11:2017-01
Certified according to
GB 4943.1-2011
Recognition Program
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2, CSA
62368-1-14 and IEC
62368-1:2014, 800 VRMS
maximum working voltage
(pollution degree 2, material
group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3+A1, 250
VRMS maximum working
voltage. Temperature rating is
90°C for reinforced insulation
and 125°C for basic insulation;
see certificate for details.
Reinforced insulation;
Maximum transient
isolation voltage, 7071
5000 VRMS Reinforced
insulation per EN 61010-
1:2010 up to working
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate, 700
VPK
;
voltage of 600 VRMS
;
Single protection, 5000
VRMS
Maximum repetitive peak
isolation voltage, 1500
5000 VRMS Reinforced
VRMS maximum working insulation per EN 60950-
VPK
;
voltage;
1:2006/A2:2013 up to
working voltage of 800
VRMS
Maximum surge isolation
voltage, 6250 VPK
Certification Planned
Certification Planned
Certification Planned
Certification Planned
Certification Planned
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
332
IS
Safety input, output, or supply current(1)
mA
RθJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
507
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
RθJA = 68.5°C/W, TJ = 150°C, TA = 25°C
1825
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Section 7.4 table is that of a device installed on a high-K test board for leaded
surface-mount packages. Use the following equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% and VISOIN power externally (over recommended operating conditions, unless otherwise
specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, VISOOUT = 5 V, VSEL = VISOOUT
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 55 mA
External IISOOUT = 0 to 110 mA
4.75
4.5
5
5
5.25
5.25
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 55 mA, VDD = 4.5 V to 5.5 V
IISOOUT = 0 to 110 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW7741); VI =0 V (ISOW7741
with F suffix).
Efficiency at maximum load
current (1)
EFF
45%
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
24
mV
mA
(pk-pk)
IISOOUT = 110 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
250
VDD = 5 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 55 mA
External IISOOUT = 0 to 110 mA
3.15
3.15
3.3
3.3
3.45
3.45
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 55 mA, VDD = 4.5 V to 5.5 V
IISOOUT = 0 to 110 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW7741); VI =0 V (ISOW7741
with F suffix).
Efficiency at maximum load
current (1)
EFF
38%
Output ripple on isolated supply 20-MHz bandwidth , CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
30
mV
mA
(pk-pk)
IISOOUT = 110 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
250
VDD = 3.3 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 30 mA
External IISOOUT = 0 to 60 mA
3.15
3
3.3
3.3
3.45
3.45
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 30 mA, VDD = 3.0 V to 3.6 V
IISOOUT = 0 to 60 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 60 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW7741); VI =0 V (ISOW7741
with F suffix).
Efficiency at maximum load
current (1)
EFF
42%
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
14
mV
mA
(pk-pk)
IISOOUT = 60 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
160
(1) Power converter ILOAD = current required to power the secondary side. ILOAD does not take into account the channel isolator current.
See Supply Current Characteristics Channel Isolator section for details.
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7.10 Supply Current Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT
Power Converter Disabled
Power converter supply
current
EN_DCDC = GND1, VISOOUT = No ILOAD
EN_DCDC = GND1
IDD
0.28
0.27
0.45
0.57
mA
mA
Logic supply current
IIO
Power Converter Enabled
VDD = 5 V, VSEL = VISOOUT
VDD = 5 V, VSEL = VISOOUT
VDD = 5 V, VSEL = GND2
VDD = 5 V, VSEL = GND2
VDD = 3.3 V, VSEL = GND2
VDD = 3.3 V, VSEL = GND2
VDD = 5 V
ILOAD = 55 mA
115
225
96
171
316
130
240
112
216
mA
mA
mA
mA
mA
mA
mA
mA
mA
ILOAD = 110 mA
ILOAD = 55 mA
ILOAD = 110 mA
ILOAD = 30 mA
ILOAD = 60 mA
VSEL = VISOOUT
VSEL = GND2
VSEL = GND2
Power converter supply
current input
IDD
187
74
143
110
110
60
Power converter output
current (1)
VDD = 5 V
IISOOUT
VDD = 3.3 V
(1) Power converter ILOAD = current required to power the secondary side. ILOAD does not take into account the channel isolator current.
See Supply Current Characteristics Channel Isolator section for details.
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UNIT
SLLSFK1 – DECEMBER 2020
7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Channel Isolation
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
–25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
IO = –4 mA, see TBD
V
V
0.4
IO = 4 mA, see TBD
0.4
Common mode transient
immunity
CMTI
VI = VSI or 0 V, VCM = 1000 V; see TBD
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% (over recommended operating conditions, unless otherwise specified)
SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
IDD_IO
2.8
4.3
2.8
4.3
2.8
4.3
6.1
5.5
4.4
4.9
5
4.1
6.3
4.1
6.3
4.1
6.3
8.4
7.9
6.3
7.1
6.9
8.7
12.9
32
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
6.3
11
100 Mbps
21.4
(1) VCCI = VIO or VISOIN
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7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Isolation
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
IO = –4 mA, see TBD
V
V
0.3
IO = 4 mA, see TBD
0.3
Common mode transient
immunity
CMTI
VI = VSI or 0 V, VCM = 1000 V; see TBD
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% (over recommended operating conditions, unless otherwise specified)
SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
IDD_IO
2.8
4.2
2.8
4.2
2.8
4.2
6.1
5.5
4.4
4.9
4.8
5.9
8.4
15.1
4
6.3
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
6.3
4
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
6.3
8.3
7.9
6.3
7.1
6.7
8.1
10.8
24.3
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
(1) VCCI = VIO or VISOIN
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UNIT
SLLSFK1 – DECEMBER 2020
7.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Channel Isolation
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
IO = –4 mA, see TBD
V
V
0.1
IO = 4 mA, see TBD
0.1
Common mode transient
immunity
CMTI
VI = VSI or 0 V, VCM = 1000 V; see TBD
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% (over recommended operating conditions, unless otherwise specified)
SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
IDD_IO
2.7
4.2
2.7
4.2
2.7
4.2
6.1
5.4
4.4
4.9
4.7
5.6
7.5
12.6
4.3
6.3
4.3
6.3
4.3
6.3
8.3
7.9
6.3
7.1
8.3
7.9
9.7
18.8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
(1) VCCI = VIO or VISOIN
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7.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±10% (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Isolation
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
IO = –4 mA, see TBD
V
V
0.1
IO = 4 mA, see TBD
0.1
Common mode transient
immunity
CMTI
VI = VSI or 0 V, VCM = 1000 V; see TBD
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% (over recommended operating conditions, unless otherwise specified)
SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
IDD_IO
2.4
3.8
2.4
3.8
2.4
3.8
5.5
5
3.6
4.6
3.6
4.6
3.6
4.6
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
6
4.4
4.9
4.6
5.4
6.2
10
6.3
7.1
6.5
7.6
8.3
14.5
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
(1) VCCI = VIO or VISOIN
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MAX UNIT
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7.19 Switching Characteristics - 5-V Supply
VIO = VISOIN = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
10.7
1
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
15.5
5
ns
ns
ns
ns
ns
ns
See TBD
|
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
See TBD
4
4.4
4
Output signal rise time
1.9
1.9
tf
Output signal fall time
4
Channel disable propagation delay, high-to-high
impedance output
tPHZ
tPLZ
24.5
24.5
26.2
26.2
25.8
25.8
33.2
33.2
33.1
33.1
33.1
33.1
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high
impedance output
Channel enable propagation delay, high impedance-
to-high output for ISOW7741
tPZH
See TBD
Channel enable propagation delay, high impedance-
to-high output for ISOW7741 with F suffix
Channel enable propagation delay, high impedance-
to-low output for ISOW7741
tPZL
Channel enable propagation delay, high impedance-
to-low output for ISOW7741 with F suffix
Measured from the time VIO or
VISOIN goes below 1.6 V at 10
mV/ns. See TBD
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.8
0.3
μs
ns
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.20 Switching Characteristics - 3.3-V Supply
VIO = VISOIN = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
6
16
5
ns
ns
ns
ns
ns
ns
See TBD
|
0.1
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
See TBD
4.1
4.5
4
Output signal rise time
0.62
0.62
tf
Output signal fall time
4
Channel disable propagation delay, high-to-high
impedance output
tPHZ
tPLZ
29.3
29.3
29.9
29.9
28.8
28.8
42
39
40
41
41
41
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high
impedance output
Channel enable propagation delay, high impedance-
to-high output for ISOW7741
tPZH
See TBD
Channel enable propagation delay, high impedance-
to-high output for ISOW7741 with F suffix
Channel enable propagation delay, high impedance-
to-low output for ISOW7741
tPZL
Channel enable propagation delay, high impedance-
to-low output for ISOW7741 with F suffix
Measured from the time VIO or
VISOIN goes below 1.6 V at
10mV/ns. See TBD
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.9
0.3
μs
ns
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SLLSFK1 – DECEMBER 2020
7.21 Switching Characteristics - 2.5-V Supply
VIO = VISOIN = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
12
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
7.5
18
5
ns
ns
ns
ns
ns
ns
See TBD
|
0.2
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
See TBD
4.1
4.6
4
Output signal rise time
0.9
0.9
tf
Output signal fall time
4
Channel disable propagation delay, high-to-high
impedance output
tPHZ
tPLZ
36.2
36.2
35.9
35.9
34.3
34.3
54.6
54.6
49.2
49.2
52.5
52.5
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high
impedance output
Channel enable propagation delay, high impedance-
to-high output for ISOW7741
tPZH
See TBD
Channel enable propagation delay, high impedance-
to-high output for ISOW7741 with F suffix
Channel enable propagation delay, high impedance-
to-low output for ISOW7741
tPZL
Channel enable propagation delay, high impedance-
to-low output for ISOW7741 with F suffix
Measured from the time VIO or
VISOIN goes below 1.6 V at 10
mV/ns. See TBD
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
ns
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.22 Switching Characteristics - 1.8-V Supply
VIO = VISOIN = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
15
MAX UNIT
tPLH, tPHL
PWD
tsk(o)
tsk(pp)
tr
7.5
22.5
5.5
4.1
4.6
4
ns
ns
ns
ns
ns
ns
See TBD
|
0.1
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
See TBD
Output signal rise time
2.2
2.2
tf
Output signal fall time
4
Channel disable propagation delay, high-to-high
impedance output
tPHZ
tPLZ
53
53
80.2
80.2
69.5
69.5
76.7
76.7
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high
impedance output
Channel enable propagation delay, high impedance-
to-high output for ISOW774x
52.6
52.6
49.6
49.6
tPZH
See TBD
Channel enable propagation delay, high impedance-
to-high output for ISOW774x with F suffix
Channel enable propagation delay, high impedance-
to-low output for ISOW774x
tPZL
Channel enable propagation delay, high impedance-
to-low output for ISOW774x with F suffix
Measured from the time VIO or
VISOIN goes below 1.6 V at
10mV/ns. See TBD
tDO
tie
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
ns
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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8 Parameter Measurement Information
In the below images, VCCI and VCCO refers to the power supplies VIO and VISOIN, respectively.
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. CL = 15 pF and The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns,
tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-1. Switching Characteristics Test Circuit and Voltage Waveforms
VCC1
VCC / 2
VCC / 2
VI
0 V
VOH
tPZH
VO
IN
OUT
0 V or 3 V
50%
0.5 V
VO
EN
0 V
RL = 1 kꢀ 1%
tPHZ
CL
See Note B
tPZL
tPLZ
Input
Generator
(See Note A)
VOH
0.5 V
VOL
VI
50 ꢀ
VO
50%
A. A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
=
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
VCCI
See Note B
V
CCI
V
1.4 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
A. A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. B. Power Supply Ramp Rate = 10 mV/ns.
Figure 8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
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5V
Connected to Visoout on PCB
VISOIN
VIO
0.01uF
1uF
10uF
10uF
1uF
0.01uF
VIO
GND1
OUT
IN
5V
GND1
VDD
C
L
10uF
1uF
0.01uF
GNDI
GND2
+
œ
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Optional 100 µF capacitor can be added between VDD and GND1; refer to Section 11.
C. Pass-fail criteria: Outputs must remain stable.
Figure 8-4. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISOW7741 device has a low-noise, low-emissions isolated DC-DC converter, and four high- speed isolated
data channels. Section 9.2 shows the functional block diagram of the ISOW7741 device.
9.1.1 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve upto 45% typical efficiency. The integrated transformer uses thin film polymer as
the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using VSEL pin. The
DC-DC converter can be switched off using the EN_DCDC (enable) pin to save power. The output voltage,
VISOOUT , is monitored and feedback information is conveyed to the primary side through a dedicated isolation
channel. VISOOUT needs to be connected to VISOIN to ensure the feedback channel is properly powered to
regulate the DC-DC converter. This can be achieved by connecting the pins directly or through an LDO that
remains powered up at all times. A ferrite bead is recommended between Visoout and Visoin to further reduce
emissions. See the Section 10.2 section. The duty cycle of the primary switching stage is adjusted accordingly.
The fast feedback control loop of the power converter ensures low overshoots and undershoots during load
transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOIN supplies which
ensures robust fails-safe system performance under noisy conditions. An integrated soft-start mechanism
ensures controlled inrush current and avoids any overshoot on the output during power up.
9.1.2 Signal Isolation
The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier across
the barrier to represent one state and sends no signal to represent the other state. The receiver demodulates the
signal after signal conditioning and produces the output through a buffer stage. The signal-isolation channels
incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions from the high frequency carrier and IO buffer switching. Figure 9-1 shows a functional block diagram
of a typical signal isolation channel. In order to keep any noise coupling from power converter away from signal
path, power supplies on side 1 for power converter (VDD) and signal path(VIO) are kept separate. Similarly on
side 2, power converter output (VISOOUT) needs to be connected to VISOIN externally on PCB. Emissions can be
further improved by placing a ferrite bead between VISOOUT and VISOIN as well as between the GND2 pins. For
more details, refer to the Layout Guidelines section.
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9.2 Functional Block Diagram
V
V
ISOIN
IO
Isolation Barrier
VISOOUT and
VISOIN needs to
be directly
connected or
through an
LDO on board
that is always
powered.
Data Channels
(4)
Data Channels
(4)
I/O Channels
I/O Channels
FB Controller
V
ref
FB Channel (Rx)
FB Channel (Tx)
Thermal
Shutdown,
UVLO, Soft-start
UVLO, Soft-start
Transformer
Driver
Power
Controller
Rectifier
V
ISOOUT
V
DD
Transformer
Figure 9-1. Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Figure 9-2. Conceptual Block Diagram of a Capacitive Data Channel
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Figure 9-3 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 9-3. On-Off Keying (OOK) Based Modulation Scheme
9.3 Feature Description
Table 9-1 shows an overview of the device features.
Table 9-1. Device Features
DEFAULT OUTPUT
STATE
PART NUMBER 1
CHANNEL DIRECTION
MAXIMUM DATA RATE
RATED ISOLATION 2
ISOW7741
High
Low
3 forward, 1 reverse
100 Mbps
5 kVRMS / 7071 VPK
ISOW7741F
1. The F suffix is part of the orderable part number. See the Section 14 section for the full orderable part
number.
2. For detailed isolation ratings, see the Section 7.7 table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
The ISOW7741 device uses emissions reduction schemes for the internal oscillator and advanced internal layout
scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISOW7741 device incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
•
•
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Power path and signal path separated to minimize internal high frequency coupling and allowing for an
external filtering knob using ferrite beads available to further reduce emissions
Reduced power converter switching frequency to 25 Mhz to reduce strength of high frequency components in
emissions spectrum
•
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9.3.2 Power-Up and Power-Down Behavior
The ISOW7741 device has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and negative-
going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to be
present for the device to work. If either of them is below its UVLO, both the signal path and the power converter
are disabled.
When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter
initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits
primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner,
avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO or VDD
voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the
secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower
threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data
outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to
discharge to zero.
9.3.3 Protection Features
The ISOW7741 devicehas multiple protection features to create a robust system level solution.
•
The first feature is an Enable DC-DC /fault protection feature. This pin can be used as either an input pin to
enable or disable the integrated DC-DC power converter or as an output pin which works as an alert signal if
the power converter is not operating properly. In the /fault use case, a fault is reported if VDD > 7 V, VDD < 2.5
V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC
converter to prevent any damage.
EN_DCDC
Powers down digital isolator
and DCDC converter.
IQ < 1mA typical
MCU
OUTPUT
≥ 5 kꢀ
MCU INPUT
Fault reported if
VDD < 2.5 V
VDD > 7 V
Junction Temp > 170° C
Figure 9-4. EN_DCDC Fault Pin Diagram
•
Over-voltage lock out on VDD will occur when a voltage higher than 7 V is seen. The device will go into a low
power state and the EN_DCDC pin will go low. It is highly recommended that the VDD abs max condition of
6V is not violated.
•
•
An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6V if there is an increase
in voltage seen.
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISO short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISO short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISO short-
circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
•
•
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•
Thermal protection is also integrated to help prevent the device from getting damaged during overload and
short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to
increase. When the temperature goes above 165°C, thermal shutdown activates and the primary controller
turns off which removes the energy supplied to the VISO load, which causes the device to cool off. When the
junction temperature goes below 150°C, the device starts to function normally. If an overload or output short-
circuit condition prevails, this protection cycle is repeated. Care should be taken in the design to prevent the
device junction temperatures from reaching such high values.
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9.4 Device Functional Modes
The below table lists the supply configurations for these devices.
Table 9-2. Supply Configuration Function Table
(1)
(3)
VDD
VIO
MODE
VISOOUT
< VDD(UVLO+)
>VDD(UVLO+)
5 V
>VIO(UVLO+)
<VIO(UVLO+)
1.71 V to 5.5 V
1.71 V to 5.5 V
X
OFF
OFF
5 V
X
High(shorted to VISOOUT
)
5 V or 3.3 V
Low(shorted to GND2) or floating (2)
3.3 V
(1) VDD= 3.3 V, MODE shorted to VISOOUT(essentially VISOOUT = 5 V) is not the recommended mode of operation
(2) The MODE pin has a weak pulldown internally. Therefore for VISOOUT = 3.3 V, the MODE pin should be strongly connected to the
GND2 pin in noisy system scenarios.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN=High
Table 9-3 lists the channel isolators functional modes for these devices.
Table 9-3. Channel Isolator Function Table
INPUT SUPPLY
OUTPUT
SUPPLY (VISOIN)
INPUT
(INx)
IO ENABLE
(ENx)
OUTPUT
(OUTx)
(1)
COMMENTS
(VIO
)
H or
Open
H
L
H
L
Normal Operation: A channel output
assumes the logic state of its input.
H or Open
Default mode(2): When INx is open, the
corresponding channel output goes to its
default logic state.
Open
H or Open
Default
PU
PU
A low value of output enable causes the
outputs of the same side to be high
impedance. The output of opposite side
will be Default if opposite side IO
ENABLE is H or open.
X
L
Z and Default
Default mode: When VCCI is unpowered,
a channel output assumes the logic state
based on the selected default option.
Default is High for ISOW7741 and Low
for ISOW7741 with F suffix. When VCCI
transitions from unpowered to powered-
up, a channel output assumes the logic
state of the input. When VCCI transitions
from powered-up to unpowered, channel
output assumes the selected default
state.
PD
PU
X
H or Open
Default
(1) PU = Powered up (VIO > 1.7 V, VISOIN > 1.7 V); PD = Powered down (VIO < 1 V, VISOIN < 1 V); X = Irrelevant; H = High level; L = Low
level, VCC = Input-side supply
(2) In the default condition, the output is high for the ISOW7741 device with the F suffix.
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9.4.1 Device I/O Schematics
VCC1 = VIO or VIOSIN
VCC1 = VIO or VIOSIN
INx (Devices without F suffix)
INx (Devices with F suffix)
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
VSEL Pin
OUTx
VISOOUT
VISOOUT
VISOOUT
VISOOUT
~20 ꢀ
1970 ꢀ
OUTx
SEL
2 Mꢀ
ENABLE_IOx
Enable_DCDC
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
550 kꢀ
550 kꢀ
20 kꢀ
20 kꢀ
985 ꢀ
985 ꢀ
INx
INx
Fault
1mA
Figure 9-5. Device I/O Schematics
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The device is a high-performance, quad channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used to
power isolated side of the device and peripherals on isolated side, thus saving board space. The device uses
single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that because
of the single-ended design structure, digital isolators do not conform to any specific interface standard and are
only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between
the data controller (that is Microcontroller or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
The device is suitable for applications that have limited board space and desire more integration. The device is
also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
10.2 Typical Application
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Design TIDA-01333, Eight-Channel, Isolated, High-Voltage
Analog Input Module With ISOW7841 Reference Design.
Figure 10-1 shows the typical schematic for SPI isolation.
Reference
10 ꢀF
1 ꢀF 10 nF
10 nF
1 ꢀF
10 ꢀF
3.3VIN
VIO
VISOIN
3.3VOUT
DVCC
AVDD
DVDD
REF
CS
CS
INA
INB
OUTA
OUTB
HV+ to Chassis
HV- to Chassis
SCLK
SCLK
ADC
MCU
DVSS
SDI
SDO
SDI
INC
OUTC
IND
SDO
OUTD
AGND
DGND
ISOW7741
GND1
GND2
330 ꢁ at 100 MHz
(BLM15EX331SN1D)
VSEL
VISOOUT
VDD
IN OUT
1 ꢀF
10 nF
10 nF
1 ꢀF
10 ꢀF
10 ꢀF
GND
GND1
GND2
330 ꢁ at 100 MHz
(BLM15EX331SN1D)
Optional LDO
Figure 10-1. Isolated Power and SPI for ADC Sensing Application with ISOW7741
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10.2.1 Design Requirements
To design with this device, use the parameters listed in Table 10-1.
Table 10-1. Design Parameters
PARAMETER
VALUE
Input voltage
3 V to 5.5 V
Decoupling capacitor between VDD and GND1
Decoupling capacitor between VISOOUT and GND2
0.01 µF to 20 µF
0.01 µF to 20 µF
Because of very-high current flowing through the ISOW7741 device device VDD and VISOOUT supplies, higher
decoupling capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor is
adequate, higher decoupling capacitors (such as 47 µF) on both the VDD and VISOOUT pins to the respective
grounds are strongly recommended to achieve the best performance.
10.2.2 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-2 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 10-3 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 10-2. Test Setup for Insulation Lifetime Measurement
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Figure 10-3. Insulation Lifetime Projection Data
11 Power Supply Recommendations
To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. VISOOUT needs to be connected to VISOIN to ensure the
feedback channel is properly powered to regulate the DC-DC converter. This can be achieved by connecting the
pins directly or through an LDO that remains powered up at all times. A ferrite bead is recommended between
VISOOUT and VISOIN to further reduce emissions. If VISOOUTand VISOIN are not connected, the DC-DC converter
will run open loop and the VISOOUT voltage will drift until the over-voltage clamp clamps at 6 V. The input supply
(VIO and VDD) must have an appropriate current rating to support output load and switching at the maximum data
rate required by the end application. For more information, refer to the Section 10.2 section.
For an output load current of 110 mA, it is recommended to have >600 mA of input current limit and for lower
output load currents, the input current limit can be proportionally lower.
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12 Layout
12.1 Layout Guidelines
A low cost two layer PCB should be sufficient to achieve good EMC performance:
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective
GND pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature
of the device from rising to unacceptable levels.
Figure 12-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines
must be followed to meet application EMC requirements:
•
High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 2 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins.
Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on VISOOUT and GND2 path so that any
high frequency noise from power converter output sees a high impedance before it goes to other components
on PCB.
•
•
•
•
•
Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT pin12
and GND2 pin11. VSEL pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for
output voltage selection.
Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
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12.2 Layout Example
Ground plane on
side2
Ground plane on
side1
C
C
C
C
C
C
VISOIN
VIO
20
19
1
10 nF 1 ꢀF 10 ꢀF
10 ꢀF 1 ꢀF
10 nF
INA
OUTA
2
INB
INC
OUTB
OUTC
3
4
18
17
16
15
14
13
OUTD
GND1
5
IND
GND2
6
EN_IO1
7
EN_IO2
VSEL
Ground
plane on
side2
EN_DCDC
8
10 ꢀF 1 ꢀF
10 nF
10 nF 1 ꢀF 10 ꢀF
FB
1
VDD
9
12 VISOOUT
C
C
C
C
C
C
FB
2
GND1
GND2
11
10
Figure 12-1. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For development support, refer to:
•
•
•
8-ch Isolated High Voltage Analog Input Module with ISOW7841 Reference Design
Isolated RS-485 With Integrated Signal and Power Reference Design
Isolated RS-232 With Integrated Signal and Power Reference Design
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, Isolation Glossary
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW7741DFM
ISOW7741DFMR
ISOW7741FDFM
ISOW7741FDFMR
XISOW7741DFMR
XISOW7741FDFMR
PREVIEW
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DFM
20
20
20
20
20
20
40
RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
PREVIEW
PREVIEW
PREVIEW
ACTIVE
DFM
2000 RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
Call TI
Call TI
DFM
40
RoHS (In work)
& Non-Green
DFM
2000 RoHS (In work)
& Non-Green
DFM
2000 RoHS (In work)
& Non-Green
ACTIVE
DFM
2000 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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