ISOW7821 [TI]
具有集成电源的双通道、1/1、增强型数字隔离器;
| 型号： | ISOW7821 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电源的双通道、1/1、增强型数字隔离器 |
| 文件： | 总43页 (文件大小：2093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
具有集成式高效低辐射直流/直流转换器的 ISOW7821 高性能 5000VRMS 增
强型双通道数字隔离器
1 特性
2 应用
1
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集成高效直流/直流转换器与片上变压器
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工业自动化
100Mbps 数据速率
电机控制
稳健可靠的隔离栅：
电网基础设施
医疗设备
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–
–
–
在 1kVRMS 工作电压下，预计寿命超过 100 年
高达 5000V 的 RMS 隔离额定值
高达 10kVPK 的浪涌保护能力
测试和测量
3 说明
±100kV/µs 最低 CMTI
ISOW7821 器件是具有集成式高效电源转换器的高性
能、双通道增强型数字隔离器。集成式直流/直流转换
器高效运行，提供高达 650mW 的隔离式电源，可配
置为各种输入和输出电压。因此，空间受限的隔离设计
凭借该器件无需单独使用隔离式电源。
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3V 至 5.5V 宽输入电源电压范围
5V 或 3.3V 稳压输出
高达 0.65W 的输出功率
5V 至 5V；5V 至 3.3V：提供的负载电流 ≥ 130mA
3.3V 至 3.3V：提供的负载电流 ≥ 75mA
限制浪涌电流的软启动
器件信息(1)
过载保护和短路保护
器件型号
ISOW7821
封装
SOIC (16)
封装尺寸（标称值）
热关断
10.30mm x 7.50mm
默认输出：高电平和低电平选项
低传播延迟：典型值为 13ns（由 5V 电源供电）
优异的电磁兼容性 (EMC)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
–
–
–
系统级 ESD、EFT 和浪涌抗扰性
±8kV IEC 61000-4-2 跨隔离栅接触放电保护
低辐射
Isolation Transformer
DC-DC
Primary
DC-DC
Secondary
VCC
VISO
•
•
•
16 引脚宽体小外形尺寸集成电路 (SOIC) 封装
扩展温度范围：-40°C 至 +125°C
安全相关认证：
VSI
VSO
Isolation Capacitors
INx
OUTx
–
–
–
符合 DIN VDE V 0884-11:2017-01 标准的
7071VPK 增强型隔离
GNDI
GNDO
符合 UL 1577 标准且长达 1 分钟的 5000VRMS
隔离
V
CC 是以 GND1 为基准的主电源电压。VISO
是以 GND2 为基准的隔离电源电压。
SI 和 VSO 可为 VCC 或 VISO，具体取决于
通道方向。
SI 是以 GNDI 为基准的输入侧电源电压，
获得 CSA 认证，符合 IEC 60950-1、IEC
62368-1 和 IEC 60601-1 终端设备标准
V
–
–
符合 GB4943.1-2011 的 CQC 认证
V
符合 EN 60950-1、EN62368-1 和 EN 61010-1
的 TUV 认证
而 VSO 是以 GNDO 为基准的输出侧电源电
压。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF40
ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
Output ...................................................................... 16
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Power Ratings........................................................... 7
7.6 Insulation Specifications............................................ 8
7.7 Safety-Related Certifications..................................... 9
7.8 Safety Limiting Values .............................................. 9
7.9 Electrical Characteristics—5-V Input, 5-V Output... 10
7.17 Switching Characteristics—3.3-V Input, 3.3-V
Output ...................................................................... 16
7.18 Insulation Characteristics Curves ......................... 17
7.19 Typical Characteristics.......................................... 18
Parameter Measurement Information ................ 22
Detailed Description ............................................ 23
9.1 Overview ................................................................. 23
9.2 Functional Block Diagram ....................................... 23
9.3 Feature Description................................................. 25
9.4 Device Functional Modes........................................ 26
8
9
10 Application and Implementation........................ 28
10.1 Application Information.......................................... 28
10.2 Typical Application ................................................ 28
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Example .................................................... 33
13 器件和文档支持 ..................................................... 34
13.1 器件支持................................................................ 34
13.2 文档支持................................................................ 34
13.3 接收文档更新通知 ................................................. 34
13.4 社区资源................................................................ 34
13.5 商标....................................................................... 34
13.6 静电放电警告......................................................... 34
13.7 Glossary................................................................ 34
14 机械、封装和可订购信息....................................... 34
7.10 Supply Current Characteristics—5-V Input, 5-V
Output ...................................................................... 11
7.11 Electrical Characteristics—5-V Input, 3.3-V
Output ...................................................................... 12
7.12 Supply Current Characteristics—5-V Input, 3.3-V
Output ...................................................................... 13
7.13 Electrical Characteristics—3.3-V Input, 3.3-V
Output ...................................................................... 14
7.14 Supply Current Characteristics—3.3-V Input, 3.3-V
Output ...................................................................... 15
7.15 Switching Characteristics—5-V Input, 5-V Output 16
7.16 Switching Characteristics—5-V Input, 3.3-V
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2018) to Revision B
Page
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通篇进行了编辑性和修饰性更改 ............................................................................................................................................. 1
在 特性中添加了“稳健可靠的隔离栅”项目符号........................................................................................................................ 1
在 特性中添加了“在 1kVRMS 工作电压下，预计寿命超过 100 年”项目符号............................................................................. 1
在 特性中添加了“高达 5000V 的 RMS 隔离额定值”项目符号.................................................................................................... 1
在 特性中添加了“高达 10kVPK 的浪涌保护能力”项目符号....................................................................................................... 1
在 特性中添加了“±8kV IEC 61000-4-2 跨隔离栅接触放电保护”项目符号............................................................................... 1
在 特性和Insulation Specifications表中将 VDE 标准名称从“DIN V VDE V 0884-11:2017-01”更改为“DIN VDE V 0884-
11:2017-01” ............................................................................................................................................................................ 1
•
•
•
•
向 “特性”中的信息的 TUV 认证项目符号中添加了“EN 62368-1”标准 ..................................................................................... 1
删除了 “为选定的器件提供了汽车级版本”中的“已计划进行所有机构认证”项目符号................................................................ 1
更新了 简化原理图，以显示信号隔离通道的两个串联隔离电容器，而不是单个电容器.......................................................... 1
Added "Contact discharge per IEC 61000-4-2; Isolation barrier withstand test" specification of ±8000 in ESD Ratings
table........................................................................................................................................................................................ 6
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Added table note "IEC ESD strike is applied across the barrier with all pins on each side tied together creating a
two-terminal device" to ESD Ratings table............................................................................................................................. 6
Deleted "TJ or Junction temperature" parameter from Recommended Operating Conditions table as it is already
specified in Absolute Maximum Ratings table........................................................................................................................ 6
Added "See 图 34" to TEST CONDITIONS of VIOWM specification ........................................................................................ 8
2
版权 © 2017–2019, Texas Instruments Incorporated
ISOW7821
www.ti.com.cn
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
修订历史记录 (接下页)
•
•
Updated Safety-Related Certifications table .......................................................................................................................... 9
Added the following note to 图 25: "Optional 100 µF capacitor can be added between VCC and GND1; refer to
Power Supply Recommendations" ...................................................................................................................................... 22
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•
•
•
Added the following note to 图 30: "Optional 100 µF capacitor can be added between VCC and GND1; refer to
Power Supply Recommendations" ...................................................................................................................................... 28
Added the following text to Design Requirements: "Optional 100 µF decoupling capacitor can be added between
VCC and GND1 pins; refer to Power Supply Recommendations for more details"............................................................... 29
Added text to Power Supply Recommendations section to emphasise that input decoupling capacitor should be
larger than output capacitor by at least 100 µF ................................................................................................................... 31
Added the following note to 图 35: "Optional 100 µF capacitor can be added between VCC and GND1; refer to
Power Supply Recommendations" ...................................................................................................................................... 33
Changes from Original (November 2017) to Revision A
Page
•
Changed OUTB to pin 4 and INB to pin 13 in the Pin Functions table .................................................................................. 5
版权 © 2017–2019, Texas Instruments Incorporated
3
ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
5 说明 （续）
ISOW7821 器件可提供高电磁抗扰度和低辐射，同时能够隔离 CMOS 或 LVCMOS 数字 I/O。信号隔离通道具有由
二氧化硅 (SiO2) 绝缘栅相隔离的逻辑输入和输出缓冲器，而电源隔离使用片上变压器，以薄膜聚合物作为绝缘材
料。提供各种正向和反向通道配置。如果输入信号丢失，则默认输出对于 ISOW7821 器件为高电平，对于具有 F
后缀的器件为低电平（请参阅器件 具有）。
这些器件有助于防止数据总线或者其他电路上的噪声电流进入本地接地并干扰或损坏敏感电路。凭借创新型芯片设
计和布局技术，ISOW7821 器件的电磁兼容性得到了显著增强，可缓解系统级 ESD、EFT 和浪涌问题并符合辐射
标准。电源转换器效率较高，允许在较高的环境温度下工作。ISOW7821 器件采用 16 引脚 SOIC 宽体 (SOIC-WB)
DWE 封装。
4
Copyright © 2017–2019, Texas Instruments Incorporated
ISOW7821
www.ti.com.cn
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
6 Pin Configuration and Functions
DWE Package
16-Pin SOIC-WB
Top View
VCC
GND1
INA
1
2
3
4
5
6
7
8
16 VISO
15 GND2
14 OUTA
13 INB
12 NC
OUTB
NC
NC
11
SEL
EN1
GND1
10 NC
9
GND2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Output enable for side 1.
EN1
7
—
Output pins on side 1 are enabled when EN1 is high or open.
Output pins on side 1 are high impedance when EN1 is low.
GND1
GND2
INA
2, 8
9, 15
3
—
—
I
Ground connection for VCC
Ground connection for VISO
Input channel A
OUTB
NC
4
I
Output channel B
Not connected
5
—
—
—
—
O
O
NC
6
Not connected
NC
10
12
14
13
Not connected
NC
Not connected
OUTA
INB
Output channel A
Input channel B
VISO selection pin.
VISO = 5 V when SEL is connected to VISO
VISO = 3.3 V, when SEL is connected to GND2 or left floating. For more information see the Device Functional
Modes.
.
SEL
11
I
VCC
1
—
—
Supply voltage
VISO
16
Isolated supply voltage determined by SEL pin
Copyright © 2017–2019, Texas Instruments Incorporated
5
ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
(1)(2)
See
MIN
–0.5
–0.5
MAX
UNIT
V
VCC
Supply voltage
6
6
VISO
Isolated supply voltage
V
VCC + 0.5,
VIO
Voltage at INx, OUTx, SEL pins
–0.5
–15
V
VISO + 0.5(3)
IO
Maximum output current through data channels
Junction temperature
15
mA
°C
TJ
150
150
Tstg
Storage temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2) and are peak voltage
values.
(3) This value depends on whether the pin is located on the VCC or VISO side. The maximum voltage at the I/O pins should not exceed 6 V.
7.2 ESD Ratings
VALUE
±2000
±1000
±8000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(3)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
7.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
VCC
IOH
Supply voltage
5.5
V
VSO(1) = 5 V
VSO = 3.3 V
VSO = 5 V
–4
–2
High level output current(2)
mA
mA
4
2
IOL
Low level output current(2)
VSO = 3.3 V
VIH
VIL
DR
TA
High-level input voltage
Low-level input voltage
Data rate
0.7 × VSI
0
VSI
V
V
0.3 × VSI
100
Mbps
°C
Ambient temperature
–40
125
(1) VSI is the input side supply, VSO is the output side supply
(2) This current is for data output channel.
6
Copyright © 2017–2019, Texas Instruments Incorporated
ISOW7821
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
7.4 Thermal Information
ISOW7821
THERMAL METRIC(1)
DWE (SOIC)
16 PINS
56.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
15.6
28.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.4
ΨJB
28.5
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VCC = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤ 80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.16
0.58
0.58
UNIT
W
PD
Maximum power dissipation (both sides)
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
PD1
PD2
W
W
Copyright © 2017–2019, Texas Instruments Incorporated
7
ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
UNIT
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
CPG
Minimum internal gap (internal clearance – capacitive
signal isolation)
> 21
DTI
CTI
Distance through the insulation
µm
V
Minimum internal gap (internal clearance –
transformer power isolation)
>120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-IV
I-III
Overvoltage category per IEC 60664-1
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
1414
VPK
voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test; See 图 34
1000
1414
7071
VRMS
VDC
VPK
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
6250
VPK
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤ 5
Vpd(m) = 1.2 × VIORM = 1697 VPK, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2263 VPK, tm = 10 s
qpd
Apparent charge(4)
pC
≤ 5
≤ 5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = 1.2 × VIOTM
,
tini = 1 s; Vpd(m) = 1.875 × VIORM = 2652 VPK, tm = 1 s
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance(5)
~3.5
> 1012
> 1011
> 109
pF
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V, TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO(UL), t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%
production)
VISO(UL)
Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
8
Copyright © 2017–2019, Texas Instruments Incorporated
ISOW7821
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-
1:2006/A2:2013 and EN
62368-1:2014
Certified according to IEC
60950-1, IEC 62368-1, and IEC 1577 Component
60601-1
Recognized under UL
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to
GB 4943.1-2011
Recognition Program
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2, CSA
62368-1-14 and IEC 62368-1
2nd Ed., 800 VRMS maximum
working voltage (pollution
degree 2, material group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14 VRMS
and IEC 60601-1 Ed. 3+A1, 250
VRMS maximum working
voltage;
5000 VRMS Reinforced
insulation per EN 61010-
1:2010/A1:2019 up to
working voltage of 600
Reinforced insulation;
Maximum transient
isolation voltage, 7071
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate, 700
VRMS maximum
VPK
;
VRMS;
Single protection, 5000
Maximum repetitive peak
isolation voltage, 1414
5000 VRMS Reinforced
insulation per EN 60950-
1:2006/A2:2013 and EN
62368-1:2014 up to
working voltage of 800
VRMS
VPK
;
working voltage;
Maximum surge isolation
voltage, 6250 VPK
Temperature rating is 90°C for
reinforced insulation and 125°C
for basic insulation; see
certificate for details.
Certificate number:
40040142
Master contract number:
220991
File number: E181974 Certificate number:
CQC15001121716
Client ID number: 77311
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 56.8°C/W, VI = 5.5 V, TJ = 150°C,
400
TA = 25°C, see 图 1
θJA = 56.8°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C, see 图 1
θJA = 56.8°C/W, TJ = 150°C, TA = 25°C,
see 图 2
IS
Safety input, output, or supply current(1)
mA
R
611
R
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
2200
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics—5-V Input, 5-V Output
VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 50 mA
MIN
4.75
4.5
TYP
5.07
5.07
2
MAX
UNIT
V
5.43
5.43
VISO
Isolated supply voltage
External IISO = 0 to 130 mA
IISO = 50 mA, VCC = 4.5 V to 5.5 V
IISO = 0 to 130 mA
VISO(LINE)
VISO(LOAD)
DC line regulation
DC load regulation
mV/V
1%
IISO = 130 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7821); VI = 0 V (ISOW7821
with F suffix)
Efficiency at maximum load
current
EFF
53%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
VCC–(UVLO)
VHYS (UVLO)
2.7
0.7
V
V
V
Negative-going UVLO threshold
on VCC, VISO
2.1
UVLO threshold hysteresis on
VCC, VISO
0.2
VITH
VITL
Input pin rising threshold
Input pin falling threshold
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
IIL
Low level input current
High level input current
VIL = 0 at INx or SEL
VIH = VSI(1) at INx or SEL
–10
µA
µA
IIH
10
(1)
VSO
–
VSO
–
VOH
High level output voltage
Low level output voltage
IO = –4 mA, see 图 24
V
V
0.4
0.2
VOL
IO = 4 mA, see 图 24
0.2
0.4
High-level common-mode
transient immunity
|CMH|
VI = VSI, VCM = 1000 V; see 图 25
100
100
kV/µs
Low-level common-mode
transient immunity
|CML|
VI = 0 V, VCM = 1000 V; see 图 25
kV/µs
mA
DC current from supply under
short circuit on VISO
ICC_SC
VISO(RIP)
VISO shorted to GND2
137
100
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,
(pk-pk) IISO = 130 mA
mV
(1) VSI= input side supply; VSO= output side supply
10
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7.10 Supply Current Characteristics—5-V Input, 5-V Output
VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No external ILOAD; VI = 0 V (ISOW7821);
VI = VSI(1) (ISOW7821 with F suffix)
21
No external ILOAD; VI = VSI (ISOW7821);
VI = 0 V (ISOW7821 with F suffix)
17
19
All channels switching with square wave clock
input of 1 Mbps; CL = 15 pF, No external ILOAD
ICC
Current drawn from supply
mA
All channels switching with square wave clock
input of 10 Mbps; CL = 15 pF, No external
ILOAD
20
33
All channels switching with square wave clock
input of 100 Mbps; CL = 15 pF, No external
ILOAD
VI = 0 V (ISOW7821); VI = VSI (ISOW7821
with F suffix)
127
130
128
128
125
VI = VSI (ISOW7821); VI = 0 V (ISOW7821
with F suffix)
Current available on isolated
supply
All channels switching with square wave clock
input of 1 Mbps; CL = 15 pF
(2)
IISO(OUT)
mA
All channels switching with square wave clock
input of 10 Mbps; CL = 15 pF
All channels switching with square wave clock
input of 100 Mbps; CL = 15 pF
(1) VSI= input side supply; VSO= output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 80°C.
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7.11 Electrical Characteristics—5-V Input, 3.3-V Output
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 50 mA
MIN
3.13
3
TYP
3.34
3.34
2
MAX
UNIT
V
3.56
3.56
VISO
Isolated supply voltage
External IISO = 0 to 130 mA
IISO = 50 mA, VCC = 4.5 V to 5.5 V
IISO = 10 to 130 mA
VISO(LINE)
VISO(LOAD)
DC line regulation
DC load regulation
mV/V
1%
IISO = 130 mA, CLOAD = 0.1 µF || 10 µF; VI =
VSI (ISOW7821); VI = 0 V (ISOW7821 with
F suffix)
Efficiency at maximum load
current
EFF
48%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
VCC–(UVLO)
VHYS (UVLO)
2.7
0.7
V
V
V
Negative-going UVLO threshold
on VCC, VISO
2.1
UVLO threshold hysteresis on
VCC, VISO
0.2
VITH
VITL
Input pin rising threshold
Input pin falling threshold
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
IIL
Low level input current
High level input current
VIL = 0 at INx or SEL
VIH = VSI(1) at INx or SEL
–10
µA
µA
IIH
10
(1)
VSO
–
VSO
–
VOH
High level output voltage
Low level output voltage
IO = –2 mA, see 图 24
V
V
0.3
0.1
VOL
IO = 2 mA, see 图 24
0.1
0.3
High-level common-mode
transient immunity
|CMH|
VI = VSI, VCM = 1000 V; see 图 25
100
100
kV/µs
Low-level common-mode
transient immunity
|CML|
VI = 0 V, VCM = 1000 V; see 图 25
kV/µs
mA
DC current from supply under
short circuit on VISO
ICC_SC
VISO(RIP)
VISO shorted to GND2
137
100
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,
(pk-pk) IISO = 130 mA
mV
(1) VSI= input side supply; VSO= output side supply
12
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7.12 Supply Current Characteristics—5-V Input, 3.3-V Output
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No external ILOAD; VI = 0 V (ISOW7821);
VI = VS(1)(ISOW7821 with F suffix)
17
No external ILOAD; VI = VSI (ISOW7821);
VI = 0 V (ISOW7821 with F suffix)
14
16
All channels switching with square wave
clock input of 1 Mbps; CL = 15 pF, No
external ILOAD
ICC
Current drawn from supply
mA
All channels switching with square wave
clock input of 10 Mbps; CL = 15 pF, No
external ILOAD
17
27
All channels switching with square wave
clock input of 100 Mbps; CL = 15 pF, No
external ILOAD
VI = 0 V (ISOW7821); VI = VSI (ISOW7821
with F suffix)
127
130
128
128
126
VI = VSI (ISOW7821); VI = 0 V (ISOW7821
with F suffix)
Current available on isolated
supply
All channels switching with square wave
clock input of 1 Mbps; CL= 15 pF
(2)
IISO(OUT)
mA
All channels switching with square wave
clock input of 10 Mbps; CL = 15 pF
All channels switching with square wave
clock input of 100 Mbps; CL = 15 pF
(1) VSI= input side supply; VSO= output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 105°C.
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7.13 Electrical Characteristics—3.3-V Input, 3.3-V Output
VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
External IISO = 0 to 30 mA
MIN
3.13
3
TYP
3.34
3.34
2
MAX
UNIT
V
3.58
3.58
VISO
Isolated supply voltage
External IISO = 0 to 75 mA
IISO = 30 mA, VCC = 3 V to 3.6 V
IISO = 0 to 75 mA
VISO(LINE)
VISO(LOAD)
DC line regulation
DC load regulation
mV/V
1%
IISO = 75 mA, CLOAD = 0.1 µF || 10 µF;
VI = VSI (ISOW7821); VI = 0 V (ISOW7821 with
F suffix)
Efficiency at maximum load
current
EFF
47%
Positive-going UVLO threshold
on VCC, VISO
VCC+(UVLO)
VCC–(UVLO)
VHYS (UVLO)
2.7
0.7
V
V
V
Negative-going UVLO threshold
on VCC, VISO
2.1
UVLO threshold hysteresis on
VCC, VISO
0.2
VITH
VITL
Input pin rising threshold
Input pin falling threshold
VSI
VSI
0.3
0.1
Input pin threshold hysteresis
(INx)
VI(HYS)
VSI
IIL
Low level input current
High level input current
VIL = 0 at INx or SEL
VIH = VSI(1) at INx or SEL
–10
µA
µA
IIH
10
(1)
VSO
–
VSO
–
VOH
High level output voltage
Low level output voltage
IO = –2 mA, see 图 24
V
V
0.3
0.1
VOL
IO = 2 mA, see 图 24
0.1
0.3
High-level common-mode
transient immunity
|CMH|
VI = VSI, VCM = 1000 V; see 图 25
100
100
kV/µs
Low-level common-mode
transient immunity
|CML|
VI = 0 V, VCM = 1000 V; see 图 25
kV/µs
mA
DC current from supply under
short circuit on VISO
ICC_SC
VISO(RIP)
VISO shorted to GND2
143
90
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.1 µF || 20 µF,
(pk-pk) IISO = 75 mA
mV
(1) VSI= input side supply; VSO= output side supply
14
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7.14 Supply Current Characteristics—3.3-V Input, 3.3-V Output
VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No external ILOAD; VI = 0 V (ISOW7821);
VI = VS(1) (ISOW7821 with F suffix)
24
No external ILOAD; VI = VSI (ISOW7821);
VI = 0 V (ISOW7821 with F suffix)
19
22
All channels switching with square wave clock
input of 1 Mbps; CL = 15 pF, No external ILOAD
ICC
Current drawn from supply
mA
All channels switching with square wave clock
input of 10 Mbps; CL = 15 pF, No external
ILOAD
22
32
All channels switching with square wave clock
input of 100 Mbps; CL = 15 pF, No external
ILOAD
VI = 0 V (ISOW7821);
VI = VSI (ISOW7821 with F suffix)
72
75
75
73
71
VI = VSI(ISOW7821);
VI = 0 V (ISOW7821 with F suffix)
Current available on isolated
supply
All channels switching with square wave clock
input of 1 Mbps; CL= 15 pF
(2)
IISO(OUT)
mA
All channels switching with square wave clock
input of 10 Mbps; CL = 15 pF
All channels switching with square wave clock
input of 100 Mbps; CL = 15 pF
(1) VSI= input side supply; VSO= output side supply
(2) Current available to load should be derated by 2 mA/°C for TA > 115°C.
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7.15 Switching Characteristics—5-V Input, 5-V Output
VCC = 5 V ±10%, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
13
MAX
UNIT
ns
tPLH, tPHL Propagation delay time
See 图 24
17.6
4.7
4
PWD
tSK(o)
tSK(p-p)
tr, tf
Pulse width distortion(1) |tPHL – tPLH
|
Channel-channel output skew time(2)
Part-part skew time(3)
0.6
ns
Same-direction channels
ns
4.5
4
ns
Output signal rise and fall times
2
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.16 Switching Characteristics—5-V Input, 3.3-V Output
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
14
MAX
19.7
4.4
4
UNIT
ns
tPLH, tPHL Propagation delay time
See 图 24
PWD
tSK(o)
tSK(p-p)
tr, tf
Pulse width distortion(1) |tPHL – tPLH
|
Channel-channel output skew time(2)
Part-part skew time(3)
0.6
ns
Same-direction channels
ns
4.5
4
ns
Output signal rise and fall times
1
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.17 Switching Characteristics—3.3-V Input, 3.3-V Output
VCC = 3.3 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
14.5
0.6
MAX
20.2
4.4
4
UNIT
ns
tPLH, tPHL Propagation delay time
See 图 24
PWD
tSK(o)
tSK(p-p)
tr, tf
Pulse width distortion(1) |tPHL – tPLH
|
Channel-channel output skew time(2)
Part-part skew time(3)
ns
Same-direction channels
ns
4.5
3
ns
Output signal rise and fall times
1
ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
16
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7.18 Insulation Characteristics Curves
2500
2000
1500
1000
500
700
VCC = 3.6 V
VCC = 5.5 V
600
500
400
300
200
100
0
0
0
20
40
60
80
100
120
140
160
0
50
100
Ambient Temperature (èC)
150
200
Ambient Temperature (èC)
D001
D002
图 1. Thermal Derating Curve for Safety Limiting Current per
图 2. Thermal Derating Curve for Safety Limiting Power per
VDE
VDE
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7.19 Typical Characteristics
3.45
5.2
5.15
5.1
VCC = 3.3 V
VCC = 5 V
3.43
3.41
3.39
3.37
3.35
3.33
3.31
3.29
3.27
3.25
5.05
5
0
20
40
60
Load Current (mA)
80
100
120
140
0
20
40
60
Load Current (mA)
80
100
120
140
VISO = 3.3 V
TA = 25°C
VISO = 5 V
TA = 25°C
图 3. Isolated Supply Voltage (VISO) vs Load Current (IISO
)
图 4. Isolated Supply Voltage (VISO) vs Load Current (IISO)
260
100
90
80
70
60
50
40
30
210
160
110
20
60
VCC = 3.3 V, VISO = 3.3 V
VCC = 5 V, VISO = 3.3 V
VCC = 5 V, VISO = 5 V
VCC = 3.3 V, VISO = 3.3 V
VCC = 5 V, VISO = 3.3 V
VCC = 5 V, VISO = 5 V
10
0
10
0
20
40
60
80
Load Current (mA)
100
120
140
0
20
40
60
80
Load Current (mA)
100
120
140
D005
TA = 25°C
TA = 25°C
图 6. Efficiency vs Load Current (IISO
)
图 5. ISOW7821 Supply Current (ICC) vs Load Current (IISO
)
640
3.4
3.35
3.3
560
480
400
320
240
160
3.25
VCC = 3.3 V, VISO = 3.3 V
VCC = 5 V, VISO = 3.3 V
VCC = 5 V, VISO = 5 V
80
0
3.2
0
20
40
60
80
Load Current (mA)
100
120
140
-40
-20
0
20
40
60
80
100
120
Free-Air Temperature (èC)
D007
D008
TA = 25°C
No IISO load
VCC = 5 V
VISO = 3.3 V
图 7. Power Dissipation vs Load Current (IISO
)
图 8. 3.3-V Isolated Supply Voltage (VISO) vs Free-Air
Temperature
18
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Typical Characteristics (接下页)
5.14
130
125
120
115
110
105
100
95
800
700
600
500
400
300
200
5.09
5.04
4.99
4.94
100
Short-circuit Supply Current
Short-circuit Power
0
90
-40
-20
0
20
40
60
80
100
120
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
Input Supply Voltage (V)
5
5.2 5.4
Free-Air Temperature (èC)
No IISO load
VCC = 5 V
VISO = 5 V
VISO shorted to GND2
TA = 25°C
图 9. 5-V Isolated Supply Voltage (VISO) vs Free-Air
图 10. Short-Circuit Supply Current (ICC) and Power (P) vs
Supply Voltage (VCC
Temperature
)
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
ICC at VCC = 3.3 V, VISO = 3.3 V
ICC at VCC = 5 V, VISO = 3.3 V
ICC at VCC = 5 V, VISO = 5 V
ICC at VCC = 3.3 V, VISO = 3.3 V
ICC at VCC = 5 V, VISO = 3.3 V
ICC at VCC = 5 V, VISO = 5 V
0
0
0
25
50
Data Rate (Mbps)
75
100
0
25
50
Data Rate (Mbps)
75
100
D001
D002
CL = 15 pF
TA = 25°C
No IISO load
CL = no load
TA = 25°C
No IISO load
图 11. Supply Current vs Data Rate
图 12. Supply Current vs Data Rate
2.6
2.5
2.4
2.3
2.2
2.1
2
17
16
15
14
13
12
11
10
9
tPHL at VCC = 3.3 V, VISO = 3.3 V
tPLH at VCC = 3.3 V, VISO = 3.3 V
tPHL at VCC = 5 V, VISO = 3.3 V
tPLH at VCC = 5 V, VISO = 3.3 V
tPHL at VCC = 5 V, VISO = 5 V
tPLH at VCC = 5 V, VISO = 5 V
VCC Rising
VCC Falling
8
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Free-Air Temperature (èC)
Free-Air Temperature (èC)
图 13. Power-Supply Undervoltage Threshold vs Free Air
图 14. Propagation Delay Time vs Free-Air Temperature
Temperature
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Typical Characteristics (接下页)
6
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
3
2
1
VSO = 3.3 V
VSO = 5 V
VSO = 3.3 V
VSO = 5 V
0
-15
-10
High-Level Output Current (mA)
-5
0
0
5 10
Low-Level Output Current (mA)
15
D015
D016
TA = 25°C
TA = 25°C
图 15. High-Level Output Voltage vs High-Level Output
图 16. Low-Level Output Voltage vs Low-Level Output
Current
Current
VISO = 3.3 V (50 mV/div)(1)
ICC (40 mA/div)
IISO
110 mA
VISO = 3.3 V (1 V/div)
10 mA
10 mA
2
100 µs/div
2 ms/div
VCC = 5 V
VISO = 3.3 V
VCC = 5 V
VISO = 3.3 V
1. Negligible undershoot and overshoot because of load transient
Current spike is because of charging the input supply capacitor
图 17. 10-mA to 110-mA Load Transient Response
图 18. Soft Start at 10-mA Load
ICC (40 mA/div)
ICC (40 mA/div)
VISO = 5 V (1 V/div)
VISO = 3.3 V (1 V/div)
2 ms/div
2 ms/div
VCC = 5 V
VISO = 3.3 V
VCC = 5 V
VISO = 5 V
Input current spike is because of charging the input supply
decoupling capacitor
Input current spike is because of charging the input supply
decoupling capacitor
图 19. Soft Start at 120-mA Load
图 20. Soft Start at 10-mA Load
20
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Typical Characteristics (接下页)
ICC (40 mA/div)
VISO = 5 V (20 mV/div)
VISO = 5 V (1 V/div)
2 ms/div
5 µs/div
VCC = 5 V
VISO = 5 V
VCC = 5 V
VISO = 5 V
Input current spike is because of charging the input supply
decoupling capacitor
图 21. Soft Start at 130-mA Load
图 22. VISO Ripple Voltage at 130 mA
VISO = 3.3 V (20 mV/div)
5 µs/div
VCC = 5 V
VISO = 3.3 V
图 23. VISO Ripple Voltage at 130 mA
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8 Parameter Measurement Information
V
SI
V
50%
I
50%
IN
OUT
0 V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
O
50 ꢀ
V
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50-Ω resistor is required to terminate the input generator signal. The resistor is
not required in the actual application.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图 24. Switching Characteristics Test Circuit and Voltage Waveforms
5 V
5 V
V
SO
V
SI
10 …F || 0.1 µF
C3
C4
10 …F
0.1 …F
GNDI
IN
OUT
C
L
GNDI
GNDO
+
œ
V
CM
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Optional 100 µF capacitor can be added between VCC and GND1; refer to Power Supply Recommendations.
Pass-fail criteria: Outputs must remain stable.
图 25. Common-Mode Transient Immunity Test Circuit
22
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ISOW7821
www.ti.com.cn
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
9 Detailed Description
9.1 Overview
The ISOW7821 device comprises a high-efficiency, low-emissions isolated DC-DC converter and two high-speed
isolated data channels. 图 26 shows the functional block diagram of the ISOW7821 device.
The integrated DC-DC converter uses switched mode operation and proprietary circuit techniques to reduce
power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of a high-Q
on-chip transformer provide high efficiency and low radiated emissions. The integrated transformer uses thin film
polymer as the insulation barrier.
The VCC supply is provided to the primary power controller that switches the power stage connected to the
integrated transformer. Power is transferred to the secondary side, rectified and regulated to either 3.3 V or 5 V,
depending on the SEL pin. The output voltage, VISO, is monitored and feedback information is conveyed to the
primary side through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted
accordingly. The fast feedback control loop of the power converter ensures low overshoots and undershoots
during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VCC and VISO supplies
which ensures robust system performance under noisy conditions. An integrated soft-start mechanism ensures
controlled inrush current and avoids any overshoot on the output during power up.
The integrated signal-isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across
the barrier to represent one state and sends no signal to represent the other state. The receiver demodulates the
signal after signal conditioning and produces the output through a buffer stage. The signal-isolation channels
incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions
from the high frequency carrier and IO buffer switching. 图 27 shows a functional block diagram of a typical
signal isolation channel.
The ISOW7821 device is suitable for applications that have limited board space and require more integration.
These devices are also suitable for very-high voltage applications, where power transformers meeting the
required isolation specifications are bulky and expensive.
9.2 Functional Block Diagram
Transformer
V
CC
V
ISO
Power
Controller
Transformer
Driver
Rectifier
UVLO, Soft-start
Thermal
Shutdown,
UVLO, Soft-start
FB Channel (Tx)
FB Controller
I/O Channels
FB Channel (Rx)
V
ref
I/O Channels
Data Channels
(2)
Data Channels
(2)
Isolation Barrier
Copyright © 2017, Texas Instruments Incorporated
图 26. ISOW7821 Block Diagram
版权 © 2017–2019, Texas Instruments Incorporated
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ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
Functional Block Diagram (接下页)
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
图 27. Conceptual Block Diagram of a Capacitive Data Channel
图 28 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图 28. On-Off Keying (OOK) Based Modulation Scheme
24
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ISOW7821
www.ti.com.cn
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
9.3 Feature Description
表 1 provides an overview of the device features.
表 1. Device Features
DEFAULT OUTPUT
RATED ISOLATION(2)
STATE
PART NUMBER(1)
CHANNEL DIRECTION
MAXIMUM DATA RATE
ISOW7821
High
1 forward, 1 reverse
100 Mbps
5000 VRMS / 7071 VPK
Low
ISOW7821F
(1) The F suffix is part of the orderable part number. See the 机械、封装和可订购信息 section for the full orderable part number.
(2) For detailed isolation ratings, see the Safety-Related Certifications table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
The ISOW7821 device uses emissions reduction schemes for the internal oscillator and advanced internal layout
scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISOW7821
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
9.3.2 Power-Up and Power-Down Behavior
The ISOW7821 device has built-in UVLO on the VCC and VISO supplies with positive-going and negative-going
thresholds and hysteresis. When the VCC voltage crosses the positive-going UVLO threshold during power-up,
the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-
start scheme limits primary peak currents drawn from the VCC supply and charges the VISO output in a controlled
manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VCC or
VISO voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on
the secondary side VISO pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When VCC power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached.
The VISO capacitor then discharges depending on the external load. The isolated data outputs on the VISO side
are returned to the default state for the brief time that the VISO voltage takes to discharge to zero.
9.3.3 Current Limit, Thermal Overload Protection
The ISOW7821 device is protected against output overload and short circuit. Output voltage starts dropping
when the power converter is not able to deliver the current demanded during overload conditions. For a VISO
short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
版权 © 2017–2019, Texas Instruments Incorporated
25
ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
Thermal protection is also integrated to help prevent the device from getting damaged during overload and short-
circuit conditions on the isolated output. Under these conditions, the device temperature starts to increase. When
the temperature goes above 180°C, thermal shutdown activates and the primary controller turns off which
removes the energy supplied to the VISO load, which causes the device to cool off. When the junction
temperature goes below 150°C, the device starts to function normally. If an overload or output short-circuit
condition prevails, this protection cycle is repeated. Care should be taken in the design to prevent the device
junction temperatures from reaching such high values.
9.4 Device Functional Modes
表 2 lists the supply configurations for these devices.
表 2. Supply Configurations
SEL INPUT
VCC
5 V
VISO
5 V
Shorted to VISO
Shorted to GND2 or floating
Shorted to GND2 or floating
5 V
3.3 V(1)
3.3 V
3.3 V(2)
(1) VCC = 3.3 V, SEL shorted to VISO (essentially VISO = 5 V) is not recommended mode of configuration.
(2) The SEL pin has a weak pulldown internally. Therefore for VISO = 3.3 V, the SEL pin should be
strongly connected to the GND2 pin in noisy system scenarios.
表 3 lists the functional modes for ISOW7821 device.
表 3. Function Table(1)
INPUT SUPPLY
INPUT
(INx)
OUTPUT
(OUTx)
COMMENTS
(VCC
)
H
L
H
Output channel assumes the logic state of its input
L
PU
Default mode(2): When INx is open, the corresponding
output channel assumes logic based on default output
mode of selected version
Open
x
Default
PD
Undetermined(3)
(1) PU = Powered up (VCC ≥ 2.7 V); PD = Powered down (VCC < 2.1 V); X = Irrelevant; H = High level; L = Low level, VCC = Input-side
supply
(2) In the default condition, the output is high for ISOW7821 and low for ISOW7821 with the F suffix.
(3) The outputs are in an undetermined state when VCC < 2.1 V.
26
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ISOW7821
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
9.4.1 Device I/O Schematics
Input (Devices without F suffix)
Input (Devices with F suffix)
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
SEL Pin
Output
V
ISO
V
V
ISO
V
ISO
ISO
~20 ꢀ
1970 ꢀ
OUTx
SEL
2 Mꢀ
图 29. Device I/O Schematics
版权 © 2017–2019, Texas Instruments Incorporated
27
ISOW7821
ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISOW7821 high-performance, dual channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the ISOW7821 device, the isolated supply is generated inside the device that can
be used to power isolated side of the device and peripherals on isolated side, thus saving board space. The
ISOW7821 device uses single-ended CMOS-logic switching technology. When designing with digital isolators,
keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific
interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator
is typically placed between the data controller (that is a microcontroller or UART), and a data converter or a line
transceiver, regardless of the interface type or standard.
The ISOW7821 device is suitable for applications that have limited board space and desire more integration.
These devices are also suitable for very high voltage applications, where power transformers meeting the
required isolation specifications are bulky and expensive.
10.2 Typical Application
图 30 shows the typical schematic for CAN isolation.
0.1 …F
22 …F
22 …F
0.1 …F
3.3VIN
VISO
SEL
VCC
3.3VOUT
EN1
DVCC
MCU
DVSS
Vcc
Tx
INA
OUTA
TXD
CANH
ISOW7821
CAN
Transceiver
CAN Bus
CANL
RXD
INB
GND
Rx
OUTB
GND1
GND2
Copyright © 2017, Texas Instruments Incorporated
Optional 100 µF capacitor can be added between VCC and GND1; refer to Power Supply Recommendations.
图 30. Isolating CAN Bus and Generating Isolated Power for CAN Transceiver
10.2.1 Design Requirements
To design with this device, use the parameters listed in 表 4.
表 4. Design Parameters
PARAMETER
VALUE
Input voltage
3 V to 5.5 V
Decoupling capacitor between VCC and GND1
Decoupling capacitor between VISO and GND2
0.1 µF to 10 µF
0.1 µF to 10 µF
28
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ISOW7821
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
Because of very-high current flowing through the ISOW7821 VCC and VISO supplies, higher decoupling capacitors
typically provide better noise and ripple performance. Although a 10-µF capacitor is adequate, higher decoupling
capacitors (such as 47 µF) on both the VCC and VISO pins to the respective grounds are strongly recommended
to achieve the best performance. Optional 100 µF decoupling capacitor can be added between VCC and GND1
pins; refer to Power Supply Recommendations for more details.
10.2.2 Detailed Design Procedure
The ISOW7821 device only requires external bypass capacitors to operate. These low-ESR ceramic bypass
capacitors must be placed as close to the chip pads as possible.
10 ꢀF
10 ꢀF
2 mm Maximum
from Vcc
2 mm Maximum
from VISO
0.1 ꢀF
0.1 ꢀF
VCC
VISO
1
2
3
4
5
6
7
8
16
GND1
15
14
13
GND2
INA
OUTA
INB
OUTB
12
11
SEL
10
9
EN1
GND1
GND2
Optional 100 µF capacitor can be added between VCC and GND1; refer to Power Supply Recommendations.
图 31. Typical Circuit Hook-Up
The VCC power-supply input provides power to isolated data channels and to the isolated DC-DC converter. Use
公式 1 to calculate the total power budget on the primary side.
ICC = (VISO × IISO) / (η × VCC) + Iinpx
where
•
•
•
•
•
•
ICC is the total current required by the primary supply.
VISO is the isolated supply voltage.
IISO is the external load on the isolated supply voltage.
η is the efficiency.
VCC is the supply voltage.
Iinpx is the total current drawn for the isolated data channels and power converter when data channels are
toggling at a specific data rate. This data is shown in the Electrical Characteristics—5-V Input, 5-V Output
table.
(1)
29
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www.ti.com.cn
10.2.3 Application Curve
ICC (40 mA/div)
VISO (600 mV/div)
VCC = 3.3 V
IISO = 70 mA
Input current spike is because of charging the input supply decoupling capacitor
图 32. Soft-Start Waveform
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 33 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 34 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime. Based
on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
图 33. Test Setup for Insulation Lifetime Measurement
30
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ISOW7821
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
图 34. Insulation Lifetime Projection Data
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, adequate decoupling capacitors must be
located as close to supply pins as possible. The input supply must have an appropriate current rating to support
output load and switching at the maximum data rate required by the end application. For more information, refer
to the Detailed Design Procedure section.
ISOW7821 integrates a synchronous, isolated DC/DC converter along with isolated data channels. Due to finite
efficiency of the integrated micro-transformer, for any given output load current, the input current will be
proportionally higher. Thus, the input supply (VCC) decoupling capacitor also needs to be sufficiently larger than
the output supply (VISO) decoupling capacitor. It is recommended to have an input capacitor that is larger than
the output capacitor by at least 100 µF. It is also recommended to have an input power supply to ISOW7821 with
sufficient current limit to support output load current requirements. For an output load current of 130 mA, it is
recommended to have >600 mA of input current limit and for lower output load currents, the input current limit
can be proportionally lower. When the input supply is lower than 2.7 V, the device can go into a protected under-
voltage lock out (UVLO) state per the UVLO thresholds specified in datasheet. Under UVLO state, it is
recommended that the output voltage also be discharged to less than 2.1 V. This can be accomplished by having
an input capacitor that is 100 µF larger compared to the output capacitor. It also helps to have a small load (~10
mA) at the output capacitor to bleed off any unwanted, residual charge. To make sure ISOW7821 quickly
transitions from UVLO state to powered state, it is recommended to have an input supply rise time of less than
10 ms.
If it is not possible to follow the aforementioned recommendations and frequent brownouts are expected on the
input supply, then simple secondary side monitoring, protection and reset components can help improve the
robustness of overall system and power-up or reset mechanisms. More details on output monitoring, protection
and an example of reset mechanism can be found in Overvoltage protection for isolated DC/DC converter.
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low-EMI PCB design (see 图 35). Layer stacking should be
in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and low-frequency
signal layer.
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Keep decoupling capacitors as close as possible to the VCC and VISO pins.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND
pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the
device from rising to unacceptable levels.
The ISOW7821 integrated signal and power isolation device simplifies system design and reduces board area.
The use of low-inductance micro-transformers in the ISOW7821 device necessitates the use of high frequency
switching, resulting in higher radiated emissions compared to discrete solutions. The ISOW7821 device uses on-
chip circuit techniques to reduce emissions compared to competing solutions. For further reduction in radiated
emissions at system level, refer to the Low-Emission Designs With ISOW7841 Integrated Signal and Power
Isolator application report.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
32
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ISOW7821
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
12.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
2 mm
maximum
from VCC
2 mm
maximum
from VISO
VCC
VISO
16
1
0.1 …F
GND2
10 …F
0.1 …F
10 …F
GND1
2
3
15
14
4
13
5
6
12
11
SEL
EN1
7
8
10
9
GND2
GND1
Solid ground islands help
dissipate heat through PCB
Optional 100 µF capacitor can be added between VCC and GND1; refer to Power Supply Recommendations.
图 35. Layout Example
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33
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ZHCSH39B –NOVEMBER 2017–REVISED SEPTEMBER 2019
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.1.1 开发支持
如需开发支持，请参阅使用数字隔离器并集成电源的尺寸和成本优化型二进制模块参考设计 TI 设计
13.2 文档支持
13.2.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《数字隔离器设计指南》
德州仪器 (TI)，《隔离相关术语》
德州仪器 (TI)，《具有集成直流/直流转换器的 ISOW784x 四通道数字隔离器评估模块》用户指南
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
34
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW7821DWE
ISOW7821DWER
ISOW7821FDWE
ISOW7821FDWER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DWE
DWE
DWE
DWE
16
16
16
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISOW7821
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ISOW7821
ISOW7821F
ISOW7821F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISOW7821DWER
ISOW7821FDWER
SOIC
SOIC
DWE
DWE
16
16
2000
2000
330.0
330.0
16.4
16.4
10.75 10.7
10.75 10.7
2.7
2.7
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISOW7821DWER
ISOW7821FDWER
SOIC
SOIC
DWE
DWE
16
16
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISOW7821DWE
ISOW7821FDWE
DWE
DWE
SO-MOD
SO-MOD
16
16
40
40
506.98
506.98
12.7
12.7
4826
4826
6.6
6.6
Pack Materials-Page 3
PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
9
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
8
9
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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