IWR1843AQGABLR [TI]

IWR1843 Single-Chip 76- to 81-GHz FMCW mmWave Sensor;


型号：	IWR1843AQGABLR
厂家：	TEXAS INSTRUMENTS
描述：	IWR1843 Single-Chip 76- to 81-GHz FMCW mmWave Sensor
文件：	总83页 (文件大小：2286K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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IWR1843

SWRS228 –SEPTEMBER 2019

IWR1843 Single-Chip 76- to 81-GHz FMCW mmWave Sensor

1 Device Overview

1.1 Features

• FMCW transceiver

• Other interfaces available to user application

– Up to 6 ADC channels

– Up to 2 SPI channels

– Up to 2 UARTs

– Integrated PLL, transmitter, receiver, Baseband,

and A2D

– 76- to 81-GHz coverage with 4 GHz available

bandwidth

– Four receive channels

– Three transmit channels

– Ultra-accurate chirp engine based on fractional-

N PLL

– I²C

– GPIOs

– 2-lane LVDS interface for raw ADC data and

debug instrumentation

• IWR1843 advanced features

– TX power: 12 dBm

– Embedded self-monitoring with no host

processor involvement

– Complex baseband architecture

• Built-in calibration and self-test (monitoring)

– ARM^®Cortex^®-R4F-based radio control system

– Built-in firmware (ROM)

– Embedded interference detection capability

– Self-calibrating system across frequency and

temperature

– Programmable phase rotators in transmit path to

enable beam forming

• C674x DSP for FMCW signal processing

• On-chip Memory: 2MB

• Cortex-R4F microcontroller for object tracking and

classification, and interface control

– Supports autonomous mode (loading user

application from QSPI flash memory)

• Integrated peripherals

– Internal memories With ECC

• Host interface

• Power management

– Built-in LDO network for enhanced PSRR

– I/Os support dual voltage 3.3 V/1.8 V

• Clock source

– Supports external oscillator at 40 MHz

– Supports externally driven clock (square/sine) at

40 MHz

– Supports 40 MHz crystal connection with load

capacitors

– CAN and CAN-FD

• Easy hardware design

– 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip

chip BGA package for easy assembly and low-

cost PCB design

– Small solution size

1.2 Applications

•

Smart/Automatic door openers Industrial sensor

for measuring range, velocity, and angle

•

Proximity sensing

Security and surveillance

Factory automation safety guards

People counting

•

Tank level probing radar

Displacement sensing

Field transmitters

Motion detection

Traffic monitoring

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

IWR1843

SWRS228 –SEPTEMBER 2019

www.ti.com

40-MHz

Crystal

Power

Management

QSPI Flash

POWER

SPI

UART Tx/Rx

CAN

Integrated MCU

ARM Cortex-R4F

Antenna

Structure

RX1

RX2

RX3

RX4

mmWave/

Radar

Front End

TX1

TX2

TX3

Integrated DSP

TI C674x

IWR1843

Figure 1-1. Autonomous Sensor For Industrial Applications

1.3 Description

The IWR1843 device is an integrated single-chip mmWave sensor based on FMCW radar technology

capable of operating in the 76- to 81-GHz band with up to 4-GHz continuous chirp. The device is built with

the low-power 45-nm RFCMOS process from Texas Instruments. This solution enables unprecedented

levels of integration in an extremely small form factor. The IWR1843 is an ideal solution for low-power,

self-monitored, ultra-accurate radar systems in industrial applications, such as, building automation,

factory automation, drones, material handling, traffic monitoring, and surveillance.

The IWR1843 device is a self-contained, single-chip solution that simplifies the implementation of

mmWave sensors in the band of 76 to 81 GHz. The IWR1843 includes a monolithic implementation of a

3TX, 4RX system with built-in PLL, and A2D converters. The IWR1843 also integrates a DSP subsystem,

which contains a TI high-performance C674x DSP for the radar signal processing. The device includes an

ARM R4F-based processor subsystem, which is responsible for front-end configuration, control, and

calibration. Simple programming model changes can enable a wide variety of sensor implementation with

the possibility of dynamic reconfiguration for implementing a multimode sensor. The Hardware Accelerator

block (HWA) can perform radar processing and can help save MIPS on the DSP for higher-level

algorithms. Additionally, the device is provided as a complete platform solution including TI reference

designs, software drivers, sample configurations, API guides, training, and user documentation.

Device Information⁽¹⁾

PART NUMBER

IWR1843AQGABL (Tray)

IWR1843AQGABLR (Reel)

PACKAGE

FCBGA (161)

BODY SIZE

10.4 mm × 10.4 mm

(1) For more information, see Section 10, Mechanical, Packaging, and Orderable Information.

Device Overview

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1.4 Functional Block Diagram

Figure 1-2 shows the functional block diagram of the device.

Serial Flash interface

QSPI

Cortex R4F

@ 200MHz

LNA

ADC

Optional External

MCU interface

SPI

(User programmable)

Digital

Front-end

PMIC control

SPI / I2C

DCAN

Prog RAM

(512kB*)

Data RAM

(192kB*)

Boot

ROM

(Decimation

filter chain)

Primary communication

interfaces (automotive)

CAN-FD

UARTs

Radar Hardware Accelerator

(FFT, Log mag, and others)

DMA

Master sub-system

(Customer programmed)

Test/

Debug

JTAG for debug/

development

ADC

Buffer

û-

Mailbox

High-speed ADC output

interface (for recording)

LVDS

HIL

Synth

(20 GHz)

Ramp

Generator

High-speed input for

hardware-in-loop verification

C674x DSP

@ 400/600 MHz

Radio (BIST)

processor

GPADC

Osc.

(For RF Calibration

& Self-test œ TI

programmed)

L1P

(32kB)

L1D

(32kB)

L2 (256kB)

Prog RAM

& ROM

Data

RAM

VMON

Temp

DMA

CRC

Radar Data Memory

1024 kB*

Radio processor

sub-system

(TI programmed)

DSP sub-system

(Customer programmed)

RF/Analog sub-system

* Up to 512kB of Radar Data Memory can be switched to the Master R4F program and data RAMs

Figure 1-2. Functional Block Diagram

Device Overview

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Table of Contents

Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 3

Revision History ......................................... 5

Device Comparison ..................................... 6

3.1 Related Products ..................................... 7

Terminal Configuration and Functions.............. 8

4.1 Pin Diagram .......................................... 8

4.2 Pin Attributes ........................................ 12

4.3 Signal Descriptions.................................. 21

Specifications ........................................... 25

5.1 Absolute Maximum Ratings......................... 25

5.2 ESD Ratings ........................................ 25

5.3 Power-On Hours (POH)............................. 26

5.4 Recommended Operating Conditions............... 27

5.5 Power Supply Specifications........................ 27

5.6 Power Consumption Summary...................... 28

5.7 RF Specification..................................... 30

5.8 CPU Specifications.................................. 30

5.10 Timing and Switching Characteristics ............... 32

Detailed Description ................................... 55

6.1 Overview ............................................ 55

6.2 Functional Block Diagram........................... 55

6.3 Subsystems ......................................... 56

6.4 Other Subsystems................................... 64

Monitoring and Diagnostics.......................... 66

7.1

Monitoring and Diagnostic Mechanisms ............ 66

Applications, Implementation, and Layout........ 68

8.1 Application Information.............................. 68

8.2 Reference Schematic ............................... 68

8.3 Layout ............................................... 70

Device and Documentation Support ............... 73

9.1 Device Nomenclature ............................... 73

9.2 Tools and Software ................................. 74

9.3 Documentation Support ............................. 74

9.4 Support Resources.................................. 76

9.5 Trademarks.......................................... 76

9.6 Electrostatic Discharge Caution..................... 76

9.7 Glossary ............................................. 76

10 Mechanical, Packaging, and Orderable

Information .............................................. 77

10.1 Packaging Information .............................. 77

5.9

Thermal Resistance Characteristics for FCBGA

Package [ABL0161] ................................. 31

Table of Contents

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2 Revision History

DATE

REVISION

NOTES

September 2019

Initial Release

Revision History

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3 Device Comparison

Table 3-1. Device Features Comparison

FUNCTION

IWR6843AOP

IWR6843

IWR1843

IWR1642

IWR1443

Antenna on Package (AOP)

Number of receivers

Number of transmitters

RF frequency range

On-chip memory

Yes

—

60 to 64 GHz

1.75MB

60 to 64 GHz

1.75MB

3⁽¹⁾

76 to 81 GHz

2MB

76 to 81 GHz

1.5MB

76 to 81 GHz

576KB

Max I/F (Intermediate Frequency) (MHz)

Max real sampling rate (Msps)

Max complex sampling rate (Msps)

Processors

12.5

37.5

12.5

6.25

18.75

MCU (R4F)

Yes

—

DSP (C674x)

Peripherals

Serial Peripheral Interface (SPI) ports

Quad Serial Peripheral Interface (QSPI)

Inter-Integrated Circuit (I²C) interface

Controller Area Network (DCAN) interface

Controller Area Network (CAN-FD) interface

Trace

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

PWM

—

Hardware In Loop (HIL/DMM)

GPADC

—

Yes

LVDS/Debug

CSI2

Hardware accelerator

1-V bypass mode

Yes

—

Yes

JTAG

Product Preview (PP),

Product

Advance Information (AI),

status

AI⁽²⁾

PD⁽³⁾

or Production Data (PD)

(1) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to

be fed on the VOUT PA pin.

(2) ADVANCE INFORMATION for pre-production products; subject to change without notice.

(3) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty.

Device Comparison

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3.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with

less power using the smallest footprint mmWave sensor portfolio for industrial applications.

mmWave IWR sensors The Texas Instruments IWR1xxx family of mmWave Sensors are highly

integrated and built on RFCMOS technology operating in 76- to 81-GHz frequency band.

The devices have a closed-loop PLL for precise and linear chirp synthesis, includes a built-in

radio processor (BIST) for RF calibration and safety monitoring. The devices have a very

small-form factor, low power consumption, and are highly accurate. Industrial applications

from long range to ultra short range can be realized using these devices.

Companion products for IWR1843 Review products that are frequently purchased or used in

conjunction with this product.

Reference designs for IWR1843 TI Designs Reference Design Library is a robust reference design

library spanning analog, embedded processor and connectivity. Created by TI experts to

help you jump-start your system design, all TI Designs include schematic or block diagrams,

BOMs, and design files to speed your time to market. Search and download designs at

ti.com/tidesigns.

Device Comparison

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4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4,

and Figure 4-5 show the same pins, but split into four quadrants.

VOUT_

14APLL

OSC

_CLKOUT

VSSA

VOUT_PA

VSSA

VOUT

_14SYNTH

VIN

_18CLK

VIN

_18VCO

VSSA

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VSSA

VBGAP

VSSA

CLKP

CLKM

VIN

_13RF2

VSSA

GPACD_5

SPIA_mosi

SPIA_clk

SPIB_mosi

SYNC_OUT

GPIO_0

VSSA

VIOIN

_18DIFF

VIN

_13RF2

GPADC_6

SPIA_miso

SPIB_clk

SPIB_miso

SPIB_cs_n

VSSA

RX4

VSSA

VSS

SPIA_cs_n

VIN_18BB

VSS

VIOIN

VIN

_13RF1

VSSA

RX3

VSSA

VSS

VIN_SRAM

VIN

_13RF1

VSSA

VSS

VDDIN

VIN

_13RF1

VSSA

RX2

VSSA

VSS

GPIO_1

LVDS_TXP0 LVDS_TXM0

LVDS_TXP1 LVDS_TXM1

LVDS_CLKP LVDS_CLKM

VSSA

VIN_18BB

VSS

GPIO_2

VSSA

RX1

VSSA

VSS

VPP

LVDS

_FRCLKP

LVDS

_FRCLKM

VSSA

MCU

_CLKOUT

Warm

_Reset

VSSA

GPADC1

VSSA

GPADC2

GPADC4

VSSA

rs232_rx

SYNC_in

GPIO_31

rs232_tx

GPIO_32

GPIO_33

nERROR_OUT nERROR_IN

TMS

TCK

VDDIN

QSPI_cs_n

TDI

QSPI[1]

QSPI[3]

QSPI_clk

TDO

DMM_SYNC

GPIO_47

VDDIN

SPI_HOST

_INTR

PMIC

_CLKOUT

GPADC3

NRESET

GPIO_34

VDDIN

GPIO_36

GPIO_35

GPIO_38

GPIO_37

VNWA

VIOIN_18

VIOIN

QSPI[0]

QSPI[2]

VSS

Not to scale

Figure 4-1. Pin Diagram

Terminal Configuration and Functions

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VSSA

VOUT_PA

VSSA

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VIN

_13RF2

VSSA

VIN

_13RF2

VSSA

VSS

RX4

VIN_18BB

VIN

_13RF1

VSSA

VSS

Not to scale

Figure 4-2. Top Left Quadrant

VOUT_

14APLL

OSC

_CLKOUT

VSSA

VOUT

_14SYNTH

VIN

_18CLK

VIN

_18VCO

VSSA

VBGAP

VSSA

CLKP

CLKM

GPACD_5

SPIA_mosi

SPIA_clk

VSSA

VIOIN

_18DIFF

GPADC_6

SPIA_miso

SPIB_clk

VSS

SPIA_cs_n

VSS

SPIB_mosi

SYNC_OUT

VIOIN

VSS

SPIB_miso

VIN_SRAM

Not to scale

Figure 4-3. Top Right Quadrant

Terminal Configuration and Functions

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VIN

_13RF1

RX3

VSSA

VSS

VIN

_13RF1

VSSA

VSS

RX2

VIN_18BB

VSSA

VSS

RX1

VSSA

MCU

_CLKOUT

VSSA

GPADC1

VSSA

rs232_rx

SYNC_in

GPIO_31

rs232_tx

GPIO_32

GPIO_33

nERROR_OUT nERROR_IN

GPADC2

GPADC4

GPADC3

NRESET

GPIO_34

GPIO_36

GPIO_35

GPIO_38

GPIO_37

VDDIN

Not to scale

Figure 4-4. Bottom Left Quadrant

Terminal Configuration and Functions

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VSS

GPIO_0

SPIB_cs_n

VDDIN

VSS

GPIO_1

GPIO_2

VPP

LVDS_TXP0 LVDS_TXM0

LVDS_TXP1 LVDS_TXM1

LVDS_CLKP LVDS_CLKM

VSS

LVDS

_FRCLKP

LVDS

_FRCLKM

Warm

_Reset

TMS

TCK

VDDIN

QSPI_cs_n

TDI

QSPI[1]

QSPI[3]

QSPI_clk

TDO

DMM_SYNC

GPIO_47

VDDIN

SPI_HOST

_INTR

PMIC

_CLKOUT

VNWA

VIOIN_18

VIOIN

QSPI[0]

QSPI[2]

VSS

Not to scale

Figure 4-5. Bottom Right Quadrant

Terminal Configuration and Functions

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4.2 Pin Attributes

Table 4-1. Pin Attributes (ABL0161 Package)

PINCNTL

SIGNAL NAME [3]

BALL RESET

STATE [7]

PULL UP/DOWN

TYPE [8]

BALL NUMBER [1]

BALL NAME [2]

MODE [5]

TYPE [6]

ADDRESS [4]

H13

J13

GPIO_0

GPIO_13

0xFFFFEA04

Output Disabled

Pull Down

GPIO_0

PMIC_CLKOUT

ePWM1b

ePWM2a

GPIO_1

GPIO_2

GPIO_31

GPIO_16

0xFFFFEA08

Output Disabled

Pull Down

GPIO_1

SYNC_OUT

DMM_MUX_IN

SPIB_cs_n_1

SPIB_cs_n_2

ePWM1SYNCI

GPIO_26

K13

0xFFFFEA64

Output Disabled

Pull Down

GPIO_2

OSC_CLKOUT

MSS_uartb_tx

BSS_uart_tx

SYNC_OUT

PMIC_CLKOUT

TRACE_DATA_0

GPIO_31

0xFFFFEA7C

Output Disabled

Pull Down

DMM0

MSS_uarta_tx

TRACE_DATA_1

GPIO_32

GPIO_33

GPIO_34

0xFFFFEA80

0xFFFFEA84

0xFFFFEA88

Output Disabled

Pull Down

DMM1

TRACE_DATA_2

GPIO_33

DMM2

TRACE_DATA_3

GPIO_34

DMM3

ePWM3SYNCO

Terminal Configuration and Functions

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Table 4-1. Pin Attributes (ABL0161 Package) (continued)

PINCNTL

SIGNAL NAME [3]

BALL RESET

STATE [7]

PULL UP/DOWN

TYPE [8]

BALL NUMBER [1]

BALL NAME [2]

MODE [5]

TYPE [6]

ADDRESS [4]

GPIO_35

GPIO_36

GPIO_37

GPIO_38

TRACE_DATA_4

GPIO_35

0xFFFFEA8C

0xFFFFEA90

0xFFFFEA94

0xFFFFEA98

Output Disabled

Pull Down

DMM4

ePWM2SYNCO

TRACE_DATA_5

GPIO_36

DMM5

MSS_uartb_tx

TRACE_DATA_6

GPIO_37

DMM6

BSS_uart_tx

TRACE_DATA_7

GPIO_38

DMM7

DSS_uart_tx

D14

B14

GPIO_39

GPIO_40

TRACE_DATA_8

GPIO_39

0xFFFFEA9C

0xFFFFEAA0

Output Disabled

Pull Down

DMM8

CAN_FD_tx

ePWM1SYNCI

TRACE_DATA_9

GPIO_40

Pull Down

DMM9

CAN_FD_rx

ePWM1SYNCO

TRACE_DATA_10

GPIO_41

B15

GPIO_41

GPIO_42

GPIO_43

0xFFFFEAA4

0xFFFFEAA8

0xFFFFEAAC

Output Disabled

Pull Down

DMM10

ePWM3a

TRACE_DATA_11

GPIO_42

DMM11

ePWM3b

TRACE_DATA_12

GPIO_43

DMM12

ePWM1a

CAN_tx

Terminal Configuration and Functions

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Table 4-1. Pin Attributes (ABL0161 Package) (continued)

PINCNTL

SIGNAL NAME [3]

BALL RESET

STATE [7]

PULL UP/DOWN

TYPE [8]

BALL NUMBER [1]

BALL NAME [2]

MODE [5]

TYPE [6]

ADDRESS [4]

GPIO_44

TRACE_DATA_13

GPIO_44

0xFFFFEAB0

Output Disabled

Pull Down

DMM13

ePWM1b

CAN_rx

GPIO_45

GPIO_46

TRACE_DATA_14

GPIO_45

0xFFFFEAB4

0xFFFFEAB8

Output Disabled

Pull Down

DMM14

ePWM2a

TRACE_DATA_15

GPIO_46

DMM15

ePWM2b

N15

N14

GPIO_47

TRACE_CLK

GPIO_47

0xFFFFEABC

0xFFFFEAC0

0xFFFFEA60

Output Disabled

Pull Down

DMM_CLK

TRACE_CTL

RESERVED

DMM_SYNC

GPIO_25

DMM_SYNC

MCU_CLKOUT

ePWM1a

nERROR_IN

nERROR_OUT

SOP[2]

0xFFFFEA44

0xFFFFEA4C

0xFFFFEA68

Input

nERROR_OUT

PMIC_CLKOUT

Hi-Z (Open Drain)

Output Disabled

During Power Up

Pull Down

GPIO_27

PMIC_CLKOUT

ePWM1b

ePWM2a

R13

N12

QSPI[0]

QSPI[1]

GPIO_8

0xFFFFEA2C

0xFFFFEA30

Output Disabled

Pull Down

QSPI[0]

SPIB_miso

GPIO_9

QSPI[1]

SPIB_mosi

SPIB_cs_n_2

GPIO_10

R14

QSPI[2]

0xFFFFEA34

Output Disabled

Pull Down

QSPI[2]

CAN_FD_tx

Terminal Configuration and Functions

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Table 4-1. Pin Attributes (ABL0161 Package) (continued)

PINCNTL

SIGNAL NAME [3]

BALL RESET

STATE [7]

PULL UP/DOWN

TYPE [8]

BALL NUMBER [1]

BALL NAME [2]

MODE [5]

TYPE [6]

ADDRESS [4]

P12

R12

QSPI[3]

GPIO_11

0xFFFFEA38

Output Disabled

Pull Down

QSPI[3]

CAN_FD_rx

GPIO_7

QSPI_clk

0xFFFFEA3C

Output Disabled

Pull Down

QSPI_clk

SPIB_clk

DSS_uart_tx

GPIO_6

P11

QSPI_cs_n

rs232_rx

0xFFFFEA40

0xFFFFEA74

Output Disabled

Input Enabled

Pull Up

QSPI_cs_n

SPIB_cs_n

GPIO_15

rs232_rx

MSS_uarta_rx

BSS_uart_tx

MSS_uartb_rx

CAN_FD_rx

I2C_scl

ePWM2a

ePWM2b

ePWM3a

rs232_tx

GPIO_14

0xFFFFEA78

Output Enabled

rs232_tx

MSS_uarta_tx

MSS_uartb_tx

BSS_uart_tx

CAN_FD_tx

I2C_sda

ePWM1a

ePWM1b

NDMM_EN

ePWM2a

E13

C13

SPIA_clk

GPIO_3

0xFFFFEA14

0xFFFFEA18

Output Disabled

Pull Up

SPIA_clk

CAN_rx

DSS_uart_tx

SPIA_cs_n

CAN_tx

SPIA_cs_n

Terminal Configuration and Functions

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Table 4-1. Pin Attributes (ABL0161 Package) (continued)

PINCNTL

SIGNAL NAME [3]

BALL RESET

STATE [7]

PULL UP/DOWN

TYPE [8]

BALL NUMBER [1]

BALL NAME [2]

MODE [5]

TYPE [6]

ADDRESS [4]

E14

D13

SPIA_miso

GPIO_20

0xFFFFEA10

Output Disabled

Pull Up

SPIA_miso

CAN_FD_tx

GPIO_19

SPIA_mosi

SPIB_clk

0xFFFFEA0C

Output Disabled

Pull Up

SPIA_mosi

CAN_FD_rx

DSS_uart_tx

GPIO_5

F14

0xFFFFEA24

Output Disabled

Pull Up

SPIB_clk1

MSS_uarta_rx

MSS_uartb_tx

BSS_uart_tx

CAN_FD_rx

GPIO_4

H14

SPIB_cs_n

0xFFFFEA28

Output Disabled

Pull Up

SPIB_cs_n

MSS_uarta_tx

MSS_uartb_tx

BSS_uart_tx

QSPI_clk_ext

CAN_FD_tx

GPIO_22

G14

SPIB_miso

0xFFFFEA20

Output Disabled

Pull Up

SPIB_miso

I2C_scl

DSS_uart_tx

GPIO_21

F13

P13

SPIB_mosi

0xFFFFEA1C

0xFFFFEA00

0xFFFFEA6C

Output Disabled

Pull Up

SPIB_mosi

I2C_sda

SPI_HOST_INTR

SYNC_in

GPIO_12

Pull Down

SPI_HOST_INTR

SPIB_cs_n_1

GPIO_28

SYNC_IN

MSS_uartb_rx

DMM_MUX_IN

SYNC_OUT

Terminal Configuration and Functions

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Table 4-1. Pin Attributes (ABL0161 Package) (continued)

PINCNTL

SIGNAL NAME [3]

BALL RESET

STATE [7]

PULL UP/DOWN

TYPE [8]

BALL NUMBER [1]

BALL NAME [2]

MODE [5]

TYPE [6]

ADDRESS [4]

G13

SYNC_OUT

SOP[1]

0xFFFFEA70

During Power Up

Output Disabled

Pull Down

GPIO_29

SYNC_OUT

DMM_MUX_IN

SPIB_cs_n_1

SPIB_cs_n_2

GPIO_17

P10

TCK

0xFFFFEA50

Input Enabled

Pull Down

Pull Up

TCK

MSS_uartb_tx

CAN_FD_tx

GPIO_23

R11

N13

TDI

0xFFFFEA58

0xFFFFEA5C

Input Enabled

TDI

MSS_uarta_rx

SOP[0]

TDO

During Power Up

Output Enabled

GPIO_24

TDO

MSS_uarta_tx

MSS_uartb_tx

BSS_uart_tx

NDMM_EN

GPIO_18

N10

TMS

0xFFFFEA54

0xFFFFEA48

Input Enabled

Pull Down

TMS

BSS_uart_tx

CAN_FD_rx

Warm_Reset

Hi-Z Input (Open

Drain)

Terminal Configuration and Functions

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The following list describes the table column headers:

1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.

2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).

3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the

signal name in muxmode 0).

4. PINCNTL ADDRESS: MSS Address for PinMux Control

5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name

for this Ball number. Mode column has bit range value.

6. TYPE: Signal type and direction:

–

I = Input

O = Output

IO = Input or Output

7. BALL RESET STATE: The state of the terminal at power-on reset

8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and

pulldown resistors can be enabled or disabled via software.

–

Pull Up: Internal pullup

Pull Down: Internal pulldown

An empty box means No pull.

9. Pin Mux Control Value maps to lower 4 bits of register.

Terminal Configuration and Functions

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IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as

follows:

Table 4-2. PAD IO Control Registers

Default Pin/Ball Name

SPI_HOST_INTR

GPIO_0

Package Ball /Pin (Address)

Pin Mux Config Register

0xFFFFEA00

0xFFFFEA04

0xFFFFEA08

0xFFFFEA0C

0xFFFFEA10

0xFFFFEA14

0xFFFFEA18

0xFFFFEA1C

0xFFFFEA20

0xFFFFEA24

0xFFFFEA28

0xFFFFEA2C

0xFFFFEA30

0xFFFFEA34

0xFFFFEA38

0xFFFFEA3C

0xFFFFEA40

0xFFFFEA44

0xFFFFEA48

0xFFFFEA4C

0xFFFFEA50

0xFFFFEA54

0xFFFFEA58

0xFFFFEA5C

0xFFFFEA60

0xFFFFEA64

0xFFFFEA68

0xFFFFEA6C

0xFFFFEA70

0xFFFFEA74

0xFFFFEA78

0xFFFFEA7C

0xFFFFEA80

0xFFFFEA84

0xFFFFEA88

0xFFFFEA8C

0xFFFFEA90

0xFFFFEA94

0xFFFFEA98

0xFFFFEABC

0xFFFFEAC0

P13

H13

J13

D13

E14

E13

E15

F13

G14

F14

H14

R13

N12

R14

P12

R12

P11

GPIO_1

SPIA_MOSI

SPIA_MISO

SPIA_CLK

SPIA_CN_EN

SPIB_MOSI

SPIB_MISO

SPIB_CLK

SPIB_CS_N

QSPI[0]

QSPI[1]

QSPI[2]

QSPI[3]

QSPI_CLK

QSPI_CS_N

NERROR_IN

WARM_RESET

NERROR_OUT

TCK

P10

N10

R11

N13

TMS

TDI

TDO

MCU_CLKOUT

GPIO_2

K13

PMIC_CLKOUT

SYNC_IN

SYNC_OUT

RS232_RX

RS232_TX

GPIO_31

G13

GPIO_32

GPIO_33

GPIO_34

GPIO_35

GPIO_36

GPIO_37

GPIO_38

GPIO_47

N15

N14

DMM_SYNC

Terminal Configuration and Functions

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The register layout is as follows:

Table 4-3. PAD IO Register Bit Descriptions

RESET

BIT FIELD

TYPE

(POWER ON

DEFAULT)

DESCRIPTION

31-11 NU

Reserved

IO slew rate control:

0 = Higher slew rate

1 = Lower slew rate

PUPDSEL

Pullup/PullDown Selection

0 = Pull Down

1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')

Pull Inhibit/Pull Disable

0 = Enable

1 = Disable

OE_OVERRIDE

Output Override

OE_OVERRIDE_CTR RW

Output Override Control:

(A '1' here overrides any o/p manipulation of this IO by any of the peripheral

block hardware it is associated with for example a SPI Chip select)

IE_OVERRIDE

Input Override

IE_OVERRIDE_CTR RW

Input Override Control:

(A '1' here overrides any i/p value on this IO with a desired value)

3-0

FUNC_SEL

Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)

Terminal Configuration and Functions

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4.3 Signal Descriptions

NOTE

All digital IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET)

are non-failsafe; hence, care needs to be taken that they are not driven externally without the

VIO supply being present to the device.

Table 4-4. Signal Descriptions - Digital

SIGNAL NAME

BSS_UART_TX

PIN TYPE

DESCRIPTION

BALL NO.

F14, H14, K13, N10, N13,

N4, N5, R8

Debug UART Transmit [Radar Block]

CAN_FD_RX

CAN_FD_TX

CAN_RX

CAN_TX

DMM0

CAN FD (MCAN) Receive Signal

D13, F14, N10, N4, P12

CAN FD (MCAN) Transmit Signal

E14, H14, N5, P10, R14

CAN (DCAN) Receive Signal

E13

E15

CAN (DCAN) Transmit Signal

Debug Interface (Hardware In Loop) - Data Line

Debug Interface (Hardware In Loop) - Clock

DMM1

DMM2

DMM3

DMM4

DMM5

DMM6

DMM7

DMM_CLK

N15

Debug Interface (Hardware In Loop) Mux Select between DMM1 and

DMM2 (Two Instances)

DMM_MUX_IN

G13, J13, P4

DMM_SYNC

DSS_UART_TX

EPWM1A

EPWM1B

EPWM1SYNCI

EPWM2A

EPWM2B

EPWM2SYNCO

EPWM3A

EPWM3SYNCO

GPIO_0

Debug Interface (Hardware In Loop) - Sync

Debug UART Transmit [DSP]

PWM Module 1 - Output A

N14

D13, E13, G14, P8, R12

N5, N8

PWM Module 1 - Output B

H13, N5, P9

D14, J13

PWM Module 2- Output A

PWM Module 2 - Output B

H13, N4, N5, P9

PWM Module 3 - Output A

General-purpose I/O

H13

J13

K13

E13

H14

F14

P11

R12

R13

N12

R14

P12

P13

H13

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

Terminal Configuration and Functions

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Table 4-4. Signal Descriptions - Digital (continued)

SIGNAL NAME

GPIO_14

PIN TYPE

DESCRIPTION

BALL NO.

General-purpose I/O

I2C Clock

GPIO_15

GPIO_16

J13

GPIO_17

P10

GPIO_18

N10

GPIO_19

D13

GPIO_20

E14

GPIO_21

F13

GPIO_22

G14

GPIO_23

R11

GPIO_24

N13

GPIO_25

GPIO_26

K13

GPIO_27

GPIO_28

GPIO_29

G13

GPIO_30

E15

GPIO_31

GPIO_32

GPIO_33

GPIO_34

GPIO_35

GPIO_36

GPIO_37

GPIO_38

N15

GPIO_47

I2C_SCL

G14, N4

F13, N5

J14

I2C_SDA

I2C Data

LVDS_TXP[0]

LVDS_TXM[0]

LVDS_TXP[1]

LVDS_TXM[1]

LVDS_CLKP

LVDS_CLKM

LVDS_FRCLKP

LVDS_FRCLKM

MCU_CLKOUT

MSS_UARTA_RX

MSS_UARTA_TX

MSS_UARTB_RX

Differential data Out – Lane 0

Differential data Out – Lane 1

Differential clock Out

J15

K14

K15

L14

L15

M14

Differential Frame Clock

M15

Programmable clock given out to external MCU or the processor

Master Subsystem - UART A Receive

F14, N4, R11

H14, N13, N5, R4

N4, P4

Master Subsystem - UART A Transmit

Master Subsystem - UART B Receive

F14, H14, K13, N13, N5,

P10, P7

MSS_UARTB_TX

NDMM_EN

Master Subsystem - UART B Transmit

Debug Interface (Hardware In Loop) Enable - Active Low Signal

N13, N5

Failsafe input to the device. Nerror output from any other device can

be concentrated in the error signaling monitor module inside the

device and appropriate action can be taken by Firmware

NERROR_IN

Open drain fail safe output signal. Connected to

NERROR_OUT

PMIC/Processor/MCU to indicate that some severe criticality fault

has happened. Recovery would be through reset.

Terminal Configuration and Functions

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Table 4-4. Signal Descriptions - Digital (continued)

SIGNAL NAME

PIN TYPE

DESCRIPTION

Output Clock from IWR1843 device for PMIC

QSPI Data Line #0 (Used with Serial Data Flash)

QSPI Data Line #1 (Used with Serial Data Flash)

QSPI Data Line #2 (Used with Serial Data Flash)

QSPI Data Line #3 (Used with Serial Data Flash)

QSPI Clock (Used with Serial Data Flash)

QSPI Chip Select (Used with Serial Data Flash)

Debug UART (Operates as Bus Master) - Receive Signal

Debug UART (Operates as Bus Master) - Transmit Signal

Sense On Power - Line#0

BALL NO.

PMIC_CLKOUT

QSPI[0]

H13, K13, P9

R13

QSPI[1]

N12

QSPI[2]

R14

QSPI[3]

P12

QSPI_CLK

QSPI_CLK_EXT

QSPI_CS_N

RS232_RX

RS232_TX

SOP[0]

R12

H14

P11

N13

SOP[1]

Sense On Power - Line#1

G13

SOP[2]

Sense On Power - Line#2

SPIA_CLK

SPI Channel A - Clock

E13

SPIA_CS_N

SPIA_MISO

SPIA_MOSI

SPIB_CLK

SPI Channel A - Chip Select

E15

SPI Channel A - Master In Slave Out

SPI Channel A - Master Out Slave In

SPI Channel B - Clock

E14

D13

F14, R12

SPIB_CS_N

SPIB_CS_N_1

SPIB_CS_N_2

SPIB_MISO

SPIB_MOSI

SPI_HOST_INTR

SYNC_IN

SPI Channel B Chip Select (Instance ID 0)

SPI Channel B Chip Select (Instance ID 1)

SPI Channel B Chip Select (Instance ID 2)

SPI Channel B - Master In Slave Out

SPI Channel B - Master Out Slave In

Out of Band Interrupt to an external host communicating over SPI

Low frequency Synchronization signal input

Low Frequency Synchronization Signal output

JTAG Test Clock

H14, P11

G13, J13, P13

G13, J13, N12

G14, R13

F13, N12

P13

SYNC_OUT

TCK

G13, J13, K13, P4

P10

R11

N13

N10

N15

N14

TDI

JTAG Test Data Input

TDO

JTAG Test Data Output

TMS

JTAG Test Mode Signal

TRACE_CLK

TRACE_CTL

TRACE_DATA_0

TRACE_DATA_1

TRACE_DATA_2

TRACE_DATA_3

TRACE_DATA_4

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

Debug Trace Output - Clock

Debug Trace Output - Control

Debug Trace Output - Data Line

Open drain fail safe warm reset signal. Can be driven from PMIC for

diagnostic or can be used as status signal that the device is going

through reset.

WARM_RESET

Terminal Configuration and Functions

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Table 4-5. Signal Descriptions - Analog

TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

BALL NO.

TX1

Single ended transmitter1 o/p

Transmitters

TX2

Single ended transmitter2 o/p

Single ended transmitter3 o/p

Single ended receiver1 i/p

Single ended receiver2 i/p

Single ended receiver3 i/p

Single ended receiver4 i/p

Power on reset for chip. Active low

TX3

RX1

RX2

Receivers

Reset

RX3

RX4

NRESET

In XTAL mode: Differential port for reference crystal

In External clock mode: Single ended input

reference clock port

CLKP

B15

Reference

Oscillator

In XTAL mode: Differential port for reference crystal

In External clock mode: Connect this port to ground

CLKM

C15

A14

Reference clock output from clocking subsystem

after cleanup PLL (1.4V output voltage swing).

Reference clock

Bandgap voltage

OSC_CLKOUT

VBGAP

VDDIN

Device's Band Gap Reference Output

1.2V digital power supply

B10

H15, N11, P15, R6

G15

Power

VIN_SRAM

VNWA

1.2V power rail for internal SRAM

1.2V power rail for SRAM array back bias

P14

I/O Supply (3.3V or 1.8V): All CMOS I/Os would

operate on this supply

VIOIN

Power

R10, F15

Power supply

VIOIN_18

VIN_18CLK

VIOIN_18DIFF

VPP

Power

1.8V supply for CMOS IO

1.8V supply for clock module

1.8V supply for LVDS port

Voltage supply for fuse chain

B11

D15

L13

1.3V Analog and RF supply,VIN_13RF1 and

VIN_13RF2 could be shorted on the board

VIN_13RF1

Power

G5, H5, J5

VIN_13RF2

VIN_18BB

VIN_18VCO

Power

1.3V Analog and RF supply

1.8V Analog base band power supply

1.8V RF VCO supply

C2,D2

K5, F5

B12

L5, L6, L8, L10,

K7, K8, K9, K10,

K11, J6, J7, J8,

VSS

Ground Digital ground

J10, H7, H9, H11,

G6, G7, G8, G10,

F9, F11, E5, E6,

E8, E10, E11, R15

Power supply

A1, A3, A5, A7,

A15, B1, B3, B5,

B7, C1, C3, C4,

C5, C6, C7, E1,

E2, E3, F3, G1,

G2, G3, H3, J1, J2,

J3, K3, L1, L2, L3,

M3, N1, N2, N3,

R1, A13, C8,A9,

B9, C9, B14, C14

VSSA

Ground Analog ground

VOUT_14APLL

Internal LDO output

A10

B13

VOUT_14SYNTH

When internal PA LDO is used this pin provides the

output voltage of the LDO. When the internal PA

Internal LDO

output/inputs

VOUT_PA

LDO is bypassed and disabled 1V supply should be A2, B2

fed on this pin. This is mandatory in 3TX

simultaneous use case.

Terminal Configuration and Functions

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Table 4-5. Signal Descriptions - Analog (continued)

TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

BALL NO.

Analog Test1 / ADC1

Analog Test2 / ADC2

Analog Test3 / ADC3

Analog Test4 / ADC4

ANAMUX / ADC5

ADC Channel 1⁽¹⁾

ADC Channel 2⁽¹⁾

ADC Channel 3⁽¹⁾

ADC Channel 4⁽¹⁾

ADC Channel 5⁽¹⁾

ADC Channel 6⁽¹⁾

Test and Debug

output for pre-

production phase.

Can be pinned out

on production

hardware for field

debug

C13

D14

VSENSE / ADC6

(1) For details, see Section 6.4.1.

5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

PARAMETERS

MIN

–0.5

MAX

1.4

UNIT

VDDIN

1.2 V digital power supply

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.4

1.2 V power rail for SRAM array back bias

1.4

I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply.

VIOIN

–0.5

3.8

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for LVDS port

–0.5

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

VIN_13RF1

1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could

be shorted on the board.

–0.5

1.45

1-V Internal LDO bypass mode. Device supports mode where

external Power Management block can supply 1 V on

VIN_13RF1 and VIN_13RF2 rails. In this configuration, the

internal LDO of the device would be kept bypassed.

–0.5

1.4

VIN_13RF2

VIN_18BB

1.8-V Analog baseband power supply

1.8-V RF VCO supply

–0.5

VIN_18VCO supply

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

–0.3V

VIOIN + 0.3

Input and output

voltage range

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

VIOIN + 20% up to

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

–0.5

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

–20

T_J

Operating junction temperature range

–40

–55

105

150

ºC

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

5.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM)⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002

(1) ANSI/ESDA/JEDEC JS0991 specification.

Specifications

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5.3 Power-On Hours (POH)⁽¹⁾

JUNCTION

TEMPERATURE (T_j)

OPERATING

CONDITION

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

90% at 85ºC T_j

10% at 105ºC T_j

80,000

50% duty cycle

1.2

100% at 85ºC T_j

100,000

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms

and conditions for TI semiconductor products.

Specifications

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5.4 Recommended Operating Conditions

MIN

1.14

3.135

1.71

NOM

1.2

3.3

1.8

MAX

1.32

3.465

1.89

1.9

UNIT

VDDIN

1.2 V digital power supply

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for LVDS port

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

1.9

1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2

could be shorted on the board

1.23

1.3

1.36

VIN_13RF1

(1-V Internal LDO

bypass mode)

0.95

1.05

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN18BB

1.8-V Analog baseband power supply

1.8V RF VCO supply

1.71

1.17

2.25

1.8

1.9

VIN_18VCO

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

V_IH

V_IL

0.3*VIOIN

0.62

V_OH

V_OL

VIOIN – 450

450

0.2

V_IH(1.8V Mode)

0.96

1.57

NRESET

SOP[2:0]

V_IL(3.3V Mode)

0.3

V_IH(3.3V Mode)

5.5 Power Supply Specifications

Table 5-1 describes the four rails from an external power supply block of the IWR1843 device.

Table 5-1. Power Supply Rails Characteristics

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOS IN THE DEVICE

Input: VIN_18VCO, VIN18CLK, VIN_18BB,

VIOIN_18DIFF, VIOIN_18IO

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, LVDS

1.8 V

1.3 V (or 1 V in internal

LDO bypass mode)

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

Input: VIN_13RF2, VIN_13RF1

LDO Output: VOUT_PA

3.3 V (or 1.8 V for 1.8 V

I/O mode)

Digital I/Os

Input VIOIN

1.2 V

Core Digital and SRAMs

Input: VDDIN, VIN_SRAM

Specifications

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The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in are defined to meet a target

spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB

relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values

quoted are rms levels for a sinusoidal input applied at the specified frequency.

Table 5-2. Ripple Specifications

RF RAIL

1.0 V (INTERNAL LDO BYPASS)

VCO/IF RAIL

FREQUENCY (kHz)

1.3 V (µV_RMS

)

1.8 V (µV_RMS)

(µV_RMS

)

137.5

275

648

550

1100

2200

4400

6600

117

5.6 Power Consumption Summary

Table 5-3 and summarize the power consumption at the power terminals.

Table 5-3. Maximum Current Ratings at Power Terminals

PARAMETER

SUPPLY NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Total current drawn by all

nodes driven by 1.2V rail

VDDIN, VIN_SRAM, VNWA

1000

Total current drawn by all

nodes driven by 1.3V or

1.0V rail (2TX, 4 RX

simultaneously)⁽¹⁾

VIN_13RF1, VIN_13RF2

2000

850

Current consumption

VIOIN_18, VIN_18CLK,

VIOIN_18DIFF, VIN_18BB,

VIN_18VCO

Total current drawn by all

nodes driven by 1.8V rail

Total current drawn by all

nodes driven by 3.3V

rail⁽²⁾

VIOIN

(1) 3 Transmitters can simultaneously be deployed only in devices with 1V / LDO bypass and PA LDO disable mode. In this mode 1-V

supply needs to be fed on the VOUT PA pin. In this case the peak 1-V supply current goes up to 2500 mA.

(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.

Specifications

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Table 5-4. Average Power Consumption at Power Terminals

PARAMETER

CONDITION

DESCRIPTION

MIN

TYP MAX UNIT

1TX, 4RX

2TX, 4RX

1TX, 4RX

2TX, 4RX

1TX, 4RX

2TX, 4RX

1TX, 4RX

2TX, 4RX

Use Case: Low power mode,

3.2 MSps complex transceiver,

25-ms frame time, 128 chirps,

128 samples/chirp, 8-µs

interchirp time (25% duty

cycle), DSP active

1.3

25% Duty

Cycle

1.38

1.77

1.92

1.0-V internal

LDO bypass

mode

Use Case: Low power mode,

3.2 MSps complex transceiver,

25-ms frame time, 256 chirps,

128 samples/chirp, 8-µs

interchirp time (50% duty

cycle), DSP active

50% Duty

Cycle

Average power

consumption

Use Case: Low power mode,

3.2 MSps complex transceiver,

25-ms frame time, 128 chirps,

128 samples/chirp, 8-µs

interchirp time (25% duty

cycle), DSP active

1.4

25% Duty

Cycle

1.48

1.94

2.14

1.3-V internal

LDO enabled

mode

Use Case: Low power mode,

3.2 MSps complex transceiver,

25-ms frame time, 256 chirps,

128 samples/chirp, 8-µs

interchirp time (50% duty

cycle), DSP active

50% Duty

Cycle

Specifications

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5.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

76 to 77 GHz

77 to 81 GHz

–8

Noise figure⁽¹⁾

1-dB compression point (Out Of Band / Specified at 10 kHz)⁽²⁾

dBm

Maximum gain

Gain range

Gain step size

Image Rejection Ratio (IMRR)

IF bandwidth⁽³⁾

MHz

A2D sampling rate (real)

A2D sampling rate (complex 1x)

A2D resolution

25 Msps

12.5 Msps

Receiver

<–10

±0.5

±3

Bits

Return loss (S11)

Gain mismatch variation (over temperature)

Phase mismatch variation (over temperature)

RX gain = 30dB

In-band IIP2

IF = 1.5, 2 MHz at

–12 dBFS

dBm

RX gain = 24dB

IF = 10 kHz at -10dBm,

1.9 MHz at -30 dBm

Out-of-band IIP2

Idle Channel Spurs

Output power

–90

dBFS

dBm

Transmitter

Amplitude noise

Frequency range

Ramp rate

–145

dBc/Hz

GHz

100 MHz/µs

Clock

subsystem

76 to 77 GHz

77 to 81 GHz

–95

–93

Phase noise at 1-MHz offset

dBc/Hz

(1) Specification is quoted for complex 1x mode.

(2) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone below the lowest HPF cut-off frequency (50 kHz).

(3) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of

available HPF corners is summarized as follows:

Available HPF Corner Frequencies (kHz)

HPF1

HPF2

175, 235, 350, 700

350, 700, 1400, 2800

The filtering performed by the digital baseband chain is targeted to provide:

•

Less than ±0.5 dB pass-band ripple/droop, and

Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

5.8 CPU Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

600

MAX UNIT

Clock Speed

DSP

MHz

L1 Code Memory

Subsystem

(C674

Family)

L1 Data Memory

L2 Memory

256

200

512

192

Master

Clock Speed

MHz

Controller

Subsystem

(R4F Family)

Tightly Coupled Memory - A (Program)

Tightly Coupled Memory - B (Data)

Specifications

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CPU Specifications (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

Shared

Shared L3 Memory

Memory

1024

5.9 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

4.2

RΘ_JC

RΘ_JB

RΘ_JA

RΘ_JMA

Psi_JT

Psi_JB

Junction-to-case

Junction-to-board

5.7

Junction-to-free air

Junction-to-moving air

Junction-to-package top

Junction-to-board

20.9

14.5⁽⁴⁾

0.38

5.6

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

A junction temperature of 105ºC is assumed.

(4)

Specifications

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5.10 Timing and Switching Characteristics

5.10.1 Power Supply Sequencing and Reset Timing

The IWR1843 device expects all external voltage rails and SOP lines to be stable before reset is

deasserted. describes the device wake-up sequence.

SOP

Setup

Time

SOP

Hold time to

nRESET

DC power

Stable before

nRESET

MSS

BOOT

START

nRESET

ASSERT

tPGDEL

Power

notOK

Power

QSPI

READ

release

VDDIN,

VIN_SRAM

VNWA

VIOIN_18

VIN18_CLK

VIOIN_18DIFF

VIN18_BB

VIN_13RF1

VIN_13RF2

VIOIN

SOP IO

Reuse

SOP IO‘s can be used as functional IO‘s

SOP[2.1.0]

nRESET

WARMRESET

OUTPUT

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

MCUCLK

OUTPUT (1)

QSPI_CS

OUTPUT

8 ms (XTAL Mode)

850 µs (REFCLK Mode)

(1) MCU_CLK_OUT in autonomous mode, where IWR1843 application is booted from the serial flash, MCU_CLK_OUT is not enabled

by default by the device bootloader.

Figure 5-1. Device Wake-up Sequence

Specifications

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5.10.2 Input Clocks and Oscillators

5.10.2.1 Clock Specifications

The IWR1843 requires external clock source (that is, a 40-MHz crystal) for initial boot and as a reference

for an internal APLL hosted in the device. An external crystal is connected to the device pins. Figure 5-2

shows the crystal implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

Figure 5-2. Crystal Implementation

NOTE

The load capacitors, C_f1and C_f2in Figure 5-2, should be chosen such that Equation 1 is

satisfied. C_Lin the equation is the load specified by the crystal manufacturer. All discrete

components used to implement the oscillator circuit should be placed as close as possible to

the associated oscillator CLKP and CLKM pins.

C _f2

C_L= C _f1

+C_P

_f1+C _f2

Table 5-5 lists the electrical characteristics of the clock crystal.

Table 5-5. Crystal Electrical Characteristics (Oscillator Mode)

(1)

NAME

DESCRIPTION

Parallel resonance crystal frequency

MIN

TYP

MAX

UNIT

MHz

f_P

C_L

Crystal load capacitance

Crystal ESR

ESR

Temperature range Expected temperature range of operation

–40

105

ºC

Frequency

tolerance

Crystal frequency tolerance⁽¹⁾⁽²⁾

–200

200

ppm

µW

Drive level

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

Table 5-6. External Clock Mode Specifications

SPECIFICATION

PARAMETER

UNIT

MIN

TYP

MAX

Frequency

MHz

mV (pp)

dBc/Hz

AC-Amplitude

700

1200

–132

–143

–152

–153

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

Input Clock:

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise referred to 40 MHz

Freq Tolerance

–50

ppm

Specifications

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5.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

5.10.3.1 Peripheral Description

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.

The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals

or another microcontroller.

Standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

8-bit baud clock generator

SPICLK can be internally-generated (master mode) or received from an external clock source

(slave mode)

•

Each word transferred can have a unique format.

SPI I/Os not used in the communication can be used as digital input/output signals

5.10.3.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a

16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer

RAM can be partitioned into multiple transfer group with variable number of buffers each.

Table 5-8 and Table 5-9 assume the operating conditions stated in Table 5-7.

Table 5-7. SPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

Output Conditions

C_LOADOutput load capacitance

Specifications

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Table 5-8. SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^(1)(2)(3)

NO.

PARAMETER

MIN

TYP

MAX

256_tc(VCLK)

UNIT

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M– 3

0.5t_c(SPC)M– 10.5

0.5t_c(SPC)M+ 4

2⁽⁴⁾

3⁽⁴⁾

4⁽⁴⁾

5⁽⁴⁾

t_w(SPCL)M

Pulse duration, SPICLK low (clock polarity = 1)

t_w(SPCL)M

Pulse duration, SPICLK low (clock polarity = 0)

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 1)

t_{d(SPCH-SIMO)M}

t_{d(SPCL-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{v(SPCH-SIMO)M}

Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)

Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)

(C2TDELAY+2)*t_c(VCLK

₎– 7.5

(C2TDELAY+2) *

t_c(VCLK)+ 7

CSHOLD = 0

Setup time CS active until SPICLK high

(clock polarity = 0)

(C2TDELAY +3) *

t_c(VCLK)– 7.5

(C2TDELAY+3) *

t_c(VCLK)+ 7

CSHOLD = 1

6⁽⁵⁾

t_C2TDELAY

(C2TDELAY+2)*t_c(VCLK

₎– 7.5

(C2TDELAY+2) *

t_c(VCLK)+ 7

CSHOLD = 0

Setup time CS active until SPICLK low

(clock polarity = 1)

(C2TDELAY +3) *

t_c(VCLK)– 7.5

(C2TDELAY+3) *

t_c(VCLK)+ 7

CSHOLD = 1

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

(T2CDELAY + 1) *

t_c(VCLK)+ 7.5

Hold time, SPICLK low until CS inactive (clock polarity = 0)

Hold time, SPICLK high until CS inactive (clock polarity = 1)

(T2CDELAY + 1)

*t_c(VCLK)– 7

7⁽⁵⁾

t_T2CDELAY

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

(T2CDELAY + 1) *

t_c(VCLK)+ 7.5

(T2CDELAY + 1)

*t_c(VCLK)– 7

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

t_{su(SOMI-SPCL)M}

t_{su(SOMI-SPCH)M}

t_{h(SPCL-SOMI)M}

t_{h(SPCH-SOMI)M}

8⁽⁴⁾

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

9⁽⁴⁾

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)}= master subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8]

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Specifications

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1

Master Out Data Is Valid

SPISIMO

Master In Data

Must Be Valid

SPISOMI

Figure 5-3. SPI Master Mode External Timing (CLOCK PHASE = 0)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

Figure 5-4. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

Specifications

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Table 5-9. SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^(1)(2)(3)

NO.

PARAMETER

MIN

TYP

MAX

256t_c(VCLK)

UNIT

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M– 3

0.5t_c(SPC)M– 10.5

0.5t_c(SPC)M+ 4

2⁽⁴⁾

3⁽⁴⁾

4⁽⁴⁾

5⁽⁴⁾

t_w(SPCL)M

Pulse duration, SPICLK low (clock polarity = 1)

t_w(SPCL)M

Pulse duration, SPICLK low (clock polarity = 0)

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 1)

t_{d(SPCH-SIMO)M}

t_{d(SPCL-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{v(SPCH-SIMO)M}

Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)

Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

CSHOLD = 0

(C2TDELAY +

2)*t_c(VCLK)– 7

(C2TDELAY+2) *

t_c(VCLK)+ 7.5

Setup time CS active until SPICLK high

(clock polarity = 0)

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

CSHOLD = 1

CSHOLD = 0

(C2TDELAY +

2)*t_c(VCLK)– 7

(C2TDELAY+2) *

t_c(VCLK)+ 7.5

6⁽⁵⁾

t_C2TDELAY

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

(C2TDELAY+2) *

t_c(VCLK)+ 7.5

(C2TDELAY+2)*t_c(

_VCLK)– 7

Setup time CS active until SPICLK low

(clock polarity = 1)

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

CSHOLD = 1

(C2TDELAY+3)*t_c(

_VCLK)– 7

(C2TDELAY+3) *

t_c(VCLK)+ 7.5

(T2CDELAY + 1)

*t_c(VCLK)– 7.5

(T2CDELAY + 1)

*t_c(VCLK)+ 7

Hold time, SPICLK low until CS inactive (clock polarity = 0)

Hold time, SPICLK high until CS inactive (clock polarity = 1)

7⁽⁵⁾

8⁽⁴⁾

9⁽⁴⁾

t_T2CDELAY

(T2CDELAY + 1)

*t_c(VCLK)– 7.5

(T2CDELAY + 1)

*t_c(VCLK)+ 7

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

t_{su(SOMI-SPCL)M}

t_{su(SOMI-SPCH)M}

t_{h(SPCL-SOMI)M}

t_{h(SPCH-SOMI)M}

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).

(2) t_{c(MSS_VCLK)}= master subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8]

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Specifications

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

Master Out Data Is Valid

Data Valid

SPISIMO

Master In Data

Must Be Valid

SPISOMI

Figure 5-5. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

Figure 5-6. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

Specifications

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5.10.3.3 SPI Slave Mode I/O Timings

Table 5-10. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output)^(1)(2)(3)

NO.

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

TYP

MAX

UNIT

t_c(SPC)S

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

2⁽⁵⁾

3⁽⁵⁾

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0)

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

4⁽⁵⁾

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

5⁽⁵⁾

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0; clock phase = 0) OR (clock polarity = 1;

clock phase = 1)

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

t_{h(SPCL-SIMO)S}

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity = 0;

clock phase = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity = 1;

clock phase = 1)

Setup time, SPISIMO before SPICLK high (clock

polarity = 1; clock phase = 0) OR (clock polarity = 0;

clock phase = 1)

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3) t_{c(MSS_VCLK)}= master subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns, where

PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S= 2t_{c(MSS_VCLK)}≥ 25 ns.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Specifications

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

SPISIMO

Figure 5-7. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

SPISIMO

Figure 5-8. SPI Slave Mode External Timing (CLOCK PHASE = 1)

Specifications

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5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)

1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI

clock.

2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.

Figure 5-9 shows the SPI communication timing of the typical interface protocol.

2 SPI clocks

CLK

0x4321

0x1234

CRC

0x5678

0x8765

MOSI

MISO

IRQ

0xDCBA

0xABCD

CRC

16 bytes

Figure 5-9. SPI Communication

Specifications

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5.10.4 LVDS Interface Configuration

The supported IWR1843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane

(LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for

debugging. The LVDS interface supports the following data rates:

•

900 Mbps (450 MHz DDR Clock)

600 Mbps (300 MHz DDR Clock)

450 Mbps (225 MHz DDR Clock)

400 Mbps (200 MHz DDR Clock)

300 Mbps (150 MHz DDR Clock)

225 Mbps (112.5 MHz DDR Clock)

150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to

data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

Figure 5-10. LVDS Interface Lane Configuration And Relative Timings

5.10.4.1 LVDS Interface Timings

Table 5-11. LVDS Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

Duty Cycle Requirements

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

Output Differential Voltage

250

450

Output Offset Voltage

Trise and Tfall

1125

1275

20%-80%, 900 Mbps

900 Mbps

Jitter (pk-pk)

Specifications

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Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

Figure 5-11. Timing Parameters

Specifications

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5.10.5 General-Purpose Input/Output

Table 5-12 lists the switching characteristics of output timing relative to load capacitance.

Table 5-12. Switching Characteristics for Output Timing versus Load Capacitance (C_L)⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

C_L= 75 pF

10.2

2.8

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

6.6

9.8

3.3

7.2

10.5

3.1

Slew control = 1

6.6

9.6

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

Specifications

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5.10.6 Controller Area Network Interface (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1

Mbps. The DCAN is ideal for applications operating in noisy and harsh environments that require reliable

serial communication or multiplexed wiring.

The DCAN has the following features:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 Mbps

Configurable Message objects

Individual identifier masks for each message object

Programmable FIFO mode for message objects

Suspend mode for debug support

Programmable loop-back modes for self-test operation

Direct access to Message RAM in test mode

Supports two interrupt lines - Level 0 and Level 1

Automatic Message RAM initialization

Table 5-13. Dynamic Characteristics for the DCANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

UNIT

t_{d(CAN_tx)}

t_{d(CAN_rx)}

Delay time, transmit shift register to CAN_tx pin⁽¹⁾

Delay time, CAN_rx pin to receive shift register⁽¹⁾

(1) These values do not include rise/fall times of the output buffer.

Specifications

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5.10.7 Controller Area Network - Flexible Data-rate (CAN-FD)

The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate)

specifications. CAN FD feature allows high throughput and increased payload per data frame. The classic

CAN and CAN FD devices can coexist on the same network without any conflict.

The CAN-FD has the following features:

•

Conforms with CAN Protocol 2.0 A, B and ISO 11898-1

Full CAN FD support (up to 64 data bytes per frame)

AUTOSAR and SAE J1939 support

Up to 32 dedicated Transmit Buffers

Configurable Transmit FIFO, up to 32 elements

Configurable Transmit Queue, up to 32 elements

Configurable Transmit Event FIFO, up to 32 elements

Up to 64 dedicated Receive Buffers

Two configurable Receive FIFOs, up to 64 elements each

Up to 128 11-bit filter elements

Internal Loopback mode for self-test

Mask-able interrupts, two interrupt lines

Two clock domains (CAN clock / Host clock)

Parity / ECC support - Message RAM single error correction and double error detection (SECDED)

mechanism

•

Full Message Memory capacity (4352 words).

Table 5-14. Dynamic Characteristics for the CANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

UNIT

Delay time, transmit shift register to

CAN_FD_tx pin⁽¹⁾

t_{d(CAN_FD_tx)}

t_{d(CAN_FD_rx)}

Delay time, CAN_FD_rx pin to receive shift

(1) These values do not include rise/fall times of the output buffer.

5.10.8 Serial Communication Interface (SCI)

The SCI has the following features:

•

Standard universal asynchronous receiver-transmitter (UART) communication

Standard non-return to zero (NRZ) format

Double-buffered receive and transmit functions

Asynchronous or iso-synchronous communication modes with no CLK pin

Capability to use Direct Memory Access (DMA) for transmit and receive data

Two external pins: RS232_RX and RS232_TX

Table 5-15. SCI Timing Requirements

MIN

TYP

921.6

MAX

UNIT

kHz

f(baud)

Supported baud rate at 20 pF

Specifications

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5.10.9 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface

between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by

an I²C-bus™. This module will support any slave or master I2C compatible device.

The I2C has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number

9398 393 40011)

–

Bit/Byte format transfer

7-bit and 10-bit device addressing modes

General call

START byte

Multi-master transmitter/ slave receiver mode

Multi-master receiver/ slave transmitter mode

Combined master transmit/receive and receive/transmit mode

Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

•

Free data format

Two DMA events (transmit and receive)

DMA event enable/disable capability

Module enable/disable capability

The SDA and SCL are optionally configurable as general purpose I/O

Slew rate control of the outputs

Open drain control of the outputs

Programmable pullup/pulldown capability on the inputs

Supports Ignore NACK mode

NOTE

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I2C sends the slave address second

byte every time it sends the slave address first byte)

Specifications

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Table 5-16. I2C Timing Requirements⁽¹⁾

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

t_c(SCL)

Cycle time, SCL

2.5

μs

Setup time, SCL high before SDA low

(for a repeated START condition)

t_{su(SCLH-SDAL)}

4.7

0.6

Hold time, SCL low after SDA low

(for a START and a repeated START condition)

t_h(SCLL-SDAL)

μs

t_w(SCLL)

Pulse duration, SCL low

4.7

1.3

0.6

100

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SCLL-SDA)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

3.45⁽¹⁾

0.9

Pulse duration, SDA high between STOP and START

conditions

t_w(SDAH)

4.7

1.3

μs

Setup time, SCL high before SDA high

(for STOP condition)

t_{su(SCLH-SDAH)}

t_w(SP)

0.6

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

(2)(3)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL

signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

Figure 5-12. I2C Timing Diagram

NOTE

•

A device must internally provide a hold time of at least 300 ns for the SDA signal

(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW

period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a

Standard-mode I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be

met. This will automatically be the case if the device does not stretch the LOW period of

the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr max + t_su(SDA-SCLH)

Specifications

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5.10.10 Quad Serial Peripheral Interface (QSPI)

The quad serial peripheral interface (QSPI) module is a kind of SPI module that allows single, dual, or

quad read access to external SPI devices. This module has a memory mapped register interface, which

provides a direct interface for accessing data from external SPI devices and thus simplifying software

requirements. The QSPI works as a master only. The QSPI in the device is primarily intended for fast

booting from quad-SPI flash memories.

The QSPI supports the following features:

•

Programmable clock divider

Six-pin interface

Programmable length (from 1 to 128 bits) of the words transferred

Programmable number (from 1 to 4096) of the words transferred

Support for 3-, 4-, or 6-pin SPI interface

Optional interrupt generation on word or frame (number of words) completion

Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles

Table 5-18 and Table 5-19 assume the operating conditions stated in Table 5-17.

Table 5-17. QSPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

Output Conditions

C_LOAD

Output load capacitance

Table 5-18. Timing Requirements for QSPI Input (Read) Timings⁽¹⁾⁽²⁾

MIN

7.3

TYP

MAX

UNIT

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

t_h(SCLK-D)

Setup time, d[3:0] valid before falling sclk edge (Q12)

Hold time, d[3:0] valid after falling sclk edge (Q13)

Setup time, final d[3:0] bit valid before final falling sclk edge

Hold time, final d[3:0] bit valid after final falling sclk edge

1.5

7.3 – P⁽³⁾

1.5 + P⁽³⁾

(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.

(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-

standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

(3) P = SCLK period in ns.

Specifications

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Table 5-19. QSPI Switching Characteristics

NO.

PARAMETER

Cycle time, sclk

MIN

TYP

MAX

UNIT

t_c(SCLK)

t_w(SCLKL)

Pulse duration, sclk low

0.5*P – 3⁽¹⁾

0.5*P – 3

–M*P – 1⁽²⁾

N*P – 1⁽²⁾

–3.5

t_w(SCLKH)

t_d(CS-SCLK)

t_d(SCLK-CS)

t_d(SCLK-D1)

t_ena(CS-D1LZ)

t_dis(CS-D1Z)

Pulse duration, sclk high

Delay time, sclk falling edge to cs active edge

Delay time, sclk falling edge to cs inactive edge

Delay time, sclk falling edge to d[0] transition

Enable time, cs active edge to d[0] driven (lo-z)

Disable time, cs active edge to d[0] tri-stated (hi-z)

–M*P + 2.5⁽²⁾

N*P + 2.5⁽²⁾

–P – 4⁽²⁾

–P +1⁽²⁾

Delay time, sclk first falling edge to first d[1] transition

(for PHA = 0 only)

t_d(SCLK-D1)

–3.5 – P⁽²⁾

7 – P⁽²⁾

(1) P = SCLK period in ns.

(2) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

PHA=0

POL=0

sclk

Q12

Q13

Q12 Q13

Read Data

Bit 0

Command

Bit n-1

Command

Bit n-2

Read Data

Bit 1

d[0]

Q12 Q13

Read Data

Bit 1

Q12 Q13

Read Data

Bit 0

d[3:1]

SPRS85v_TIMING_OSPI1_02

Figure 5-13. QSPI Read (Clock Mode 0)

Specifications

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PHA=0

POL=0

sclk

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

Figure 5-14. QSPI Write (Clock Mode 0)

Specifications

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5.10.11 ETM Trace Interface

Table 5-21 and assume the recommended operating conditions stated in Table 5-20.

Table 5-20. ETMTRACE Timing Conditions

MIN

TYP

MAX

UNIT

Output Conditions

C_LOADOutput load capacitance

Table 5-21. ETM TRACE Switching Characteristics

NO.

PARAMETER

Cycle time, TRACECLK period

Pulse Duration, TRACECLK High

Pulse Duration, TRACECLK Low

Clock and data rise time

MIN

TYP

MAX

UNIT

t_cyc(ETM)

t_h(ETM)

t_l(ETM)

t_r(ETM)

3.3

t_f(ETM)

Clock and data fall time

t_d(ETMTRAC

ECLKH-

Delay time, ETM trace clock high to ETM data valid

Delay time, ETM trace clock low to ETM data valid

ETMDATAV)

t_d(ETMTRAC

ECLKl-

ETMDATAV)

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

Figure 5-15. ETMTRACECLKOUT Timing

Figure 5-16. ETMDATA Timing

Specifications

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5.10.12 Data Modification Module (DMM)

A Data Modification Module (DMM) gives the ability to write external data into the device memory.

The DMM has the following features:

•

Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention

Writes to memory locations specified in the received packet (leverages packets defined by trace mode

of the RAM trace port [RTP] module)

•

Writes received data to consecutive addresses, which are specified by the DMM (leverages packets

defined by direct data mode of RTP module)

•

Configurable port width (1, 2, 4, 8, 16 pins)

Up to 65 Mbit/s pin data rate

Table 5-22. DMM Timing Requirements

MIN

TYP

MAX

UNIT

t_cyc(DMM)

Clock period

15.4

t_R

Clock rise time

t_F

Clock fall time

t_h(DMM)

t_l(DMM)

t_ssu(DMM)

t_sh(DMM)

t_dsu(DMM)

t_dh(DMM)

High pulse width

Low pulse width

SYNC active to clk falling edge setup time

DMM clk falling edge to SYNC deactive hold time

DATA to DMM clk falling edge setup time

DMM clk falling edge to DATA hold time

t_l(DMM)

t_h(DMM)

t_f

t_r

t_cyc(DMM)

Figure 5-17. DMMCLK Timing

t_ssu(DMM)

t_sh(DMM)

DMMSYNC

DMMCLK

DMMDATA

t_dsu(DMM)

t_dh(DMM)

Figure 5-18. DMMDATA Timing

Specifications

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5.10.13 JTAG Interface

Table 5-24 and Table 5-25 assume the operating conditions stated in Table 5-23.

Table 5-23. JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

Output Conditions

C_LOADOutput load capacitance

Table 5-24. Timing Requirements for IEEE 1149.1 JTAG

NO.

MIN

TYP

MAX

UNIT

t_c(TCK)

Cycle time TCK

66.66

26.67

2.5

t_w(TCKH)

Pulse duration TCK high (40% of tc)

Pulse duration TCK low(40% of tc)

Input setup time TDI valid to TCK high

Input setup time TMS valid to TCK high

Input hold time TDI valid from TCK high

Input hold time TMS valid from TCK high

t_w(TCKL)

t_su(TDI-TCK)

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

2.5

Table 5-25. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

TCK

TDO

TDI/TMS

SPRS91v_JTAG_01

Figure 5-19. JTAG Timing

Specifications

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6 Detailed Description

6.1 Overview

The IWR1843 device includes the entire Millimeter Wave blocks and analog baseband signal chain for

three transmitters and four receivers, as well as a customer-programmable MCU, Radar Hardware

accelerator, and a DSP. This device is applicable as a radar-on-a-chip in use-cases with modest

requirements for memory, processing capacity, and application code size. These could be cost-sensitive

industrial radar-sensing applications. Examples are:

•

Industrial-level sensing

Industrial automation sensor fusion with radar

Traffic intersection monitoring with radar

Industrial radar-proximity monitoring

People counting

Gesturing

6.2 Functional Block Diagram

Serial Flash interface

QSPI

SPI

Cortex R4F

@ 200MHz

LNA

ADC

Optional External

MCU interface

(User programmable)

Digital

Front-end

PMIC control

SPI / I2C

DCAN

Prog RAM

(512kB*)

Data RAM

(192kB*)

Boot

ROM

(Decimation

filter chain)

Primary communication

interfaces (automotive)

CAN-FD

UARTs

Radar Hardware Accelerator

(FFT, Log mag, and others)

DMA

Master sub-system

(Customer programmed)

Test/

Debug

JTAG for debug/

development

ADC

Buffer

û-

Mailbox

High-speed ADC output

interface (for recording)

LVDS

HIL

Synth

(20 GHz)

Ramp

Generator

High-speed input for

hardware-in-loop verification

C674x DSP

@ 400/600 MHz

Radio (BIST)

processor

GPADC

Osc.

(For RF Calibration

& Self-test œ TI

programmed)

L1P

(32kB)

L1D

(32kB)

L2 (256kB)

Prog RAM

& ROM

Data

RAM

VMON

Temp

DMA

CRC

Radar Data Memory

1024 kB*

Radio processor

sub-system

(TI programmed)

DSP sub-system

(Customer programmed)

RF/Analog sub-system

* Up to 512kB of Radar Data Memory can be switched to the Master R4F program and data RAMs

Figure 6-1. Functional Block Diagram

Detailed Description

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6.3 Subsystems

6.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA,

mixer, IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The

three transmit channels can be operated up to a maximum of two at a time (simultaneously) for transmit

beamforming purpose as required; whereas the four receive channels can all be operated simultaneously.

Detailed Description

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6.3.1.1 Clock Subsystem

The IWR1843 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has

a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF

synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz

spectrum. The RF synthesizer output is modulated by the timing engine block to create the required

waveforms for effective sensor operation.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring

the quality of the generated clock.

Figure 6-2 describes the clock subsystem.

Self Test

RF SYNTH

Timing

SYNC_OUT

Engine

Lock Detect

SoC Clock

Clean-

Up PLL

MULT

XO/

Slicer

CLK Detect

40 MHz

Figure 6-2. Clock Subsystem

Detailed Description

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6.3.1.2 Transmit Subsystem

The IWR1843 transmit subsystem consists of three parallel transmit chains, each with independent phase

and amplitude control. All three transmitters can be used simultaneously. For IWR1843, additional phase

shifters are associated with Tx channels, and these can programmed on a per chirp basis.

Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit

chains also support programmable backoff for system optimization.

Figure 6-3 describes the transmit subsystem.

Loopback Path

Fine Phase Shifter Control

PCB

6 bits

12dBm

@ 50 Ω

û-

0/180°

(from Timing Engine)

Self Test

Figure 6-3. Transmit Subsystem (Per Channel)

6.3.1.3 Receive Subsystem

The IWR1843 receive subsystem consists of four parallel channels. A single receive channel consists of

an LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational

at the same time an individual power-down option is also available for system optimization.

Unlike conventional real-only receivers, the IWR1843 device supports a complex baseband architecture,

which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each

receiver channel. The IWR1843 is targeted for fast chirp systems. The band-pass IF chain has

configurable lower cutoff frequencies above 175 kHz and can support bandwidths up to 10 MHz.

Figure 6-4 describes the receive subsystem.

Self Test

DAC

Loopback

Path

DSM

PCB

RSSI

50 W

GSG

DSM

DAC

Figure 6-4. Receive Subsystem (Per Channel)

Detailed Description

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6.3.2 Processor Subsystem

Unified

128KB x 2

ROM

Cache/

RAM

TCM A 512KB

Master

R4F

L1P

32KB

EDMA

DSP

HIL

JTAG

CRC

HIL

TCM B 192KB

L1d

DSP Interconnect œ 128 bit @ 200 MHz

Master Interconnect

BSS Interconnect

Data

Handshake

Memory

CRC

ADC Buffer

Mail

Box

MSS

DMA

HWA

32KB

32KB Ping-Pong

1024 KB

(static sharing

with R4F Space)

Interconnect

LVDS

PWM,

PMIC

CLK

CAN

I²C

QSPI

UART

CAN

SPI

Figure 6-5. Processor Subsystem

Figure 6-5 shows the block diagram for customer programmable processor subsystems in the IWR1843

device. At a high level there are two customer programmable subsystems, as shown separated by a

dotted line in the diagram. Left hand side shows the DSP Subsystem which contains TI's high-

performance C674x DSP, a hardware accelerator, a high-bandwidth interconnect for high performance

(128-bit, 200MHz), and associated peripherals – four DMAs for data transfer,

LVDS interface for Measurement data output, L3 Radar data cube memory, ADC buffers, CRC engine,

and data handshake memory (additional memory provided on interconnect).

The right side of the diagram shows the Master subsystem. Master subsystem as name suggests is the

master of the device and controls all the device peripherals and house-keeping activities of the device.

Master subsystem contains Cortex-R4F (Master R4F) processor and associated peripherals and house-

keeping components such as DMAs, CRC and Peripherals (I²C, UART, SPIs, CAN, PMIC clocking

module, PWM, and others) connected to Master Interconnect through Peripheral Central Resource (PCR

interconnect).

Details of the DSP CPU core can be found at http://www.ti.com/product/TMS320C6748.

HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the

captured data from outside into the device without involving the RF subsystem. HIL on master SS is for

controlling the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL

modules uses the same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of

the two.

Detailed Description

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6.3.3 Host Interface

The host interface can be provided through a SPI, UART, or CAN-FD interface. In some cases the serial

interface for industrial applications is transcoded to a different serial standard.

The IWR1843 device communicates with the host radar processor over the following main interfaces:

•

Reference Clock – Reference clock available for host processor after device wakeup

Control – 4-port standard SPI (slave) for host control. All radio control commands (and response) flow

through this interface.

•

Reset – Active-low reset for device wakeup from host

Host Interrupt - an indication that the mmwave sensor needs host interface

Error – Used for notifying the host in case the radio controller detects a fault

6.3.4 Master Subsystem Cortex-R4F Memory Map

Table 6-1 shows the master subsystem, Cortex-R4F memory map.

NOTE

There are separate Cortex-R4F addresses and DMA MSS addresses for the master

subsystem. See the Technical Reference Manual for a complete list.

Table 6-1. Master Subsystem, Cortex-R4F Memory Map

FRAME ADDRESS (HEX)

NAME

SIZE

DESCRIPTION

START

CPU Tightly-Coupled Memories

END

TCMA ROM

TCM RAM-A

0x0000_0000

0x0020_0000

0x0001_FFFF

128 KiB

512 KiB

Program ROM

Data RAM

0x0023_FFFF (or

0x0027_FFFF)

TCM RAM-B

0x0800_0000

0x0802_FFFF

192 KB

8 KB

S/W Scratch Pad Memory

SW_ Buffer

0x0C20_0000

0x0C20_1FFF

S/W Scratchpad memory

System Peripherals

Mail Box

MSS<->RADARSS

0xF060_1000

0xF060_2000

0xF060_8000

0xF060_17FF

0xF060_27FF

0xF060_80FF

2 KB

RADARSS to MSS mailbox memory space

MSS to RADARSS mailbox memory space

188 B

MSS to RADARSS mailbox Configuration

registers

0xF060_8060

0xF060_86FF

RADARSS to MSS mailbox Configuration

registers

Mail Box

MSS<->DSPSS

0xF060_4000

0xF060_5000

0xF060_8400

0xF060_8300

0xF060_6000

0xF060_7000

0xF060_8200

0xF060_47FF

0xF060_57FF

0xF060_84FF

0xF060_83FF

0xF060_67FF

0xF060_7FFF

0xF060_82FF

2 KB

DSPSS to MSS mailbox memory space

MSS to DSPSS mailbox memory space

188 B

2 KB

MSS to DSPSS mailbox Configuration registers

DSPSS to MSS mailbox Configuration registers

RADARSS to DSPSS mailbox memory space

DSPSS to RADARSS mailbox memory space

Mail Box

RADARSS<-

>DSPSS

188 B

RADARSS to DSPSS mailbox Configuration

registers

0xF060_8100

0xF060_81FF

DSPSS to RADARSS mailbox Configuration

registers

PRCM and Control

Module

0xFFFF_E100

0xFFFF_FF00

0xFFFF_EA00

0xFFFF_F800

0xFFFF_E2FF

0xFFFF_FFFF

0xFFFF_EBFF

0xFFFF_FBFF

756 B

256 B

512 KB

352 B

TOP Level Reset, Clock management registers

MSS Reset, Clock management registers

IO Mux module registers

General-purpose control registers

Detailed Description

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Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued)

FRAME ADDRESS (HEX)

START END

NAME

SIZE

DESCRIPTION

GIO

0xFFF7_BC00

0xFFFF_F000

0xFCFF_F800

0xFCFF_F700

0xFCFF_F600

0xFFFF_FD00

0xFFFF_FC00

0xFFFF_EE00

0xFFF7_BDFF

0xFFFF_F3FF

0xFCFF_FBFF

0xFCFF_F7FF

0xFCFF_F6FF

0xFFFF_FEFF

0xFFFF_FCFF

0xFFFF_EEFF

180 B

GIO module configuration registers

DMA-1 module configuration registers

DMA-2 module configuration registers

DMM-1 module configuration registers

DMM-2 module configuration registers

VIM module configuration registers

RTI-A module configuration registers

RTI-B module configuration registers

DMA-1

DMA-2

DMM-1

DMM-2

VIM

1 KB

472 B

512 B

192 B

RTI-A/WD

RTI-B

Serial Interfaces and Connectivity

QSPI

0xC000_0000

0xC080_0000

0xFFF7_F400

0xFFF7_F600

0xFFF7_E500

0xFFF7_E700

0xFFF7_DC00

0xFFF7_C800

0xFFF7_A000

0xFFF7_D400

0xC07F_FFFF

0xC0FF_FFFF

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_E5FF

0xFFF7_E7FF

0xFFF7_DDFF

0xFFF7_CFFF

0xFFF7_A1FF

0xFFF7_D4FF

8 MB

QSPI –flash memory space

116 B

512 B

148 B

512 B

768 B

452 B

112 B

QSPI module configuration registers

MIBSPI-A module configuration registers

MIBSPI-B module configuration registers

SCI-A module configuration registers

SCI-B module configuration registers

CAN module configuration registers

CAN-FD module configuration registers

MCAN ECC module registers

MIBSPI-A

MIBSPI-B

SCI-A

SCI-B

CAN

CAN_FD(MCAN)

I2C

I2C module configuration registers

Interconnects

PCR-1

0xFFF7_8000

0xFCFF_1000

0xFFF7_87FF

0xFCFF_17FF

1 KiB

PCR-1 interconnect configuration port

PCR-2 interconnect configuration port

PCR-2

Safety Modules

CRC

0xFE00_0000

0xFFFF_E400

0xFFFF_E600

0xFFFF_EC00

0xFFFF_F400

0xFFFF_F500

0xFFFF_F600

0xFEFF_FFFF

0xFFFF_E5FF

0xFFFF_E7FF

0xFFFF_ECFF

0xFFFF_F4FF

0xFFFF_F5FF

0xFFFF_F6FF

16 KiB

464 B

284 B

44 B

CRC module configuration registers

PBIST module configuration registers

STC module configuration registers

DCC-A module configuration registers

DCC-B module configuration registers

ESM module configuration registers

CCMR4 module configuration registers

PBIST

STC

DCC-A

DCC-B

44 B

ESM

156 B

136 B

CCMR4

Security Modules

Crypto

0xFD00_0000

0XFDFF_FFFF

3 KiB

Crypto module configuration registers

Other Subsystems

DSS_TPTC0

DSS_REG

DSS_TPTC1

DSS_REG2

DSS_TPCC0

DSS_RTIA/WDT

DSS_SCI

0x5000 0000

0x5000 0400

0x5000 0800

0x5000 0C00

0x5001 0000

0x5002 0000

0x5003 0000

0x5004 0000

0x5007 0000

0x5009 0000

0x5009 0400

0x500A 0000

0x500D 0000

0x5000 0317

0x5000 075F

0x5000 0B17

0x5000 0EA3

0x5001 3FFF

0x5002 00BF

0x5003 0093

0x5004 011B

0x5007 0233

0x5009 0317

0x5009 0717

0x500A 3FFF

0x500D 005B

792 B

864 B

792 B

676 B

16 KB

192 B

148 B

284 B

564 B

792 B

16 KB

92 B

TPTC0 module configuration space

DSPSS control module registers

TPTC1 module configuration space

DSPSS control module registers

TPCC0 module configuration space

DSS_RTIA/WDT configuration space

SCI memory space

DSS_STC

DSS_CBUFF

DSS_TPTC2

DSS_TPTC3

DSS_TPCC1

DSS_ESM

STC module configuration space

Common Buffer module configuration registers

TPTC2 module configuration space

TPTC3 module configuration space

TPCC1 module configuration space

ESM module configuration registers

Detailed Description

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Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued)

FRAME ADDRESS (HEX)

START END

NAME

DSS_RTIB

SIZE

DESCRIPTION

0x500F 0000

0x5100 0000

0x500F 00BF

0x511F FFFF

192 B

RTI-B module configuration registers

L3 shared memory space

DSS_L3RAM

Shared memory

2 MB⁽¹⁾

32 KB

DSS_ADCBUF

Buffer

0x5200 0000

0x5200 7FFF

ADC buffer memory space

DSS_CBUFF_FIFO 0x5202 0000

DSS_HSRAM1 0x5208 0000

0x5202 3FFF

0x5208 7FFF

0x577F FFFF

16 KB

32 KB

128 KB

Common buffer FIFO space

Handshake memory space

L2 RAM space

DSS_DSP_L2_UMA 0x577E 0000

DSS_DSP_L2_UMA 0x5780 0000

0x5781 FFFF

128 KB

L2 RAM space

DSS_DSP_L1P

DSS_DSP_L1D

0x57E0 0000

0x57F0 0000

0x57E0 7FFF

0x57F0 7FFF

32 KB

L1 program memory space

L1 data memory space

Peripheral Memories (System and Nonsystem)

CAN RAM

0xFF1E_0000

0xFF50_0000

0xFFF8_0000

0xFCF8 1000

0xFFF8_2000

0xFF0C_0000

0xFF0C_0200

0xFF0E_0000

0xFF1F_FFFF

0xFF51_FFFF

0xFFF8_0FFF

0xFCF8_0FFF

0xFFF8_2FFF

0xFF0C_01FF

0xFF0C_03FF

0xFF0E_01FF

0xFF0E_03FF

128 KB

68 KB

4 KB

CAN RAM memory space

CAN-FD RAM

DMA1 RAM

CAN-FD RAM memory space

DMA1 RAM memory space

DMA2 RAM

4 KB

DMA2 RAM memory space

VIM RAM

2 KB

VIM RAM memory space

MIBSPIB-TX RAM

MIBSPIB-RX RAM

MIBSPIA-TX RAM

0.5 KB

MIBSPIB-TX RAM memory space

MIBSPIB-RX RAM memory space

MIBSPIA-TX RAM memory space

MIBSPIA- RX RAM memory space

MIBSPIA- RX RAM 0xFF0E_0200

Debug Modules

Debug subsystem

0xFFA0_0000

0xFFAF_FFFF

244 KB

Debug subsystem memory space and registers

(1) 768 KB memory within 2 MB memory space

6.3.5 DSP Subsystem Memory Map

Table 6-2 shows the DSP C674x memory map.

Table 6-2. DSP C674x Memory Map

Name

Frame Address (Hex)

End

Size

Description

Start

DSP Memories

DSP_L1D

0x00F0_0000

0x00E0_0000

0x00F0_7FFF

32 KiB

L1 data memory space

DSP_L1P

0x00E0_7FFF

L1 program memory

space

DSP_L2_UMAP0

DSP_L2_UMAP1

EDMA

0x0080_0000

0x007E_0000

0x0081_FFFF

0x007F_FFFF

128 KiB

L2 RAM space

TPCC0

0x0201_0000

0x020A_0000

0x0200 0000

0x0200 0800

0x0201_3FFF

0x020A_3FFF

0x0200 03FF

0x0200 0BFF

16 KiB

1 KiB

TPCC0 module

configuration space

TPCC1

TPTC0

TPTC1

TPCC1 module

configuration space

TPTC0 module

configuration space

1 KiB

TPTC1 module

configuration space

Detailed Description

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Table 6-2. DSP C674x Memory Map (continued)

Frame Address (Hex)

End

Size

Description

Start

TPTC2

TPTC3

0x0209_0000

0x0209_03FF

1 KiB

TPTC2 module

configuration space

0x0209_0400

0x0209_07FF

TPTC3 module

configuration space

Control Registers

DSS_REG

0x0200_0400

0x0200_0C00

0x0200_07FF

0x0200_0FFF

864 B

624 B

DSPSS control module

registers

DSS_REG2

DSPSS control module

registers

System Memories

ADC Buffer

0x2100_0000

0x2102_0000

0x2100_7FFC

0x2102_3FFC

32 KiB

16 KiB

ADC buffer memory space

CBUFF-FIFO

Common buffer FIFO

space

L3-Shared memory

HS-RAM

0x2000_0000

0x2108_0000

0x201F_FFFF

0x2108_7FFC

2 MB

L3 shared memory space

32 KiB

Handshake memory

space

System Peripherals

RTI-A/WD

0x0202_0000

0x020F_0000

0x0207_0000

0x5060_1000

0x5060_2000

0x0460_8000

0x0202_00FF

0x020F_00FF

0x0207_03FF

0x5060_17FF

0x5060_27FF

0x0460_80FF

192 B

564 B

2 KiB

RTI-A module

configuration registers

RTI-B

RTI-B module

configuration registers

CBUFF

Common Buffer module

Configuration registers

Mail Box

MSS<->RADARSS

RADARSS to MSS

mailbox memory space

MSS to RADARSS

mailbox memory space

188 B

MSS to RADARSS

mailbox Configuration

registers

0x0460_8060

0x0460_86FF

RADARSS to MSS

mailbox Configuration

registers

Mail Box

MSS<->DSPSS

0x5060_4000

0x5060_5000

0x0460_8400

0x0460_8300

0x5060_6000

0x5060_7000

0x0460_8200

0x5060_47FF

0x5060_57FF

0x0460_84FF

0x0460_83FF

0x5060_67FF

0x5060_7FFF

0x0460_82FF

2 KiB

188 B

2 KiB

188 B

DSPSS to MSS mailbox

memory space

MSS to DSPSS mailbox

memory space

MSS to DSPSS mailbox

Configuration registers

DSPSS to MSS mailbox

Configuration registers

Mail Box

RADARSS<->DSPSS

RADARSS to DSPSS

mailbox memory space

DSPSS to RADARSS

mailbox memory space

RADARSS to DSPSS

mailbox Configuration

registers

0x0460_8100

0x020D_0000

0x0460_81FF

DSPSS to RADARSS

mailbox Configuration

registers

Safety Modules

ESM

92 B

ESM module

Configuration registers

Detailed Description

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Table 6-2. DSP C674x Memory Map (continued)

Name

Frame Address (Hex)

End

Size

Description

Start

CRC

STC

0x2200_0000

0x2200_03FF

1 KiB

284 B

CRC module

Configuration registers

0x0204_0000

0x0203_0000

0x0204_01FF

0x0203_00FF

STC module Configuration

registers

Nonsystem Peripherals

SCI

148 B

SCI module Configuration

registers

6.3.6 Hardware Accelerator

The Radar Hardware Accelerator (HWA) is an IP that enables off-loading the burden of certain frequently

used computations in FMCW radar signal processing from the main processor. FMCW radar signal

processing involves the use of FFT and Log-Magnitude computations to obtain a radar image across the

range, velocity, and angle dimensions. Some of the frequently used functions in FMCW radar signal

processing can be done within the radar hardware accelerator, while still retaining the flexibility of

implementing other proprietary algorithms in the main processor. See the Radar Hardware Accelerator

User's Guide for a functional description and features of this module and see the Technical Reference

Manual for a complete list of register and memory map.

6.4 Other Subsystems

6.4.1 ADC Channels (Service) for User Application

The IWR1843 device includes provision for an ADC service for user application, where the

GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1,

ADC2, ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.

•

ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for

customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST

subsystem. This API could be linked with the user application running on the Master R4.

•

BIST subsystem firmware will internally schedule these measurements along with other RF and Analog

monitoring operations. The API allows configuring the settling time (number of ADC samples to skip)

and number of consecutive samples to take. At the end of a frame, the minimum, maximum and

average of the readings will be reported for each of the monitored voltages.

GPADC Specifications:

•

625 Ksps SAR ADC

0 to 1.8V input range

10-bit resolution

For 5 out of the 6 inputs, an optional internal buffer is available. Without the buffer, the ADC has a

switched capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic

capacitance (GPADC channel 6, the internal buffer is not available).

Detailed Description

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ANALOG TEST 1-4,

ANAMUX

GPADC

VSENSE

A. GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these

measurements is ±7ºC.

Figure 6-6. ADC Path

Table 6-3. GP-ADC Parameter

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TYP

1.8

UNIT

ADC supply

ADC unbuffered input voltage range

ADC buffered input voltage range⁽¹⁾

ADC resolution

0 – 1.8

0.4 – 1.3

bits

LSB

Ksps

ADC offset error

±5

ADC gain error

±5

ADC DNL

–1/+2.5

±2.5

625

400

ADC INL

ADC sample rate⁽²⁾

ADC sampling time⁽²⁾

ADC internal cap

ADC buffer input capacitance

ADC input leakage current

(1) Outside of given range, the buffer output will become nonlinear.

(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.

Detailed Description

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7 Monitoring and Diagnostics

7.1 Monitoring and Diagnostic Mechanisms

Table 7-1 is a list of the main monitoring and diagnostic mechanisms available in the IWR1843.

Table 7-1. Monitoring and Diagnostic Mechanisms for IWR1843

FEATURE

DESCRIPTION

IWR1843 architecture supports various temperature sensors all across the device (next to

power hungry modules such as PAs, DSP, etc.) which is monitored during the inter-frame

period.⁽¹⁾

Temperature Sensors

Provision to detect ADC saturation du;e to excessive incoming signal level and/or

interference.

RX saturation detect

(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the temperature

sensed via API by customer application.

•

Report the temperature sensed after every N frames

Report the condition once the temperature crosses programmed threshold.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.

Monitoring and Diagnostics

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7.1.1 Error Signaling Module

When a diagnostic detects a fault, the error must be indicated. IWR1843 architecture provides aggregation

of fault indication from internal diagnostic mechanisms using a peripheral logic known as the error

signaling module (ESM). The ESM provides mechanisms to classify faults by severity and allows

programmable error response. Below is the high level block diagram for ESM module.

Low Priority

Interrupt

Interrupy

Handing

Error Group 1

Interrupt Enable

High Priority

Interrupt

Handing

High Priority

Interrupy

Interrupt Priority

Error Group 2

Error Group 3

Nerror Enable

Error Signal

Handling

Device Output

Figure 7-1. ESM Module Diagram

Monitoring and Diagnostics

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8 Applications, Implementation, and Layout

NOTE

Information in the following Applications section is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI's customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

8.1 Application Information

The IWR1843 can be a radar sensor, or can be combined with an MSP432, or for LVDS processing with a

LVDS to DSP subsystem for more advanced applications. Some applications are:

•

Liquid and solid level sensing for process sensors or industrial automation

Industrial proximity sensing, non-contact sensing for security, traffic monitoring, and industrial

transportation

•

Sensor fusion of camera and radar instruments for security, factory automation, robotics

Sensor fusion with multiple camera and radar instruments for object identification, manipulation, and

flight avoidance for security, robotics, material handling, or drone devices

•

People counting

Gesturing

Motion detection

40-MHz

Crystal

Power

Management

QSPI Flash

POWER

SPI

UART Tx/Rx

CAN

Integrated MCU

ARM Cortex-R4F

Antenna

Structure

RX1

RX2

RX3

RX4

mmWave/

Radar

Front End

TX1

TX2

TX3

Integrated DSP

TI C674x

IWR1843

Figure 8-1. Autonomous Sensor For Industrial Applications

8.2 Reference Schematic

Figure 8-2 shows the reference schematic for the IWR1843 device.

Applications, Implementation, and Layout

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DUT REFERENCE

AR_1P0_RF1

U2B

AR_VOUT_PA

AR_1V4_APLL

A13

A15

B14

C14

VIN_13RF1

VSSA

AR_1P0_RF2

U2A

VIN_13RF2

AR_1V4_SYNTH

AR_1V8

RX1

RX2

RX3

RX4

TX1

TX2

TX3

RX1

RX2

RX3

RX4

TX1

TX2

TX3

VOUT_PA

B11

B12

VIN_18CLK

VIN_18VCO

50 OHMS RF TRACES

A10

B13

VOUT_14APLL

VOUT_14SYNTH

VIN_18BB

AR_3V3

AR_1V24

J14

K15

K14

J15

L14

L15

M14

M15

LVDS_TXP[0]

LVDS_TXM[1]

LVDS_TXP[1]

LVDS_TXM[0]

LVDS_CLKP

AR_LVDS_0_P

A14

B15

C15

G15

AR_OSC_CLKOUT

AR_XTALP

OSC_CLKOUT

CLKP

AR_LVDS_1_N

VIN_SRAM

AR_LVDS_1_P

100 OHMS

DIFFERENTIAL TRACES

F15

R10

AR_XTALM

CLKM

AR_LVDS_0_N

VIOIN

AR_MCUCLKOUT

MCU_CLKOUT

PMIC_CLKOUT

AR_LVDS_CLK_P

AR_LVDS_CLK_N

AR_LVDS_FRCLK_P

AR_LVDS_FRCLK_N

AR_1V8

AR_PMIC_CLKOUT_SOP2

LVDS_CLKM

LVDS_FRCLKP

LVDS_FRCLKM

VIOIN_18

AR_ANATEST1

AR_ANATEST2

AR_ANATEST3

AR_ANATEST4

AR_ANAMUX

AR_VSENSE

GPADC_1

GPADC_2

GPADC_3

GPADC_4

GPADC_5

GPADC_6

AR_1V24

D15

VIOIN_18DIFF

RESET

AR_NRST

H15

N11

P15

WARM_RESET

AR_WARMRST

AR_NERRIN

AR_NERR_OUT

VDDIN

OPENDRAIN SIGNALS

PLACE ONBOARD

PULLUPS

VPP_1P7

C13

D14

ERROR_IN

ERROR_OUT

H13

J13

K13

AR_GPIO_0

AR_GPIO_1

AR_GPIO_2

GPIO[0]

GPIO[1]

GPIO[2]

RS232_TX

RS232_RX

AR_RS232TX

AR_RS232RX

L13

P14

VPP

0.1µF

R12

P11

R13

N12

R14

P12

QSPI_CLK

QSPI_CS

QSPI[0]

AR_QSPI_SCLK

AR_QSPI_CS

AR_QSPI_D0

AR_QSPI_D1

AR_QSPI_D2

AR_QSPI_D3

VNWA

AR_DP0

AR_DP1

AR_DP2

AR_DP3

AR_DP4

AR_DP5

AR_DP6

AR_DP7

DP0

DP1

DP2

DP3

DP4

DP5

DP6

DP7

VSS

GND

QSPI[1]

QSPI[2]

E10

E11

QSPI[3]

P10

R11

N13

N10

TCK

TDI

AR_TCK

F11

G10

H11

AR_TDI

TDO

TMS

AR_TDO_SOP0

AR_TMS

E14

D13

E13

E15

AR_MISO1

AR_MOSI1

AR_SPICLK1

AR_CS1

MISO_1

MOSI_1

P13

SPI_CLK_1

SPI_CS_1

SPI_HOST_INTR_1

AR_HOSTINTR1

SYNC_IN

AR_SYNC_IN

VSS

R47

R81

G14

F13

F14

H14

G13

K10

K11

AR_SCL

MISO_2

SYNC_OUT

AR_SYNC_OUT_SOP1

AR_VBGAP

AR_SDA

MOSI_2

B10

AR_MSS_LOGGER

AR_BSS_LOGGER

SPI_CLK_2

SPI_CS_2

VBGAP

J10

N15

N14

L10

R15

AR_DMM_CLK

DMM_CLK

AR_DMM_SYNC

DMM_SYNC

IWR1843ABL

GND

Pullups/Pulldowns

+3.3VD

QSPI FLASH REFERENCE

3V3_REF

AR_HOSTINTR1

R37

R16

10.0k

R15

10.0k

R14

10.0k

R91

10.0k

R171

2.94k

R170

2.94k

R13

10.0k

3V3_REF

AR_NERRIN

1uF

Net Class

C15

0.1uF

AR_WARMRST

AR_CS1

R38

47.5k

4.7pF

3V3_REF

AR_SCL

AR_QSPI_CS

GND

AR_SDA

GND

R44

AR_NERR_OUT

AR_QSPI_SCLK

33.2

GND

Net Class

VCC

R43

10.0k

GND

R45

AR_QSPI_D0

SCLK

SI/SIO0

SO/SIO1

33.2

R39

33.2

AR_QSPI_D1

R42

33.2

AR_QSPI_D2

WP/SIO2

GND

HOLD/SIO3

R98

AR_PMIC_CLKOUT_SOP2

AR_SYNC_OUT_SOP1

AR_TDO_SOP0

3V3_REF

MX25V1635FZNQ

10.0k

GND

R113

R41

10.0k

SOP lines to be driven via 10K series

10.0k

prior to bootup to ensure bootup in the desired mode

R89

R40

33.2

AR_QSPI_D3

10.0k

DECOUPLING CAPS REFERENCE

BB SUPPLY

AR_1V8

DIFF SUPPLY

AR_1V8

1P8V IO SUPPLY

AR_1V8

VCOLDO SUPPLY

AR_1V8

VCLK SUPPLY

AR_1V8

AR_VBGAP

DIG SUPPLY

AR_1V24

VNWA SUPPLY

AR_1V24

SRAM SUPPLY

AR_1V24

AR_1V4_APLL

C56

C13

1uF

C39

C51

C52

C53

C48

C12

C90

C17

0.22µF

C89

C101

0.22µF 0.22µF 10uF

0.22µF

0.22µF 10uF

0.1uF

2.2uF

0.22µF

0.01uF

GND

RF1 SUPPLY

AR_1P0_RF1

RF2 SUPPLY

AR_1P0_RF2

3V3IO SUPPLY

AR_3V3

GND

AR_VOUT_PA

AR_1V4_SYNTH

AR_1P0_RF2

AR_VOUT_PA

C47

C45

10uF

C57

C58

0.22µF

C84

C87

C14

1uF

C10

C65

C83

10uF

0.22µF

10uF

0.22µF

2.2uF

R137

0.22µF

10uF

GND

Figure 8-2. IWR1843 Reference Schematic

Applications, Implementation, and Layout

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8.3 Layout

The top layer routing, top layer closeup, and bottom layer routing are shown in Figure 8-3, Figure 8-4, and

Figure 8-5, respectively.

8.3.1 Layout Guidelines

Figure 8-3. Top Layer Routing

Figure 8-4. Top Layer Routing Closeup

Applications, Implementation, and Layout

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Figure 8-5. Bottom Layer Routing

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8.3.2 Stackup Details

0.689

Rogers 4835 4.000

1.260

2.067

4.000

1.260

100.000

73.000

Rogers 4835 4mil coreH/1 Low Pro

3.480

Iteq IT180A Prepreg 1080

Dielectric

4.195

2.830

3.700

1.260

28.000

1.260

28.000

1.260

69.000

48.000

Iteq IT180A 28 mil core 1/1

FR4

4.280

Iteq IT180A Prepreg 1080

Dielectric

4.195

2.691

3.700

1.260

4.000

0.689

1.260

4.000

2.067

72.000

Iteq IT180A 4 mil core 1/H

FR4

3.790

100.000

Applications, Implementation, and Layout

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the

device, generate code, and develop solutions follow.

9.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)

(for example, IWR1843). Texas Instruments recommends two of three possible prefix designators for its

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development

from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

Experimental device that is not necessarily representative of the final device's electrical

specifications and may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications.

null

Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, ), the temperature range (for example, blank is the default commercial

temperature range). Figure 9-1 provides a legend for reading the complete device name for any IWR1843

device.

For orderable part numbers of IWR1843 devices in the ABL0161 package types, see the Package Option

Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the IWR1843 Device

Errata.

Device and Documentation Support

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IWR

ABL

Qualification

Blank= no special qual

Tray or Tape & Reel

Prefix

IWR = Industrial

Generation

1 = 76 GHz to 81 GHz

Variant

R = Tape & Reel

Blank = Tray

2 = FE

4 = FE + FFT + MCU

6 = FE + MCU + DSP

Package

ABL = BGA

Security

8 = FE + FFT + MCU + DSP + 2MB

Num RX/TX Channels

G = General

S = Secure

RX = 1,2,3,4

TX = 1,2,3

Silicon PG Revision

blank = Rev1.0

A = Rev2.0

Features

blank = baseline

Safety Level

Q = Quality Manage

Figure 9-1. Device Nomenclature

9.2 Tools and Software

Models

IWR1843 BSDL model Boundary scan database of testable input and output pins for IEEE 1149.1 of the

specific device.

IWR1843 IBIS model IO buffer information model for the IO buffers of the device. For simulation on a

circuit board, see IBIS Open Forum.

Software Tools

Code Composer Studio™ (CCS) Integrated Development Environment (IDE)

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller

and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop

and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project

build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user

interface taking the user through each step of the application development flow. Familiar tools and

interfaces allow users to get started faster than ever before. Code Composer Studio combines the

advantages of the Eclipse software framework with advanced embedded debug capabilities from TI

resulting in a compelling feature-rich development environment for embedded developers.

UniFlash Standalone Flash Tool

UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or

scripting interface.

9.3 Documentation Support

To receive notification of documentation updates—including silicon errata—go to the product folder for

your device on ti.com (IWR1843). In the upper right corner, click the "Alert me" button. This registers you

to receive a weekly digest of product information that has changed (if any). For change details, check the

revision history of any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral

follows.

Errata

Device and Documentation Support

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IWR1843 device errata Describes known advisories, limitations, and cautions on silicon and provides

workarounds.

Device and Documentation Support

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9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design

help—straight from the experts. Search existing answers or ask your own question to get the quick design

help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications

and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

E2E is a trademark of Texas Instruments.

ARM, Cortex are registered trademarks of ARM Limited.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Device and Documentation Support

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10 Mechanical, Packaging, and Orderable Information

10.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the

most current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

CAUTION

The following package information is subject to change without notice.

Mechanical, Packaging, and Orderable Information

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PACKAGE OUTLINE

ABL0161B

FCBGA - 1.17 mm max height

SCALE 1.400

PLASTIC BALL GRID ARRAY

10.5

10.3

BALL A1 CORNER

10.5

10.3

1.17 MAX

SEATING PLANE

0.1 C

BALL TYP

0.37

0.27

TYP

9.1 TYP

PKG

(0.65) TYP

PKG

9.1

TYP

0.45

161X

0.35

0.15

0.08

C A B

0.65 TYP

BALL A1 CORNER

9 10 11

12 13 14 15

0.65 TYP

4223365/A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

ABL0161B

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

10 11

12 13 14 15

(0.65) TYP

PKG

LAND PATTERN EXAMPLE

SCALE:10X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

( 0.32)

METAL

(

0.32)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223365/A 10/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

Mechanical, Packaging, and Orderable Information

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EXAMPLE STENCIL DESIGN

ABL0161B

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

10 11

12 13 14 15

(0.65) TYP

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4223365/A 10/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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PACKAGE OPTION ADDENDUM

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9-Dec-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

IWR1843ABGABL

ACTIVE

FCCSP

ABL

161

176

TBD

Call TI

-40 to 105

IWR1843

502A

502AD ABL

IWR1843AQGABL

IWR1843AQGABLR

ACTIVE

ABL

176

RoHS & Green

SNAGCU

Level-3-260C-168 HR

-40 to 105

IWR1843

(502A, 502AD)

(502AD ABL, 502A

D ABL)

FCCSP

161

1000 RoHS & Green

Level-3-260C-168 HR

IWR1843

(502A, 502AD)

(502AD ABL, 502A

D ABL)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

9-Dec-2021

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

IWR1843AQGABLR [TI]

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