JFE2140DR [TI]
双路、超低噪声、低栅极电流、音频、N 沟道 JFET | D | 8 | -40 to 125;
| 型号： | JFE2140DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、超低噪声、低栅极电流、音频、N 沟道 JFET | D | 8 | -40 to 125 栅 栅极 |
| 文件： | 总30页 (文件大小：1744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JFE2140
ZHCSLE0A –AUGUST 2021 –REVISED MARCH 2022
JFE2140 超低噪声、匹配低栅电流双离散音频N 通道JFET
mA。当偏置电流为 5 mA 时，该器件会产生 0.9 nV/√
Hz 的输入参考噪声，从而以极高的输入阻抗 (>1TΩ)
提供超低噪声性能。此外，可按照 ±4 mV 测试 JFET
之间的匹配性，确保差分对配置具有低失调电压和高
CMRR 性能。JFE2140 还具有连接到独立钳位节点的
集成二极管，无需添加高泄漏、非线性外部二极管即可
提供保护。
1 特性
• 超低噪声：
– 电压噪声：
• 1 kHz 时为0.9 nV/√Hz，IDS = 5 mA
• 1 kHz 时为1.1 nV/√Hz，IDS = 2mA
– 电流噪声：1 kHz 时为1.6 fA/√Hz
• 低VGS 失配：4 mV（最大值）
• 低栅极电流：10 pA（最大值）
• 低输入电容：VDS = 5V 时为13 pF
• 高栅漏电压和栅源击穿电压：-40 V
• 高跨导：30 mS
JFE2140 可承受 40V 的高漏源电压，以及低至 –40V
的栅源电压和栅漏电压。该器件额定工作温度范围为
–40°C 至+125°C。
器件信息
封装(1)
WSON (8) - 预发布
SOIC (8)
封装尺寸（标称值）
2.00mm × 2.00mm
4.90mm × 3.90mm
器件型号
JFE2140
• 封装：SOIC，2mm × 2mm WSON（预发布）
2 应用
• 麦克风输入
• 水听器和船用设备
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• DJ 控制器、混频器和其他DJ 设备
• 专业音频混合器或控制平面
• 吉他放大器和其他乐器放大器
• 状态监控传感器
器件概述
参数
值
VGSS
VDSS
CISS
-40 V
栅源电压
漏源电压
输入电容
±40 V
13 pF
±4 mV
3 说明
V
GS1 –VGS2
差分栅源电压匹配
JFE2140 是使用德州仪器 (TI) 现代高性能模拟双极工
艺构建的 Burr-Brown™ 匹配对分立式 JFET 。
JFE2140 具有以前较旧的分立式 JFET 技术所不具备
的性能。JFE2140 在所有电流范围内均提供出色的噪
声性能，静态电流可由用户设置，范围为50 μA 至20
–40°C
至
+125°C
TJ
结温
IDSS
18 mA
漏源饱和电流
D1
D2
VCH
CLAMPING
DIODES
G1
G2
S1
VCL
S2
简化版原理图
超低输入电压噪声
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS730
JFE2140
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ZHCSLE0A –AUGUST 2021 –REVISED MARCH 2022
Table of Contents
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Applications.................................................. 18
10 Power Supply Recommendations..............................21
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 Documentation Support.......................................... 23
12.3 接收文档更新通知................................................... 23
12.4 支持资源..................................................................23
12.5 Trademarks.............................................................23
12.6 Electrostatic Discharge Caution..............................23
12.7 术语表..................................................................... 23
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................7
7 Parameter Measurement Information.......................... 11
7.1 AC Measurement Configurations..............................11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
Information.................................................................... 23
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (August 2021) to Revision A (March 2022)
Page
• Changed ESD JEDEC specification to JS-002 ..................................................................................................4
• Changed gate-to-source voltages from –1.2 V to –1.3 V (100 µA), –0.9 V to –1.1 V (2 mA) .....................6
• Changed Y-axis range from 0 to 33 to 0 to 16 on Figure 6-1, Drain-to-Source Current vs Gate-to-Source
Voltage ...............................................................................................................................................................7
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5 Pin Configuration and Functions
S1
D1
1
2
3
4
8
7
6
5
G2
VCL
D2
VCH
G1
S2
Not to scale
图5-1. D (8-Pin SOIC) Package, Top View
S1
D1
1
2
3
4
8
7
6
5
G2
VCL
D2
Thermal Pad
VCH
G1
S2
Not to scale
图5-2. DSG (8-Pin WSON, Preview) Package, Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
D1
2
Output
Output
Drain, channel 1
Drain, channel 2
D2
6
G1
4
8
1
5
3
7
Input
Input
Output
Output
—
Gate, channel 1
Gate, channel 2
Source, channel 1
Source, channel 2
G2
S1
S2
VCH
VCL
Positive diode clamp voltage. Float this pin if clamp diodes are not used.
Negative diode clamp voltage. Float this pin if clamp diodes are not used.
—
Exposed thermal pad. This pad is internally connected to the VCL node. Connect this pad to
the same node as VCL or leave floating.
Thermal Pad
Thermal Pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–40
–40
MAX
UNIT
VDS
Drain-to-source voltage
40
0.1
40
V
V
V
VGS, VGD
VVCH
Gate-to-source voltage, gate-to-drain voltage
Voltage between VCH to D, G, or S
Voltage between VCL to D, G, or S
VVCL
–40
DC
50-ms pulse(3)
20
200
50
IVCL, IVCH
Clamp diode current
mA
IDS
Drain-to-source current
mA
mA
°C
–50
–20
–55
–55
–55
IGS, IGD
TA
Gate-to-source current, gate-to-drain current
Ambient temperature
20
150
150
175
TJ
Junction temperature
°C
Tstg
Storage temperature
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All gate, drain and source voltages are referred to the same-channel JFET (that is, VGS applies to both VG1S1 and VG2S2).
(3) Maximum diode current pulse specified for 50 ms at 1% duty cycle.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.02
NOM
MAX
IDSS
0
UNIT
IDS
VGS
TJ
Drain-to-source current
Gate-to-source voltage
Specified temperature
mA
V
–1.2
–40
125
°C
6.4 Thermal Information
JFE2140
D (SOIC)
8 PINS
139.8
80.0
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
83.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.1
82.4
ψJB
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JFE2140
THERMAL METRIC(1)
D (SOIC)
8 PINS
N/A
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, IDS = 2 mA, VDS = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
f = 1 kHz
2.5
5.4
nV/√Hz
µVPP
IDS = 100 µA
IDS = 2 mA
f = 10 Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
0.26
1.1
en
Input-referred noise
nV/√Hz
f = 10 Hz
2.4
f = 0.1 Hz to 10 Hz
0.12
1.6
µVPP
ei
Input current noise, each input
f = 1 kHz, IDS = 2 mA, VDS = 5 V
fA/√Hz
INPUT CURRENT
1
±10
±60
VDS = 2 V, VVCH = 5 V, VVCL = –5 V
pA
nA
0.2
IG
Input gate current
VDS = 0 V,
0.85
TA = –40°C to +85°C
VGS = –30 V
TA = –40°C to
9
+125°C
INPUT VOLTAGE
VGSS
VGSC
Gate-to-source breakdown voltage
V
V
VDS = 0 V, IG = –100 µA
VDS = 10 V, IDS = 0.1 µA
IDS = 100 µA
−40
−0.9
−0.7
−0.5
4
Gate-to-source cutoff voltage
−1.5
−1.3
−1.1
−1.15
−0.85
−0.6
1
VGS
Gate-to-source voltage
V
IDS = 2 mA
Differential VGS mismatch
IDS = 2 mA
mV
ΔVGS
TA = –40°C to
+125°C
1.1
1.7
4.2
TA = –40°C to
+125°C
Differential VGS mismatch drift
±10 µV/°C
INPUT IMPEDANCE
RIN
Gate input resistance
1
17
13
VGS = –30 V to –1 V, VDS = 0 V
VDS = 0 V
TΩ
CISS
Input capacitance
pF
VDS = 5 V
OUTPUT
12
10
18
23
IDSS
Drain-to-source saturation current VGS = 0 V
Drain-to-source saturation current
mA
28
TA = –40°C to
+125°C
VGS = 0 V, IDSS1 / IDSS2
0.95
1
1.05
ratio
IDS = 100 µA
IDS = 2 mA
2.1
10
30
43
4.5
Transconductance
mS
GFS
Full conduction transconductance VGS = 0 V
Drain-to-source breakdown voltage IDS = 100 µA
24
40
mS
V
VDSS
COSS
Output capacitance
IDS = 2 mA
pF
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6.6 Typical Characteristics
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 10 V (unless otherwise noted)
图6-1. Drain-to-Source Current vs Gate-to-Source Voltage
图6-2. Drain-to-Source Current vs Drain-to-Source Voltage
图6-3. Drain-to-Source Current vs Drain-to-Source Voltage
图6-4. Common Source Transconductance vs Drain‑to‑Source
Current
图6-5. Common Source Transconductance vs Drain‑to‑Source
图6-6. Gate Current vs Drain-to-Source Voltage
Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 10 V (unless otherwise noted)
VDS = 5 V
图6-8. Gate-to-Source Voltage vs Temperature
图6-7. Gate Current vs Gate-to-Source Voltage
IDS = 2 mA
VGS(Ch.1) –VGS(Ch.2)
图6-9. IDSS vs Drain-to-Source Voltage
图6-10. VGS Mismatch Histogram
VDS = 5 V
5 Units
IDS = 2 mA
5 Units
VGS(Ch.1) –VGS(Ch.2)
VGS(Ch.1) –VGS(Ch.2)
图6-11. VGS Mismatch vs Drain-to-Source Current
图6-12. VGS Mismatch vs Temperature
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6.6 Typical Characteristics (continued)
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 10 V (unless otherwise noted)
VGS(Ch.1) –VGS(Ch.2)
图6-14. Input-Referred Noise Density vs Frequency
图6-13. VGS Mismatch vs VDS
f = 1 kHz
f = 1 kHz
图6-16. Input-Referred Noise Spectral Density
vs Drain‑to‑Source Current
图6-15. Noise Density Contributors vs Input Gate Resistance
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6.6 Typical Characteristics (continued)
at TA = 25°C, IDS = 2 mA, common-source configuration, and VDS = 10 V (unless otherwise noted)
图6-17. Input, Output, and Reverse Transfer Capacitance vs Drain-to-Source Voltage
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7 Parameter Measurement Information
7.1 AC Measurement Configurations
The circuit configuration used for noise measurements is seen in 图7-1. The nominal IDS current is configured in
the schematic by calibrating V–. After IDS is fixed, the VDS voltage is set by calibrating V+. For input-referred
noise data, the gain of the circuit is calibrated from VIN to VOUT and used for the input-referred gain calculation.
V+
100 ꢀ
10 kꢀ
RD
10 kꢀ
49.9 ꢀ
œ
VOUT
+
JFE2140
OPA210
1 ꢁF
RG
0 ꢀ
100 kꢀ
+
VIN
RS
œ
3 mF
10 kꢀ
Vœ
图7-1. AC Measurement Reference Schematic
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8 Detailed Description
8.1 Overview
The JFE2140 is a ultra-low noise, matched-input pair N-type JFET designed to create low-noise gain stages for
very high output impedance sensors or microphones. Advanced, high precision processing technology gives the
JFE2140 tight channel-to-channel matching, extremely low-noise performance, a high gm/CISS ratio, and ultra-
low gate-current performance. The integrated Input-protection diodes clamp high-voltage spurious input signals
without the need for additional input diodes that can add leakage current or distortion-creating nonlinear
capacitance. The JFE2140 provides a next-generation device to implement low-noise amplifiers for piezoelectric
sensors, transducers, large-area condenser microphones, and hydrophones in small-package options.
8.2 Functional Block Diagram
D1
D2
VCH
G1
G2
S1
VCL
S2
8.3 Feature Description
8.3.1 Precision Matching
The JFE2140 features matched-pair, n-type JFET transistors fabricated on a high-precision analog process.
Precision matching between opposite JFETs is required in differential-pair configurations, where any mismatch
between input devices results in gain and common-mode rejection degradation. Precision matching also
minimizes offset voltages that produce excessive error voltages in high-gain, dc-coupled composite amplifiers.
Matching distribution for a production lot of units can be seen in 图6-10.
8.3.2 Ultra-Low Noise
Junction field effect transistors (JFETs) are commonly used as an input stage in high-input-impedance, low-noise
designs in audio, SONAR, vibration analysis, and other technologies. The JFE2140 is a new generation JFET
device that offers very low noise performance at the lowest possible current consumption in high-input-
impedance amplifier designs. The JFE2140 is manufactured on a high-performance analog process technology,
giving tighter process parameter control than a standard JFET.
Designs that feature operational amplifiers (op amps) as the primary gain stage are common, but these designs
are not able to achieve the lowest possible noise as a result of the inherent challenges and tradeoffs required
from a full operational amplifier design. Noise in JFET designs can be evaluated in two separate regions: low-
frequency flicker noise and wideband thermal noise. Flicker, or 1/f noise, is extremely important for systems that
require signal gain at frequencies less that 100 Hz. The JFE2140 achieves extremely low 1/f noise in this range.
Thermal noise is noise in the region greater than 1 kHz and depends on the gain, or gm, of the circuit. The gm is
a function of the drain-to-source bias current; therefore, thermal noise is also a function of drain-to-source bias
current. 图6-14 shows both 1/f and thermal noise with multiple bias conditions measured using the circuit shown
in 图7-1.
Noise is typically modeled as a voltage source (voltage noise) and current source (current noise) on the input.
The 1/f and thermal noise can be represented as voltage noise. Current noise is dominated by current flow into
the gate, and is called shot noise. The JFE2140 features extremely low gate current, and therefore, extremely
low current noise. 图 6-15 shows how source impedance on the input is the dominant noise source. In nearly all
cases, noise created as a result of current noise is negligible.
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8.3.3 Low Gate Current
The JFE2140 features a maximum gate current of 10 pA at room temperature, making the device an excellent
choice for maximizing the gain and dynamic range from extremely high impedance sensors. Additionally, any
noise contributions as a result of gate current are minimized because of the negligible shot noise at low current
levels. As with all JFET devices, when the drain-to-source voltage increases, the gate current also increases.
Keep the drain-to-source voltage to less than 5 V for the lowest gate input current operation.
8.3.4 Input Protection
The JFE2140 features input protection diodes that are used for surge clamping and ESD events. The diodes are
rated to withstand high current surges for short times, steering current from the gate (G) pin to the VCH and VCL
pins. The diodes also feature very low leakage, removing the need for external protection devices that may have
high leakage currents or nonlinear capacitance that degrade the distortion performance.
8.4 Device Functional Modes
The JFE2140 functionality is identical to standard N-channel depletion JFET devices. The gate-to-source (VGS
voltage, drain-to-source voltage (VDS) and drain-to-source current (IDS) determine the region of operation.
)
• For VGS < VGSC: JFE2140 conduction channel is closed; IDS is only determined by junction leakage current.
• For VGS > VGSC: Two modes of operation can exist depending on VDS. When VDS is less than the linear
(saturation) region threshold (see 图8-1), the device operates in the linear region, meaning that the device
behaves as a resistor connected from drain-to-source with minimal variation from any changes in VGS. When
VDS is greater than the linear (saturation) region threshold, IDS has a strong dependance on VGS, where the
relationship is described by the parameter gm.
Linear Region
Saturation Region
图8-1. VDS vs IDS
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Input Protection Diodes
The JFE2140 features diodes that are used to help clamp voltage surges that can occur on the input sensor to
the gate. The diodes are connected between the gates, sources, and drains of each JFET to two separate pins,
VCL and VCH. The clamping mechanism works by steering current from the gate into the VCL or VCH nodes
when the voltage at the gate, source or drain is less than VCL or greater than VCH. 图 9-1 shows an example of
a microphone input circuit where a dc blocking capacitor operates with a large dc voltage. When the microphone
input is dropped or shorted, the dc blocking capacitor discharges into the VCL or VCH nodes, thus helping
eliminate large signal transient voltages on the gate. There are also clamping diodes from the drain and source
to VCL and VCH, respectively. The clamping diodes can withstand high surge currents up to 200 mA for 50 ms;
however, limit dc current to less than 20 mA.
48 V
VCH
Dx
6.8 kΩ
CDC
10 …F
RG
Gx
1/2
JFE2140
iG
RB
VCL
Sx
RL
图9-1. JFE2140 Clamping Diode Example
The example in 图 9-1 shows the diode clamp used to protect the JFET against overvoltage in a phantom-
powered microphone circuit. Phantom power typically delivers 48 V through a 6.8-kΩ pullup resistor to a
microphone or dynamic load. If the microphone is disconnected, dc blocking capacitor CDC can be biased up to
48 V. If the input to the capacitor is then shorted to ground (shown by the switch in 图 9-1), the gate voltage can
exceed the absolute maximum rating for VGS. In this case, the blocking diode is used, along with current limiting
resistors RG and RL, to clamp the gate voltage to a safe level. Be aware that the thermal noise of RG couples
directly into the gate input; therefore, make sure to minimize the resistance of RG.
The clamping diodes are not required for operation. The VGS voltage can withstand –40 V, so clamping is not
required if the VGS voltage is kept greater than this limit. If the diodes are not needed, leave the VCL and VCH
nodes floating.
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9.1.2 Cascode Configuration
The JFE2140 can be configured as a cascoded JFET front end. Cascode refers to using a second transistor in-
series with the input transistor; see 图9-2 for an example.
VDD
RD
VOUT
VBIAS
JFE2140
VIN
RS
图9-2. JFE2140 connected in Cascode Configuration
Using a cascode configuration, as shown in 图 9-2, increases the output impedance of the stage, resulting in
higher gain, as well as buffers the input node from gate current that flows when the VDS voltages are higher. The
VBIAS node must be forced to a voltage greater than what is required to allow both JFETs to remain in the
saturated region. A JFET is not required to be used as the cascode device; the benefits of cascoding can be
realized with other transistor types, while still maintaining the low-noise, high-impedance benefits of the
JFE2140.
9.1.3 Common-Source Amplifier
The common-source amplifier is a commonly used open-loop gain stage for JFET amplifiers, the basic circuit is
shown in 图9-3.
V+
RD
1/2
VOUT
JFE2140
RG
+
VIN
RS
œ
图9-3. Common-Source Amplifier
The equation for gain of the circuit in 图9-3 is shown in 方程式1.
V
gm*R
D
1 + gm*R
OUT
= −
(1)
V
IN
S
Generally, higher gain results in improved noise performance. Gain increases as the bias current is increased as
a result of increasing gm (see 图 6-4). As a result, the input-referred noise decreases as bias current is
increased (see 图 6-14). Any JFET design must make a tradeoff between current consumption and noise
performance. The JFE2140, however, delivers significantly lower noise performance than most operational
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amplifiers at the same current consumption. The bias current (IDS) is set by the value of the source resistor, RS,
and the threshold voltage, VT, of the JFE2140. A graph showing nominal IDS vs RS is shown in 图9-4.
图9-4. Drain-to-Source Current vs RS, VDS = 5 V
The bias current varies according to the resistor and threshold voltage tolerances. Additionally, thermal noise
associated with RS couples directly into the gain of the circuit, degrading the overall noise performance. To
improve the circuit in 图 9-5, use a current-source biasing scheme. Current-source biasing removes the JFET
threshold variation from the biasing scheme, and allows for lower-value filtering capacitance (CS) for equivalent
filtering due to the high output impedance of current sources.
V+
RD
1/2
VOUT
JFE2140
RG
+
CS
VIN
œ
IBIAS
Vœ
图9-5. Common-Source Amplifier With Current-Source Biasing
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9.1.4 Composite Amplifiers
The JFE2140 can be configured to provide a low-noise, high-input impedance front-end stage for a typical op
amp. Open-loop transistor gain stages shown previously suffer from wide gain variations that are dependent on
the forward transcondutance of the JFE2140. When precision gain is required, the composite amplifier (JFET
front-end + operational amplifier) achieves excellent results by allowing for a fixed gain determined by external
resistors, and improving the noise and bandwidth of the operational amplifier. The JFE2140 gain stage provides
a boost to the open-loop performance of the system, extending the bandwidth beyond what the operational
amplifier alone can provide, and gives a high-input impedance, ultra-low noise input stage to interface with high
source impedance microphones.
图 9-6 shows a generic schematic representation of a voltage-feedback composite amplifier. The component
requirements and tradeoffs are listed in 表9-1.
VDD
VDD
RD
RD
œ
OPA
VOUT
+
RG
JFE2140
RS1 RS1
+
VIN
RF2
œ
RS2
CS2
图9-6. Low Noise, High Input Impedance Composite Amplifier
The gain of 图9-6 can be calculated using the equation below.
R
R
F1
F2
A = 1 +
(2)
表9-1. Composite Amplifier Component List and Function
COMPONENT
DESCRIPTION
Degeneration resistors. These resistors reduce the overall gain of the JFET stage, however, improve the
linearity performance. Also, when used in differential configurations (see OPA1637 reference design) they
will reduce CMRR errors that occur as a result of input mismatch voltages.
RS1
Bias-current setting resistor. This resistor, along with RS1, determine the bias current when using resistive
biasing (see 图9-4). Note both RS1 and RS2 resistance will directly impact noise performance.
RS2
RG
RD
Gate resistor. Can be used to help limit current flow into gate in overvoltage cases. For improved DC
precision, match RG to the equivalent parallel resistance of RS1 || RS2. Use the low resistance values to
minimize the thermal noise impact on the circuit.
Drain resistor. Sets gain of JFET stage in common source biasing, along with gm and RS1 + RS2. Higher
resistance will increase gain, however will lower the nominal VDS voltage.
RF1
RF2
RS2
CS
Feedback resistor 1. Along with RF2, sets the gain of the composite amplifier.
Feedback resistor 2. Along with RF1, sets the gain of the composite amplifier.
Source resistor 2. Along with RS1, sets the DC bias current where the JFET is nominally operated.
Source capacitor. Reduces the noise coupling from RS2
.
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9.2 Typical Applications
9.2.1 Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
The JFE2140 can be configured to provide a low-noise, high-input impedance single-ended amplifier stage that
can be optimized for ultra-low noise performance at low power levels. This configuration is designed for battery-
powered audio applications such as guitar pedals, amplifiers and handheld recorders. The OPA1692, a low-
power, dual audio amplifier, is used for the composite voltage-feedback amplifier, as well as a rail-splitting
amplifier that centers the ground voltage between the battery positive and negative voltage.
4.5 V
4.5 V
RD2
2.49 kꢀ
RD1
2.49 kꢀ
VOUT
OPA1692
œ
+
BASS
GAIN
BOOST
RG
10 ꢀ
VIN
JFE2140
RF3
10 kꢀ
RF2
499
RF1
10 kꢀ
49.9 ꢀ 49.9 ꢀ
RB
1 Mꢀ
RS2
100 ꢀ
CF1
10 nF
RS1
499 ꢀ
CB
100 nF
CF3
100 pF
GROUND
DRIVER
4.5 V
4.5 V
œ
OPA1692
9 V
+
100 ꢀ
œ4.5 V
œ4.5 V
All R = 10 kꢀ unless otherwise noted
All C = 0.1 ꢁF
图9-7. Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
9.2.1.1 Design Requirements
PARAMETER
DESIGN GOAL
15 dB to 40 dB nominal with
low‑frequency boost
Gain
Frequency response
Noise
1 Hz to 20 kHz
< 3 nV/√Hz at 1 kHz
< 4 mA
Total current consumption
Input current
< 100 pA
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9.2.1.2 Detailed Design Procedure
This design provides single-ended, adjustable gain from 15 dB to 40 dB with extremely high input impedance at
a very low frequency response. The power consumption is optimized for battery-powered audio applications.
• The JFE2140 is configured as a differential pair in a voltage-feedback composite amplifier. This configuration
allows for low-frequency gain without large dc-blocking capacitors.
• The bias current is set by selecting the desired bias current and noise tradeoff (see 图6-16). To set the bias
current point, adjust the source resistance according to 图9-4 .
• After the bias current is selected, set the JFET stage gain as high as possible. To avoid pushing the device
into the linear region of operation, use the largest drain resistor (RD1,2) possible while maintaining a minimum
of 1 V across the drain-to-source nodes.
• The overall gain can be configured with the feedback resistors RF1, RF2 and RF3. Capacitor CF3 may be
required depending on the gain configuration for amplifier stability; use amplifier stability best practices to
maintain stability at both maximum and minimum gain configurations.
9.2.1.3 Application Curves
图9-8. Gain/Phase
图9-9. Input-Referred Noise Density
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9.2.2 Differential Front-End Design
Differential pair architectures are useful for differential small signal amplification where high common-mode
voltage rejection (CMRR) is required. In typical differential amplifiers or fully-differential amplifiers (FDA), the
tolerance of the resistors alone dominates the CMRR performance. In addition, these amplifiers cannot be
configured with high input impedance because of the requirement of input resistors. When used on the front-end
of an FDA, the precision-matching on the JFE2140 removes the requirement of extremely low resistor matching
(< 1%) by creating a matched-input gain stage. In addition, high input impedance significantly reduces the
effects of source impedance mismatch on CMRR performance, creating a differential input designed for noisy
environments that are common in professional audio.
RF1
2 kꢀ
CF1
1 nF
RI1
2 kꢀ
CA1
47 pF
RO1
20 ꢀ
RA1
100 ꢀ
+5 V
+5 V
RD2
1.5 kꢀ
+5 V
RD1
1.5 kꢀ
œ
+
CA2
1 nF
OPA
1637
VOCM
ADC
œ
+
PD
RG1
10 ꢀ
RG2
10 ꢀ
RI2
2 kꢀ
5 V
œ5 V
JFE2140
RO2
20 ꢀ
RA2
100 ꢀ
CA3
47 pF
CF2
1 nF
XLR
Cable
+5 V
RS1
10 kꢀ
OPA197
RF2
2 kꢀ
+
RS2
20 ꢀ
œ
RS3
10 ꢀ
œ5 V
œ5 V
图9-10. The JFE2140 as a High Input Impedance Front End for the OPA1637
9.2.2.1 Application Curves
1-mV mismatch between JFETs
图9-11. Gain and Phase vs Frequency
图9-12. CMRR vs Frequency
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10 Power Supply Recommendations
The JFE2140 is a dual, matched JFET transistor pair with clamping diodes. There are no specific power-supply
connections; however, take care not to exceed any absolute maximum voltages on any of the pins if system
supply voltages greater than or equal to 40 V are used.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
• Reduce parasitic coupling by running the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Keep high impedance input signals away from noisy traces.
• Make sure supply voltages are adequately filtered.
• Minimize distance between source-connected and drain-connected components to the JFE2140.
• Consider a driven, low-impedance guard ring around the critical gate traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
S1
VINœ
VDD
VSS
G2
VCL
D2
VDD
VSS
D1
VDD
VCH
G1
VIN+
S2
图11-1. JFE2140 Layout Example: Differential Pair Configuration
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
12.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully functional version of the TINA software, preloaded with a library of macro
models, in addition to a range of both passive and active models. TINA-TI software provides all the conventional
dc, transient, and frequency domain analyses of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the
ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-
start tool.
备注
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
12.1.1.3 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at http://
www.ti.com/ww/en/analog/precision-designs/.
12.1.1.4 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
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12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx202 Precision, Low-Noise, Heavy Capacitive Drive, 36-V Operational Amplifiers
data sheet
• Texas Instruments, OPAx210 2.2-nV/√Hz Precision, Low-Power, 36-V Operational Amplifiers data sheet
• Texas Instruments, OPA1692 Low-Power, Low-Noise and Low-Distortion SoundPlus™ Audio Operational
Amplifiers data sheet
• Texas Instruments, OPAx197 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage Operational
Amplifiers data sheet
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
Burr-Brown™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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8-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
JFE2140DR
ACTIVE
SOIC
D
8
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
JF2140
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
JFE2140DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
JFE2140DR
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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