JL411BPA_技术文档

October 2005

LF411JAN

Low Offset, Low Drift JFET Input Operational Amplifier

General Description

Features

n Internally trimmed offset voltage:

n Input offset voltage drift:

n Low input bias current:

n Low input noise current:

n Wide gain bandwidth:

n High slew rate:

0.5 mV(Typ)

30 µV/˚C

50 pA

This device is a low cost, high speed, JFET input operational

amplifier with very low input offset voltage and guaranteed

input offset voltage drift. It requires low supply current yet

maintains a large gain bandwidth product and fast slew rate.

In addition, well matched high voltage JFET input devices

provide very low input bias and offset currents. The LF411 is

pin compatible with the standard LM741 allowing designers

to immediately upgrade the overall performance of existing

designs.

√

0.01 pA/ Hz

3 MHz Typ.

7V/µs (min.)

1.8 mA

n Low supply current:

n High input impedance:

n Low total harmonic distortion: A_V= 10, R_L= 10KΩ,

V_O= 20V_P-P, BW = 20Hz - 20KHz

n Low 1/f noise corner:

n Fast settling time to 0.01%:

10¹²

Ω

This amplifier may be used in applications such as high

speed integrators, fast D/A converters, sample and hold

circuits and many other circuits requiring low input offset

voltage and drift, low input bias current, high input imped-

ance, high slew rate and wide bandwidth.

<

0.02%

50 Hz

1.5 µs

Ordering Information

NS Part Number

JAN Part Number

NS Package Number

Package Description

JL411BPA

JM38510/11904BPA

J08A

8LD CERDIP

Connection Diagram

Typical Connection

8LD Ceramic Dual-in Line Package

20152407

Top View

See NS Package Number J08A

20152401

™

BI-FET II is a trademark of National Semiconductor Corporation.

DS201524

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Simplified Schematic

20152406

Detailed Schematic

20152434

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2

Absolute Maximum Ratings (Note 1)

Supply Voltage

18V

30V

Differential Input Voltage

Input Voltage Range (Note 4)

Output Short Circuit Duration

Power Dissipation (Note 2), (Note 3)

T_Jmax

15V

Continuous

400mW

175˚C

Thermal Resistance

θ_JA

Still Air

162˚C/W

65˚C/W

400LF/Min Air Flow

θ_JC

20˚C/W

Operating Temperature Range

Storage Temperature Range

Lead Temperature (Soldering, 10 seconds)

Package Weight (Typical)

ESD Tolerance (Note 5)

−55˚C ≤ T_A≤ 125˚C

−65˚C ≤ T_A≤ 150˚C

300˚C

TBD

750V

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup

Description

Static tests at

Temp ˚C

25

1

2

Static tests at

125

-55

25

3

Static tests at

4

Dynamic tests at

Functional tests at

Switching tests at

Settling time at

5

125

-55

25

6

7

8A

8B

9

125

-55

25

10

11

12

13

14

125

-55

25

125

-55

3

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Electrical Characteristics

DC Parameters

The following conditions apply to all the following parameters, unless otherwise specified.

DC: V_CC

=

15V, V_CM= 0V

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max

Unit

V_IO

Input Offset Voltage

+V_CC= 26V, -V_CC= -4V,

V_CM= -11V

-5.0

-7.0

-5.0

-7.0

-5.0

-7.0

-5.0

-7.0

-0.4

-10

5.0

7.0

5.0

7.0

5.0

7.0

5.0

7.0

0.2

50

mV

nA

1

2, 3

+V_CC= 4V, -V_CC= -26V,

V_CM= 11V

1

2, 3

1

2, 3

V_CC

=

5V

1

2, 3

I_IB

Input Bias Current

+V_CC= 26V, -V_CC= -4V,

1

V_CM= -11V, t ≤ 25mS

nA

2

t ≤ 25mS

-0.2

-10

0.2

50

nA

1

nA

2

+V_CC= 4V, -V_CC= -26V,

-0.2

-10

1.2

70

nA

1

V_CM= 11V, t ≤ 25mS

nA

2

I_IO

Input Offset Current

t ≤ 25mS

-0.1

-20

0.1

20

nA

1

2

nA

+PSRR

-PSRR

CMR

Power Supply Rejection Ratio

+V_CC= 10V to 20V,

-V_CC= -15V

80

dB

1, 2, 3

+V_CC= 15V,

80

dB

1, 2, 3

-V_CC= -10V to -20V

V_CM= -11V to +11V

Input Voltage Common Mode

Rejection

V_{IO Adj}

+

-

Adjustment for Input Offset

Voltage

8.0

mV

Adjustment for Input Offset

Voltage

-8.0

I_OS

I_CC

+

Output Short Circuit Current

Supply Current

t ≤ 25mS

-80

mA

µV/˚C

V

1, 2, 3

1, 2

3

-

80

3.5

4.0

30

∆V_IO/ ∆T

+V_OP

-V_OP

Input Offset Voltage

25˚C ≤ T_A≤ +125˚C

-55˚C ≤ T_A≤ 25˚C

R_L= 10KΩ

(Note 6)

-30

12

2

30

3

Output Voltage Swing

Open Loop Voltage Gain

4, 5, 6

4

R_L= 2KΩ

10

V

R_L= 10KΩ

-12

-10

V

R_L= 2KΩ

V

+A_VS

-A_VS

R_L= 2KΩ,

V_O= 0 to 10V

(Note 7)

50

25

50

25

20

K

5, 6

4

R_L= 2KΩ,

V_O= 0 to -10V

K

5, 6

4, 5, 6

A_VS

R_L= 10KΩ, V_O

V_CC5V

=

2V,

K

=

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4

Electrical Characteristics (Continued)

AC Parameters

The following conditions apply to all the following parameters, unless otherwise specified.

AC: V_CC

=

15V, V_CM= 0V

Parameter

Sub-

groups

7

Symbol

Conditions

V_I= -5V to +5V

Notes

Min Max

Unit

SR+

Slew Rate

7.0

5.0

7.0

5.0

200

V/µS

nS

8A, 8B

7

SR-

V_I= +5V to -5V

8A, 8B

7, 8A, 8B

TR_TR

TR_OS

Transient Response Rise Time A_V= 1, V_I= 50mV,

C_L= 100pF, R_L= 2KΩ

Transient Response Overshoot A_V= 1, V_I= 50mV,

C_L= 100pF, R_L= 2KΩ

40

%

7, 8A, 8B

NI_BB

NI_PC

Noise Broadband

Noise Popcorn

BW of 10Hz to 15KHz

BW of 10Hz to 15KHz,

R_S= 100KΩ

15

80

µV_RMS

µV_PK

7

+tS

-tS

Settling Time

A_V= 1

1,500

nS

12

A_V= 1

DC Drift Parameters

The following conditions apply to all the following parameters, unless otherwise specified.

DC: V_CC15V, V_CM= 0V

Delta Calculations performed at Group B, subgroup 5, Only

=

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max

Unit

V_IO

I_IB

Input Offset Voltage

Input Bias Current

-1.0

-0.1

1.0

0.1

mV

nA

1

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

(maximum junction temperature), θ (package junction

JA

Jmax

to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is P

= (T

- T )/θ or the

A

Dmax

Jmax A JA

number given in the Absolute Maximum Ratings, whichever is lower.

Note 3: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside

guaranteed limits.

Note 4: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.

Note 5: Human body model, 100pF discharged through 1.5KΩ.

Note 6: Calculated parameter. For calculation use V test at

V

=

CC

15V

IO

Note 7: Datalog in K = V/mV.

5

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Typical Performance Characteristics

Input Bias Current

20152411

20152412

Positive Common-Mode

Input Voltage Limit

Supply Current

20152413

20152414

Negative Common-Mode

Input Voltage Limit

Positive Current Limit

20152415

20152416

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6

Typical Performance Characteristics (Continued)

Negative Current Limit

Output Voltage Swing

Gain Bandwidth

Slew Rate

20152417

20152418

Output Voltage Swing

20152419

20152420

Bode Plot

20152422

20152421

7

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Typical Performance Characteristics (Continued)

Undistorted Output

Voltage Swing

Distortion vs Frequency

20152423

20152424

Open Loop Frequency

Response

Common-Mode Rejection

Ratio

20152425

20152426

Power Supply

Rejection Ratio

Equivalent Input Noise

Voltage

20152427

20152428

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8

Typical Performance Characteristics (Continued)

Open Loop Voltage Gain

Output Impedance

20152429

20152430

Inverter Settling Time

20152431

Pulse Response R_L=2 kΩ, C_L10 pF

Small Signal Non-Inverting

Small Signal Inverting

20152440

20152439

9

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Pulse Response R_L=2 kΩ, C_L10

Large Signal Non-Inverting

pF (Continued)

Large Signal Inverting

20152442

20152441

Current Limit (R_L=100Ω)

20152443

The LF411 is biased by a zener reference which allows

normal circuit operation on 4.5V power supplies. Supply

voltages less than these may result in lower gain bandwidth

and slew rate.

Application Hints

The LF411JAN series of internally trimmed JFET input op

™

amps ( BI-FET II ) provide very low input offset voltage and

guaranteed input offset voltage drift. These JFETs have

large reverse breakdown voltages from gate to source and

drain eliminating the need for clamps across the inputs.

Therefore, large differential input voltages can easily be

accommodated without a large increase in input current. The

maximum differential input voltage is independent of the

supply voltages. However, neither of the input voltages

should be allowed to exceed the negative supply as this will

cause large currents to flow which can result in a destroyed

unit.

The LF411 will drive a 2 kΩ load resistance to 10V over the

full temperature range. If the amplifier is forced to drive

heavier load currents, however, an increase in input offset

voltage may occur on the negative voltage swing and finally

reach an active current limit on both positive and negative

swings.

Precautions should be taken to ensure that the power supply

for the integrated circuit never becomes reversed in polarity

or that the unit is not inadvertently installed backwards in a

socket as an unlimited current surge through the resulting

forward diode within the IC could cause fusing of the internal

conductors and result in a destroyed unit.

Exceeding the negative common-mode limit on either input

will force the output to a high state, potentially causing a

reversal of phase to the output. Exceeding the negative

common-mode limit on both inputs will force the amplifier

output to a high state. In neither case does a latch occur

since raising the input back within the common-mode range

again puts the input stage and thus the amplifier in a normal

operating mode.

As with most amplifiers, care should be taken with lead

dress, component placement and supply decoupling in order

to ensure stability. For example, resistors from the output to

an input should be placed with the body close to the input to

minimize “pick-up” and maximize the frequency of the feed-

back pole by minimizing the capacitance from the input to

ground.

Exceeding the positive common-mode limit on a single input

will not change the phase of the output; however, if both

inputs exceed the limit, the output of the amplifier may be

forced to a high state.

A feedback pole is created when the feedback around any

amplifier is resistive. The parallel resistance and capacitance

from the input of the device (usually the inverting input) to AC

ground set the frequency of the pole. In many instances the

frequency of this pole is much greater than the expected

3 dB frequency of the closed loop gain and consequently

there is negligible effect on stability margin. However, if the

feedback pole is less than approximately 6 times the ex-

The amplifier will operate with a common-mode input voltage

equal to the positive supply; however, the gain bandwidth

and slew rate may be decreased in this condition. When the

negative common-mode voltage swings to within 3V of the

negative supply, an increase in input offset voltage may

occur.

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10

added capacitor should be such that the RC time constant of

this capacitor and the resistance it parallels is greater than or

equal to the original feedback pole time constant.

Application Hints (Continued)

pected 3 dB frequency, a lead capacitor should be placed

from the output to the input of the op amp. The value of the

Typical Applications

High Speed Current Booster

20152409

PNP=2N2905

NPN=2N2219 unless noted

TO-5 heat sinks for Q6-Q7

11

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Typical Applications (Continued)

10-Bit Linear DAC with No V_OSAdjust

20152432

where A =1 if the A digital input is high

N

A =0 if the A digital input is low

N N

Single Supply Analog Switch with Buffered Output

20152433

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12

Revision History

Date

Revision

Section

Originator

Changes

Released

10/11/05

A

New Release to corporate format

L. Lytle

1 MDS data sheet was converted into the

corporate data sheet format. MDS

MJLF411-X Rev 0C1 will be archived.

13

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Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Dual-in-Line Package (J)

NS Package Number J08A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

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型号：	JL411BPA
厂家：	TEXAS INSTRUMENTS
描述：	LF411JAN Low Offset, Low Drift JFET Input Operational Amplifier LF411JAN低失调，低漂移JFET输入运算放大器运算放大器
文件：	总16页 (文件大小：874K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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