JM38510/31202BFAW [TI]
ADDER/SUBTRACTOR;
| 型号： | JM38510/31202BFAW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ADDER/SUBTRACTOR 逻辑集成电路 |
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LMP91050
www.ti.com
SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
LMP91050 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications
Check for Samples: LMP91050
1
FEATURES
DESCRIPTION
The LMP91050 is a programmable integrated Sensor
Analog Front End (AFE) optimized for thermopile
sensors, as typically used in NDIR applications. It
provides a complete signal path solution between a
sensor and microcontroller that generates an output
voltage proportional to the thermopile voltage. The
LMP91050's programmability enables it to support
multiple thermopile sensors with a single design as
opposed to the multiple discrete solutions.
2
•
Programmable Gain Amplifier
“Dark Signal” Offset Cancellation
Supports External Filtering
•
•
•
Common Mode Generator and 8 bit DAC
APPLICATIONS
•
•
•
•
•
•
•
NDIR Sensing
Demand Control Ventilation
Building Monitoring
The LMP91050 features
a programmable gain
amplifier (PGA), “dark phase” offset cancellation, and
an adjustable common mode generator (1.15V or
2.59V) which increases output dynamic range. The
PGA offers a low gain range of 167V/V to 1335V/V
plus a high gain range of 1002V/V to 7986V/V which
enables the user to utilize thermopiles with different
sensitivities. The PGA is highlighted by low gain drift
(100 ppm/°C), output offset drift (1.2mV/°C at G =
1002 V/V), phase delay drift (500ns) and noise
specifications (0.1 μVRMS 0.1 to 10Hz) . The offset
cancellation circuitry compensates for the “dark
signal” by adding an equal and opposite offset to the
input of the second stage, thus removing the original
offset from the output signal. This offset cancellation
circuitry allows optimized usage of the ADC full scale
and relaxes ADC resolution requirements.
CO2 Cabin Control — Automotive
Alcohol Detection — Automotive
Industrial Safety and Security
GHG & Freons Detection Platforms
KEY SPECIFICATIONS
•
•
•
•
•
Programmable gain 167 to 7986 V/V
Low noise (0.1 to 10 Hz) 0.1 μVRMS
Gain Drift 100 ppm/°C (max)
Phase Delay Drift 500 ns (max)
Power supply voltage range 2.7 to 5.5 V
The LMP91050 allows extra signal filtering (high
pass, low pass or band pass) through dedicated pins
A0 and A1, in order to remove out of band noise. The
user can program through the on board SPI interface.
Available in a small form factor 10–pin package, the
LMP91050 operates from -40 to +105°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMP91050
SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
www.ti.com
Block Diagram
CMOUT
A1
VDD
A0
LMP91050
G2=4,8,16,32
G1=250,42
IN
OUT
PGA2
PGA1
SPI
DAC
CMOUT
SPI
CM GEN
VREF
GND
CSB SCLK SDIO
Figure 1. Configurable AFE for NDIR
Typical Application
10 µF
160 kꢀ
VDD
160 kꢀ
6.8 nF
CMOUT
A1
10 µF
10 nF
VDD
A0
OUT
Thermopile
IN
1 kO
ꢁû ADC
10 nF
1 µF
LMP91050
CSB
CMOUT
SCLK
SDIO
10 nF
GND
Figure 2. Typical NDIR Sensing Application Circuit
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SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
Connection Diagram
IN
CMOUT
A0
VDD
SDIO
SCLK
CSB
LMP91050
A1
GND
OUT
Pin Descriptions
Type
Pin
1
Symbol
IN
Description
Analog Input
Analog Output
Analog Output
Analog Input
Power
Signal Input
2
CMOUT
A0
Common Mode Voltage Output
First Stage Output
Second Stage Input
Ground
3
4
A1
5
GND
Signal Output, reference to the same potential as
CMOUT
6
OUT
Analog Output
7
8
CSB
SCLK
SDIO
VDD
Digital Input
Digital Input
Chip Select, active low
Interface Clock
9
Digital Input / Output
Power
Serial Data Input / Output
Positive Supply
10
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
ESD Tolerance(3)
Human Body Model
Machine Model
2500V
250V
Charged Device Model
1250V
Supply Voltage (VDD)
Voltage at Any Pin
–0.3V to 6.0V
– 0.3V to VDD + 0.3V
5mA
Input Current at Any Pin
Storage Temperature Range
Junction Temperature(4)
For soldering specifications:
-65°C to 150°C
150°C
see product folder at www.ti.com and http://www.ti.com/lit/SNOA549.
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
Copyright © 2011–2013, Texas Instruments Incorporated
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SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
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(1)
Operating Ratings
Supply Voltage
2.7V to 5.5V
-40°C to 105°C
176 °C/W
Junction Temperature Range
(2)
Package Thermal Resitance, θJA
10 Lead VSSOP
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
Electrical Characteristics(1)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Power Supply
VDD
IDD
Supply Voltage
Supply Current
Power Down Supply Current
2.7
3.3
5.5
4.2
121
V
All analog block ON
3.1
45
3.7
85
mA
μA
All analog block OFF
Offset Cancellation (Offset DAC)
Resolution
LSB
256
steps
mV
All gains
33.8
DNL
-1
2
LSB
mV
Error
Output referred offset error, all gains
Output referred, all gains
±100
480
VDD –
0.2
Offset adjust Range
DAC settling time
0.2
V
μs
Programmable Gain Amplifier (PGA) 1st Stage, RL = 10kΩ, CL = 15pF
IBIAS
Bias Current
5
200
pA
VINMAX
_HGM
Max input signal High gain
mode
Referenced to CMOUT voltage, it refers to the
maximum voltage at the IN pin before clipping; It
includes dark voltage of the thermopile and
signal voltage.
±2
mV
VINMAX
_LGM
Max input signal Low gain
mode
±12
mV
VOS
Input Offset Voltage
Gain High gain mode
Gain Low gain mode
Gain Error
-165
250
42
µV
V/V
V/V
%
G _HGM
G_LGM
GE
Both HGM and LGM
2.5
VDD –
0.5
VOUT
PhDly
Output Voltage Range
Phase Delay
0.5
V
1mV input step signal, HGM, Vout measured at
Vdd/2
6
μs
Phase Delay variation with
Temperature
1mV input step signal, HGM, Vout measured at
Vdd/2,
TCPhDly
416
ns
SSBW
Cin
Small Signal Bandwidth
Input Capacitance
Vin = 1mVpp, Gain = 250 V/V
18
kHz
pF
100
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
Electrical Characteristics(1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Programmable Gain Amplifier (PGA) 2nd Stage, RS = 1kΩ, CL = 1µF
VINMAX
VINMIN
G
Max input signal
Min input signal
Gain
GAIN = 4 V/V
1.65
V
V
0.82
Programmable in 4 steps
Any gain
4
32
V/V
%
GE
Gain Error
2.5
VDD –
0.2
VOUT
Output Voltage Range
Phase Delay
0.2
V
100mV input sine 35kHz signal, Gain = 8, VOUT
measured at 1.65V, RL = 10kΩ
PhDly
1
µs
ns
Phase Delay variation with
Temperature
250mV input step signal, Gain = 8, Vout
measured at Vdd/2
TCPhDly
84
SSBW
Cin
Small Signal Bandwidth
Input Capacitance
Gain = 32 V/V
360
5
kHz
pF
CLOAD,
OUT
OUT Pin Load Capacitance
OUT Pin Load Resistance
Series RC
Series RC
1
1
µF
RLOAD,
OUT
kΩ
Combined Amplifier Chain Specification
Combination of both current and voltage noise,
with a 86kΩ source impedance at 5Hz, Gain =
7986
en Input-Referred Noise Density
30
nV/√Hz
Combination of both current and voltage noise,
Input-Referred Integrated Noise with a 86kΩ source impedance 0.1Hz to 10Hz,
0.12
0.1
µVrms
(4)
Gain = 7986
PGA1 GAIN = 42, PGA2 GAIN = 4
PGA1 GAIN = 42, PGA2 GAIN = 8
PGA1 GAIN = 42, PGA2 GAIN = 16
167
335
669
PGA1 GAIN = 42, PGA2 GAIN = 32
1335
1002
2004
4003
7986
5
G
Gain
V/V
PGA1 GAIN = 250, PGA2 GAIN = 4
PGA1 GAIN = 250, PGA2 GAIN = 8
PGA1 GAIN = 250, PGA2 GAIN = 16
PGA1 GAIN = 250, PGA2 GAIN = 32
GE
Gain Error
Any gain
%
ppm/°C
dB
(5)
TCCGE
PSRR
Gain Temp Coefficient
100
500
Power Supply Rejection Ratio
DC, 3.0V to 3.6V supply, gain = 1002V/V
90
110
9
1mV input step signal, Gain = 1002, Vout
measured at Vdd/2
PhDly
Phase Delay
µs
ns
Phase Delay variation with
Temperature
1mV input step signal, Gain=1002, Vout
measured at Vdd/2
TCPhDly
(6)
(4) Specified by design and characterization. Not tested on shipped production material.
(5) TCCGE and TCVOS are calculated by taking the largest slope between -40°C and 25°C linear interpolation and 25°C and 85°C linear
interpolation.
(6) TCPhDly is largest change in phase delay between -40°C and 25°C measurements and 25°C and 85°C measurements.
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Electrical Characteristics(1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
(2)
(3)
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Gain = 167 V/V
Gain = 335 V/V
Gain = 669 V/V
Gain = 1335 V/V
Gain = 1002 V/V
Gain = 2004 V/V
Gain = 4003 V/V
Gain = 7986V/V
–0.525
–0.60
–0.90
–1.50
–1.20
–1.90
–3.70
–7.10
0.525
0.60
0.90
1.50
1.20
1.90
3.70
7.10
Output Offset Voltage
Temperature Drift
TCVOS
mV/°C
(5)
Common Mode Generator
1.15 or
2.59
VCM
Common Mode Voltage
V
Programmable, see Common Mode Generation
VCM accuracy
2
%
CLOAD
CMOut Load Capacitance
10
nF
SPI Interface(1)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
Min
Typ
Max
Symbol
VIH
Parameter
Logic Input High
Conditions
Units
(2)
(3)
(2)
0.7
× VDD
V
V
VIL
Logic Input Low
Logic Output High
Logic Output Low
0.8
0.4
VOH
VOL
2.6
V
V
–100
–200
100
200
IIH/IIL
Input Digital Leakage Current
nA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(1)
Timing Characteristics
The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
Min
Typ
Max
Symbol
Parameter
Conditions
Units
(2)
(3)
(2)
tWU
fSCLK
Wake up time
Serial Clock Frequency
1
ms
10
MHz
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
6
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SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
Timing Characteristics (1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
Min
Typ
Max
Symbol
Parameter
Conditions
Units
(2)
(3)
(2)
tPH
SCLK Pulse Width High
SCLK Pulse Width Low
CSB Setup Time
0.4/fSCLK
0.4/fSCLK
10
ns
ns
ns
ns
tPL
tCSS
tCSH
CSB Hold Time
10
SDI Setup Time prior to rise
edge of SCLK
tSU
10
10
ns
ns
ns
ns
ns
ns
ns
SDI Hold Time prior to rise
edge of SCLK
tSH
SDO Disable Time after rise
edge of CSB
SDO Disable Time after 16th
rise edge of SCLK
tDOD1
tDOD2
tDOE
tDOA
tDOH
45
45
35
35
SDO Enable Time from the fall
edge of 8th SCLK
SDO Access Time after the fall
edge of SCLK
SDO hold time after the fall
edge of SCLK
5
tDOR
tDOF
SDO Rise time
SDO Fall time
5
5
ns
ns
Timing Diagrams
Figure 3. SPI Timing Diagram
t
t
PL
PH
16th clock
SCLK
t
t
H
SU
SDI
Valid Data
Valid Data
Figure 4. SPI Set-up Hold Time
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Figure 5. SDO disable time after 16th rise edge of SCLK
Figure 6. SDO access time (tDOA) and SDO hold time (tDOH) after the fall edge of SCLK
Figure 7. SDO Enable time from the fall edge of 8th SCLK
Figure 8. SDO disable time after rise edge of CSB
Figure 9. SDO rise and fall times
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SNAS517D –NOVEMBER 2011–REVISED MARCH 2013
Typical Performance Characteristics
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Gain = 167 V/V vs. Temperature
Gain = 335 V/V vs. Temperature
168.4
168.3
168.2
168.1
168.0
167.9
167.8
336.0
335.9
335.8
335.7
335.6
335.5
335.4
-50 -25
0
25
50
75 100
-50 -25
0
25
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10.
Figure 11.
Gain = 669 V/V vs. Temperature
Gain = 1002 V/V vs. Temperature
672.5
672.4
672.3
672.2
672.1
672.0
671.9
671.8
671.7
1011
1010
1009
1008
-50 -25
0
25
50
75 100
-50 -25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12.
Figure 13.
Gain = 2004 V/V vs. Temperature
Phase Delay vs. Temperature
2014
2013
2012
2011
2010
2009
2008
9.3
9.2
9.1
9.0
8.9
8.8
8.7
8.6
-50 -25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Output Offset vs. Temperature
Common Mode Voltage vs. Temperature
1.160
100
90
80
70
60
50
40
1.158
1.156
1.154
1.152
1.150
30
G = 1002 V/V
20
10
0
-50
-25
0
25
50
75
100
-50 -25
0
25
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16.
Figure 17.
Input Bias Current vs. Temperature
Supply Current vs. Temperature
0
-1
-2
-3
-4
-5
5
4
3
2
1
0
G = 1002 V/V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18.
Figure 19.
Supply Current vs. Supply Voltage
Power Down Supply Current vs. Supply Voltage
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
120
110
100
90
80
PGA ALL ON
PGA2 ON
PGA1 ON
70
60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
VDD (V)
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Output Offset vs. Supply Voltage
PGA1 Small Signal Bandwidth
70
60
50
40
30
20
10
0
G = 250 V/V
G = 42 V/V
G = 1002 V/V
65
60
55
50
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1k
10k
100k
1M
VDD (V)
FREQUENCY (Hz)
Figure 22.
PGA2 Small Signal Bandwidth
Figure 23.
Power Supply Rejection Ratio vs. Frequency
40
120
G = 32 V/V
G = 7986 V/V
G = 16 V/V
G = 8 V/V
G = 4 V/V
G = 4003 V/V
G = 2004 V/V
G = 1002 V/V
110
100
90
30
20
10
0
80
70
60
10k
100k
1M
10M
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24.
Figure 25.
Input-Referred Noise Density vs. Frequency
DAC DC Sweep
140
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
G = 1002 V/V
120
100
80
60
40
20
0
G = 2004 V/V
G = 4003 V/V
G = 7986 V/V
VDD = 3.3V
100m
1
10
100
1k
10k
0
50
100 150 200 250 300
DAC CODE
FREQUENCY (Hz)
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
DAC DC Sweep
5.50
4.75
4.00
3.25
2.50
1.75
1.00
0.25
-0.50
G = 1002 V/V
G = 2004 V/V
G = 4003 V/V
G = 7986 V/V
VDD = 5V
0
50
100 150 200 250 300
DAC CODE
Figure 28.
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FUNCTIONAL DESCRIPTION
PROGRAMMABLE GAIN AMPLIFIER
The LMP91050 offers two programmable gain modes (low/high) with four programmable gain settings each. The
purpose of the gain mode is to enable thermopiles with larger dark voltage levels. All gain settings are accessible
through bits GAIN1 and GAIN2[1:0]. The low gain mode has a range of 167 V/V to 1335 V/V while the high gain
mode has a range of 1002 V/V to 7986 V/V. The PGA is referenced to the internally generated VCM. Input
signal, referenced to this VCM voltage, should be within +/-2mV (see VINMAX_HGM specification) in high gain
mode. In the low gain mode the first stage will provide a gain of 42 V/V instead of 250 V/V, thus allowing a larger
maximum input signal up to +/-12mV (VINMAX_LGM).
Table 1. Gain Modes
Bit Symbol
Gain
0: 250 (default)
1: 42
GAIN1
00: 4 (default)
01: 8
GAIN2 [1:0]
10: 16
11: 32
EXTERNAL FILTER
The LMP91050 offers two different measurement modes selectable through EXT_FILT bit. EXT_FILT bit is
present in the Device configuration register and is programmable through SPI.
Table 2. Measurement Modes
Bit Symbol
Measurement Mode
EXT_FILT
0: The signal from the thermopile is being processed by the internal PGAs, without
additional external decoupling or filtering (default).
1: The signal from the thermopile is being processed by the first internal PGA and fed to the A0
pin. An external low pass, high pass or band pass filter can be connected through pins A0, A1.
An external filter can be applied when EXT_FILT = 1. A typical band pass filter is shown in the picture below.
Resistor and capacitor can be connected to the CMOUT pin of the LMP91050 as shown. Discrete component
values have been added for reference.
10 µF
160 kꢀ
A0
A1
160 kꢀ
6.8 nF
CMOUT
Figure 29. Typical Bandpass Filter
OFFSET ADJUST
Procedure of the offset adjust is to first measure the “dark signal”, program the DAC to adjust, and then measure
in a second cycle the residual of the dark signal for further signal manipulation within the µC. The signal source
is expected to have an offset component (dark signal) larger than the actual signal. During the “dark phase”, the
time when no light is detected by the sensor, the µC can program LMP91050 internal DAC to compensate for a
measured offset. A low output offset voltage temperature drift (TCVOS) ensures system accuracy over
temperature. See Figure 30 below which plots the maximum TCVOS allowed over a given temperature drift in
order to achieve n bit system accuracy.
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100
12 bit Accuracy
11 bit Accuracy
10 bit Accuracy
9 bit Accuracy
8 bit Accuracy
10
1
100m
10m
1
2
3
4
5
6
7
8
9
10
TEMPERATURE DRIFT (°C)
Figure 30. System Accuracy vs. TCVOS and Temperature Drift
COMMON MODE GENERATION
As the sensor's offset is bipolar, there is a need to supply a VCM to the sensor. This can be programmed as
1.15V or 2.59V (approximately mid rail of 3.3V or 5V supply). It is not recommended to use 2.59V VCM with 3.3V
supply
SPI INTERFACE
An SPI interface is available in order to program the device parameters like PGA gain of two stages, enabling
external filter, enabling power for PGAs, offset adjust and common mode (VCM) voltage.
Interface Pins
The Serial Interface consists of SDIO (Serial Data Input / Output), SCLK (Serial Interface Clock) and CSB (Chip
Select Bar). The serial interface is write-only by default. Read operations are supported after unlocking the
SDIO_MODE_PASSWD. This is discussed in detail later in the document.
CSB
Chip Select is a active-low signal. CSB needs to be asserted throughout a transaction. That is, CSB should not
pulse between the Instruction Byte and the Data Byte of a single transaction.
Note that CSB de-assertion always terminates an on-going transaction, if it is not already complete. Likewise,
CSB assertion will always bring the device into a state, ready for next transaction, regardless of the termination
status of a previous transaction.
CSB may be permanently tied low for a 2-wire SPI communication protocol.
SCLK
SCLK can idle High or Low for a write transaction. However, for a READ transaction, SCLK should idle high.
SCLK features a Schmitt-triggered input and although it has hysterisis, it is recommened to keep SCLK as clean
as possible to prevent glitches from inadvertently spoiling the SPI frame.
Communication Protocol
Communication on the SPI normally involves Write and Read transactions. Write transaction consists of single
Write Command Byte, followed by single Data byte. The following figure shows the SPI Interface Protocol for
write transaction.
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CSB
11
14
1
2
3
4
5
6
7
8
9
10
12
13
15
16
SCK
COMMAND FIELD
DATA FIELD
MSB
LSB
c0
d6
d0
c7
c6
c5
c4
c3
c2
c1
d7
d5
d4
d3
d2
d1
Reserved to 0
Address (4 bits)
Wb=0
Write Data (8-bits)
Figure 31. SPI Interface Protocol
For Read transactions, user first needs to write into a SDIO mode enable register for enabling the SPI read
mode. Once the device is enabled for Reading, the data is driven out on the SDIO pin during the Data field of the
Read Transaction. SDIO pin is designed as a bidirectional pin for this purpose. Figure 32 shows the Read
transaction. The sequence of commands that need to be issued by the SPI Master to enable SPI read mode is
illustrated in Figure 33.
Figure 32. Read Transaction
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Sequence of transactions for unlocking SDIO_MODE
CSB
SDI
Write data
(0xFE first
byte of
sdio_mode
_en reg)
Write cmd
(sdio_mode
_en reg)
Write cmd
(sdio_mod
e_en reg)
Read cmd (to
read contents of
any register
specified by the
address bits)
Write
data
(0xED)
SDO
Read data
Bus turnaround time = half cycle
Note:
1. Once the SDIO_mode is unlocked. The user can read as many registers as long as nothing
else is written to sdio_mode_en register to disturb the state of SDIO_mode
2. The separate signals SDI and SDO are given in the figure for the sake of understanding.
However, only one signal SDIO exists in the design
Figure 33. Enable SDIO Mode for reading SPI registers
Registers Organization
Configuring the device is achieved using ‘Write’ of the designated registers in the device. All the registers are
organized into individually addressable byte-long registers that have a unique address. The format of the Write/
Read instruction is as shown below.
Table 3. Write / Read Instruction Format
Bit[7]
0 : Write Instruction
1 : Read Instruction
Bit[6:4]
Bit[3:0]
Reserved to 0
Address
REGISTERS
This section describes the programmable registers and the associated programming sequence, if any, for the
device. The following table shows the summary listing of all the registers that are available to the user and their
power-up values.
Power-up/Reset
Value (Hex)
Title
Address (Hex)
Type
Read-Write
(Read allowed in SDIO Mode)
Read-Write
Device Configuration
0x0
0x0
DAC Configuration
SDIO Mode Enable
0x1
0xF
0x80
0x0
(Read allowed in SDIO Mode)
Write-only
Device Configuration – Device Configuration Register (Address 0x0)
Bit
Bit Symbol
Description
7
RESERVED
Reserved to 0.
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Bit
Bit Symbol
Description
00: PGA1 OFF PGA2 OFF (default)
01: PGA1 OFF, PGA2 ON
10: PGA1 ON, PGA2 OFF
11: PGA1 ON, PGA2 ON
0: PGA1 to PGA2 direct (default)
1: PGA1 to PGA2 via external filter
0 : 1.15V (default)
1 : 2.59V
[6:5]
EN
4
3
EXT_FILT
CMN_MODE
00: 4 (default)
01: 8
[2:1]
0
GAIN2
GAIN1
10: 16
11: 32
0: 250 (default)
1: 42
DAC Configuration – DAC Configuration Register (Address 0x1)
The output DC level will shift according to the formula Vout_shift = -33.8mV * (NDAC - 128).
Bit
Bit Symbol
Description
[7:0]
NDAC
128 (0x80): Vout_shift = -33.8mV * (128 - 128) = 0mV (default)
SDIO Mode – SDIO Mode Enable Register (Address 0xf)
Write-only
Bit
Bit Symbol
Description
To enter SDIO Mode, write the successive sequence 0xFE and 0xED.
Write anything other than this sequence to get out of mode.
[7:0]
SDIO_MODE_EN
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMP91050MM/NOPB
LMP91050MME/NOPB
LMP91050MMX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
VSSOP
VSSOP
VSSOP
DGS
10
10
10
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
AN8A
ACTIVE
ACTIVE
DGS
DGS
250
Green (RoHS
& no Sb/Br)
-40 to 105
AN8A
AN8A
3500
Green (RoHS
& no Sb/Br)
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP91050MM/NOPB
VSSOP
DGS
DGS
DGS
10
10
10
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
LMP91050MME/NOPB VSSOP
LMP91050MMX/NOPB VSSOP
3500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP91050MM/NOPB
LMP91050MME/NOPB
LMP91050MMX/NOPB
VSSOP
VSSOP
VSSOP
DGS
DGS
DGS
10
10
10
1000
250
210.0
210.0
367.0
185.0
185.0
367.0
35.0
35.0
35.0
3500
Pack Materials-Page 2
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