JM38510/32803B2A [TI]
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 八路总线收发器与3态输出
| 型号： | JM38510/32803B2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总15页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
SN54LS245 . . . J OR W PACKAGE
SN74LS245 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
3-State Outputs Drive Bus Lines Directly
PNP Inputs Reduce dc Loading on Bus
Lines
Hysteresis at Bus Inputs Improves Noise
Margins
DIR
A1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
A2
Typical Propagation Delay Times Port to
Port, 8 ns
A3
A4
A5
I
I
OL
OH
TYPE
(SINK
A6
(SOURCE
CURRENT)
CURRENT)
A7
SN54LS245
SN74LS245
12 mA
24 mA
–12 mA
–15 mA
A8
GND
SN54LS245 . . . FK PACKAGE
(TOP VIEW)
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
3
2
1
20 19
18
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
4
5
6
7
8
The devices allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE) input can disable the device so that the
buses are effectively isolated.
17
16
15
14
9 10 11 12 13
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74LS245N
SN74LS245N
Tube
SN74LS245DW
SN74LS245DWR
SN74LS245NSR
SN74LS245DBR
SN54LS245J
SOIC – DW
LS245
0°C to 70°C
Tape and reel
Tape and reel
Tape and reel
Tube
SOP – NS
74LS245
SSOP – DB
LS245
SN54LS245J
SNJ54LS245J
SNJ54LS245W
SN54LS245FK
CDIP – J
Tube
SNJ54LS245J
SNJ54LS245W
SN54LS245FK
–55°C to 125°C
CFP – W
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
50 Ω NOM
9 kΩ NOM
Input
Output
logic diagram (positive logic)
1
DIR
19
OE
2
A1
18
B1
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Package thermal impedance,
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
JA
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54LS245
MIN NOM
SN74LS245
MIN NOM
UNIT
MAX
5.5
MAX
5.25
–15
24
V
Supply voltage
4.5
5
4.75
5
V
CC
OH
OL
I
I
High-level output current
Low-level output current
Operating free-air temperature
–12
12
mA
mA
°C
T
A
–55
125
0
70
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS245
SN74LS245
†
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
High-level input voltage
Low-level input voltage
Input clamp voltage
2
2
V
V
V
V
IH
0.7
0.8
IL
V
V
= MIN,
= MIN
= MIN,
I = –18 mA
–1.5
–1.5
IK
CC
CC
CC
I
Hysteresis (V – V
T+
)
T–
A or B
0.2
2.4
0.4
3.4
0.2
2.4
0.4
3.4
V
V
V
I
I
I
I
= –3 mA
= MAX
OH
OH
OL
OL
V
V
High-level output voltage
Low-level output voltage
V
V
= 2 V,
= V
OH
IH
IL
2
2
IL(max)
V
V
V
= MIN,
= 12 mA
= 24 mA
0.4
0.4
0.5
CC
IH
IL
= 2 V,
= V
OL
IL(max)
Off-state output current,
high-level voltage applied
V
= MAX,
CC
I
I
V
= 2.7 V
= 0.4 V
20
20
µA
µA
OZH
O
O
OE at 2 V
Off-state output current,
low-level voltage applied
V
= MAX,
CC
OE at 2 V
V
–200
–200
OZL
Input current at
maximum input
voltage
A or B
DIR or OE
V = 5.5 V
I
0.1
0.1
0.1
0.1
I
I
V
CC
= MAX
mA
V = 7 V
I
I
I
I
High-level input current
Low-level input current
Short-circuit output current
V
V
V
= MAX,
= MAX,
= MAX
V
= 2.7 V
= 0.4 V
20
–0.2
–225
70
20
–0.2
–225
70
µA
mA
mA
IH
CC
CC
CC
IH
IL
V
IL
§
–40
40
OS
Total, outputs high
Total, outputs low
Outputs at high Z
48
62
64
48
62
64
I
Supply current
V
CC
= MAX
Outputs open
90
90
mA
CC
95
95
†
‡
§
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
CC
A
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
A
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Output enable time to low level
8
8
12
12
40
40
25
28
PLH
PHL
PZL
PZH
PLZ
PHZ
C
C
= 45 pF,
= 45 pF,
= 5 pF,
R
R
R
= 667
= 667
= 667
ns
L
L
L
L
L
27
25
15
15
ns
ns
Output enable time to high level
Output disable time from low level
C
L
Output disable time from high level
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
OL
t
t
PHZ
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
5962-8002101VRA
5962-8002101VSA
80021012A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
W
FK
W
FK
J
20
20
20
20
20
20
20
20
20
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
LCCC
CFP
8002101SA
JM38510/32803B2A
JM38510/32803BRA
JM38510/32803BSA
SN54LS245J
LCCC
CDIP
CFP
W
J
CDIP
SSOP
SN74LS245DBR
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS245DBRE4
SN74LS245DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
DB
DW
DW
DW
DW
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS245DWG4
SN74LS245DWR
SN74LS245DWRG4
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS245J
SN74LS245N
OBSOLETE
ACTIVE
CDIP
PDIP
J
20
20
TBD
Call TI
Call TI
N
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS245N3
SN74LS245NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS245NSR
SN74LS245NSRE4
SN74LS245NSRG4
ACTIVE
ACTIVE
ACTIVE
SO
SO
SO
NS
NS
NS
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54LS245FK
SNJ54LS245J
SNJ54LS245W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
JM38510/32901B2A
LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CQCC20, LCC-20
MOTOROLA
JM38510/32901BCA
LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, CERDIP-14
MOTOROLA
JM38510/32901BDA
Parity Generator/Checker, LS Series, 9-Bit, Complementary Output, TTL, CDFP14, CERAMIC, FP-14
MOTOROLA
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