JM38510/65308BEA [TI]
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR; 翻两番D型触发器与Clear
| 型号： | JM38510/65308BEA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| 文件： | 总16页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢂ
ꢉ ꢊꢋꢌꢍ ꢊꢎꢏ ꢐ ꢌꢑꢒ ꢓꢎ ꢐ ꢔ ꢏ ꢕꢎ ꢑ ꢔꢏꢖ ꢎ ꢀ
ꢗ ꢕꢒꢄ ꢅ ꢏꢐ ꢋꢍ
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Low Power Consumption, 80-µA Max I
Applications Include:
− Buffer/Storage Registers
− Shift Registers
CC
Contain Four Flip-Flops With Double-Rail
Outputs
− Pattern Generators
D
Typical t = 13 ns
pd
SN54HC175 . . . FK PACKAGE
(TOP VIEW)
SN54HC175 . . . J OR W PACKAGE
SN74HC175 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
V
CC
4Q
1
2
3
4
5
6
7
8
16
15
3
2
1
20 19
18
4Q
4D
NC
1Q
1D
NC
2D
2Q
4
5
6
7
8
14 4Q
13 4D
12 3D
11 3Q
17
16
15 3D
14
3Q
9 10 11 12 13
10
9
3Q
CLK
NC − No internal connection
description/ordering information
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature
complementary outputs from each flip-flop.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC175N
SN74HC175N
SN74HC175D
SN74HC175DR
SN74HC175DT
SN74HC175NSR
SN74HC175DBR
SN74HC175PW
SN74HC175PWR
SN74HC175PWT
SNJ54HC175J
SNJ54HC175W
SNJ54HC175FK
HC175
SOP − NS
HC175
HC175
−40°C to 85°C
SSOP − DB
TSSOP − PW
HC175
CDIP − J
CFP − W
LCCC − FK
SNJ54HC175J
SNJ54HC175W
SNJ54HC175FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢖ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢕ ꢏꢑ ꢎꢍ ꢔ ꢑꢯꢰꢂ ꢯꢂꢈ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
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ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢖ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢈ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢂ
ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢏ ꢐ ꢌꢑꢒ ꢓꢎ ꢐ ꢔꢏ ꢕ ꢎ ꢑꢔꢏ ꢖꢎ ꢀ
ꢗꢕ ꢒ ꢄ ꢅ ꢏ ꢐꢋ ꢍ
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
related directly to the transition time of the positive-going edge of CLK. When CLK is at either the high or low
level, the D input has no effect at the output.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR
L
CLK
X
D
X
H
L
Q
L
Q
H
L
H
↑
H
L
H
↑
H
H
L
X
Q
Q
0
0
logic diagram (positive logic)
1
CLR
9
4
CLK
1D
2
3
1D
C1
1Q
1Q
R
To Three Other Channels
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢂ
ꢉ ꢊꢋꢌꢍ ꢊꢎꢏ ꢐ ꢌꢑꢒ ꢓꢎ ꢐ ꢔ ꢏ ꢕꢎ ꢑ ꢔꢏꢖ ꢎ ꢀ
ꢗ ꢕꢒꢄ ꢅ ꢏꢐ ꢋꢍ
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC175
MIN NOM
SN74HC175
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC175
SN74HC175
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
OH
V
OL
V = V or V
IH
V
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
80
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢂ
ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢏ ꢐ ꢌꢑꢒ ꢓꢎ ꢐ ꢔꢏ ꢕ ꢎ ꢑꢔꢏ ꢖꢎ ꢀ
ꢗꢕ ꢒ ꢄ ꢅ ꢏ ꢐꢋ ꢍ
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC175
SN74HC175
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
Clock frequency
Pulse duration
MHz
clock
36
25
29
2 V
80
16
14
80
16
14
100
20
17
100
20
17
0
120
24
20
120
24
20
150
30
25
150
30
25
0
100
20
17
100
20
17
125
25
21
125
25
21
0
4.5 V
6 V
CLR low
t
w
ns
2 V
4.5 V
6 V
CLK high or low
Data
2 V
4.5 V
6 V
t
t
Setup time before CLK↑
ns
ns
su
2 V
4.5 V
6 V
CLR inactive
2 V
Hold time, data after CLK↑
4.5 V
6 V
0
0
0
h
0
0
0
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
12
SN54HC175
SN74HC175
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
31
36
50
25
29
f
t
t
MHz
max
pd
t
60
25
2 V
52
150
30
255
45
190
38
4.5 V
6 V
15
CLR
CLK
Any
Any
Any
13
26
38
32
ns
ns
2 V
58
150
30
255
45
190
38
4.5 V
6 V
16
13
26
38
32
2 V
38
75
110
22
90
4.5 V
6 V
8
15
19
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per flip-flop
No load
30
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢂ
ꢉ ꢊꢋꢌꢍ ꢊꢎꢏ ꢐ ꢌꢑꢒ ꢓꢎ ꢐ ꢔ ꢏ ꢕꢎ ꢑ ꢔꢏꢖ ꢎ ꢀ
ꢗ ꢕꢒꢄ ꢅ ꢏꢐ ꢋꢍ
SCLS299D − JANUARY 1996 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
84089012A
8408901EA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
16
16
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
8408901FA
W
J
JM38510/65308BEA
JM38510/65308BFA
SN54HC175J
CDIP
CFP
A42 SNPB
A42
W
J
CDIP
SOIC
A42 SNPB
SN74HC175D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC175DBR
SN74HC175DBRE4
SN74HC175DE4
SN74HC175DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DB
D
16
16
16
16
16
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC175DRE4
SN74HC175DT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC175DTE4
SN74HC175N
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC175NE4
SN74HC175NSR
SN74HC175NSRE4
SN74HC175PW
SN74HC175PWE4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC175PWLE
SN74HC175PWR
OBSOLETE TSSOP
PW
PW
16
16
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC175PWRE4
SN74HC175PWT
PW
PW
PW
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC175PWTE4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54HC175FK
SNJ54HC175J
SNJ54HC175W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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