JM54ACT74B2A [TI]
FF/Latch;
| 型号： | JM54ACT74B2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FF/Latch |
| 文件： | 总8页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2003
54AC74/54ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Clear and Set are independent of clock
General Description
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive-going pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be trans-
ferred to the outputs until the next rising edge of the Clock
Pulse input.
Features
n ICC reduced by 50%
n Output source/sink 24 mA
n ’ACT74 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC74: 5962-88520
— ’ACT74: 5962-87525
n 54AC74 now qualified to 300Krad RHA designation,
refer to the SMD for more information
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Logic Symbols
10026602
10026601
IEEE/IEC
Pin Names
Description
Data Inputs
D1, D2
CP1, CP2
D1, CD2
D1, SD2
Q1, Q1, Q2, Q2
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
C
S
10026603
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS100266
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Connection Diagrams
Pin Assignment for DIP
and Flatpak
Pin Assignment for LCC
10026604
10026605
Truth Table
(Each Half)
Inputs
Outputs
SD
L
CD
H
L
CP
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
X
H
H
L
L
X
H
H
L
N
H
H
H
H
H
H
N
H
L
X
Q0
Q0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Clock Transition
Q (Q ) = Previous Q(Q) before LOW-to-HIGH Transition of Clock
0
0
Logic Diagram
10026606
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
’ACT
4.5V to 5.5V
0V to VCC
0V to VCC
Input Voltage (VI)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Output Voltage (VO)
Operating Temperature (TA)
54AC/ACT
Supply Voltage (VCC
)
−0.5V to +7.0V
−55˚C to +125˚C
DC Input Diode Current (IIK
VI = −0.5V
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
−20 mA
+20 mA
VI = VCC + 0.5V
VIN from 30% to 70% of VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
125 mV/ns
DC Output Diode Current (IOK
VO = −0.5V
)
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
−20 mA
+20 mA
VO = VCC + 0.5V
VIN from 0.8V to 2.0V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
@
VCC 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
or Sink Current (IO)
DC VCC or Ground Current
50 mA
per Output Pin (ICC or IGND
)
50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
175˚C
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
DC Characteristics for ’AC Family Devices
54AC
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
2.1
VIH
Minimum High
Level Input
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
VOUT = 0.1V
3.15
3.85
0.9
V
V
V
or VCC − 0.1V
VIL
Maximum Low
Level Input
Voltage
VOUT = 0.1V
1.35
1.65
2.9
or VCC − 0.1V
VOH
Minimum High
Level Output
Voltage
IOUT = −50 µA
4.4
5.4
(Note 2)
VIN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
−12 mA
V
V
IOH
−24 mA
−24 mA
VOL
Maximum Low
Level Output
Voltage
IOUT = 50 µA
(Note 2)
VIN = VIL or VIH
3
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DC Characteristics for ’AC Family Devices (Continued)
54AC
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
0.5
3.0
4.5
5.5
5.5
12 mA
0.5
V
IOL
24 mA
24 mA
0.5
IIN
Maximum Input
Leakage Current
(Note 3) Minimum
Dynamic Output
Current
1.0
µA
VI = VCC, GND
IOLD
IOHD
ICC
5.5
5.5
5.5
50
mA
mA
µA
VOLD = 1.65V Max
VOHD = 3.85V Min
−50
40.0
Maximum Quiescent
Supply Current
VIN = VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4: I and I
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
.
CC
IN
CC
@ @
for 54AC 25˚C is identical to 74AC 25˚C.
I
CC
DC Characteristics for ’ACT Family Devices
54ACT
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
VIH
Minimum High
Level Input
Voltage
4.5
5.5
4.5
5.5
2.0
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
V
2.0
0.8
0.8
VIL
Maximum Low
Level Input
Voltage
V
V
VOH
Minimum High
Level Output
Voltage
4.5
5.5
4.4
5.4
(Note 5)
VIN = VIL or VIH
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
IOH
−24 mA
−24 mA
VOL
Maximum Low
Level Output
Voltage
IOUT = 50 µA
0.1
(Note 5)
VIN = VIL or VIH
4.5
5.5
5.5
0.50
0.50
1.0
V
IOL
24 mA
24 mA
IIN
Maximum Input
Leakage Current
Maximum
µA
mA
VI = VCC, GND
ICCT
5.5
1.6
VI = VCC − 2.1V
I
CC/Input
IOLD
IOHD
(Note 6) Minimum
Dynamic Output
Current
5.5
5.5
50
mA
mA
VOLD = 1.65V Max
VOHD = 3.85V Min
−50
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4
DC Characteristics for ’ACT Family Devices (Continued)
54ACT
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
ICC
Maximum Quiescent
Supply Current
5.5
40.0
µA
VIN = VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25˚C is identical to 74ACT 25˚C.
Note 7: I
CC
AC Electrical Characteristics
VCC
(V)
54AC
Symbol
Parameter
TA = −55˚C to +125˚C
CL = 50 pF
Units
Fig.
No.
(Note 8)
Min
70
Max
fmax
Maximum Clock
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
MHz
ns
Frequency
95
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
13.0
9.5
14.0
10.5
17.5
12.0
13.5
10.0
ns
ns
Propagation Delay
CPn to Qn or Qn
ns
Note 8: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
Symbol
Parameter
VCC
(V)
TA = −55˚C to +125˚C
Units
Fig.
No.
CL = 50 pF
(Note 9)
3.3
Guaranteed Limits
ts
Set-up Time, HIGH or LOW
Dn to CPn
5.0
4.0
0.5
0.5
8.0
5.5
0.5
0.5
ns
ns
ns
ns
5.0
th
tw
trec
Hold Time, HIGH or LOW
Dn to CPn
3.3
5.0
CPn or CDn or SDn
Pulse Width
3.3
5.0
Recovery Time
3.3
CDn or SDn to CP
5.0
Note 9: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
5
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AC Electrical Characteristics
54ACT
VCC
(V)
TA = −55˚C
to +125˚C
CL = 50 pF
Fig.
No.
Symbol
Parameter
Units
(Note 10)
Min
Max
fmax
Maximum Clock
5.0
5.0
5.0
5.0
5.0
85
MHz
ns
Frequency
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
1.0
1.0
1.0
1.0
11.5
12.5
14.0
12.0
ns
ns
Propagation Delay
CPn to Qn or Qn
ns
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
TA = −55˚C
CL = 50 pF
Guaranteed
Limits
Symbol
Parameter
VCC
Units
Fig.
No.
(V)
(Note 11)
ts
Set-up Time, HIGH or
LOW
5.0
5.0
4.0
ns
ns
Dn to CPn
th
Hold Time, HIGH or
LOW
1.0
Dn to CPn
tw
CPn or CDn or SDn
Pulse Width
5.0
5.0
7.0
0.5
ns
ns
trec
Recovery Time
CDn or SDn to CP
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
Units
pF
Conditions
VCC = OPEN
VCC = 5.0V
CIN
Input Capacitance
Power Dissipation
Capacitance
4.5
CPD
35.0
pF
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
14-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J14A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Ceramic Flatpak (F)
NS Package Number W14B
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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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