LF147JAN_V01 [TI]
LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier;
| 型号： | LF147JAN_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier |
| 文件： | 总18页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF147JAN
LF147JAN Wide Bandwidth Quad JFET Input Operational Amplifier
Literature Number: SNOSAJ9
April 2005
LF147JAN
Wide Bandwidth Quad JFET Input Operational Amplifier
General Description
Features
The LF147 is a low cost, high speed quad JFET input
operational amplifier with an internally trimmed input offset
j
j
j
j
j
j
j
j
Internally trimmed offset voltage:
Low input bias current:
Low input noise current:
Wide gain bandwidth:
5 mV max
50 pA Typ.
™
voltage (BI-FET II technology). The device requires a low
√
0.01 pA/ Hz Typ.
supply current and yet maintains a large gain bandwidth
product and a fast slew rate. In addition, well matched high
voltage JFET input devices provide very low input bias and
offset currents. The LF147 is pin compatible with the stan-
dard LM148. This feature allows designers to immediately
upgrade the overall performance of existing LF148 and
LM124 designs.
4 MHz Typ.
13 V/µs Typ.
7.2 mA Typ.
1012Ω Typ.
High slew rate:
Low supply current:
High input impedance:
Low total harmonic distortion:
AV = 10, RL = 10KΩ, VO = 20VP-P
BW = 20Hz — 20KHz
Low 1/f noise corner:
The LF147 may be used in applications such as high speed
integrators, fast D/A converters, sample-and-hold circuits
and many other circuits requiring low input offset voltage,
low input bias current, high input impedance, high slew rate
and wide bandwidth. The device has low noise and offset
voltage drift.
≤0.02% Typ.
50 Hz Typ.
2 µs Typ.
j
j
Fast settling time to 0.01%:
Ordering Information
NS Part Number
JAN Part Number
NS Package Number
Package Description
JL147BCA
JM38510/11906BCA
J14A
14LD CERDIP
Connection Diagram
Dual-In-Line Package
20129801
Top View
See NS Package Number J14A
™
BI-FET II is a trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201298
www.national.com
Simplified Schematic
1
⁄4
Quad
20129813
Detailed Schematic
20129809
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2
Absolute Maximum Ratings (Note 1)
Supply Voltage
18V
30V
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short Circuit Duration (Note 3)
Power Dissipation (Notes 4, 5)
TJ max
15V
Continuous
900 mW
150˚C
θJA CERDIP
70˚C/W
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
ESD (Note 6)
−55˚C ≤ TA ≤ 125˚C
−65˚C ≤ TA ≤ 150˚C
260˚C
900V
Recommended Operating Conditions
Supply Voltage Range
5V to 15V
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp (˚C)
1
2
Static tests at
Static tests at
25
125
-55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling Time at
5
125
-55
25
6
7
8A
8B
9
125
-55
25
10
11
12
125
-55
25
3
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LF147 JAN Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified: VCC
=
15V, VCM = 0V
Sub-
groups
Symbol
VIO
Parameter
Conditions
Notes
Min Max
Unit
Input Offset Voltage
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
-0.4
-10
5.0
7.0
5.0
7.0
5.0
7.0
5.0
7.0
0.2
50
mV
mV
mV
mV
mV
mV
mV
mV
nA
1
2, 3
1
+VCC = 26V, -VCC = -4V,
VCM = -11V
+VCC = 4V, -VCC = -26V,
VCM = 11V
2, 3
1
+VCC = 15V, -VCC = -15V,
VCM = 0V
2, 3
1
+VCC = 5V, -VCC = -5V,
VCM = 0V
2, 3
1
IIB
Input Bias Current
+VCC = 26V, -VCC = -4V,
VCM = -11V
nA
2
-0.2
-10
0.2
50
nA
1
+VCC = 15V, -VCC = -15V,
VCM = 0V
nA
2
-0.2
-10
1.2
70
nA
1
+VCC = 4V, -VCC = -26V,
VCM = 11V
nA
2
IIO
Input Offset Current
-0.1
-20
0.1
20
nA
1
+VCC = 15V, -VCC = -15V,
VCM = 0V
nA
2
+PSRR
-PSRR
CMRR
+IOS
Power Supply Rejection Ratio
Power Supply Rejection Ratio
-VCC = -15V,
80
80
dB
dB
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+VCC = 20V to 10V
+VCC = 15V,
-VCC = -20V to -10V
Input Voltage Common Mode
Rejection
VCC
=
4V to 26V,
80
dB
VCM = -11V to +11V
Output Short Circuit Current
+VCC = 15V, -VCC = -15V,
VCM = -10V, t ≤ 25mS
+VCC = 15V, -VCC = -15V,
VCM = 10V, t ≤ 25mS
-80
mA
mA
−IOS
Output Short Circuit Current
Supply Current
80
ICC
14
16
30
30
mA
mA
1, 2
3
+VCC = 15V, -VCC = -15V
Delta VIO
Delta T
/
Input Offset Voltage Temp.
Sensitivity
25˚C ≤ TA ≤ +125˚C
(Note 7)
(Note 7)
-30
-30
µV/˚C
µV/˚C
2
-55˚C ≤ TA ≤ 25˚C
3
+VOP
Output Voltage Swing
+VCC = 15V, -VCC = -15V,
RL=10KΩ, VCM = -15V
+VCC = 15V, -VCC = -15V,
RL=2KΩ, VCM = -15V
+VCC = 15V, -VCC = -15V,
RL=10KΩ, VCM = 15V
+VCC = 15V, -VCC = -15V,
RL = 2KΩ, VCM = 15V
12
10
V
V
V
V
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
-VOP
Output Voltage Swing
-12
-10
+AVS
−AVS
AVS
Open Loop Voltage Gain
Open Loop Voltage Gain
Open Loop Voltage Gain
50
25
50
25
V/mV
V/mV
V/mV
V/mV
4
+VCC = 15V, -VCC = -15V,
RL = 2KΩ, VO = 0 to 10V
5, 6
4
+VCC = 15V, -VCC = -15V,
RL = 2KΩ, VO = 0 to -10V
5, 6
+VCC = 5V, -VCC = -5V,
20
V/mV
4, 5, 6
RL = 10KΩ, VO
=
2V
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4
LF147 JAN Electrical Characteristics (Continued)
AC Parameters
The following conditions apply, unless otherwise specified: VCC
=
15V
Sub-
groups
7
Symbol
+SR
Parameter
Conditions
VI = -5V to +5V
VI = +5V to -5V
Notes
Min Max
Unit
Slew Rate
Slew Rate
7
5
7
5
V/µS
V/µS
V/µS
V/µS
8A, 8B
7
-SR
8A, 8B
TRTR
TROS
Transient Response Rise Time AV=1, VI=50mV, CL= 100pF,
200
nS
7, 8A, 8B
RL=2KΩ
Transient Response Overshoot AV=1, VI=50mV, CL= 100pF,
RL=2KΩ
40
15
80
%
7, 8A, 8B
NIBB
NIPC
Noise Broadband
Noise Popcorn
BW = 10Hz to 15KHz, RS = 0Ω
BW = 10Hz to 15KHz,
µVRMS
µVPK
7
7
RS = 100KΩ
CS
Channel Separation
RL = 2KΩ
80
80
80
80
80
80
80
80
80
80
80
80
80
1,500
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
nS
7
7
RL = 2KΩ, VI = 10V, A to B
RL = 2KΩ, VI = 10V, A to C
RL = 2KΩ, VI = 10V, A to D
RL = 2KΩ, VI = 10V, B to A
RL = 2KΩ, VI = 10V, B to C
RL = 2KΩ, VI = 10V, B to D
RL = 2KΩ, VI = 10V, C to A
RL = 2KΩ, VI = 10V, C to B
RL = 2KΩ, VI = 10V, C to D
RL = 2KΩ, VI = 10V, D to A
RL = 2KΩ, VI = 10V, D to B
RL = 2KΩ, VI = 10V, D to C
AV = 1
7
7
7
7
7
7
7
7
7
7
7
tS
Settling Time
12
Drift Values
The following conditions apply, unless otherwise specified: DC
JAN S and QMLV devices at group B, subgroup 5 only”
VCC
=
15V, VCM = 0V, “Delta calculations performed on
Sub-
Symbol
VIO
Parameters
Conditions
Notes
Min Max
Unit
mV
nA
groups
+VCC = 15V, -VCC = -15V,
VCM = 0V
Input Offset Voltage
Input Bias Current
-1.0
-0.1
1.0
0.1
1
1
+IIB
+VCC = 15V, -VCC = -15V,
VCM = 0V
-IIB
Input Bias Current
+VCC = 15V, -VCC = -15V,
VCM = 0V
-0.1
0.1
nA
1
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction
temperature will be exceeded.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature), θ (Package junction
JA
Jmax
to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is P
= (T
— T ) / θ or the
A
Dmax
Jmax A JA
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside
guaranteed limits.
Note 6: Human body model, 1.5 kΩ in series with 100 pF.
Note 7: Calculated parameters.
5
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Typical Performance Characteristics
Input Bias Current
Input Bias Current
20129814
20129815
Positive Common-Mode
Input Voltage Limit
Supply Current
20129816
20129817
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
20129819
20129818
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6
Typical Performance Characteristics (Continued)
Negative Current Limit
Output Voltage Swing
Gain Bandwidth
Slew Rate
20129820
20129821
Output Voltage Swing
20129823
20129822
Bode Plot
20129824
20129825
7
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Typical Performance Characteristics (Continued)
Undistorted Output Voltage
Swing
Distortion vs Frequency
20129826
20129827
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
20129829
20129828
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
20129830
20129831
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8
Typical Performance Characteristics (Continued)
Open Loop Voltage Gain
Output Impedance
20129833
20129832
Inverter Settling Time
20129834
9
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Pulse Response RL=2 kΩ, CL=10 pF
Large Signal Inverting
Small Signal Inverting
20129806
20129804
Large Signal Non-Inverting
Small Signal Non-Inverting
20129807
20129805
Current Limit (RL=100Ω)
20129808
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10
The LF147 will drive a 2 kΩ load resistance to 10V over the
full temperature range. If the amplifier is forced to drive
heavier load currents, however, an increase in input offset
voltage may occur on the negative voltage swing and finally
reach an active current limit on both positive and negative
swings.
Application Hints
The LF147 is an op amp with an internally trimmed input
offset voltage and JFET input devices (BI-FET II). These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs. Therefore, large differential input voltages can easily
be accommodated without a large increase in input current.
The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequently there
is negligible effect on stability margin. However, if the feed-
back pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the added
capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
The amplifiers will operate with a common-mode input volt-
age equal to the positive supply; however, the gain band-
width and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on 4.5V power sup-
plies. Supply voltages less than these may result in lower
gain bandwidth and slew rate.
11
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Typical Applications
Digitally Selectable Precision Attenuator
20129810
All resistors 1% tolerance
•
Accuracy of better than 0.4% with standard 1% value resistors
No offset adjustment necessary
Expandable to any number of stages
Very high input impedance
•
•
A1 A2 A3
VO
Attenuation
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
−7 dB
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12
Typical Applications (Continued)
Long Time Integrator with Reset, Hold and Starting Threshold Adjustment
20129811
•
VO starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage:
•
•
•
Output starts when VIN ≥ VTH
Switch S1 permits stopping and holding any output value
Switch S2 resets system to zero
13
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Typical Applications (Continued)
Universal State Variable Filter
20129812
For circuit shown:
f =3 kHz, f
O
=9.5 kHz
NOTCH
Q=3.4
Passband gain:
Highpass — 0.1
Bandpass — 1
Lowpass — 1
Notch — 10
• f xQ≤200 kHz
o
• 10V peak sinusoidal output swing without slew limiting to 200 kHz
• See LM148 data sheet for design equations
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14
Date
Revision
Section
Originator
Changes
Released
04/18/05
A
New Release into corporate format
L. Lytle
1 MDS datasheets converted into one Corp.
datasheet format. MJLF147–X rev 1B1 MDS
will be archived
15
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Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
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the right at any time without notice to change said circuitry and specifications.
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