LF156 MD8 [TI]
Single, 40-V, 5-MHz, -55 to 125°C, FET-input operational amplifier | Y | 0 | -55 to 125;
| 型号： | LF156 MD8 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single, 40-V, 5-MHz, -55 to 125°C, FET-input operational amplifier | Y | 0 | -55 to 125 |
| 文件： | 总24页 (文件大小：1099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
National Semiconductor is now part of
Texas Instruments.
Search http://www.ti.com/ for the latest technical
information and details on our current products and services.
December 2001
LF155/LF156/LF256/LF257/LF355/LF356/LF357
JFET Input Operational Amplifiers
n Logarithmic amplifiers
n Photocell amplifiers
These are the first monolithic JFET input operational ampli-
n Sample and Hold circuits
General Description
fiers to incorporate well matched, high voltage JFETs on the
Common Features
™
same chip with standard bipolar transistors (BI-FET Tech-
nology). These amplifiers feature low input bias and offset
currents/low offset voltage and offset voltage drift, coupled
with offset adjust which does not degrade drift or
common-mode rejection. The devices are also designed for
high slew rate, wide bandwidth, extremely fast settling time,
low voltage and current noise and a low 1/f noise corner.
n Low input bias current: 30pA
n Low Input Offset Current: 3pA
n High input impedance: 1012Ω
n Low input noise current:
n High common-mode rejection ratio: 100 dB
n Large dc voltage gain: 106 dB
Features
Advantages
Uncommon Features
n Replace expensive hybrid and module FET op amps
n Rugged JFETs allow blow-out free handling compared
with MOSFET input devices
n Excellent for low noise applications using either high or
low source impedance—very low 1/f corner
n Offset adjust does not degrade drift or common-mode
rejection as in most monolithic amplifiers
n New output stage allows use of large capacitive loads
(5,000 pF) without stability problems
LF155/ LF156/ LF257/
Units
LF355
LF256/
LF356
1.5
LF357
(AV=5)
1.5
j
Extremely
fast settling
time to
4
µs
0.01%
j
j
j
Fast slew
rate
5
12
5
50
20
12
V/µs
MHz
n Internal compensation and large differential input voltage
capability
Wide gain
bandwidth
Low input
noise
2.5
20
Applications
n Precision high speed integrators
n Fast D/A and A/D converters
n High impedance buffers
12
voltage
n Wideband, low noise, low drift amplifiers
Simplified Schematic
00564601
*
3pF in LF357 series.
™
™
BI-FET , BI-FET II are trademarks of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation
DS005646
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for
availability and specifications.
LF155/6
LF256/7/LF356B
LF355/6/7
±
±
±
±
±
±
±
±
±
Supply Voltage
22V
40V
20V
22V
40V
20V
18V
30V
16V
Differential Input Voltage
Input Voltage Range (Note 2)
Output Short Circuit Duration
TJMAX
Continuous
Continuous
Continuous
H-Package
150˚C
115˚C
100˚C
100˚C
115˚C
100˚C
100˚C
N-Package
M-Package
Power Dissipation at TA = 25˚C (Notes
1, 8)
H-Package (Still Air)
H-Package (400 LF/Min Air Flow)
N-Package
560 mW
400 mW
1000 mW
670 mW
380 mW
400 mW
1000 mW
670 mW
380 mW
1200 mW
M-Package
Thermal Resistance (Typical) θJA
H-Package (Still Air)
H-Package (400 LF/Min Air Flow)
N-Package
160˚C/W
65˚C/W
160˚C/W
65˚C/W
160˚C/W
65˚C/W
130˚C/W
195˚C/W
130˚C/W
195˚C/W
M-Package
(Typical) θJC
H-Package
23˚C/W
23˚C/W
23˚C/W
Storage Temperature Range
Soldering Information (Lead Temp.)
Metal Can Package
Soldering (10 sec.)
Dual-In-Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
−65˚C to +150˚C
−65˚C to +150˚C
−65˚C to +150˚C
300˚C
260˚C
300˚C
260˚C
300˚C
260˚C
215˚C
220˚C
215˚C
220˚C
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of
soldering surface mount devices.
ESD tolerance
(100 pF discharged through 1.5kΩ)
1000V
1000V
1000V
DC Electrical Characteristics
(Note 3)
LF256/7
LF356B
Min Typ Max Min Typ Max Min Typ Max
LF155/6
LF355/6/7
Symbol
VOS
Parameter
Conditions
Units
Input Offset Voltage
RS=50Ω, TA=25˚C
Over Temperature
RS=50Ω
3
5
7
3
5
3
10
13
mV
mV
6.5
∆VOS/∆T
Average TC of Input
Offset Voltage
5
5
5
µV/˚C
∆TC/∆VOS Change in Average TC RS=50Ω, (Note 4)
µV/˚C
per mV
pA
0.5
3
0.5
3
0.5
3
with VOS Adjust
IOS
Input Offset Current
TJ=25˚C, (Notes 3, 5)
20
20
20
1
50
2
TJ≤THIGH
nA
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2
DC Electrical Characteristics (Continued)
(Note 3)
LF256/7
LF356B
LF155/6
LF355/6/7
Symbol
IB
Parameter
Conditions
Units
Min Typ Max Min Typ Max Min Typ Max
Input Bias Current
TJ=25˚C, (Notes 3, 5)
TJ≤THIGH
30
100
50
30
100
5
30
200
8
pA
nA
RIN
Input Resistance
Large Signal Voltage
Gain
TJ=25˚C
1012
200
1012
200
1012
200
Ω
±
AVOL
VS= 15V, TA=25˚C
50
25
50
25
25
15
V/mV
±
VO= 10V, RL=2k
Over Temperature
V/mV
±
±
±
±
±
±
±
±
±
±
VO
Output Voltage Swing
VS= 15V, RL=10k
12
10
13
12
12
10
13
12
12
10
13
12
V
V
V
V
±
±
±
±
VS= 15V, RL=2k
±
±
15.1
VCM
Input Common-Mode
Voltage Range
VS= 15V
+15.1
−12
+15.1
−12
±
±
11
11
+10
80
−12
CMRR
PSRR
Common-Mode
Rejection Ratio
Supply Voltage
Rejection Ratio
85
85
100
100
85
85
100
100
100
dB
dB
(Note 6)
100
80
DC Electrical Characteristics
±
TA = TJ = 25˚C, VS
=
15V
LF155
Max
LF355
Max
LF156/256/257/356B
LF356
Typ Max
LF357
Typ Max
Parameter
Units
Typ
Typ
Typ
Max
Supply
Current
2
4
2
4
5
7
5
10
5
10
mA
AC Electrical Characteristics
±
15V
TA = TJ = 25˚C, VS
=
LF155/355
LF156/256/
356B
LF156/256/356/
LF257/357
Typ
LF356B
Typ
Symbol
Parameter
Slew Rate
Conditions
Units
Typ
Min
SR
LF155/6:
AV=1,
5
7.5
12
V/µs
LF357: AV=5
50
20
V/µs
MHz
µs
GBW
ts
Gain Bandwidth Product
Settling Time to 0.01%
Equivalent Input Noise
Voltage
2.5
4
5
(Note 7)
1.5
1.5
en
RS=100Ω
f=100 Hz
25
20
15
12
15
12
f=1000 Hz
f=100 Hz
f=1000 Hz
in
Equivalent Input Current
Noise
0.01
0.01
3
0.01
0.01
3
0.01
0.01
3
CIN
Input Capacitance
pF
Notes for Electrical Characteristics
Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature,
JMAX JA
T . The maximum available power dissipation at any temperature is P =(T
−T )/θ or the 25˚C P
, whichever is less.
A
D
JMAX
A
JA
dMAX
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: Unless otherwise stated, these test conditions apply:
3
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Notes for Electrical Characteristics (Continued)
LF155/156
LF256/257
LF356B
LF355/6/7
±
±
±
±
±
±
±
Supply Voltage, VS
15V ≤ VS
≤
20V
15V ≤ VS
≤
20V
15V ≤ VS 20V
VS= 15V
TA
−55˚C ≤ TA ≤ +125˚C
−25˚C ≤ TA ≤ +85˚C
0˚C ≤ TA ≤ +70˚C
0˚C ≤ TA ≤ +70˚C
THIGH
+125˚C
+85˚C
+70˚C
+70˚C
and V , I and I
are measured at V
= 0.
CM
OS
B
OS
Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5µV/˚C typically) for each mV of adjustment from its original
unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.
Note 5: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, T . Due to limited
J
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, Pd. T = T + θ Pd where θ is the thermal resistance from junction to ambient. Use of a heat sink is
J
A
JA
JA
recommended if input bias current is to be kept to a minimum.
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kΩ resistors for the LF155/6. It is the time required for the error voltage (the voltage
at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, A = −5,
V
the feedback resistor from output to input is 2kΩ and the output step is 10V (See Settling Time Test Circuit).
Note 8: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside
guaranteed limits.
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise
specified.
Input Bias Current
Input Bias Current
00564638
00564637
Input Bias Current
Voltage Swing
00564640
00564639
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4
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise
specified. (Continued)
Supply Current
Supply Current
00564642
00564641
Negative Current Limit
Positive Current Limit
00564643
00564644
Positive Common-Mode
Input Voltage Limit
Negative Common-Mode
Input Voltage Limit
00564645
00564646
5
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Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise
specified. (Continued)
Open Loop Voltage Gain
Output Voltage Swing
00564648
00564647
Typical AC Performance Characteristics
Gain Bandwidth
Gain Bandwidth
00564650
00564649
Normalized Slew Rate
Output Impedance
00564651
00564652
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6
Typical AC Performance Characteristics (Continued)
Output Impedance
LF155 Small Signal Pulse Response, AV = +1
00564605
00564653
LF156 Small Signal Pulse Response, AV = +1
LF155 Large Signal Pulse Response, AV = +1
00564608
00564606
LF156 Large Signal Puls
Response, AV = +1
Inverter Settling Time
00564609
00564655
7
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Typical AC Performance Characteristics (Continued)
Inverter Settling Time
Open Loop Frequency Response
00564656
00564657
Bode Plot
Bode Plot
00564658
00564659
Bode Plot
Common-Mode Rejection Ratio
00564660
00564661
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8
Typical AC Performance Characteristics (Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
00564662
00564663
Undistorted Output Voltage Swing
Equivalent Input Noise Voltage
00564664
00564665
Equivalent Input Noise
Voltage (Expanded Scale)
00564666
9
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Detailed Schematic
00564613
*
C = 3pF in LF357 series.
Connection Diagrams (Top Views)
Metal Can Package (H)
Dual-In-Line Package (M and N)
00564614
Order Number LF155H, LF156H, LF256H, LF257H,
LF356BH, LF356H, or LF357H
00564629
Order Number LF356M, LF356MX, LF355N, or LF356N
See NS Package Number M08A or N08E
See NS Package Number H08C
*
Available per JM38510/11401 or JM38510/11402
Application Hints
These are op amps with JFET input devices. These JFETs
have large reverse breakdown voltages from gate to source
and drain eliminating the need for clamps across the inputs.
Therefore large differential input voltages can easily be ac-
commodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
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10
Application Hints (Continued)
Typical Circuit Connections
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
VOS Adjustment
Exceeding the positive common-mode limit on a single input
will not change the phase of the output however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
These amplifiers will operate with the common-mode input
voltage equal to the positive supply. In fact, the
common-mode voltage can exceed the positive supply by
approximately 100 mV independent of supply voltage and
over the full operating temperature range. The positive sup-
ply can therefore be used as a reference on an input as, for
example, in a supply current monitor and/or limiter.
00564667
•
•
•
VOS is adjusted with a 25k potentiometer
The potentiometer wiper is connected to V+
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
For potentiometers with temperature coefficient of 100
ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/
˚C/mV of adjustment
±
•
Typical overall drift: 5µV/˚C (0.5µV/˚C/mV of adj.)
Driving Capacitive Loads
All of the bias currents in these amplifiers are set by FET
current sources. The drain currents for the amplifiers are
therefore essentially independent of supply voltage.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pickup” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
00564668
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3dB
frequency of the closed loop gain and consequently there is
negligible effect on stability margin. However, if the feedback
pole is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the output
to the input of the op amp. The value of the added capacitor
should be such that the RC time constant of this capacitor
and the resistance it parallels is greater than or equal to the
original feedback pole time constant.
*
LF155/6 R = 5k
LF357 R = 1.25k
Due to a unique output stage design, these amplifiers
have the ability to drive large capacitive loads and still
maintain stability. CL(MAX) . 0.01µF.
Overshoot ≤ 20%
Settling time (ts) . 5µs
LF357. A Large Power BW Amplifier
00564615
For distortion ≤ 1% and a 20 Vp-p V
swing, power bandwidth is:
OUT
500kHz.
11
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Typical Applications
Settling Time Test Circuit
00564616
•
•
•
•
Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = −5
FET used to isolate the probe capacitance
Output = 10V step
AV = −5 for LF357
Large Signal Inverter Output, VOUT (from Settling Time Circuit)
LF355
LF357
00564619
00564617
LF356
00564618
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12
Typical Applications (Continued)
Low Drift Adjustable Voltage Reference
00564620
±
•
•
•
•
•
∆ VOUT/∆T = 0.002%/˚C
All resistors and potentiometers should be wire-wound
P1: drift adjust
P2: VOUT adjust
Use LF155 for
j
j
j
Low IB
Low drift
Low supply current
Fast Logarithmic Converter
00564621
•
•
•
•
•
Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades), |VO| = 1V/decade
Transient response: 3µs for ∆Ii = 1 decade
C1, C2, R2, R3: added dynamic compensation
VOS adjust the LF156 to minimize quiescent error
RT: Tel Labs type Q81 + 0.3%/˚C
13
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Typical Applications (Continued)
Precision Current Monitor
00564631
•
•
•
VO = 5 R1/R2 (V/mA of IS)
R1, R2, R3: 0.1% resistors
Use LF155 for
j
j
j
j
Common-mode range to supply range
Low IB
Low VOS
Low Supply Current
8-Bit D/A Converter with Symmetrical Offset Binary Operation
00564632
±
•
•
R1, R2 should be matched within 0.05%
Full-scale response time: 3µs
EO
B1 B2 B3 B4 B5 B6 B7 B8
Comments
Positive Full-Scale
(+) Zero-Scale
+9.920
+0.040
−0.040
−9.920
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(−) Zero-Scale
Negative Full-Scale
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14
Typical Applications (Continued)
Wide BW Low Noise, Low Drift Amplifier
00564670
•
Parasitic input capacitance C1 . (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts with
feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1.
Boosting the LF156 with a Current Amplifier
00564673
•
•
IOUT(MAX).150mA (will drive RL≥ 100Ω)
No additional phase shift added by the current amplifier
15
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Typical Applications (Continued)
3 Decades VCO
00564624
R1, R4 matched. Linearity 0.1% over 2 decades.
Isolating Large Capacitive Loads
00564622
•
•
•
Overshoot 6%
ts 10µs
When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX)
:
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16
Typical Applications (Continued)
Low Drift Peak Detector
00564623
•
•
•
•
By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf.
Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp.
Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2.
1
<<
Maximum input frequency should be
⁄2πRfCD2 where CD2 is the shunt capacitance of D2.
Non-Inverting Unity Gain Operation for LF157
00564675
Inverting Unity Gain for LF157
00564625
17
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Typical Applications (Continued)
High Impedance, Low Drift Instrumentation Amplifier
00564626
•
•
System VOS adjusted via A2 VOS adjust
Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift
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18
Typical Applications (Continued)
Fast Sample and Hold
00564633
•
•
Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)
Acquisition time TA, estimated by:
•
•
•
LF156 develops full Sr output capability for VIN ≥ 1V
Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop
Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2
19
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Typical Applications (Continued)
High Accuracy Sample and Hold
00564627
•
•
By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.
No VOS adjust required for A2.
TA can be estimated by same considerations as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
Overall system slower than fast sample and hold
R1, CC: additional compensation
•
•
•
Use LF156 for
j
j
Fast settling time
Low VOS
High Q Band Pass Filter
00564628
•
•
•
By adding positive feedback (R2)
Q increases to 40
fBP = 100 kHz
•
•
Clean layout recommended
Response to a 1Vp-p tone burst: 300µs
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20
Typical Applications (Continued)
High Q Notch Filter
00564634
•
2R1 = R = 10MΩ
2C = C1 = 300pF
•
•
•
Capacitors should be matched to obtain high Q
>
fNOTCH = 120 Hz, notch = −55 dB, Q 100
Use LF155 for
j
j
Low IB
Low supply current
21
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Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H or LF357H
NS Package Number H08C
Small Outline Package (M)
Order Number LF356M or LF356MX
NS Package Number M08A
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22
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number LF356N
NS Package Number N08E
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