LF156JAN_13 [TI]
JFET Input Operational Amplifiers;
| 型号： | LF156JAN_13 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | JFET Input Operational Amplifiers |
| 文件： | 总23页 (文件大小：998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF156JAN
LF156JAN JFET Input Operational Amplifiers
Literature Number: SNOSAQ0
March 2006
LF156JAN
JFET Input Operational Amplifiers
General Description
Applications
n Precision high speed integrators
n Fast D/A and A/D converters
n High impedance buffers
This is the first monolithic JFET input operational amplifier to
incorporate well matched, high voltage JFETs on the same
™
chip with standard bipolar transistors (BI-FET Technology).
This amplifier features low input bias and offset currents/low
offset voltage and offset voltage drift, coupled with offset
adjust which does not degrade drift or common-mode rejec-
tion. The device is also designed for high slew rate, wide
bandwidth, extremely fast settling time, low voltage and
current noise and a low 1/ƒ noise corner.
n Wideband, low noise, low drift amplifiers
n Logarithmic amplifiers
n Photocell amplifiers
n Sample and Hold circuits
Common Features
n Low input bias current:
n Low Input Offset Current:
n High input impedance:
n Low input noise current:
n High common-mode rejection ratio:
n Large dc voltage gain:
30pA
3pA
1012
Features
Ω
Advantages
n Replace expensive hybrid and module FET op amps
n Rugged JFETs allow blow-out free handling compared
with MOSFET input devices
100 dB
106 dB
Uncommon Features
n Extremely fast settling
time to 0.01%
n Fast slew rate
n Wide gain bandwidth
n Low input noise voltage
n Excellent for low noise applications using either high or
low source impedance—very low 1/f corner
n Offset adjust does not degrade drift or common-mode
rejection as in most monolithic amplifiers
n New output stage allows use of large capacitive loads
(5,000 pF) without stability problems
1.5µs
12V/µs
5MHz
12
n Internal compensation and large differential input voltage
capability
Ordering Information
NS PART NUMBER
JL156BGA
SMD PART NUMBER
JM38510/11402
NS PACKAGE NUMBER
PACKAGE DISCRIPTION
8LD Metal Can
H08C
H08C
JL156SGA
JM38510/11402
8LD Metal Can
Connection Diagrams
Metal Can Package (H)
20151114
Top View
See NS Package Number H08C
™
™
BI-FET , BI-FET II are trademarks of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS201511
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Simplified Schematic
20151101
*3pF in LF357 series.
Detailed Schematic
20151113
*C = 3pF in LF357 series.
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2
Absolute Maximum Ratings (Note 1)
Supply Voltage
22V
40V
Differential Input Voltage
Input Voltage Range (Note 3)
Output Short Circuit Duration (Note 4)
TJMAX
20V
Continuous
175˚C
Power Dissipation at TA = 25˚C (Note 2)
Still Air
560 mW
500 LF/Min Air Flow
Thermal Resistance
θJA
1200 mW
Still Air
160˚C/W
65˚C/W
400 LF/Min Air Flow
θJC
23˚C/W
Storage Temperature Range
Lead Temperature (Soldering 10 sec.)
ESD tolerance (Note 5)
−65˚C ≤ TA ≤ +150˚C
300˚C
1200V
Recommended Operating Conditions
Supply voltage range
5 to 20 VDC
Ambient temperature range
−55˚C ≤ TA ≤ +125˚C
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Static tests at
Static tests at
Temp ( C)
+25
1
2
3
+125
-55
4
5
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
+25
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
12
+125
-55
+25
3
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LF156 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
DC: VCC
Symbol
ICC
VIO
=
20V, VCM = 0V
Sub-
groups
Parameter
Conditions
Notes
Min Max
Unit
mA
mA
mA
mV
mV
mV
mV
mV
mV
mV
mV
nA
7.0
6.0
11
1
Supply Current
Input Offset Voltage
+VCC = 15V, -VCC = -15V
2
3
+VCC = 5V, -VCC = -35V,
VCM = 15V
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
-0.1
-10
5.0
7.0
5.0
7.0
5.0
7.0
5.0
7.0
3.5
60
1
2, 3
+VCC = 35V, -VCC = -5V,
VCM = -15V
1
2, 3
1
2, 3
+VCC = 5V, -VCC = -5V
1
2, 3
IIB
Input Bias Current
+VCC = 5V, -VCC = -35V,
VCM = 15V
1
nA
2
+VCC = 35V, -VCC = -5V,
VCM = -15V
-0.1
-10
0.1
50
nA
1
nA
2
-0.1
-10
0.1
50
nA
1
nA
2
+VCC = 5V, -VCC = -25V,
VCM = 10V
-0.1
-10
0.3
50
nA
1
nA
2
1
IIO
Input Offset Current
-0.02 0.02
nA
-20
85
85
+20
nA
2
+PSRR
-PSRR
CMR
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Common Mode
Rejection
+VCC = 10V, -VCC = -20V
+VCC = 20V, -VCC = -10V
VCM = -15V to 15V
dB
1, 2, 3
1, 2, 3
dB
85
dB
mV
mV
mA
mA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VIO Adj(+)
VIO Adj(-)
+IOS
Adjustment for Input Offset
Voltage
8.0
Adjustment for Input Offset
Voltage
-8.0
50
Output Short Circuit Current
(For Positive Output)
Output Short Circuit Current
(For Negative Output)
Temperature Coefficient of
Input Offset Voltage
+VCC = 15V, -VCC = -15V,
t ≤ 25mS
-50
-IOS
+VCC = 15V, -VCC = -15V,
t ≤ 25mS
∆ VIO/∆T
-AVS
25˚C ≤ TA ≤ +125˚C
-55˚C ≤ TA ≤ 25˚C
VO = -15V, RL = 2KΩ
(Note 7)
(Note 7)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
-30
-30
50
25
50
25
30
30
µV/˚C
µV/˚C
V/mV
V/mV
V/mV
V/mV
2
3
Open Loop Voltage Gain
(Single Ended)
4
5, 6
4
+AVS
Open Loop Voltage Gain
(Single Ended)
VO = +15V, RL = 2KΩ
5, 6
AVS
Open Loop Voltage Gain
(Single Ended)
VCC
=
5V, VO
=
2V,
(Note 6)
10
V/mV
4, 5, 6
RL = 2KΩ
-VOP
Output Voltage Swing
VCM = 20V, RL = 10KΩ
VCM = 20V, RL = 2KΩ
VCM = -20V, RL = 10KΩ
VCM = -20V, RL = 2KΩ
-16
-15
V
V
V
V
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
+VOP
Output Voltage Swing
16
15
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4
LF156 Electrical Characteristics (Continued)
AC Parameters
The following conditions apply, unless otherwise specified.
AC: VCC
=
15V, VCM = 0V
Sub-
groups
7
Symbol
Parameter
Conditions
Notes
Min Max
Unit
V/µS
V/µS
V/µS
V/µS
7.5
5
-SR
Slew Rate Fall
Slew Rate Rise
VI = 5V to -5V, AV = 1
VI = -5V to 5V, AV = 1
8A, 8B
7
+SR
7.5
5
8A, 8B
TRTR
TROS
Transient Response Rise Time RL = 2KΩ, CL= 100pF,
VI = 50mV, AV = 1
100
40
nS
%
7, 8A, 8B
7, 8A, 8B
Transient Response Overshoot RL = 2KΩ, CL = 100pF,
VI = 50mV, AV = 1
NIBB
NIPC
tS (+)
tS (-)
Noise Broad Band
Noise Popcorn
Settling Time
BW = 5KHz, VCC
BW = 5KHz, VCC
AV = -1
=
=
20V
20V
10
40
µVRMS
µVPK
nS
7
7
1500
1500
12
12
Settling Time
AV = -1
nS
Drift Values
The following conditions apply, unless otherwise specified.
AC: VCC 20V, VCM = 0V
Delta calculations performed on JAN S devices at group B, subgroup 5 only
=
Sub-
Symbol
VIO
Parameter
Conditions
Notes
Min Max
Unit groups
Input Offset Voltage
Input Bias Current
-1.0
1.0
mV
nA
1
1
IIB
-0.05 0.05
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condition for which the device is
functional, but do not guarantee specific performance limits . For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature), θ (package junction
JA
Jmax
to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is P =(T
−T )/θ or the number
A
D
Jmax
A JA
given in the Absolute Maximum Ratings, whichever is lower.
Note 3: The absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: Short circuit may be to ground or either supply. Rating applies to +125˚C case temperature or +75˚C ambient temperature.
Note 5: Human body model, 100pF discharged through 1.5KΩ.
Note 6: Datalog Reading in K = V/mV.
Note 7: Calculated parameter.
5
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Typical DC Performance Characteristics
Input Bias Current
Input Bias Current
20151138
20151140
20151142
20151137
Input Bias Current
Voltage Swing
20151139
Supply Current
Supply Current
20151141
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6
Typical DC Performance Characteristics (Continued)
Negative Current Limit
Positive Current Limit
20151143
20151144
Positive Common-Mode
Input Voltage Limit
Negative Common-Mode
Input Voltage Limit
20151145
20151146
Open Loop Voltage Gain
Output Voltage Swing
20151148
20151147
7
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Typical AC Performance Characteristics
Gain Bandwidth
Normalized Slew Rate
20151150
20151151
Output Impedance
Output Impedance
20151153
20151152
LF156 Small Signal Pulse
Response, AV = +1
LF156 Large Signal Puls
Response, AV = +1
20151109
20151106
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8
Typical AC Performance Characteristics (Continued)
Inverter Settling Time
Open Loop Frequency Response
20151156
20151157
Bode Plot
Common-Mode Rejection Ratio
20151159
20151161
Power Supply Rejection Ratio
20151163
9
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Typical AC Performance Characteristics (Continued)
Undistorted Output Voltage Swing
Equivalent Input Noise Voltage
20151164
20151165
Equivalent Input Noise
Voltage (Expanded Scale)
20151166
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10
negligible effect on stability margin. However, if the feedback
pole is less than approximately six times the expected 3 dB
frequency a lead capacitor should be placed from the output
to the input of the op amp. The value of the added capacitor
should be such that the RC time constant of this capacitor
and the resistance it parallels is greater than or equal to the
original feedback pole time constant.
Application Hints
These are op amps with JFET input devices. These JFETs
have large reverse breakdown voltages from gate to source
and drain eliminating the need for clamps across the inputs.
Therefore large differential input voltages can easily be ac-
commodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Typical Circuit Connections
VOS Adjustment
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
20151167
These amplifiers will operate with the common-mode input
voltage equal to the positive supply. In fact, the common-
mode voltage can exceed the positive supply by approxi-
mately 100 mV independent of supply voltage and over the
full operating temperature range. The positive supply can
therefore be used as a reference on an input as, for ex-
ample, in a supply current monitor and/or limiter.
•
•
•
VOS is adjusted with a 25k potentiometer
The potentiometer wiper is connected to V+
For potentiometers with temperature coefficient of 100
ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/
˚C/mV of adjustment
•
Typical overall drift: 5µV/˚C (0.5µV/˚C/mV of adj.)
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
Driving Capacitive Loads
All of the bias currents in these amplifiers are set by FET
current sources. The drain currents for the amplifiers are
therefore essentially independent of supply voltage.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pickup” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
20151168
* LF156 R = 5k
Due to a unique output stage design, these amplifiers
have the ability to drive large capacitive loads and still
maintain stability. CL(MAX) . 0.01µF.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3dB
frequency of the closed loop gain and consequently there is
Overshoot ≤ 20%
Settling time (ts) . 5µs
11
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Typical Applications
Settling Time Test Circuit
20151116
•
•
•
Settling time is tested with the LF156 connected as unity gain inverter.
FET used to isolate the probe capacitance
Output = 10V step
Large Signal Inverter Output, VOUT (from Settling Time Circuit)
LF356
20151118
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12
Typical Applications (Continued)
Low Drift Adjustable Voltage Reference
20151120
•
•
•
•
∆ VOUT/∆T = 0.002%/˚C
All resistors and potentiometers should be wire-wound
P1: drift adjust
P2: VOUT adjust
Fast Logarithmic Converter
20151121
•
•
•
•
•
Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades), |VO| = 1V/decade
Transient response: 3µs for ∆Ii = 1 decade
C1, C2, R2, R3: added dynamic compensation
VOS adjust the LF156 to minimize quiescent error
RT: Tel Labs type Q81 + 0.3%/˚C
13
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Typical Applications (Continued)
Precision Current Monitor
20151131
•
•
VO = 5 R1/R2 (V/mA of IS)
R1, R2, R3: 0.1% resistors
8-Bit D/A Converter with Symmetrical Offset Binary Operation
20151132
•
•
R1, R2 should be matched within 0.05%
Full-scale response time: 3µs
EO
B1 B2 B3 B4 B5 B6 B7 B8
Comments
Positive Full-Scale
(+) Zero-Scale
+9.920
+0.040
−0.040
−9.920
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(−) Zero-Scale
Negative Full-Scale
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14
Typical Applications (Continued)
Wide BW Low Noise, Low Drift Amplifier
20151170
•
Parasitic input capacitance C1 . 3pF interacts with feedback elements and creates undesirable high frequency pole. To
compensate add C2 such that: R2 C2 . R1 C1.
Boosting the LF156 with a Current Amplifier
20151173
•
•
IOUT(MAX).150mA (will drive RL≥ 100Ω)
•
No additional phase shift added by the current amplifier
15
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Typical Applications (Continued)
3 Decades VCO
20151124
R1, R4 matched. Linearity 0.1% over 2 decades.
Isolating Large Capacitive Loads
20151122
•
•
•
Overshoot 6%
ts 10µs
When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX)
:
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16
Typical Applications (Continued)
Low Drift Peak Detector
20151123
•
•
•
•
By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf.
Leakage of circuit is essentially Ib plus capacitor leakage of Cp.
Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2.
1
<<
Maximum input frequency should be
⁄2πRfCD2 where CD2 is the shunt capacitance of D2.
High Impedance, Low Drift Instrumentation Amplifier
20151126
•
•
System VOS adjusted via A2 VOS adjust
Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift
17
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Typical Applications (Continued)
Fast Sample and Hold
20151133
•
•
Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)
Acquisition time TA, estimated by:
•
•
•
LF156 develops full Sr output capability for VIN ≥ 1V
Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop
Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2
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18
Typical Applications (Continued)
High Accuracy Sample and Hold
20151127
•
•
By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.
No VOS adjust required for A2.
TA can be estimated by same considerations as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
Overall system slower than fast sample and hold
R1, CC: additional compensation
•
•
•
Use LF156 for
j
Fast settling time
Low VOS
j
High Q Notch Filter
20151134
•
2R1 = R = 10MΩ
2C = C1 = 300pF
•
•
•
Capacitors should be matched to obtain high Q
>
fNOTCH = 120 Hz, notch = −55 dB, Q 100
Use LF155 for
j
Low IB
j
Low supply current
19
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Revision History
Date
Released
Revision
Section
Originator
Changes
New Release, Corporate format 1 MDS
data sheet converted into a Corp. data
sheet format. Following MDS data sheet
will be Archived MJLF156-X, Rev. 0A0.
03/10/06
A
New Released, Corporate format.
R. Malone
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20
Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
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相关型号：
LF157AD/883B
Operational Amplifier, 1 Func, 2500uV Offset-Max, BIPolar, CDIP8, CERAMIC, DIP-8
RAYTHEON
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