LF411-N [TI]
Low Offset, Low Drift JFET Input Operational Amplifier;
| 型号： | LF411-N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Offset, Low Drift JFET Input Operational Amplifier |
| 文件： | 总16页 (文件大小：878K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF411-N
www.ti.com
SNOSBH6D –APRIL 1998–REVISED MARCH 2013
LF411 Low Offset, Low Drift JFET Input Operational Amplifier
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1
FEATURES
DESCRIPTION
These devices are low cost, high speed, JFET input
operational amplifiers with very low input offset
voltage and specified input offset voltage drift. They
require low supply current yet maintain a large gain
bandwidth product and fast slew rate. In addition, well
matched high voltage JFET input devices provide
very low input bias and offset currents. The LF411 is
pin compatible with the standard LM741 allowing
designers to immediately upgrade the overall
performance of existing designs.
23
•
Internally trimmed offset voltage: 0.5 mV(max)
Input offset voltage drift: 10 μV/°C(max)
Low input bias current: 50 pA
•
•
•
•
•
•
•
•
•
•
Low input noise current: 0.01 pA/√Hz
Wide gain bandwidth: 3 MHz(min)
High slew rate: 10V/μs(min)
Low supply current: 1.8 mA
High input impedance: 1012Ω
These amplifiers may be used in applications such as
high speed integrators, fast D/A converters, sample
and hold circuits and many other circuits requiring low
input offset voltage and drift, low input bias current,
high input impedance, high slew rate and wide
bandwidth.
Low total harmonic distortion: ≤0.02%
Low 1/f noise corner: 50 Hz
Fast settling time to 0.01%: 2 μs
Typical Connection
Figure 1.
Connection Diagram
Note: Pin 4 connected to case.
Figure 2. TO – Top View
See Package Number NEV0008A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
BI-FET II is a trademark of dcl_owner.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
LF411-N
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Figure 3. PDIP – Top View
See Package Number P0008E
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
LF411A
±22V
LF411
±18V
Supply Voltage
Differential Input Voltage(2)
±38V
±30V
±19V
±15V
Output Short Circuit Duration
Continuous
Continuous
TO Package
670 mW
PDIP Package
670 mW
Power Dissipation(3) (4)
Tjmax
150°C
115°C
θjA
162°C/W (Still Air)
65°C/W (400 LF/min Air Flow)
20°C/W
120°C/W
θjC
(5)
(5)
Operating Temp. Range
Storage Temp. Range
Lead Temp. (Soldering, 10 sec.)
ESD Tolerance
See
See
−65°C≤TA≤150°C
−65°C≤TA≤150°C
260°C
260°C
Rating to be determined.
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
(3) For operating at elevated temperature, these devices must be derated based on a thermal resistance of θjA.
(4) Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the
part to operate outside specified limits.
(5) These devices are available in both the commercial temperature range 0°C≤TA≤70°C and the military temperature range
−55°C≤TA≤125°C. The temperature range is designated by the position just before the package type in the device number. A “C”
indicates the commercial temperature range and an “M” indicates the military temperature range. The military temperature range is
available in the TO package only.
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(1)(2)
DC Electrical Characteristics
LF411A
Typ
LF411
Units
Symbol
Parameter
Conditions
Min
Max Min
Typ
Max
VOS
Input Offset Voltage
RS=10 kΩ, TA=25°C
0.3
0.5
0.8
2.0
mV
(3)
(3)
ΔVOS/ΔT Average TC of Input
RS=10 kΩ
20
7
10
7
μV/°C
Offset Voltage
(2) (4)
IOS
Input Offset Current
VS=±15V
Tj=25°C
Tj=70°C
Tj=125°C
Tj=25°C
Tj=70°C
Tj=125°C
25
100
2
25
100
2
pA
nA
nA
pA
nA
nA
Ω
25
200
4
25
200
4
(2) (4)
IB
Input Bias Current
VS=±15V
50
50
50
50
RIN
Input Resistance
Large Signal Voltage
Gain
Tj=25°C
1012
200
1012
200
AVOL
VS=±15V, VO=±10V,
50
25
15
V/mV
V/mV
V
RL=2k, TA=25°C Over Temperature 25
200
200
VO
Output Voltage Swing
Input Common-Mode
Voltage Range
VS=±15V, RL=10k
±12
±16
±13.5
+19.5
−16.5
±12
±11
±13.5
+14.5
−11.5
VCM
V
V
CMRR
PSRR
IS
Common-Mode Rejection RS≤10k
Ratio
80
80
100
70
100
dB
(5)
Supply Voltage Rejection
Ratio
See
100
1.8
70
100
1.8
dB
Supply Current
2.8
3.4
mA
(1) RETS 411X for LF411MH and LF411MJ military specifications.
(2) Unless otherwise specified, the specifications apply over the full temperature range and for VS=±20V for the LF411A and for VS=±15V
for the LF411. VOS, IB, and IOS are measured at VCM=0.
(3) The LF411A is 100% tested to this specification. The LF411 is sample tested to insure at least 90% of the units meet this specification.
(4) The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature,
Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the
junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the
thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
(5) Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with
common practice, from ±15V to ±5V for the LF411 and from ±20V to ±5V for the LF411A.
(1)(2)
AC Electrical Characteristic
LF411A
LF411
Typ
15
Symbol
Parameter
Conditions
Units
Min
10
3
Typ
15
4
Max
Min
8
Max
SR
Slew Rate
VS=±15V, TA=25°C
VS=±15V, TA=25°C
V/μs
GBW
en
Gain-Bandwidth Product
2.7
4
MHz
Equivalent Input Noise Voltage
TA=25°C, RS=100Ω,
f=1 kHz
25
25
nV / √Hz
in
Equivalent Input Noise Current
Total Harmonic Distortion
TA=25°C, f=1 kHz
0.01
0.01
pA / √Hz
THD
AV=+10, RL=10k, VO=20
<0.02
<0.02
%
Vp-p, BW=20 Hz−20 kHz
(1) Unless otherwise specified, the specifications apply over the full temperature range and for VS=±20V for the LF411A and for VS=±15V
for the LF411. VOS, IB, and IOS are measured at VCM=0.
(2) RETS 411X for LF411MH and LF411MJ military specifications.
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Typical Performance Characteristics
Input Bias Current
Input Bias Current
Figure 4.
Figure 5.
Positive Common-Mode
Input Voltage Limit
Supply Current
Figure 6.
Figure 7.
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
Negative Current Limit
Output Voltage Swing
Figure 10.
Figure 11.
Output Voltage Swing
Gain Bandwidth
Figure 12.
Bode Plot
Figure 13.
Slew Rate
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
Distortion
vs
Frequency
Undistorted Output
Voltage Swing
Figure 16.
Figure 17.
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
Figure 18.
Figure 19.
Power Supply
Rejection Ratio
Equivalent Input Noise
Voltage
Figure 20.
Figure 21.
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SNOSBH6D –APRIL 1998–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Open Loop Voltage Gain
Output Impedance
Figure 22.
Figure 23.
Inverter Settling Time
Figure 24.
PULSE RESPONSE (RL=2 KΩ, CL10 PF)
Figure 25. Small Signal Inverting
Figure 26. Small Signal Non-Inverting
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Figure 27. Large Signal Inverting
Figure 28. Large Signal Non-Inverting
Figure 29. Current Limit (RL=100Ω)
APPLICATION HINTS
The LF411 series of internally trimmed JFET input op amps (BI-FET II™ ) provide very low input offset voltage
and specified input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source
and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily
be accommodated without a large increase in input current. The maximum differential input voltage is
independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the
negative supply as this will cause large currents to flow which can result in a destroyed unit. BI-FET II™
Exceeding the negative common-mode limit on either input will force the output to a high state, potentially
causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force
the amplifier output to a high state. In neither case does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if
both inputs exceed the limit, the output of the amplifier may be forced to a high state.
The amplifier will operate with a common-mode input voltage equal to the positive supply; however, the gain
bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings
to within 3V of the negative supply, an increase in input offset voltage may occur.
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SNOSBH6D –APRIL 1998–REVISED MARCH 2013
The LF411 is biased by a zener reference which allows normal circuit operation on ±4.5V power supplies. Supply
voltages less than these may result in lower gain bandwidth and slew rate.
The LF411 will drive a 2 kΩ load resistance to ±10V over the full temperature range. If the amplifier is forced to
drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing
and finally reach an active current limit on both positive and negative swings.
Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through
the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed
unit.
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in
order to ensure stability. For example, resistors from the output to an input should be placed with the body close
to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the
capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole.
In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed
loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less
than approximately 6 times the expected 3 dB frequency, a lead capacitor should be placed from the output to
the input of the op amp. The value of the added capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.
TYPICAL APPLICATIONS
PNP=2N2905
NPN=2N2219 unless noted
TO-5 heat sinks for Q6-Q7
Figure 30. High Speed Current Booster
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where AN=1 if the AN digital input is high
AN=0 if the AN digital input is low
Figure 31. 10-Bit Linear DAC with No VOS Adjust
Figure 32. Single Supply Analog Switch with Buffered Output
SIMPLIFIED SCHEMATIC
(1) Available per JM38510/11904
Figure 33. Single Supply Analog Switch with Buffered Output
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SNOSBH6D –APRIL 1998–REVISED MARCH 2013
DETAILED SCHEMATIC
Figure 34.
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Mar-2014
PACKAGING INFORMATION
Orderable Device
LF411ACN
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LIFEBUY
PDIP
PDIP
PDIP
PDIP
P
8
8
8
8
40
TBD
Call TI
Call TI
Call TI
CU SN
Call TI
LF
411ACN
LF411ACN/NOPB
LF411CN
ACTIVE
LIFEBUY
ACTIVE
P
P
P
40
40
40
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
Call TI
0 to 70
LF
411ACN
TBD
0 to 70
LF
411CN
LF411CN/NOPB
Green (RoHS
& no Sb/Br)
Level-1-NA-UNLIM
0 to 70
LF
411CN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Mar-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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相关型号：
LF411ACN/NOPB
IC OP-AMP, 500 uV OFFSET-MAX, 4 MHz BAND WIDTH, PDIP8, DIP-8, Operational Amplifier
NSC
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