LM10506TME [TI]
Triple Buck LDO Power Management Unit; 三联降压LDO电源管理单元
| 型号： | LM10506TME |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Triple Buck LDO Power Management Unit |
| 文件： | 总35页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 5, 2012
LM10506
Triple Buck + LDO Power Management Unit
1.0 General Description
3.0 Features
The LM10506 is an advanced PMU containing three config-
urable, high-efficiency buck regulators for supplying variable
voltages. The device is ideal for supporting ASIC and SOC
designs for Solid-State and Flash drives.
Three highly efficient programmable buck regulators
■
Integrated FETs with low RDSON
—
—
Bucks operate with their phases shifted to reduce the
input current ripple and capacitor size
The LM10506 operates cooperatively with ASIC to optimize
the supply voltage for low-power conditions and Power Sav-
ing modes via the SPI interface. It also supports a 100 mA
LDO and a programmable Interrupt Comparator.
Programmable Output Voltage via the SPI interface
Overvoltage and Undervoltage Lockout
—
—
—
—
—
—
Automatic internal soft start with Power-on reset
Current overload and thermal shutdown protection
Bypass mode available on Bucks 1 and 2
2.0 Key Specifications
PFM mode for low-load, high-efficiency operation
Programmable Buck Regulators:
■
Low-dropout LDO 3.2V, 100 mA
■
■
■
■
Buck 1: 1.1V to 3.6V; 1.3A
—
—
—
SPI-programmable interrupt comparator (2.0V to 4.0V)
Alternate Buck VOUTS selectable via H/L logic pins
RESET, STANDBY pins
Buck 2: 1.1V to 3.6V; 400 mA
Buck 3: 0.7V to 1.335V; 600 mA
±3% feedback voltage accuracy
■
■
■
■
Up to 95% efficient buck regulators
4.0 Applications
2MHz switching frequency for smaller inductor size
2.8 x 2.8 mm, 0.4 mm pitch, 34-bump micro SMD package
Solid-State Drives
■
5.0 Typical Application Diagram
30166201
© 2012 Texas Instruments Incorporated
301662 SNVS729B
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Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Key Specifications ........................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
4.0 Applications .................................................................................................................................... 1
5.0 Typical Application Diagram .............................................................................................................. 1
6.0 Overview ........................................................................................................................................ 3
6.1 SUPPLY SPECIFICATION ........................................................................................................ 3
7.0 Connection Diagram and Package Marking ......................................................................................... 4
8.0 LM10506 Pin Descriptions ................................................................................................................ 5
9.0 Ordering Information ........................................................................................................................ 5
10.0 Absolute Maximum Ratings ............................................................................................................. 6
11.0 Operating Ratings .......................................................................................................................... 6
12.0 General Electrical Characteristics .................................................................................................... 6
13.0 Buck 1 Electrical Characteristics ..................................................................................................... 7
14.0 Buck 2 Electrical Characteristics ..................................................................................................... 8
15.0 Buck 3 Electrical Characteristics ..................................................................................................... 8
16.0 LDO Electrical Characteristics ........................................................................................................ 9
17.0 Comparators Electrical Characteristics ............................................................................................. 9
18.0 Typical Performance Characteristics .............................................................................................. 11
19.0 General Description ..................................................................................................................... 15
19.1 SPI DATA INTERFACE ......................................................................................................... 16
19.1.1 Registers Configurable Via The SPI Interface ................................................................. 17
19.1.1.1 ADDR 0x07& 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping ........ 19
19.1.1.2 ADDR 0x00 & 0x09: Buck 3 Voltage Code and VOUT Level Mapping ........................ 20
19.1.1.3 ADDR 0x0B: Comparator Threshold Mapping ....................................................... 21
19.2 BUCK REGULATORS OPERATION ....................................................................................... 22
19.2.1 Buck Regulators Description ........................................................................................ 22
19.2.2 PWM Operation .......................................................................................................... 22
19.2.3 PFM Operation (Bucks 1, 2 & 3) ................................................................................... 23
19.2.4 Soft Start ................................................................................................................... 23
19.2.5 Current Limiting .......................................................................................................... 23
19.2.6 Internal Synchronous Rectification ................................................................................ 24
19.2.7 Bypass-FET Operation on Buck 1 and Buck 2 ................................................................ 24
19.2.8 Low Dropout Operation ............................................................................................... 24
20.0 Device Operating Modes .............................................................................................................. 25
20.1 STARTUP SEQUENCE ......................................................................................................... 25
20.2 POWER-ON DEFAULT AND DEVICE ENABLE ....................................................................... 25
20.3 RESET: PIN FUNCTION ....................................................................................................... 25
20.4 STANDBY: FUNCTION ......................................................................................................... 25
20.4.1 STANDBY Pin ............................................................................................................ 25
20.4.2 STANDBY Programming via SPI .................................................................................. 26
20.5 HL_B2, HL_B3 FUNCTION .................................................................................................... 26
20.6 UNDERVOLTAGE LOCKOUT (UVLO) .................................................................................... 26
20.7 OVERVOLTAGE LOCKOUT (OVLO) ...................................................................................... 26
20.8 DEVICE STATUS, INTERRUPT ENABLE ................................................................................ 26
20.9 THERMAL SHUTDOWN (TSD) .............................................................................................. 26
20.10 COMPARATOR .................................................................................................................. 27
21.0 External Components Selection ..................................................................................................... 28
21.1 OUTPUT INDUCTORS & CAPACITORS SELECTION .............................................................. 28
21.2 INDUCTOR SELECTION ...................................................................................................... 28
21.2.1 Recommended Method for Inductor Selection: ................................................................ 28
21.2.2 Alternate Method for Inductor Selection: ........................................................................ 28
21.2.2.1 Suggested Inductors and Their Suppliers ............................................................. 28
21.2.3 OUTPUT AND INPUT CAPACITORS CHARACTERISTICS ............................................. 29
21.2.3.1 Output Capacitor Selection ................................................................................. 29
21.2.3.2 Input Capacitor Selection ................................................................................... 30
22.0 PCB Layout Considerations .......................................................................................................... 31
22.1 PCB LAYOUT THERMAL DISSIPATION FOR MICRO SMD PACKAGE ...................................... 32
23.0 Physical Dimensions .................................................................................................................... 33
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2
B2 and B3 if tied High or Low at startup, and show the part's
behavior in standby. The tables also describe the SPI-pro-
grammable output voltage range for each buck regulator as
well as the maximum output current for the buck regulators
and LDO.
6.0 Overview
The LM10506 contains three buck converters and one LDO.
Table 1 and Table 2 below list the output characteristics of the
power regulators. They explain the function of the H/L pins for
6.1 SUPPLY SPECIFICATION
TABLE 1. Output Voltage Configurations for LM10506
VOUT if
VOUT if
VOUT if
Maximum
Output
Current
Typical
Application
VOUT
Regulator
Comments
H/L=High H/L=Low STANDBY=High
(B2, B3)
(B2, B3) (STANDBY Mode)
1.1V to 3.6V;
50 mV steps
VCC
VCCQ
VCORE
Buck 1*
Buck 2*
Buck 3*
LDO
3.0V
3.0V
1.8V
1.0V
3.2V
Off
Off
1.3A
Flash
Interface
Core
1.1V to 3.6V;
50 mV steps
3.0V
1.2V
3.2V
400 mA
600 mA
100 mA
0.7V to 1.335V;
5mV steps
VNOM - 7%
3.2V
VHOST
Reference for
Digital
N/A
controller
* Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode.
TABLE 2. Output Voltage Configurations for LM10506-A
VOUT if
VOUT if
VOUT if
Maximum
Output
Current
Typical
Application
VOUT
Regulator
Comments
H/L=High H/L=Low STANDBY=High
(B2, B3)
(B2, B3) (STANDBY Mode)
1.1V to 3.6V;
50 mV steps
VCC
VCCQ
VCORE
Buck 1*
Buck 2*
Buck 3*
LDO
3.0V
3.0V
1.8V
1.0V
3.2V
Off
Off
1.3A
Flash
Interface
Core
1.1V to 3.6V;
50 mV steps
2.0V
1.2V
3.2V
400 mA
600 mA
100 mA
0.7V to 1.335V;
5mV steps
VNOM - 7%
3.2V
VHOST
Reference for
Digital
N/A
controller
* Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode.
3
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7.0 Connection Diagram and Package Marking
30166202
30166219
Note: The actual physical placement of the package marking may vary from part to part. The marking “XY” designates the date
code; “TT” is an internal code for die traceability. Both will vary in production. V037 is device identification marking.
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8.0 LM10506 Pin Descriptions
Pin #
Pin Name
I/O
Type
Functional Description
Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET,
if Buck 1 is not used, tie to ground to reduce leakage.
A/B5
VIN_B1
I
P
A/B6
A/B4
A/B7
SW_B1
FB_B1
I/O
I/O
G
P
A
P
Buck Switcher Regulator 1 - Power Switching node, connect to inductor
Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power
Buck Switcher Regulator 1 - Power ground for Buck Regulator
GND_B1
Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET,
if Buck 2 is not used, tie to ground to reduce leakage.
G3
VIN_B2
I
P
F/G2
F3
SW_B2
FB_B2
GND_B2
VIN_B3
SW_B3
FB_B3
GND_B3
VIN
I/O
I
P
A
P
P
P
A
P
P
P
Buck Switcher Regulator 2 - Power Switching node, connect to inductor
Buck Switcher Regulator 2 - Voltage output feedback
G1
G
I
Buck Switcher Regulator 2 - Power ground for Buck Regulator
Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET
Buck Switcher Regulator 3 - Power Switching node, connect to inductor
Buck Switcher Regulator 3 - Voltage output feedback
G5
F/G6
F5
I/O
I
G7
G
I
Buck Switcher Regulator 3 - Power ground for Buck Regulator
Power supply Input Voltage, must be present for device to work
LDO Regulator - LDO regulator output voltage
A3
A2
LDO
O
Digital Input Startup Control Signal to change predefined output Voltage of Buck
2, internally pulled down as a default
G4
F4
E7
F7
HL_B2
HL_B3
I
I
I
I
D
D
D
D
Digital Input Startup Control Signal to change predefined output Voltage of Buck
3, internally pulled up as a default
Digital Input Control Signal for entering Standby Mode. This is an active High pin
with an internal pulldown resistor.
STANDBY
RESET
Digital Input Control Signal to abort SPI transactions; resets the PMIC to default
voltages. This is an active Low pin with an internal pullup.
C7
A1
F1
D1
E1
C1
B1
B2
B3
D7
VCOMP
IRQ
I
O
I
A
D
D
D
D
D
A
G
G
G
Analog Input for Comparator
Digital Output of Comparator to signal interrupt condition
SPI Interface - chip select
SPI_CS
SPI_DI
SPI_DO
SPI_CLK
VIN_IO
GND
I
SPI Interface - serial data input
O
I
SPI Interface - serial data output
SPI Interface - serial clock input
I
Supply Voltage for Digital Interface
Ground. Connect to system Ground.
Ground. Connect to system Ground.
Ground. Connect to system Ground.
G
G
G
GND
GND
Type
I/O
Input Pin
Output Pin
A
D
G
P
Analog Pin
Digital Pin
I
O
Ground
Power Connection
9.0 Ordering Information
Order Number
LM10506TME
LM10506TMX
LM10506TME-A
LM10506TMX-A
Package Type
Product Identification
Supplied as
250 Tape & Reel
3000 Tape & Reel
250 Tape & Reel
3000 Tape & Reel
V037
micro SMD
V045
5
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10.0 Absolute Maximum Ratings (Note
1)
11.0 Operating Ratings
(Note 7, Note 8)
VIN_B1, VIN_B2_VIN_B3, VIN
3.0V to 5.5V
1.72V to 3.63V but < VIN
0V to VIN
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
VIN_IO
All pins except VIN_IO
Junction Temperature (TJ)
Ambient Temperature (TA)
VIN, VCOMP
−0.3V to +6.0V
−40°C to 125°C
−40°C to 85°C
VIN_IO, VIN_B1, VIN_B2, VIN_B3,
SPI_CS, SPI_DI, SPI_CLK, SPI_DO,
IRQ, HL_B2, HL_B3, STANDBY,
RESET, SW_B1, SW_B2, SW_B3,
FB_B1, FB_B2, FB_B3, LDO
Junction-to-Ambient Thermal
Resistance (θJA) (Note 7)
Maximum Continuous Power
Dissipation (PD-MAX) (Note 7)
44.5°C/W
0.9W
−0.3V to +6.0V
150°C
Junction Temperature (TJ-MAX
Storage Temperature
ESD Rating
)
−65°C to 150°C
Human Body Model (HBM)
2.0kV
12.0 General Electrical Characteristics (Note 3, Note 4) Unless otherwise noted, VIN = 5.0V where:
VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over
the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IQ(STANDBY)
Quiescent Supply Current
STANDBY = HIGH, no load
100
200
µA
UNDER/OVERVOLTAGE LOCK OUT
VUVLO_RISING
2.75
2.45
2.9
2.6
5.7
5.6
3.05
2.75
VUVLO_FALLING
V
V
VOVLO_RISING
VOVLO_FALLING
DIGITAL INTERFACE
VIL
Logic input low
Logic input high
Logic input low
Logic input high
Logic output low
Logic output high
0.3*VIN_IO
0.3*VIN
SPI_CS, SPI_DI, SPI_CLK, RESET,
STANDBY
VIH
VIL
0.7*VIN_IO
0.7*VIN
HL_B2, HL_B3
SPI_DO
VIH
VOL
VOH
0.2*VIN_IO
0.8*VIN_IO
SPI_CS, SPI_DI, SPI_CLK, HL_B2,
STANDBY
−2
−5
IIL
Input current, pin driven low
µA
µA
HL_B3, RESET
SPI_CS, SPI_DI, SPI_CLK, HL_B3,
RESET
2
IIH
Input current, pin driven high
SPI max frequency
HL_B2, STANDBY
5
fSPI_MAX
tRESET
10
MHz
µsec
2
2
Minimum high-pulse width
(Note 2)
tSTANDBY
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13.0 Buck 1 Electrical Characteristics (Note 3, Note 4, Note 6) Unless otherwise noted, VIN = 5.0V
where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply
over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IQ
DC Bias Current in VIN
Peak switching current limit
No Load, PFM Mode
Buck 1 enabled, switching in PWM
15
50
µA
IPEAK
1.6
1.8
2.1
A
Efficiency peak, Buck 1 (Note
2)
IOUT = 0.3A
90
%
MHz
µF
η
FSW
CIN
Switching Frequency
1.75
2
2.3
Input Capacitor (Note 2)
4.7
10
Output Filter Capacitor (Note 2)
Output Capacitor ESR (Note 2)
10
100
20
COUT
L
0mA ≤ IOUT ≤ 1.3A
mΩ
Output Filter Inductance (Note
2)
2.2
0.5
µH
DC Line regulation (Note 2)
DC Load regulation (Note 2)
Feedback pin input bias current
%/V
%/A
µA
3.3V ≤ VIN ≤ 5.0V, IOUT = 1.3A
ΔVOUT
IFB
0.3
2.1
135
215
85
0.13A ≤ IOUT ≤ 1.3A
VFB = 3.0V
5
RDS-ON-HS
RDS-ON-LS
High Side Switch On Resistance
Low Side Switch On Resistance
mΩ
mΩ
VIN = 2.6V
190
Used in parallel with the high side FET
while in Bypass mode. Resistance
(DCR) of inductor = 100 mΩ
RDS-ON_BYPASS
Bypass FET On Resistance
VIN = 3.3V
85
mΩ
VIN = 2.6V
120
STARTUP
Startup from shutdown, VOUT = 0V, no
Internal soft-start (turn on time) load, LC = recommended circuit, using
TSTART
0.1
ms
(Note 2)
software enable, to VOUT = 95% of final
value
7
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14.0 Buck 2 Electrical Characteristics (Note 3, Note 4, Note 6) Unless otherwise noted, VIN = 5.0V
where: VIN=VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply
over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
Symbol
Parameter
Conditions
Min
0.65
1.75
Typ
15
1.1
90
2
Max
Units
IQ
DC Bias Current in VIN
No Load, PFM Mode
50
µA
IPEAK
Peak switching current limit
Efficiency peak, Buck 2 (Note 2)
Switching Frequency
Buck 2 enabled, switching in PWM
IOUT = 0.3A
1.55
A
%
η
FSW
2.3
MHz
CIN
Input Capacitor (Note 2)
4.7
µF
Output Filter Capacitor
(Note 2)
10
10
100
20
COUT
L
0mA ≤ IOUT ≤ 400 mA
Output Capacitor ESR (Note 2)
Output Filter Inductance (Note 2)
DC Line regulation (Note 2)
mΩ
µH
2.2
0.5
%/V
3.3V ≤ VIN ≤ 5.0V, IOUT = 400 mA
ΔVOUT
IFB
DC Load regulation (Note 2)
0.3
1.8
135
260
85
%/A
µA
100 mA ≤ IOUT ≤ 400 mA
VFB = 1.8V
Feedback pin input bias current
5
RDS-ON-HS
High Side Switch On Resistance
Low Side Switch On Resistance
VIN = 2.6V
mΩ
RDS-ON-LS
190
STARTUP
Startup from shutdown, VOUT = 0V, no
load, LC = recommended circuit, using
software enable, to VOUT = 95% of final
value
Internal soft-start (turn on time)
(Note 2)
TSTART
0.1
ms
15.0 Buck 3 Electrical Characteristics (Note 3, Note 4, Note 6) Unless otherwise noted, VIN = 5.0V
where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply
over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
Symbol
Parameter
Conditions
Min
Typ
15
1.2
90
2
Max
Units
IQ
DC Bias Current in VIN
No Load, PFM Mode
Buck 3 enabled, switching in PWM
IOUT = 0.3A
50
µA
IPEAK
Peak switching current limit
Efficiency peak, Buck 3 (Note 2)
Switching Frequency
0.9
1.7
A
%
η
FSW
1.75
10
2.3
MHz
CIN
Input Capacitor (Note 2)
Output Filter Capacitor (Note 2)
Output Capacitor ESR (Note 2)
Output Filter Inductance (Note 2)
DC Line regulation (Note 2)
4.7
10
µF
100
20
COUT
L
0mA ≤ IOUT ≤ 600 mA
mΩ
µH
2.2
0.5
%/V
3.3V ≤ VIN ≤ 5.0V, IOUT = 600 mA
ΔVOUT
IFB
DC Load regulation (Note 2)
0.3
0.9
135
260
85
%/A
µA
150 mA ≤ IOUT ≤ 600 mA
VFB = 1.2V
Feedback pin input bias current
5
RDS-ON-HS
High Side Switch On Resistance
Low Side Switch On Resistance
VIN = 2.6V
mΩ
RDS-ON-LS
190
STARTUP
Startup from shutdown, VOUT = 0V, no
load, LC = recommended circuit, using
software enable, to VOUT = 95% of final
value
Internal soft-start (turn on time)
(Note 2)
TSTART
0.1
ms
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16.0 LDO Electrical Characteristics (Note 3, Note 4) Unless otherwise noted, VIN = 5.0V where: VIN
VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the
entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
=
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOUT
IOUT = 1mA
VOUT = 0V
Output Voltage Accuracy
−3
+3
%
0.3
0.5
60
5
ISC
Short-Circuit Current Limit
A
VIN = 3.3V,VOUT = 0V (Note 2)
VDO
IOUT = 100 mA
Dropout Voltage
Line Regulation
Load Regulation
100
3.3V ≤ VIN ≤ 5.5V, IOUT = 1mA
mV
ΔVOUT
5
1mA ≤ IOUT ≤ 100 mA, VIN = 3.3V, 5.0V
VIN = 5.0V
10
35
65
40
45
60
Output Noise Voltage
(Note 2)
eN
µVRMS
dB
10 Hz ≤ f ≤ 100 kHz
VIN = 3.3V
VIN = 5.0V
F = 10 kHz, COUT = 4.7 µF,
Power Supply Rejection
Ratio (Note 2)
PSRR
IOUT = 20 mA
VIN = 3.3V
VIN = 5.0V
VIN = 3.3V
µs
COUT = 4.7 µF IOUT = 100
mA
Startup Time from
Shutdown (Note 2)
tSTARTUP
TTRANSIENT
Startup Transient
Overshoot (Note 2)
COUT = 4.7 µF IOUT = 100 mA
30
mV
17.0 Comparators Electrical Characteristics (Note 3, Note 4) Unless otherwise noted, VIN = 5.0V
where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply
over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ +85°C.
Symbol
IVCOMP
VCOMP_RISE
VCOMP_FALL
Parameter
Conditions
VCOMP = 0.0V
VCOMP = 5.0V
Min
Typ
0.1
0.1
Max
Units
2
VCOMP pin bias current
µA
2
Comparator rising edge trigger
level
2.826
V
Comparator falling edge trigger
level
2.768
60
Hysteresis
IRQVOH
IRQVOL
tCOMP
30
80
mV
V
Output voltage high
0.8*VIN_IO
Output voltage low
0.2*VIN_IO
Transition time of IRQ output
6
15
µsec
9
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Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: Specification guaranteed by design. Not tested during production.
Note 3: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production
with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Note 4: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Note 5: Internal thermal shutdown protects device from permanent damage. Thermal shutdown engages at TJ = +140°C and disengages at TJ = +120°C (typ.).
Thermal shutdown is guaranteed by design.
Note 6: BUCK normal operation is guaranteed if VIN ≥ VOUT+1.0V.
Note 7: In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to be derated.
Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C), the maximum power dissipation of
the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation:
TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 8: The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula:
P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. θJA is highly application
and board-layout dependent. Internal thermal shutdown circuitry protects the device from permanent damage. (See General Electrical Characteristics.)
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18.0 Typical Performance Characteristics
Efficiency of Buck 1: VIN=5.0V, VOUT=3.0V
Efficiency of Buck 2: VIN=5.0V, VOUT=1.8V and 3.0V
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
VOUT = 1.8V
VOUT = 3.0V
30
20
1
10
100
(mA)
1k
10k
1
10
I
100
(mA)
1000
I
OUT
OUT
30166233
30166234
Startup of Buck 1: VIN=3.3V
(VOUT=3.0V, IOUT=1.0A)
Startup of Buck 1: VIN=5.0V
(VOUT=3.0V, IOUT=1.0A)
30166232
30166237
LDO VOUT vs. IOUT
LDO VIN vs. VOUT
3210
3208
3206
3204
3202
3200
3198
3196
3194
3192
3190
3.210
3.208
3.206
3.204
3.202
3.200
3.198
3.196
3.194
3.192
3.190
IOUT = 1mA
IOUT = 100mA
VIN = 5.0V
VIN = 3.3V
0
20
40
I
60
(mA)
80
100 120
3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
V
OUT
IN
30166251
30166236
11
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Buck 1 VOUT vs. IOUT
VIN=5.0V, VOUT=3.0V
Buck 2 VOUT vs. IOUT
VIN=5.0V, VOUT=1.8V
3000
2998
2996
2994
2992
2990
2988
2986
2984
2982
2980
1810
1808
1806
1804
1802
1800
1798
1796
1794
1792
1790
100 300 500 700 900 1100 1300
(mA)
100 150 200 250 300 350 400
(mA)
I
I
OUT
OUT
30166246
30166248
Buck 2 VOUT vs. IOUT
VIN=5.0V, VOUT=3.0V
Buck 3 VOUT vs. IOUT
VIN=5.0V, VOUT=1.0V
3010
3008
3006
3004
3002
3000
2998
2996
2994
2992
2990
1015
1013
1011
1009
1007
1005
1003
1001
999
997
995
100 150 200 250 300 350 400
(mA)
150 200 250 300 350 400 450 500 550 600
(mA)
I
I
OUT
OUT
30166250
30166247
Buck 3 VOUT vs. IOUT
VIN=5.0V, VOUT=1.2V
Buck 2 VOUT vs. VIN
VOUT=1.8V, IOUT=400mA
1213
1211
1209
1207
1205
1203
1201
1199
1197
1195
1193
1.805
1.800
1.795
1.790
1.785
1.780
1.775
150 200 250 300 350 400 450 500 550 600
(mA)
3.0
3.5
4.0
(V)
4.5
5.0
I
V
OUT
IN
30166249
30166242
www.ti.com
12
Buck 2 VOUT vs. VIN
VOUT=3.0V, IOUT=400mA
Buck 3 VOUT vs VIN
VOUT=1.0V, IOUT=600mA
3.000
2.995
2.990
2.985
2.980
2.975
2.970
1.015
1.010
1.005
1.000
0.995
0.990
0.985
3.5
4.0
4.5
5.0
3.0
3.5
4.0
(V)
4.5
5.0
V
(V)
V
IN
IN
30166243
30166244
Buck 3 VOUT vs VIN
LDO Startup Time from VIN Rise
VOUT=1.2V, IOUT=600mA
1.215
1.210
1.205
1.200
1.195
1.190
1.185
30166238
3.0
3.5
4.0
(V)
4.5
5.0
V
IN
30166245
From LDO Startup to Buck 1 Startup
From Buck 1 Startup to Buck 2 Startup
30166239
30166240
13
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From Buck 2 Startup to Buck 3 Startup
30166241
www.ti.com
14
The device incorporates three high-efficiency synchronous
buck regulators and one LDO that deliver four output voltages
from a single power source. The device also includes a SPI-
programmable Comparator Block that provides an interrupt
output signal.
19.0 General Description
LM10506 is a highly efficient and integrated Power Manage-
ment Unit for Systems-on-a-Chip (SoCs), ASICs, and pro-
cessors. It operates cooperatively and communicates with
processors over an SPI interface with output Voltage pro-
grammability and Standby Mode.
30166204
FIGURE 1. Internal Block Diagram of the LM10506 PMIC
15
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19.1 SPI DATA INTERFACE
By accessing the registers in the device through this interface,
the user can get access and control the operation of the buck
controllers and program the reference voltage of the com-
parator in the device.
The device is programmable via 4-wire SPI Interface. The
signals associated with this interface are CS, DI, DO and CLK.
Through this interface, the user can enable/disable the de-
vice, program the output voltages of the individual Bucks and
of course read the status of Flag registers.
30166210
FIGURE 2. SPI Interface Write
•
Data In (DI)
•
Data Out (DO)
All Os
—
1 to 0 Write Command
—
—
—
A4to A0 Register address to be written
D7 to D0 Data to be written
30166227
FIGURE 3. SPI Interface Read
•
Data In (DI)
•
Data Out (DO)
D7 to D0 Data Read
—
1 to 1 Read Command
—
—
A4to A0 Register address to be read
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16
19.1.1 Registers Configurable Via The SPI Interface
Addr
Reg Name
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
R/W
—
Default
Description
Notes
Reset default:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Buck 3 Voltage Code[6]
Buck 3 Voltage Code[5]
Buck 3 Voltage Code[4]
HL_B3=1 → 0x64 (1.2V)
HL_B3=0 → 0x3C (1.0V)
0x00 Buck 3 Voltage
See Notes
Buck 3 Voltage Code[3] Range: 0.7V to 1.335V
Buck 3 Voltage Code[2]
Buck 3 Voltage Code[1]
Buck 3 Voltage Code[0]
Reset default:
0x26 (3.0V)
—
R/W
R/W
R/W
R/W
R/W
R/W
—
Buck 1 Voltage Code[5]
Buck 1 Voltage Code[4] Range: 1.1V to 3.6V
Buck 1 Voltage Code[3]
Buck 1 Voltage Code[2]
Buck 1 Voltage Code[1]
Buck 1 Voltage Code[0]
Reset default:
0x07 Buck 1 Voltage
See Notes
HL_B2=1 → 0x26 (3.0V)/
0x12 (2.0V for LM10506−A)
6
—
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Buck 2 Voltage Code[5]
HL_B2=0 → 0x0E (1.8V)
0x08 Buck 2 Voltage
See Notes
Buck 2 Voltage Code[4]
Buck 2 Voltage Code[3] Range: 1.1V to 3.6V
Buck 2 Voltage Code[2]
Buck 2 Voltage Code[1]
Buck 2 Voltage Code[0]
Reset default:
Buck 3 Voltage Code[6]
HL_B3=1 → 0x53 (1.115V)
HL_B3=0 → 0x2E (0.93V)
Buck 3 Voltage Code[5]
Standby Mode
0x09 Voltage for
Buck 3
Buck 3 Voltage Code[4]
Buck 3 Voltage Code[3]
Buck 3 Voltage Code[2]
Buck 3 Voltage Code[1]
Buck 3 Voltage Code[0]
See Notes
BK3EN
Reads Buck 3 enable status
1
—
—
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
BK1FPWM
BK2FPWM
BK3FPWM
BK1EN
Buck 1 forced PWM mode when high
Buck 2 forced PWM mode when high
Buck 3 forced PWM mode when high
Enables Buck 1 0-disabled, 1-enabled
Enables Buck 2 0-disabled, 1-enabled
0x0A Buck Control
BK2EN
17
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Addr
Reg Name
Bit
R/W
Default
Description
Comp_hyst[0]
Notes
7
R/W
Doubles Comparator hysteresis
0
Programmable range of 2.0V to 4.0V, step
size = 31.75 mV
6
R/W
0
Comp_thres[5]
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
—
1
1
0
0
1
1
Comp_thres[4]
Comp_thres[3]
Comp_thres[2]
Comp_thres[1]
Comp_thres[0]
COMPEN
Comparator Threshold reset default: 0x19
Comparator
Control
0x0B
Comp_hyst=1 → min 80 mV hysteresis
Comp_hyst=0 → min 40 mV hysteresis
Comparator enable
—
—
LDO OK
R/W
R/W
R/W
R/W
R/W
—
0
0
0
0
1
0x0C Interrupt Enable
Buck 3 OK
Buck 2 OK
Buck 1 OK
Comparator
Interrupt comp event
—
—
R
LDO OK
LDO is greater than 90% of target
Buck 3 is greater than 90% of target
Buck 2 is greater than 90% of target
Buck 1 is greater than 90% of target
Comparator output is high
0x0D Interrupt Status
R
Buck 3 OK
Buck 2 OK
Buck 1 OK
Comparator
R
R
R
—
—
—
—
0x0E MISC Control
—
—
R/W
0
0
LDO Sleep Mode
IRQ Polarity
LDO goes into extra power save mode
IRQ_polarity=0→Active low IRQ
IRQ_polarity=1→Active high IRQ
0
R/W
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18
19.1.1.1 ADDR 0x07& 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping
Voltage code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Voltage
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
Voltage code
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Voltage
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
3.60
19
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19.1.1.2 ADDR 0x00 & 0x09: Buck 3 Voltage Code and VOUT Level Mapping
Voltage Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Voltage
0.700
0.705
0.710
0.715
0.720
0.725
0.730
0.735
0.740
0.745
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
0.825
0.830
0.835
0.840
0.845
0.850
0.855
Voltage Code
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Voltage
0.860
0.865
0.870
0.875
0.880
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0.930
0.935
0.940
0.945
0.950
0.955
0.960
0.965
0.970
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
Voltage Code
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
Voltage
1.020
1.025
1.030
1.035
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
1.095
1.100
1.105
1.110
1.115
1.120
1.125
1.130
1.135
1.140
1.145
1.150
1.155
1.160
1.165
1.170
1.175
Voltage Code
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Voltage
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
1.325
1.330
1.335
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20
19.1.1.3 ADDR 0x0B: Comparator Threshold Mapping
Voltage code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Voltage
2.000
2.032
2.064
2.095
2.127
2.159
2.191
2.222
2.254
2.286
2.318
2.349
2.381
2.413
2.445
2.476
2.508
2.540
2.572
2.603
2.635
2.667
2.699
2.730
2.762
2.794
2.826
2.857
2.889
2.921
2.953
2.984
Voltage code
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Voltage
3.016
3.048
3.080
3.111
3.143
3.175
3.207
3.238
3.270
3.302
3.334
3.365
3.397
3.429
3.461
3.492
3.524
3.556
3.588
3.619
3.651
3.683
3.715
3.746
3.778
3.810
3.842
3.873
3.905
3.937
3.969
4.000
21
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19.2 BUCK REGULATORS OPERATION
ing NFET connected between the output and ground and a
feedback path. The following figure shows the block diagram
of each of the three buck regulators integrated in the device.
A buck converter contains a control block, a switching PFET
connected between input and output, a synchronous rectify-
30166208
FIGURE 4. Buck Functional Diagram
During the first portion of each switching cycle, the control
block turns on the internal PFET switch. This allows current
to flow from the input through the inductor to the output filter
capacitor and load. The inductor limits the current to a ramp
with a slope of (VIN – VOUT)/L by storing energy in a magnetic
field. During the second portion of each cycle, the control
block turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The
inductor draws current from ground through the NFET to the
output filter capacitor and load, which ramps the inductor cur-
rent down with a slope of (–VOUT)/L.
of the output. The lowest input to output dropout voltage is
achieved by keeping the PMOS switch on.
Additional features include soft-start, undervoltage lockout,
bypass, and current and thermal overload protection. To re-
duce the input current ripple, the device employs a control
circuit that operates the 3 bucks at 120° phase. These bucks
are nearly identical in performance and mode of operation.
They can operate in FPWM (forced PWM) or automatic mode
(PWM/PFM).
19.2.2 PWM Operation
During PWM operation the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, a feed forward voltage
inversely proportional to the input voltage is introduced.
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load. The output voltage is regulated by modulating the
PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated
rectangular wave formed by the switch and synchronous rec-
tifier at the SW pin to a low-pass filter formed by the inductor
and output filter capacitor. The output voltage is equal to the
average voltage at the SW pin.
In Forced PWM Mode the bucks always operate in PWM
mode regardless of the output current.
In Automatic Mode, if the output current is less than 70 mA
(typ.), the bucks automatically transition into PFM (Pulse Fre-
quency Modulation) operation to reduce the current con-
sumption. At higher than 100 mA (typ.) they operate in PWM
mode. This increases the efficiency at lower output currents.
The 30 mA (typ.) hysteresis is designed in for stable Mode
transition.
19.2.1 Buck Regulators Description
The LM10506 incorporates three high-efficiency synchronous
switching buck regulators that deliver various voltages from a
single DC input voltage. They include many advanced fea-
tures to achieve excellent voltage regulation, high efficiency
and fast transient response time. The bucks feature voltage
mode architecture with synchronous rectification.
While in PWM mode, the output voltage is regulated by
switching at a constant frequency and then modulating the
energy per cycle to control power to the load. At the beginning
of each clock cycle the PFET switch is turned on, and the
inductor current ramps up until the comparator trips and the
control logic turns off the switch. The current limit comparator
can also turn off the switch in case the current limit of the
PFET is exceeded. In this case the NFET switch is turned on
and the inductor current ramps down. The next cycle is initi-
ated by the clock turning off the NFET and turning on the
PFET.
Each of the switching regulators is specially designed for
high-efficiency operation throughout the load range. With a
2MHz typical switching frequency, the external L- C filter can
be small and still provide very low output voltage ripple. The
bucks are internally compensated to be stable with the rec-
ommended external inductors and capacitors as detailed in
the application diagram. Synchronous rectification yields high
efficiency for low voltage and high output currents.
All bucks can operate up to a 100% duty cycle allowing for the
lowest possible input voltage that still maintains the regulation
www.ti.com
22
30166209
FIGURE 5. PFM vs PWM Operation
19.2.3 PFM Operation (Bucks 1, 2 & 3)
achieve high efficiencies under extremely light load condi-
tions. When the output drops below the ‘low’ PFM threshold,
the cycle repeats to restore the output voltage to ~1.6% above
the nominal PWM output voltage.
At very light loads, Buck 1, 2 and Buck 3 enter PFM mode and
operate with reduced switching frequency and supply current
to maintain high efficiency.
If the load current should increase during PFM mode causing
the output voltage to fall below the ‘low2’ PFM threshold, the
part will automatically transition into fixed-frequency PWM
mode.
Buck 1, 2 and 3 will automatically transition into PFM mode
when either of two conditions occurs for a duration of 32 or
more clock cycles:
1. The inductor current becomes discontinuous, or
2. The peak PMOS switch current drops below the IMODE
level.
19.2.4 Soft Start
Each of the buck converters has an internal soft-start circuit
that limits the in-rush current during startup. This allows the
converters to gradually reach the steady-state operating
point, thus reducing startup stresses and surges. During start-
up, the switch current limit is increased in steps.
During PFM operation, the converter positions the output volt-
age slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The PFM
comparators sense the output voltage via the feedback pin
and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical) above
the nominal PWM output voltage. If the output voltage is be-
low the ‘high’ PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage ex-
ceeds the ‘high’ PFM threshold or the peak current exceeds
the IPFM level set for PFM mode.
For Buck 1, 2 and 3 the soft start is implemented by increas-
ing the switch current limit in steps that are gradually set
higher. The startup time depends on the output capacitor size,
load current and output voltage. Typical startup time with the
recommended output capacitor of 10 µF is 0.2 to 1ms. It is
expected that in the final application the load current condition
will be more likely in the lower load current range during the
start up.
Once the PMOS power switch is turned off, the NMOS power
switch is turned on until the inductor current ramps to zero.
When the NMOS zero-current condition is detected, the
NMOS power switch is turned off. If the output voltage is be-
low the ‘high’ PFM comparator threshold (see Figure 5), the
PMOS switch is again turned on and the cycle is repeated
until the output reaches the desired level. Once the output
reaches the ‘high’ PFM threshold, the NMOS switch is turned
on briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an ex-
tremely low power mode. Quiescent supply current during this
‘idle’ mode is less than 100 µA, which allows the part to
19.2.5 Current Limiting
A current limit feature protects the device and any external
components during overload conditions. In PWM mode the
current limiting is implemented by using an internal compara-
tor that trips at current levels according to the buck capability.
If the output is shorted to ground the device enters a timed
current limit mode where the NFET is turned on for a longer
duration until the inductor current falls below a low threshold,
ensuring inductor current has more time to decay, thereby
preventing runaway.
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19.2.6 Internal Synchronous Rectification
bypass mode or standard switching regulation is constantly
monitored while the regulators are enabled. If at any time the
input voltage goes above 3.5V (2.6V for Buck 2) while in by-
pass mode, the regulators will transition to normal operation.
While in PWM mode, the bucks use an internal NFET as a
synchronous rectifier to reduce the rectifier forward voltage
drop and the associated power loss. Synchronous rectifica-
tion provides a significant improvement in efficiency whenev-
er the output voltage is relatively low compared to the voltage
drop across an ordinary rectifier diode.
When the bypass mode is enabled, the output voltage of the
buck that is in bypass mode is not regulated, but instead, the
output voltage follows the input voltage minus the voltage
drop seen across the FET and DCR of the inductor. The volt-
age drop is a direct result of the current flowing across those
resistive elements. When Buck 1 transitions into bypass
mode, there is an extra FET used in parallel along with the
high side FET for transmission of the current to the load. This
added FET will help reduce the resistance seen by the load
and decrease the voltage drop. For Buck 2, the bypass func-
tion uses the same high side FET.
19.2.7 Bypass-FET Operation on Buck 1 and Buck 2
There is an additional bypass FET used on Buck 1. The FET
is connected in parallel to High Side FET and inductor. Buck
2 has no extra bypass FET – it uses High Side FET (PFET)
for bypass operation. If Buck 1 input voltage is greater than
3.5V (2.6V for Buck 2), the bypass function is disabled. The
determination of whether or not the Buck regulators are in
30166212
19.2.8 Low Dropout Operation
The minimum input voltage needed to support the output volt-
age:
The device can operate at 100% duty cycle (no switching;
PMOS switch completely on) for low dropout support. In this
way the output voltage will be controlled down to the lowest
possible input voltage. When the device operates near 100%
duty cycle, output voltage ripple is approximately 25 mV.
VIN_MIN=VOUT+ILOAD*(RDSON_PFET+RIND), where
•
•
ILOAD = Load Current
RDSON_PFET = Drain to source resistance of PFET (high
side) switch in the triode region
•
RIND = Inductor resistance
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24
The Startup Sequence will be:
1. 15 msec (±30%) delay after VIN above UVLO
2.
20.0 Device Operating Modes
20.1 STARTUP SEQUENCE
LDO → 3.2V → 3.2V
The startup mode of the LM10506 will depend on the input
voltage. Once VIN reaches the UVLO threshold, there is a 15
msec delay before the LM10506 determines how to set up the
buck regulators. If VIN is below 3.6V, then Buck 1 and Buck 2
will be in bypass mode, see Section 19.2.7 Bypass-FET Op-
eration on Buck 1 and Buck 2 for functionality description. If
the VIN voltage is greater than 3.6V the bucks will start up as
the standard regulators. The 3 buck regulators are staggered
during startup to avoid large inrush currents. There is a fixed
delay of 2 msec between the startup of each regulator.
3. 2 msec delay
4. Buck 1 → 3.0V → 3.0V
5. 2 msec delay
6. Buck 2 → 3.0V or if H/L_B2 = Low → 1.8V
(For LM10506-A Buck 2 → 2.0V or if H/L_B2 = Low →
1.8V)
7. 2 msec delay
8. Buck 3 → 1.2V or if H/L_B3 = Low → 1.0V
30166206
FIGURE 6. Operating Modes
20.2 POWER-ON DEFAULT AND DEVICE ENABLE
age settings on the regulators will go back to their default
states.
The device is always enabled and the LDO is always on, un-
less outside of operating voltage range. There is no LM10506
Enable Pin. Once VIN reaches a minimum required input Volt-
age the power-up sequence will be started automatically and
the startup sequence will be initiated. Once the device is
started, the output voltage of the Bucks 1 and 2 can be indi-
vidually disabled by accessing their corresponding BKEN
register bits (BUCK CONTROL).
20.4 STANDBY: FUNCTION
The Device can be programmed into Standby mode. There
are 2 ways for doing that:
1. STANDBY pin
2. Programming via SPI
20.4.1 STANDBY Pin
20.3 RESET: PIN FUNCTION
When the STANDBY pin is asserted high, the LM10506 will
enter Standby Mode. While in Standby Mode, Buck 1 and
Buck 2 are disabled. Buck 3’s output voltage is transitioned
to the PSML (Programmable Standby Mode Level) as set by
The RESET pin is internally pulled high. If the reset pin is
pulled low, the device will perform a complete reset of all the
registers to their default states. This means that all of the volt-
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register 0x09. The STANDBY pin is internally pulled down,
and there is a 1 second delay during powerup before the state
of the STANDBY pin is checked. Note: If Buck 1 and Buck 2
are already disabled, and the STANDBY pin is asserted high,
then Buck 3 will not go to PSML – for further instructions, see
Section 20.4.2 STANDBY Programming via SPI.
unstable operation, the undervoltage lockout (UVLO) has a
hysteresis window of about 300 mV. An UVLO will force the
device into the reset state, all internal registers are reset.
Once the supply voltage is above the UVLO hysteresis, the
device will initiate a power-up sequence and then enter the
active state.
Bucks 1 and 2 will be ramped down when the disable signal
is given. Buck 1 starts ramping 2ms after Buck 2 has started
ramping.
Buck 1 and Buck 2 will remain in bypass mode after VIN pass-
es the UVLO until VIN reaches approximately 1.9V. When
Buck 2 is set to 1.8V, the voltage will jump from 1.8V to
VUVLO_FALLING, and then follow VIN.
Entering Standby Sequence will be:
1. Buck 3 → PSML (Programmable Standby Mode Level)
2. 2 msec delay
The LDO and the Comparator will remain functional past the
UVLO threshold until VIN reaches approximately 2.25V.
3. Buck 2 → Disabled
20.7 OVERVOLTAGE LOCKOUT (OVLO)
4. 2 msec delay
The VIN voltage is monitored for a supply over voltage condi-
tion, for which the operation of the device cannot be guaran-
teed. The purpose of overvoltage lockout (OVLO) is to protect
the part and all other consumers connected to the PMU out-
puts from any damage and malfunction. Once VIN rises over
5.7V all the Bucks, and LDO will be disabled automatically.
To prevent unstable operation, the OVLO has a hysteresis
window of about 100 mV. An OVLO will force the device into
the reset state; all internal registers are reset. Once the supply
voltage is below the OVLO hysteresis, the device will initiate
a power-up sequence, and then enter the active state. Oper-
ating maximum input voltage at which parameters are guar-
anteed is 5.5V. Absolute maximum of the device is 6.0V.
5. Buck 1 → Disabled
An internal 22 kΩ pull down resistor (±30%) is attached to the
FB pin of Buck 1 and Buck 2. Buck 1 and 2 outputs are pulled
to ground level when they are disabled to discharge any
residual charge present in the output circuitry. When STAND-
BY transitions to a low, Buck 1 is again enabled followed by
Buck 2. Buck 3 will go back to its previous state.
When waking up from Standby, the sequence will be:
1. Buck 1 → Previous State
2. 2 msec delay
3. Buck 2 and Buck 3 transition together → Previous State
20.8 DEVICE STATUS, INTERRUPT ENABLE
20.4.2 STANDBY Programming via SPI
The LM10506 has 2 interrupt registers, INTERRUPT EN-
ABLE and INTERRUPT STATUS. These registers can be
read via the serial interface. The interrupts are not latched to
the register and will always represent the current state and
will not be cleared on a read.
There is no bit which has the same function as STANDBY
PIN. There is only one requirement programming LM10506
into Standby Mode via SPI. Setting LDO Sleep Mode bit high
must be the last move when entering Standby Mode and pro-
gramming the bit low when waking from Standby Mode must
be the first move. Disabling or programming the Bucks to new
level is the user’s decision based on power consumption and
other requirements.
If interrupt condition is detected, then corresponding bit in the
INTERRUPT STATUS register (0x0D) is set to '1', and IRQ
output is asserted. There are 5 interrupt generating condi-
tions:
The following section describes how to program the chip into
Standby Mode corresponding to STANDBY PIN function. To
program the LM10506 to Standby Mode via SPI Buck 1 and
Buck 2 must be disabled by host device (Register 0x0A bit 1
and 0). Buck 3 must be programmed to desired level using
Register 0x00. After Buck 3 has finished ramping LDO Sleep
Mode bit must be set high (Register 0x0E bit 1). To wake
LM10506 from Standby Mode LDO Sleep Mode bit must be
set low (Register 0x0E bit 1). Buck 1 and 2 must be enabled.
Buck 3 voltage must be programmed to previous output level.
•
•
•
Buck 3 output is over flag level (90% when rising, 85%
when falling)
Buck 2 output is over flag level (90% when rising, 85%
when falling)
Buck 1 output is over flag level (90% when rising, 85%
when falling)
•
•
LDO is over flag level (90% when rising, 85% when falling
Comparator input voltage crosses over selected threshold
Reading the interrupt register will not release IRQ output. In-
terrupt generation conditions can be individually enabled or
disabled by writing respective bits in INTERRUPT ENABLE
register (0x0C) to '1' or '0'.
20.5 HL_B2, HL_B3 FUNCTION
The HL_B2/3 pins are digital pins which control alternate volt-
age selections of Buck 2 and Buck 3, respectively. HL_B2 has
an internal pulldown which defaults to a 1.8V output voltage
selection for Buck 2. Alternatively, if HL_B2 is driven high, an
output voltage of 3.0V (or 2.0V for LM10506-A) is selected.
HL_B3 has an internal pullup which defaults to a 1.2V output
voltage selection for Buck 3. Alternatively, if HL_B3 is driven
low, an output voltage of 1.0V is selected. The pullup resistor
is connected to the main input voltage. Transitions of the pins
will not affect the output voltage, the state is only checked
during startup.
20.9 THERMAL SHUTDOWN (TSD)
The temperature of the silicon die is monitored for an over-
temperature condition, for which the operation of the device
can not be guaranteed. The part will automatically be disabled
if the temperature is too high. The thermal shutdown (TSD)
will force the device into the reset state. In reset, all circuitry
is disabled. To prevent unstable operation, the TSD has a
hysteresis window of about 20°C. Once the temperature has
decreased below the TSD hysteresis, the device will initiate
a powerup sequence and then enter the active state. In the
active state, the part will start up as if for the first time, all
registers will be in their default state.
20.6 UNDERVOLTAGE LOCKOUT (UVLO)
The VIN voltage is monitored for a supply under voltage con-
dition, for which the operation of the device can not be guar-
anteed. The part will automatically disable Buck 3. To prevent
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26
20.10 COMPARATOR
output is high if the VCOMP value is less than the threshold
level. If IRQ_polarity = 1 → Active high is selected then the
output is high if VCOMP value is greater than the threshold lev-
el. The output is low if the VCOMP value is less than the
threshold level. There is some hysteresis when VCOMP tran-
sitions from high to low, typically 60 mV. There is a control bit
in register 0x0B, comparator control, that can double the hys-
teresis value.
The comparator on the LM10506 takes its inputs from the
VCOMP pin and an internal threshold level which is pro-
grammed by the user. The threshold level is programmable
between 2.0 and 4.0V with a step of 31 mV and a default comp
code of 0x19. The output of the comparator is the IRQ pin. Its
polarity can be changed using Register 0x0E bit 0. If IRQ_po-
larity = 0 → Active low (default) is selected, then the output is
low if VCOMP value is greater than the threshold level. The
30166207
27
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21.2.1 Recommended Method for Inductor Selection:
21.0 External Components
Selection
All three switchers require an input capacitor and an output
inductor-capacitor filter. These components are critical to the
performance of the device. All three switchers are internally
compensated and do not require external components to
achieve stable operation. The output voltages of the bucks
can be programmed through the SPI pins.
The best way to guarantee the inductor does not saturate is
to choose an inductor that has saturation current rating
greater than the maximum device current limit, as specified
in the Electrical Characteristics tables. In this case the device
will prevent inductor saturation by going into current limit be-
fore the saturation level is reached.
21.2.2 Alternate Method for Inductor Selection:
If the recommended approach cannot be used care must be
taken to guarantee that the saturation current is greater than
the peak inductor current:
21.1 OUTPUT INDUCTORS & CAPACITORS SELECTION
There are several design considerations related to the selec-
tion of output inductors and capacitors:
•
•
•
•
•
Load transient response
Stability
Efficiency
Output ripple voltage
Over current ruggedness
The device has been optimized for use with nominal LC val-
ues as shown in the Typical Application Circuit (page 1).
21.2 INDUCTOR SELECTION
ISAT
:
Inductor saturation current at operating tempera-
ture
The recommended inductor values are shown in Section 5.0
Typical Application Diagram. It is important to guarantee the
inductor core does not saturate during any foreseeable oper-
ational situation. The inductor should be rated to handle the
peak load current plus the ripple current:
ILPEAK
:
Peak inductor current during worst case conditions
IOUTMAX: Maximum average inductor current
IRIPPLE
:
Peak-to-Peak inductor current
Output voltage
Care should be taken when reviewing the different saturation
current ratings that are specified by different manufacturers.
Saturation current ratings are typically specified at 25°C, so
ratings at maximum ambient temperature of the application
should be requested from the manufacturer.
VOUT
VIN:
L:
:
Input voltage
Inductor value in Henries at IOUTMAX
Switching frequency, Hertz
Estimated duty factor
F:
D:
EFF:
Estimated power supply efficiency
ISAT may not be exceeded during any operation, including
transients, startup, high temperature, worst-case conditions,
etc.
21.2.2.1 Suggested Inductors and Their Suppliers
The designer should choose the inductors that best match the
system requirements. A very wide range of inductors are
available as regarding physical size, height, maximum current
(thermally limited, and inductance loss limited), series resis-
tance, maximum operating frequency, losses, etc. In general,
smaller physical size inductors will have higher series resis-
tance (DCR) and implicitly lower overall efficiency is
achieved. Very low-profile inductors may have even higher
series resistance. The designer should try to find the best
compromise between system performance and cost.
There are two methods to choose the inductor saturation cur-
rent rating:
TABLE 3. Recommended Inductors
Value
2.2 µH
2.2 µH
2.2 µH
Manufacturer
Murata
Part Number DCR
Current
2.5A
Package
2220
LQH55PN2R2NR0L
NLC565050T-2R2K-PF
LQM2MPN2R2NG0
31 mΩ
60 mΩ
110 mΩ
TDK
1.3A
2220
Murata
1.2A
806
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21.2.3 OUTPUT AND INPUT CAPACITORS
CHARACTERISTICS
0.47 µF to 44 µF range. Another important consideration is
that tantalum capacitors have higher ESR values than equiv-
alent size ceramics. This means that while it may be possible
to find a tantalum capacitor with an ESR value within the sta-
ble range, it would have to be larger in capacitance (which
means bigger and more costly) than a ceramic capacitor with
the same ESR value. It should also be noted that the ESR of
a typical tantalum will increase about 2:1 as the temperature
goes from 25°C down to −40°C, so some guard band must
be allowed.
Special attention should be paid when selecting these com-
ponents. As shown in the following figure, the DC bias of these
capacitors can result in a capacitance value that falls below
the minimum value given in the recommended capacitor
specifications table. Note that the graph shows the capaci-
tance out of spec for the 0402 case size capacitor at higher
bias voltages. It is therefore recommended that the capacitor
manufacturers’ specifications for the nominal value capacitor
are consulted for all conditions, as some capacitor sizes (e.g.,
0402) may not be suitable in the actual application.
21.2.3.1 Output Capacitor Selection
The output capacitor of a switching converter absorbs the AC
ripple current from the inductor and provides the initial re-
sponse to a load transient. The ripple voltage at the output of
the converter is the product of the ripple current flowing
through the output capacitor and the impedance of the ca-
pacitor. The impedance of the capacitor can be dominated by
capacitive, resistive, or inductive elements within the capaci-
tor, depending on the frequency of the ripple current. Ceramic
capacitors have very low ESR and remain capacitive up to
high frequencies. Their inductive component can usually be
neglected at the frequency ranges at which the switcher op-
erates.
30166215
FIGURE 7. Typical Variation in Capacitance vs.
DC Bias
30166216
The output-filter capacitor smooths out the current flow from
the inductor to the load and helps maintain a steady output
voltage during transient load changes. It also reduces output
voltage ripple. These capacitors must be selected with suffi-
cient capacitance and low enough ESR to perform these
functions.
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a temper-
ature range of −55°C to +125°C, will only vary the capacitance
to within ±15%. The capacitor type X5R has a similar toler-
ance over a reduced temperature range of −55°C to +85°C.
Many large value ceramic capacitors, larger than 1µF are
manufactured with Z5U or Y5V temperature characteristics.
Their capacitance can drop by more than 50% as the tem-
perature varies from 25°C to 85°C. Therefore X7R is recom-
mended over Z5U and Y5V in applications where the ambient
temperature will change significantly above or below 25°C.
Note that the output voltage ripple increases with the inductor
current ripple and the Equivalent Series Resistance of the
output capacitor (ESRCOUT). Also note that the actual value
of the capacitor’s ESRCOUT is frequency and temperature de-
pendent, as specified by its manufacturer. The ESR should
be calculated at the applicable switching frequency and am-
bient temperature.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
30166217
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Output ripple can be estimated from the vector sum of the
reactive (capacitance) voltage component and the real (ESR)
voltage component of the output capacitor where:
The device is designed to be used with ceramic capacitors on
the outputs of the buck regulators. The recommended dielec-
tric type of these capacitors is X5R, X7R, or of comparable
material to maintain proper tolerances over voltage and tem-
perature. The recommended value for the output capacitors
is 22 μF, 6.3V with an ESR of 2mΩ or less. The output ca-
pacitors need to be mounted as close as possible to the
output/ground pins of the device.
where:
VOUT-RIPPLE-PP
:
estimated output ripple,
VROUT
VCOUT
:
estimated real output ripple,
estimated reactive output ripple.
TABLE 4. Recommended Output Capacitors
Type
Vendor
Model
Vendor
Voltage Rating
Case Size
08056D226MAT2A
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
Ceramic, X5R
AVX Corporation
Kemet
6.3V
6.3V
6.3V
6.3V
6.3V
0805, (2012)
0805, (2012)
0805, (2012)
0603, (1608)
0603, (1608)
C0805L226M9PACTU
ECJ-2FB0J226M
Panasonic - ECG
Taiyo Yuden
JMK212BJ226MG-T
C2012X5R0J226M
TDK Corporation
21.2.3.2 Input Capacitor Selection
capacitor is 10 µF with an ESR of 10 mΩ or less. The input
capacitors need to be mounted as close as possible to the
power/ground input pins of the device.
There are 3 buck regulators in the LM10506 device. Each of
these buck regulators has its own input capacitor which
should be located as close as possible to their corresponding
SWx_VIN and SWx_GND pins, where x designates Buck 1,
2 or 3. The 3 buck regulators operate at 120° out of phase,
which means that they switch on at equally spaced intervals,
in order to reduce the input power rail ripple. It is recommend-
ed to connect all the supply/ground pins of the buck regula-
tors, SWx_VIN to two solid internal planes located under the
device. In this way, the 3 input capacitors work together and
further reduce the input current ripple. A larger tantalum ca-
pacitor can also be located in the proximity of the device.
The input power source supplies the average current contin-
uously. During the PFET switch on-time, however, the de-
manded di/dt is higher than can be typically supplied by the
input power source. This delta is supplied by the input capac-
itor.
A simplified “worst case” assumption is that all of the PFET
current is supplied by the input capacitor. This will result in
conservative estimates of input ripple voltage and capacitor
RMS current.
Input ripple voltage is estimated as follows:
The input capacitor supplies the AC switching current drawn
from the switching action of the internal power FETs. The in-
put current of a buck converter is discontinuous, so the ripple
current supplied by the input capacitor is large. The input ca-
pacitor must be rated to handle both the RMS current and the
dissipated power.
where:
VPPIN
The input capacitor must be rated to handle this current:
:
estimated peak-to-peak input ripple voltage,
Output Current
IOUT
:
CIN:
Input capacitor value
ESRCIN
:
input capacitor ESR.
This capacitor is exposed to significant RMS current, so it is
important to select a capacitor with an adequate RMS current
rating. Capacitor RMS current estimated as follows:
The power dissipated in the input capacitor is given by:
The device is designed to be used with ceramic capacitors on
the inputs of the buck regulators. The recommended dielectric
type of these capacitors is X5R, X7R, or of comparable ma-
terial to maintain proper tolerances over voltage and temper-
ature. The minimum recommended value for the input
IRMSCIN
:
estimated input capacitor RMS current.
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30
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
22.0 PCB Layout Considerations
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
30166225
FIGURE 8. Schematic of LM10506 Highlighting Layout Sensitive Nodes
1. Minimize area of switched current loops. In a buck
regulator there are two loops where currents are
be placed as close as possible to the SW pins to further
minimize the copper area of the switch node.
switched rapidly. The first loop starts from the CIN input
capacitor, to the regulator SWx_VIN pin, to the regulator
SW pin, to the inductor then out to the output capacitor
COUT and load. The second loop starts from the output
capacitor ground, to the regulator SWx_GND pins, to the
inductor and then out to COUT and the load (see figure
above). To minimize both loop areas the input capacitor
should be placed as close as possible to the VIN pin.
Grounding for both the input and output capacitors
should consist of a small localized top side plane that
connects to PGND. The inductor should be placed as
close as possible to the SW pin and output capacitor.
3. Have a single point ground for all device analog grounds.
The ground connections for the feedback components
should be connected together then routed to the GND pin
of the device. This prevents any switched or load currents
from flowing in the analog ground plane. If not properly
handled, poor grounding can result in degraded load
regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. The feedback trace
should be routed away from the SW pin and inductor to
avoid contaminating the feedback signal with switch
noise.
5. Make input and output bus connections as wide as
possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If
voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will
correct for voltage drops at the load and provide the best
output accuracy.
2. Minimize the copper area of the switch node. The SW
pins should be directly connected with a trace that runs
on top side directly to the inductor. To minimize IR losses
this trace should be as short as possible and with a
sufficient width. However, a trace that is wider than 100
mils will increase the copper area and cause too much
capacitive loading on the SW pin. The inductors should
31
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30166226
FIGURE 9. Possible PCB Layout Configuration to Use
6X Through Hole Vias in the Middle
Outside 7x7 array 0.4 mm micro SMD 34-bump, with 24
peripheral and 6 inner vias = 30 individual signals
22.1 PCB LAYOUT THERMAL DISSIPATION FOR MICRO SMD PACKAGE
1. Position ground layer as close as possible to micro SMD
package. Second PCB layer is usually good option.
LM10506 evaluation board is a good example.
2. Draw power traces as wide as possible. Bumps which
carry high currents should be connected to wide traces.
This helps the silicon to cool down.
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23.0 Physical Dimensions inches (millimeters) unless otherwise noted
34-bump micro SMD Package
Package Number TME34AAA
X1 = 2.815 mm ±0.030 mm
X2 = 2.815 mm ±0.030 mm
X3 = 0.600 mm ±0.075 mm
33
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Notes
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www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
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DLP® Products
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www.ti.com/energy
dsp.ti.com
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Interface
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interface.ti.com
logic.ti.com
www.ti.com/industrial
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www.ti.com/security
Medical
Logic
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Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
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www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
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